SI3010-X-FSR_技术文档

Si3056

Si3018/19/10

GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT

Features

Complete DAA includes the following:

ꢀ

Programmable line interface

ꢀ

Pulse dialing support

Overload detection

ꢁAC termination

ꢁDC termination

3.3 V power supply

ꢁRing detect threshold

ꢁRinger impedance

Direct interface to DSPs

Serial interface control for up to eight

devices

ꢀ

80 dB dynamic range TX/RX paths

Integrated codec and 2- to 4-wire ꢀ >5000 V isolation

hybrid

ꢀ

Proprietary isolation technology

Parallel handset detection

+3.2 dBm TX/RX level mode

Programmable digital hybrid for near-

end echo reduction

Low-profile SOIC packages

Lead-free/RoHS-compliant packages

available

ꢀ

Integrated ring detector

Type I and II caller ID support

Line voltage monitor

Loop current monitor

Polarity reversal detection

Programmable digital gain

Clock generation

Ordering Information

See page 88.

ꢀ

Pin Assignments

Si3056

Applications

MCLK

FSYNC

SCLK

V_D

SDO

SDI

FC/RGDT

RESET

1

16

OFHK

RGDT/FSD/M1

M0

V_A

GND

AOUT/INT

C1A

C2A

2

3

4

5

6

15

14

13

12

11

10

9

ꢀ

V.92 modems

ꢀ

Set-top boxes

ꢀ

Internet appliances

Personal digital

assistants

Voice mail systems ꢀ Fax machines

Multi-function printers

Description

7

8

The Si3056 is an integrated direct access arrangement (DAA) with a

programmable line interface to meet global telephone line requirements. Available

in two 16-pin small outline packages, it eliminates the need for an analog front end

(AFE), isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The

Si3056 dramatically reduces the number of discrete components and cost

required to achieve compliance with global regulatory requirements. The Si3056

interfaces directly to standard modem DSPs.

Si3018/19/10

1

16

15

14

13

12

11

10

9

DCT2

IGND

DCT3

QB

QE2

SC

QE

DCT

RX

2

3

4

5

6

7

8

IB

Functional Block Diagram

C1B

C2B

VREG

Si3056

Si3018/19/10

VREG2

RNG2

RNG1

MCLK

SCLK

RX

IB

FSYNC

Digital

SC

Interface

SDI

US Patent # 5,870,046

US Patent # 6,061,009

Other Patents Pending

Hybrid and

SDO

FC/RGDT

dc

DCT

Termination

VREG

VREG2

DCT2

DCT3

Isolation

Interface

Isolation

Interface

RGDT/FSD/M1

RNG1

RNG2

OFHK

M0

RESET

Control

Interface

Ring Detect

Off-Hook

QB

QE

QE2

AOUT/INT

Rev. 1.05 6/05

Si3056

Si3018/19/10

2

Rev. 1.05

Si3056

Si3018/19/10

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4. AOUT PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.1. Upgrading from the Si3034/35/44 to Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.2. Line-Side Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.3. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.4. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.5. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.6. Transmit/Receive Full Scale Level (Si3019 Line-Side Only) . . . . . . . . . . . . . . . . . . .25

5.7. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.8. Line Voltage/Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.9. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5.10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

5.11. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

5.12. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

5.13. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.14. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.15. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.16. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.17. Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.18. Billing Tone Protection and Receive Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.19. Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.20. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.21. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.22. Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5.23. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5.24. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

5.25. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

5.26. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.27. Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

5.28. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

5.29. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

5.30. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

5.31. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

5.32. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

7. Pin Descriptions: Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

8. Pin Descriptions: Si3018/19/10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Rev. 1.05

3

Si3056

Si3018/19/10

9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

10. Evaluation Board Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

11. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Silicon Laboratories Si3056 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

4

Rev. 1.05

Si3056

Si3018/19/10

1. Electrical Specifications

Table 1. Recommended Operating Conditions

1

2

Parameter

Symbol

Test Condition

Min

Typ

25

Max

70

Unit

°C

Ambient Temperature

Si3056 Supply Voltage, Digital

Notes:

T

F and K-Grade

0

A

3

V

3.0

3.3

3.6

V

D

1. The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the

Si3056 and any Si3018 or Si3019 are used. See Figure 17 on page 18 for typical application schematic.

2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.

3. 3.3 V applies to both the digital and serial interface and the digital signals RGDT/FSD, OFHK, RESET, M0, and M.

Rev. 1.05

5

Si3056

Si3018/19/10

Table 2. Loop Characteristics

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C, see Figure 1)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

DC Termination Voltage

V

I = 20 mA, MINI = 11,

—

6.0

V

TR

L

ILIM = 0, DCV = 00, DCR = 0

DC Termination Voltage

I = 120 mA, MINI = 11,

9

—

7.5

—

V

L

ILIM = 0, DCV = 00, DCR = 0

I = 20 mA, MINI = 00,

—

9

L

ILIM = 0, DCV = 11, DCR = 0

I = 120 mA, MINI = 00,

L

ILIM = 0, DCV = 11, DCR = 0

I = 20 mA, MINI = 00,

—

40

—

7.5

—

L

ILIM = 1, DCV = 11, DCR = 0

I = 60 mA, MINI = 00,

L

ILIM = 1, DCV = 11, DCR = 0

I = 50 mA, MINI = 00,

40

L

ILIM = 1, DCV = 11, DCR = 0

On Hook Leakage Current

Operating Loop Current

DC Ring Current

I

V

= –48 V

TR

—

10

—

5

120

60

3

µA

mA

µA

LK

LP

MINI = 00, ILIM = 0

MINI = 00, ILIM = 1

1.5

DC current flowing through ring

detection circuitry

Ring Detect Voltage*

Ring Frequency

V

F

RT = 0

RT = 1

13.5

19.35

13

15

21.5

—

16.5

23.65

68

V

Hz

RD

rms

R

Ringer Equivalence Number

REN

—

0.2

*Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected

above the maximum.

TIP

+

600 Ω

I_L

V_TR

Si3018

10 µF

–

RING

Figure 1. Test Circuit for Loop Characteristics

6

Rev. 1.05

Si3056

Si3018/19/10

Table 3. DC Characteristics, V_D= 3.3 V

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C)

Parameter

Symbol

Test Condition

Min

2.4

—

Typ

—

15

9

Max

—

Unit

V

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Power Supply Current, Digital

V

IH

V

0.8

—

V

IL

V

I = –2 mA

2.4

—

V

OH

O

V

I = 2 mA

0.35

10

V

OL

O

I

–10

—

µA

mA

L

D

1

I

V pin

—

D

1

Total Supply Current, Sleep Mode

PDN = 1, PDL = 0

PDN = 1, PDL = 1

—

1,2

Total Supply Current, Deep Sleep

—

1

—

Notes:

1. All inputs at 0.4 or V_D– 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded

(Static I_OUT= 0 mA).

2. RGDT is not functional in this state.

Rev. 1.05

7

Si3056

Si3018/19/10

Table 4. AC Characteristics

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C; see Figure 17 on page 18)

Parameter

Symbol

Test Condition

Fs = F /5120

Min

7.2

—

Typ

Max

16

—

Unit

kHz

MHz

Hz

1

Sample Rate

Fs

—

PLL2

1

PLL Output Clock Frequency

F

= (F x M)/N

MCLK

98.304

PLL1

Transmit Frequency Response

Receive Frequency Response

Low –3 dBFS Corner

—

0

5

—

Low –3 dBFS Corner,

FILT = 0

—

Hz

Receive Frequency Response

Low –3 dBFS Corner,

—

200

—

Hz

11

FILT = 1

2,3

Transmit Full Scale Level

V

FULL = 0 (0 dBm)

—

1.1

1.58

2.16

1.1

—

V

FS

PEAK

11

FULL = 1 (3.2 dBm)

V

FULL2 = 1 (6.0 dBm)

FULL = 0 (0 dBm)

2,4

Receive Full Scale Level

V

11

FULL = 1 (3.2 dBm)

—

1.58

2.16

80

—

FULL2 = 1 (6.0 dBm)

PEAK

5,6,7

Dynamic Range

DR

ILIM = 0, DCV = 11, DCR = 0,

dB

I = 100 mA, MINI = 00

L

5,6,7

Dynamic Range

ILIM = 0, DCV = 00, DCR = 0,

—

80

—

dB

I = 20 mA, MINI = 11

L

5,6,7

Dynamic Range

DR

ILIM = 1, DCV = 11, DCR = 0,

I = 50 mA, MINI = 00

L

Transmit Total Harmonic

THD

ILIM = 0, DCV = 11, DCR = 0,

–72

–78

8,9

Distortion

I = 100 mA, MINI = 00

L

Transmit Total Harmonic

ILIM = 0, DCV = 00, DCR = 0,

8,9

Distortion

I = 20 mA, MINI = 11

L

Notes:

1. See Figure 26 on page 37.

2. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.

3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600 Ω ac termination, while

the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all

reference impedances in “FULL” mode. With FULL2 = 1, the transmit and receive full scale level of +6.0 dBm can be

achieved with a 600 Ω ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5 dBV into all reference

impedances.

4. Receive full scale level produces –0.9 dBFS at SDO.

5. DR = 20 x log (RMS V_FS/RMS V_IN).+ 20 x log (RMS V_IN/RMS noise). The RMS noise measurement excludes

harmonics. V_FSis the 0 dBm full-scale level.

6. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. V_IN= 1 kHz, –3 dBFS, Fs = 10300 Hz.

7. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.

8. THD = 20 x log (RMS distortion/RMS signal). V_IN= 1 kHz, –3 dBFS, Fs = 10300 Hz.

9. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.

10. DR_CID= 20 x log (RMS V_CID/RMS V_IN) + 20 x log(RMS V_IN/RMS noise). V_CIDis the 6 V full-scale level for the typical

application circuit in Figure 17. With the enhanced CID circuit, the V_CIDfull-scale level is 1.5 V peak, and DR_CID

increases to 62 dB.

11. Available on the Si3019 line-side device only.

8

Rev. 1.05

Si3056

Si3018/19/10

Table 4. AC Characteristics (Continued)

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C; see Figure 17 on page 18)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Receive Total Harmonic

THD

ILIM = 0, DCV = 00, DCR = 0,

—

–78

—

dB

8,9

Distortion

I = 20 mA, MINI = 11

L

Receive Total Harmonic

THD

ILIM = 1, DCV = 11, DCR = 0,

—

–78

50

—

dB

8,9

Distortion

I = 50 mA, MINI = 00

L

Dynamic Range (caller ID

DR

VIN = 1 kHz, –13 dBFS

CID

10,7

mode)

10

Caller ID Full Scale Level

AOUT Low Level Current

AOUT High Level Current

V

—

6

—

10

V

PEAK

CID

—

mA

Notes:

1. See Figure 26 on page 37.

2. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.

3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600 Ω ac termination, while

the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all

reference impedances in “FULL” mode. With FULL2 = 1, the transmit and receive full scale level of +6.0 dBm can be

achieved with a 600 Ω ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5 dBV into all reference

impedances.

4. Receive full scale level produces –0.9 dBFS at SDO.

5. DR = 20 x log (RMS V_FS/RMS V_IN).+ 20 x log (RMS V_IN/RMS noise). The RMS noise measurement excludes

harmonics. V_FSis the 0 dBm full-scale level.

6. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. V_IN= 1 kHz, –3 dBFS, Fs = 10300 Hz.

7. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.

8. THD = 20 x log (RMS distortion/RMS signal). V_IN= 1 kHz, –3 dBFS, Fs = 10300 Hz.

9. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.

10. DR_CID= 20 x log (RMS V_CID/RMS V_IN) + 20 x log(RMS V_IN/RMS noise). V_CIDis the 6 V full-scale level for the typical

application circuit in Figure 17. With the enhanced CID circuit, the V_CIDfull-scale level is 1.5 V peak, and DR_CID

increases to 62 dB.

11. Available on the Si3019 line-side device only.

Rev. 1.05

9

Si3056

Si3018/19/10

Table 5. Absolute Maximum Ratings

Parameter

Symbol

Value

–0.5 to 3.6

±10

Unit

V

DC Supply Voltage

V

D

Input Current, Si3056 Digital Input Pins

Digital Input Voltage

I

mA

V

IN

V

–0.3 to (V + 0.3)

IND

D

Operating Temperature Range

Storage Temperature Range

T

–40 to 100

–65 to 150

°C

A

T

STG

Note: Permanent device damage can occur if the above absolute maximum ratings are exceeded. Restrict functional

operation to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods might affect device reliability.

Table 6. Switching Characteristics—General Inputs

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C, C_L= 20 pF)

1

Symbol

Min

Typ

Max

Unit

Parameter

Cycle Time, MCLK

MCLK Duty Cycle

MCLK Jitter Tolerance

Rise Time, MCLK

Fall Time, MCLK

MCLK Before RESET ↑

t

16.67

40

—

50

—

1000

60

±2

5

ns

%

mc

dty

t

—

ns

jitter

t

—

ns

r

t

—

5

ns

f

t

10

—

cycles

ns

mr

2

RESET Pulse Width

t

250

20

rl

3

M0, M Before RESET↑

t

ns

mxr

Notes:

1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are

V_IH= V_D– 0.4 V, V_IL= 0.4 V. Rise and fall times are referenced to the 20% and 80% levels of the waveform.

2. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times.

3. M0 and M are typically connected to V_Dor GND and should not be changed during normal operation.

t_mc

t_r

t_f

V_IH

V_IL

MCLK

t_mr

RESET

t_rl

M0, M1

t_mxr

Figure 2. General Inputs Timing Diagram

10

Rev. 1.05

Si3056

Si3018/19/10

Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0)

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C, C_L= 20 pF)

Parameter

Symbol

Min

244

—

Typ

Max

—

Unit

ns

%

Cycle time, SCLK

t

1/256 Fs

c

SCLK Duty Cycle

t

50

—

dty

Delay Time, SCLK↑ to FSYNC↓

Delay Time, SCLK↑ to SDO Valid

Delay Time, SCLK↑ to FSYNC↑

Setup Time, SDI Before SCLK ↓

Hold Time, SDI After SCLK ↓

Setup Time, FC↑ Before SCLK↑

Hold time, FC↑ After SCLK↑

t

—

20

—

ns

d1

d2

d3

t

—

t

25

20

40

su

t

—

h

t

—

sfc

hfc

t

—

Note: All timing is referenced to the 50% level of the waveform. Input test levels are V_IH= V_D– 0.4 V, V_IL= 0.4 V.

t_c

V_OH

V_OL

SCLK

t_d1

t_d3

FSYNC

(mode 0)

t_d3

FSYNC

(mode 1)

t_d2

16-Bit

SDO

D15

D14

D1

DD00

D0

t_su

t_h

16-Bit

SDI

D15

t_sfc

t_hfc

FC

Figure 3. Serial Interface Timing Diagram (DCE = 0)

Rev. 1.05

11

Si3056

Si3018/19/10

Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 0)

(V_A= Charge Pump, V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C, C_L= 20 pF)

1,2

Symbol

Min

Typ

Max

Unit

Parameter

Cycle Time, SCLK

SCLK Duty Cycle

t

244

—

25

20

1/256 Fs

—

20

—

ns

%

c

t

50

—

dty

Delay Time, SCLK↑ to FSYNC↑

Delay Time, SCLK↑ to FSYNC↓

Delay Time, SCLK↑ to SDO valid

Delay Time, SCLK↑ to SDO Hi-Z

Delay Time, SCLK↑ to FSD↓

Delay Time, SCLK↑ to FSD↑

Setup Time, SDO Before SCLK↓

Hold Time, SDO After SCLK↓

Notes:

t

ns

d1

d2

d3

d4

d5

d6

t

su

t

h

1. All timing is referenced to the 50% level of the waveform. Input test levels are V_IH= V_D– 0.4 V, V_IL= 0.4 V.

2. See "5.27.Multiple Device Support" on page 38 for functional details.

32 SCLKs

16 SCLKs

t_c

SCLK

t_d1

t_d2

FSYNC

(mode 1)

t_d2

t_d6

t_d2

FSYNC

(mode 0)

t_d3

t_su

D15

t_h

t_d4

SDO

(master)

D14

D13

D0

t_d3

SDO

D15

(slave 1)

t_d5

FSYNC

(Mode 0)

t_d5

FSYNC

(Mode 1)

t_su

t_h

D14

SDI

D15

D13

D0

Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)

12

Rev. 1.05

Si3056

Si3018/19/10

Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 1)

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C, C_L= 20 pF)

1, 2

Symbol

Min

Typ

Max

Unit

Parameter

Cycle Time, SCLK

t

244

—

1/256 Fs

—

20

—

ns

%

c

SCLK Duty Cycle

t

50

—

dty

Delay Time, SCLK↑ to FSYNC↑

Delay Time, SCLK↑ to FSYNC↓

Delay Time, SCLK↑ to SDO Valid

Delay Time, SCLK↑ to SDO Hi-Z

Delay Time, SCLK↑ to FSD↓

Setup Time, SDO Before SCLK↓

Hold Time, SDO After SCLK↓

Notes:

t

—

ns

d1

d2

d3

d4

d5

t

—

t

—

t

25

20

su

t

h

1. All timing is referenced to the 50% level of the waveform. Input test levels are V_IH= V_D– 0.4 V, V_IL= 0.4 V.

2. See "5.27.Multiple Device Support" on page 38 for functional details.

t_c

SCLK

t_d1

t_d2

FSYNC

(mode 1)

t_d3

t_su

t_h

t_d4

SDO

D15

D14

D13

D0

(master)

t_d3

SDO

D15

t_d5

(slave 1)

FSD

SDI

t_su

t_h

D14

D15

D1

D0

Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)

Rev. 1.05

13

Si3056

Si3018/19/10

Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = 1)

(V_A= Charge Pump, V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C, C_L= 20 pF)

Symbol

Min

Typ

Max

Unit

Parameter

Cycle Time, MCLK

t

244

—

1/256 Fs

—

20

ns

c

Setup Time, FSYNC↑ before MCLK↓*

Delay Time, FSYNC↑ after MCLK↓*

Setup Time, SDI before MCLK↓

Hold Time, SDI After MCLK↓

Delay Time, MCLK↑ to SDO

Delay Time, MCLK↑ to FSYNC↑

Delay Time, MCLK↑ to FSYNC↓

t

—

su1

t

d1

su3

t

h2

d3

d1

d2

t

*Note: T_su1and T_h1are listed for applications where the controller drives the MCLK and FSYNC instead of a master DAA.

t_C

MCLK

t_SU1

t_d1

t_h1

FSYNC

(mode 1)

t_d2

FSYNC

(mode 0)

t_h2

t_su3

D15

D14

D0

SDI

t_d3

SDO

D14

Figure 6. Serial Interface Timing Diagram (Slave Mode, DCE = 1, FSD = 1)

14

Rev. 1.05

Si3056

Si3018/19/10

Table 11. Digital FIR Filter Characteristics—Transmit and Receive

(V_D= 3.0 to 3.6 V, Sample Rate = 8 kHz, T_A= 0 to 70 °C)

Parameter

Symbol

Min

0

Typ

—

Max

3.3

3.6

0.1

—

Unit

kHz

dB

Passband (0.1 dB)

Passband (3 dB)

Passband Ripple Peak-to-Peak

Stopband

F

(0.1 dB)

F

0

—

(3 dB)

–0.1

—

4.4

—

kHz

dB

Stopband Attenuation

Group Delay

–74

—

t

—

12/Fs

—

s

gd

Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10.

Table 12. Digital IIR Filter Characteristics—Transmit and Receive

(V_D= 3.0 to 3.6 V, Sample Rate = 8 kHz, T_A= 0 to 70 °C)

Parameter

Symbol

Min

0

Typ

—

Max

3.6

0.2

—

Unit

kHz

dB

Passband (3 dB)

Passband Ripple Peak-to-Peak

Stopband

F

(3 dB)

–0.2

—

4.4

kHz

dB

Stopband Attenuation

Group Delay

–40

—

t

1.6/Fs

—

s

gd

Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 11, 12, 13, and 14. Figures 15 and 16 show

group delay versus input frequency.

Rev. 1.05

15

Si3056

Si3018/19/10

Figure 7. FIR Receive Filter Response

Figure 9. FIR Transmit Filter Response

Figure 8. FIR Receive Filter Passband Ripple

Figure 10. FIR Transmit Filter Passband Ripple

For Figures 7–10, all filter plots apply to a sample rate of Fs = 8 kHz.

16

Rev. 1.05

Si3056

Si3018/19/10

Figure 11. IIR Receive Filter Response

Figure 12. IIR Receive Filter Passband Ripple

Figure 13. IIR Transmit Filter Response

Figure 14. IIR Transmit Filter Passband Ripple

Figure 15. IIR Receive Group Delay

Figure 16. IIR Transmit Group Delay

Rev. 1.05

17

Si3056

Si3018/19/10

2. Typical Application Schematic

18

Rev. 1.05

Si3056

Si3018/19/10

3. Bill of Materials

Component(s)

Value

Supplier(s)

33 pF, Y2, X7R, ±20%

Panasonic, Murata, Vishay

C1, C2

C3¹

C4

10 nF, 250 V, X7R, ±10%

1.0 uF, 50 V, Elec/Tant, ±20%

0.1 uF, 16V, X7R, ±20%

Venkel, SMEC

Panasonic

C5, C6, C50, C51

C7

Venkel, SMEC

2.7 nF, 50V, X7R, 20%

680 pF, Y2, X7R, ±10%

Venkel, SMEC

C8, C9

C10

Panasonic, Murata, Vishay

0.01 uF, 16 V, X7R, ±20%

Not installed, 120 pF, 250V, X7R, ±10%

Venkel, SMEC

C30, C31³

D1, D2²

FB1, FB2

Q1, Q3

Q2

Venkel, SMEC

Dual Diode, 225 mA, 300 V, CMPD2004S

Ferrite Bead, BLM18AG601SN1B

NPN, 300 V, MMBTA42

Central Semiconductor

Murata

OnSemi, Fairchild

PNP, 300 V, MMBTA92

OnSemi, Fairchild

Q4, Q5

RV1

NPN, 80 V, 330 mW, MMBT2484

Sidactor, 275 V, 100 A

OnSemi, Fairchild

Teccor, Protek, ST Micro

Venkel, SMEC, Panasonic

1.07 kohm, 1/2 W, 1%

R1

150 ohm, 1/16 W, 5%

R2

R3

3.65 kohm, 1/2 W, 1%

R4

2.49 kohm, 1/2 W, 1%

R5, R6

R7, R8³

R9

100 kohm, 1/16 W, 5%

20 Mohm, 1/16 W, 5%

1 Mohm, 1/16 W, 1%

536 ohm, 1/4 W, 1%

73.2 ohm, 1/2 W, 1%

56.2 ohm, 1/16 W, 1%

R10

R11

R12, R13

R15, R16⁴

R30, R32³

0 ohm, 1/16 W

Not installed, 15 Mohm,, 1/8 W, 5%

Not installed, 5.1 Mohm,, 1/8 W, 5%

4.7 kohm,, 1/10 W, 5%

Si3056

Si3018/19/10

Zener Diode, 43 V, 1/2 W, ZMM43

Venkel, SMEC, Panasonic

Silicon Labs

General Semiconductor

R31, R33³

R51, R52

U1

U2

Z1

1. Value for C3 above is recommended for use with the Si3018. In voice appliations, a C3 value of 3.9 nF (250 V,

X7R, 20%) is recommended to improve return loss performance

2. Several diode bridge configurations are acceptable, parts such as a single DF-04S or four 1N4004 diodes may be

used (suppliers include General Semiconductor, Diodes Inc., etc.)

3. C30-31 and R30-33 can be substitued for R7-8 to implent the enhanced caller ID circuit.

4. Murata BLM18AG601SN1B may be substituted for R15-R16 (0 ohm) to decrease emissions.

Rev. 1.05

19

Si3056

Si3018/19/10

4. AOUT PWM Output

Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3056

for call progress monitoring purposes. Set the PWME bit (Register 1, bit 3) to enable this mode.

+5 VA

LS1

Q6

NPN

R41

AOUT

C41

Figure 18. AOUT PWM Circuit for Call Progress

Table 13. Component Values—AOUT PWM

Component

LS1

Value

Supplier

Intervox

Speaker BRT1209PF-06

NPN KSP13

Q6

Fairchild

C41

0.1 µF, 16 V, X7R, ±20%

150 Ω, 1/16 W, ±5%

Venkel, SMEC

Venkel, SMEC, Panasonic

R41

Registers 20 and 21 allow the receive and transmit paths to be attenuated linearly. When these registers are set to

all 0s, the receive and transmit paths are muted. These registers affect the call progress output only and do not

affect transmit and receive operations on the telephone line.

The PWMM[1:0] bits (Register 1, bits 5:4) select one of the three different PWM output modes for the AOUT signal,

including a delta-sigma data stream, a conventional 32 kHz return to zero PWM output, and balanced 32 kHz PWM

output.

20

Rev. 1.05

Si3056

Si3018/19/10

ꢀ

New features have been added to the Si3056

including more ac terminations, a programmable

hybrid, finer gain/attenuation step resolution, finer

resolution loop current monitoring capability, ring

validation, more HW interrupts, a 200 Hz low

frequency filter pole. (See the appropriate functional

descriptions.)

5. Functional Description

The Si3056 is an integrated direct access arrangement

(DAA) that provides a programmable line interface to

meet global telephone line interface requirements. The

®

Si3056 implements Silicon Laboratories patented

isolation technology and offers the highest level of

integration by replacing an analog front end (AFE), an

isolation transformer, relays, opto-isolators, and a 2- to

4-wire hybrid with two 16-pin packages.

ꢀ

The secondary communication data format (see

"5.26.Digital Interface" on page 37).

The low-power sleep mode, and system

requirements to support wake-on-ring. (See

"5.28.Power Management" on page 39.)

The Si3056 DAA is software programmable to meet

global requirements and is compliant with FCC, TBR21,

JATE, and other country-specific PTT specifications as

shown in Table 16 on page 26. In addition, the Si3056

meets the most stringent worldwide requirements for

out-of-band energy, emissions, immunity, high-voltage

surges, and safety, including FCC Part 15 and 68,

EN55022, EN55024, and many other standards.

5.2. Line-Side Device Support

Three different line-side devices can be used with the

Si3056 system-side device:

ꢀ

Globally-compliant line-side device—Targets global

DAA requirements. Use the Si3018 global line-side

device for this configuration. This line-side device

supports both FCC-compliant countries and non-

FCC-compliant countries.

Globally-compliant, enhanced features line-side

device—Targets embedded and voice applications

with global DAA requirements. Use the Si3019 line-

side device for this configuration. The Si3019

contains all the features available on the Si3018,

plus the following additional features/enhancements:

5.1. Upgrading from the Si3034/35/44 to

Si3056

The Si3056 offers Silicon Laboratories customers

®

ꢀ

currently using Si3034/35/44 standard serial interface

DAA chipsets with an upgrade path for use in new

designs. The Si3056 digital interface is similar to the

Si3034/35/44 DAAs, thus the Si3056 retains the ability

to connect to many widely available DSPs. This also

allows customers to leverage software developed for

existing Si3034/35/44 designs. More importantly, the

Si3056 also offers a number of new features not

provided in the Si3034/35/44 DAAs. An overview of the

feature differences between the Si3044 and the Si3056

is presented in Table 14. Finally, the globally-compliant

Si3056 can be implemented with roughly half the

external components required in the already highly

integrated Si3034/35/44 DAA application circuits. The

following items have changed in the Si3056 as

compared to the Si3034/35/44 DAAs:

ꢁ Sixteen selectable ac terminations to increase return

loss and trans-hybrid loss performance.

ꢁ Higher transmit and receive level mode.

ꢁ Selectable 200 Hz low frequency pole.

ꢁ –16 to 13.5 dB digital gain/attenuation adjustment in

0.1 dB increments for the transmit and receive paths.

ꢁ Programmable line current/voltage threshold interrupt.

Globally-compliant, low-speed only line-side

device—Targets embedded 2400 bps soft modem

applications. Use the Si3010 line-side device for this

configuration. The Si3010 contains all the features

available on the Si3018, except the transmit and

receive paths are optimized and tested only for

modem connect rates up to 2400 bps.

ꢀ

The pinout, the application circuit, and the bill of

materials. The Si3056 is not pin compatible with

Si3034/35/44 DAA chipsets.

Rev. 1.05

21

Si3056

Si3018/19/10

Table 14. New Si3056 Features

Chipset

Si3044

Si3021

Si3056

System-Side Part #

Line-Side Part #

Si3015

Yes

Si3010

Yes

Si3018

Yes

Si3019

Yes

Global DAA

Digital Interface

SSI

Power Supply

3.3 V or 5 V

56 kbps

16-bit

3.3 V

Max Modem Connect Rate

Data Bus Width

2400 bps

16-bit

56 kbps

16-bit

56 kbps

16-bit

Control Register Addressing

Max Sampling Frequency

AC Terminations

6-bit

8-bit

11.025 kHz

2

16 kHz

4

16 kHz

4

16 kHz

16

Programmable Gain

Loop Current Monitoring

Line Voltage Monitoring

Polarity Reversal Detection

Line I/V Threshold Detection

Ring Qualification

Wake-on-Ring Support

HW Interrupts

3 dB steps

3 mA/bit

2.75 V per bit

3 dB steps

1.1 mA/bit

1 V per bit

3 dB steps

1.1 mA/bit

1 V per bit

0.1 dB steps

1.1 mA/bit

1 V per bit

Yes (SW polling) Yes (HW interrupt) Yes (HW interrupt) Yes (HW interrupt)

No

Yes

No

Yes

Yes (MCLK active) Yes (MCLK active) Yes (MCLK active)

Ring detect only

Yes

7 HW interrupts

Yes

7 HW interrupts

Yes

8 HW interrupts

Yes

Integrated Fixed Analog

Hybrid

Programmable Digital Hybrid

No

Yes

Full Scale Transmit/Receive

Level

+3.2 dBm

0 dBm

+3.2 dBm

22

Rev. 1.05

Si3056

Si3018/19/10

Table 15. Country Specific Register Settings

2

3

Register

Country

16

OHS

0

1

0

31

OHS2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16

RZ

0

16

RT

0

26

ILIM

0

1

0

1

0

1

0

1

0

1

0

1

0

1

26

30

16

DCV[1:0] MINI[1:0] ACIM[3:0]

ACT

0

ACT2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Argentina

11

01

11

01

11

00

01

00

01

00

0000

0011

0010

0000

0011

0000

0000/1010

0000

0010

0000

0010

0000

0010

0000

0010

0000

0010

0000

0010

4

Australia

Austria

Bahrain

Belgium

Brazil

Bulgaria

Canada

Chile

5

China

Colombia

Croatia

Cyprus

Czech Republic

Denmark

Ecuador

Egypt

El Salvador

Finland

France

Germany

Greece

Guam

Hong Kong

Hungary

Iceland

India

Indonesia

Ireland

Israel

Italy

Japan

Jordan

Kazakhstan

Kuwait

Latvia

Note:

0

1

1. Supported for loop current ≥ 20 mA.

2. Available with Si3019 line-side only.

3. Available with Si3018 and Si3010 line-sides only.

4. See "5.11.DC Termination" on page 27 for DCV and MINI settings.

5. ACIM is 0000 for data applications and 1010 for voice applications.

6. For South Korea, set the TB3 bit in conjunction with the RZ bit. (See Register 59 description.)

Rev. 1.05

23

Si3056

Si3018/19/10

Table 15. Country Specific Register Settings (Continued)

2

3

Register

Country

16

OHS

0

31

OHS2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

16

RZ

0

1

0

16

RT

0

26

ILIM

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

26

30

16

DCV[1:0] MINI[1:0] ACIM[3:0]

ACT

0

1

0

1

0

ACT2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Lebanon

11

01

11

01

11

01

11

01

11

00

01

00

01

00

01

00

01

00

0010

0000

0010

0000

0010

0100

0010

0000

0010

0000

0010

0011

0000

0010

0000

0010

0000

0101

0000

Luxembourg

Macao

1

Malaysia

Malta

Mexico

Morocco

Netherlands

New Zealand

Nigeria

Norway

Oman

Pakistan

Peru

Philippines

Poland

Portugal

Romania

Russia

Saudi Arabia

Singapore

Slovakia

Slovenia

South Africa

6

South Korea

Spain

Sweden

Switzerland

Taiwan

TBR21

Thailand

UAE

United Kingdom

USA

Yemen

Note:

0

1

0

1

0

1. Supported for loop current ≥ 20 mA.

2. Available with Si3019 line-side only.

3. Available with Si3018 and Si3010 line-sides only.

4. See "5.11.DC Termination" on page 27 for DCV and MINI settings.

5. ACIM is 0000 for data applications and 1010 for voice applications.

6. For South Korea, set the TB3 bit in conjunction with the RZ bit. (See Register 59 description.)

24

Rev. 1.05

Si3056

Si3018/19/10

The capacitive communications link is disabled by

default. To enable it, the PDL bit (Register 6, bit 4) must

be cleared. No communication between the system-

side and line-side can occur until this bit is cleared. The

clock generator must be programmed to an acceptable

sample rate before clearing the PDL bit.

5.3. Power Supplies

The Si3056 system-side device operates from a 3.0–

3.6 V power supply. The Si3056 input pins are 5 V

tolerant. The Si3056 output pins only drive 3.3 V. The

line-side device derives its power from two sources: The

Si3056 and the telephone line. The Si3056 supplies

power over the patented isolation link between the two

devices, allowing the line-side device to communicate

with the Si3056 while on-hook and perform other on-

hook functions such as line voltage monitoring. When

off-hook, the line-side device also derives power from

the line current supplied from the telephone line. This

5.6. Transmit/Receive Full Scale Level

(Si3019 Line-Side Only)

The Si3056 supports programmable maximum transmit

and receive levels. The default signal level supported by

the Si3056 is 0 dBm into a 600 Ω load. Two additional

modes of operation offer increased transmit and receive

level capability to enable use of the DAA in applications

that require higher signal levels. The full scale mode is

enabled by setting the FULL bit in Register 31. With

FULL = 1, the full scale signal level increases to

+3.2 dBm into a 600 Ω load, or 1 dBV into all reference

impedances. The enhanced full scale mode (or 2X full

scale) is enabled by setting the FULL2 bit in Register

30. Will FULL2 = 1, the full scale signal level increases

to +6.0 dBm into a 600 Ω load, or 1.5 dBV into all

reference impedances. The full scale and enhanced full

scale modes provide the ability to trade off TX power

and TX distortion for a peak signal. By using the

programmable digital gain registers in conjunction with

the enhanced full scale signal level mode, a specific

power level (+3.2 dBm for example) could be achieved

across all ACT settings.

®

feature is exclusive to DAAs from Silicon Laboratories

and allows the most cost-effective implementation for a

DAA while still maintaining robust performance over all

line conditions.

5.4. Initialization

When the Si3056 is powered up, assert the RESET pin.

When the RESET pin is deasserted, the registers have

default values. This reset condition guarantees the line-

side device is powered down without the possibility of

loading the line (i.e., off-hook). An example initialization

procedure is outlined in the following list:

1. Program the PLL with registers 8 and 9 (N[7:0],

M[7:0]) to the appropriate divider ratios for the

supplied MCLK frequency and the sample rate in

register 7 (SRC), as defined in "5.25.Clock

Generation" on page 36.

5.7. Parallel Handset Detection

2. Wait 1 ms until the PLL is locked.

The Si3056 can detect a parallel handset going off-

hook. When the Si3056 is off-hook, the loop current can

be monitored with the LCS bits. A significant drop in

loop current signals that a parallel handset is going off-

hook. If a parallel handset causes the LCS bits to read

all 0s, the Drop-Out Detect (DOD) bit can be checked to

verify a valid line exists.

3. Write a 00H into Register 6 to power up the line-side

device.

4. Set the required line interface parameters (i.e.,

DCV[1:0], MINI[1:0], ILIM, DCR, ACT and ACT2 or

ACIM[3:0], OHS, RT, RZ, ATX[2:0] or TGA2 and

TXG2) as defined by “Country Specific Register

Settings” shown in Table 15.

The LVS bits can be read to determine the line voltage

when on-hook and off-hook. Significant drops in line

voltage can signal a parallel handset. For the Si3056 to

operate in parallel with another handset, the parallel

handset must have a sufficiently high dc termination to

support two off-hook DAAs on the same line. Improved

parallel handset operation can be achieved by changing

the dc impedance from 50 to 800 Ω and reducing the

DCT pin voltage with the DVC[1:0] bits.

When this procedure is complete, the Si3056 is ready

for ring detection and off-hook.

5.5. Isolation Barrier

The Si3056 achieves an isolation barrier through low-

cost, high-voltage capacitors in conjunction with Silicon

®

Laboratories proprietary signal processing techniques.

These techniques eliminate signal degradation from

capacitor mismatches, common mode interference, or

noise coupling. As shown in Figure 17 on page 18, the

C1, C2, C8, and C9 capacitors isolate the Si3056

(system-side) from the line-side device. Transmit,

receive, control, ring detect, and caller ID data are

passed across this barrier. Y2 class capacitors can be

used to achieve surge performance of 5 kV or greater.

5.8. Line Voltage/Loop Current Sensing

The Si3056 can measure loop current and line voltage

with the Si3010, Si3018, and the Si3019 line-side

devices. The 8-bit LCS2[7:0] and LCS[4:0] registers

report loop current. The 8-bit LVS[7:0] register reports

line voltage.

Rev. 1.05

25

Si3056

Si3018/19/10

These registers can help determine the following:

detection of another phone going off-hook by monitoring

the dc loop current. The LCS bits are decoded from

LCS2; so, both are available at the same time. The line

current sense transfer function is shown in Figure 19

and detailed in Table 16. The LCS and LCS2 bits report

loop current down to the minimum operating loop

current for the DAA. Below this threshold, the reported

value of loop current is unpredictable.

ꢀ

When on-hook, detect if a line is connected.

When on-hook, detect if a parallel phone is off-hook.

When off-hook, detect if a parallel phone goes on or

off-hook.

Detect if enough loop current is available to operate.

When used in conjunction with the OPD bit, detect if

an overcurrent condition exists. (See "5.22.Overload

Detection" on page 35.)

ꢀ

Table 16. Loop Current Transfer Function

5.8.1. Line Voltage Measurement

LCS[4:0]

Condition

The Si3056 device reports line voltage with the LVS[7:0]

bits (Register 29) in both on- and off-hook states with a

resolution of 1 V per bit. The accuracy of these bits is

approximately ±10%. Bits 0 through 6 of this register

indicate the value of the line voltage in 2s compliment

format. Bit 7 of this register indicates the polarity of the

tip/ring voltage.

If the INTE bit (Register 2) and the POLM bit (Register

3) are set, a hardware interrupt is generated on the

AOUT/INT pin when bit 7 of the LVS register changes

00000

Insufficient line current for normal

operation. Use the DOD bit (Register 19,

bit 1) to determine if a line is connected.

00100

11111

Minimum line current for normal operation.

Loop current is greater than 127 mA. An

overcurrent situation may exist.

5.9. Off-Hook

state. The edge-triggered interrupt is cleared by writing The communication system generates an off-hook

0 to the POLI bit (Register 4). The POLI bit is set each command by applying a logic 0 to the OFHK pin or by

time bit 7 of the LVS register changes state and must be setting the OH bit (Register 5, bit 0).The OFHK pin must

written to 0 to clear it.

be enabled by setting the OHE bit (Register 5, bit 1).

The polarity of the OFHK pin is selected by the OPOL

bit (Register 5, bit 4). With OFHK asserted, the system

is in an off-hook state.

The default state of the LVS register forces the LVS bits

to 0 when the line voltage is 3 V or less. The LVFD bit

(Register 31, bit 0) disables the force-to-zero function

and allows the LVS register to display non-zero values The off-hook state seizes the line for incoming/outgoing

of 3 V and below. This register might display calls and also can be used for pulse dialing. With OFHK

unpredictable values at line voltages between 0 to 2 V. deasserted, negligible dc current flows through the

At 0 V, the LVS register displays all 0s.

5.8.2. Loop Current Measurement

When the Si3056 is off-hook, the LCS2[7:0] and

LCS[4:0] bits measure loop current in 1.1 mA/bit and

3.3 mA/bit resolution respectively. These bits enable

hookswitch. When the OFHK pin is asserted, the

hookswitch transistor pair, Q1 and Q2, turn on. This

applies a termination impedance across TIP and RING

and causes dc loop current to flow. The termination

impedance has an ac and dc component.

Possible Overload

30

25

20

LCS

BITS

15

10

5

0

3.3 6.6 9.9 13.2 16.5 19.8 23.1 26.4 29.7 33 36.3 39.6 42.9 46.2 49.5 52.8

59.1 62.7

69.3 72.6 75.9

79.2 82.5 85.8 89.1 92.4 95.7 99 102.3

Loop ⁵C^6.u¹rrent (m⁶A⁶)

127

Figure 19. Typical Loop Current LCS Transfer Function

26

Rev. 1.05

Si3056

Si3018/19/10

Several events occur in the DAA when the OFHK pin is Registers 43 and 44 contain the line current/voltage

asserted or the OH bit is set. There is a 250 µs latency threshold interrupt. This interrupt will trigger when either

to allow the off-hook command to be communicated to the measured line voltage or current in the LVS or LCS2

the line-side device. Once the line-side device goes off- registers, as selected by the CVS bit (Register 44, bit 2),

hook, an off-hook counter forces a delay for line crosses the threshold programmed into the CVT[7:0]

transients to settle before transmission or reception bits. An interrupt can be programmed to occur when the

occurs. This off-hook counter time is controlled by the measured value rises above or falls below the

FOH[1:0] bits (Register 31, bits 6:5). The default setting threshold. Only the magnitude of the measured value is

for the off-hook counter time is 128 ms, but can be used to compare to the threshold programmed into the

adjusted up to 512 ms or down to either 64 or 8 ms.

CVT[7:0] bits, and thus only positive numbers should be

used as a threshold. This line current/voltage threshold

interrupt is only available with the Si3019 line-side

device.

After the off-hook counter has expired, a resistor

calibration is performed for 17 ms. This allows circuitry

internal to the DAA to adjust to the exact conditions

present at the time of going off-hook. This resistor

calibration can be disabled by setting the RCALD bit

(Register 25, bit 5).

5.11. DC Termination

The DAA has programmable settings for dc impedance,

minimum operational loop current, and TIP/RING

voltage. The dc impedance of the DAA is normally

represented with a 50 Ω slope as shown in Figure 20,

but can be changed to an 800 Ω slope by setting the

DCR bit. This higher dc termination presents a higher

resistance to the line as loop current increases.

.

After the resistor calibration is performed, an ADC

calibration is performed for 256 ms. This calibration

helps to remove offset in the A/D sampling the

telephone line. This ADC calibration can be disabled by

setting the CALD bit (Register 17, bit 5). See

“5.29.Calibration” on page 39. for more information on

automatic and manual calibration.

®

FCC DCT Mode

12

Silicon Laboratories recommends that the resistor and

the ADC calibrations not be disabled except when a fast

response is needed after going off-hook, such as when

responding to a Type II caller-ID signal. See “5.21.Caller

ID” on page 32.

11

10

9

To calculate the total time required to go off-hook and

start transmission or reception, the digital filter delay

(typically 1.5 ms with the FIR filter) should be included

in the calculation.

8

7

5.10. Interrupts

6

The AOUT/INT pin can be used as a hardware interrupt

pin by setting the INTE bit (Register 2, bit 7). When this

bit is set, the call progress output function (AOUT) is not

available. The default state of this interrupt output pin is

active low, but active high operation can be enabled by

setting the INTP bit (Register 2, bit 6). This pin is an

open-drain output when the INTE bit is set, and requires

a 4.7 kΩ pullup or pulldown for correct operation. If

multiple INT pins are connected to a single input, the

combined pullup or pulldown resistance should equal

4.7 kΩ. Bits 7–2, and 0 in Register 3 and bit 1 in

Register 44 can be set to enable hardware interrupt

sources. When one or more of these bits are set, the

AOUT/INT pin becomes active and stays active until the

interrupts are serviced. If more than one hardware

interrupt is enabled in Register 3, software polling

determines the cause of the interrupts. Register 4 and

bit 3 of Register 44 contain sticky interrupt flag bits.

Clear these bits after being set to service the interrupt.

.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11

Loop Current (A)

Figure 20. FCC Mode I/V Characteristics,

DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 0

For applications that require current limiting per the

TBR21 standard, the ILIM bit can be set to select this

mode. In the current limiting mode, the dc I/V curve is

changed to a 2000 Ω slope above 40 mA, as shown in

Figure 21. The DAA operates with a 50 V, 230 Ω feed,

which is the maximum line feed specified in the TBR21

standard.

Rev. 1.05

27

Si3056

Si3018/19/10

Table 17. AC Termination Settings for the Si3010

and Si3018 Line-Side Devices

TBR21 DCT Mode

45

40

35

30

25

20

15

10

5

ACT ACT2

AC Termination

0

Real, nominal 600 Ω termination that sat-

isfies the impedance requirements of

FCC part 68, JATE, and other countries.

1

0

1

Complex impedance that satisfies global

impedance requirements.

Complex impedance that satisfies global

impedance requirements EXCEPT New

Zealand. Achieves higher return loss for

countries requiring complex ac termina-

tion. [220 Ω + (820 Ω || 120 nF) and

220 Ω + (820 Ω || 115 nF)]

.015 .02 .025 .03 .035 .04 .045 .05 .055 .06

Loop Current (A)

Figure 21. TBR21 Mode I/V Characteristics,

DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 1

The MINI[1:0] bits select the minimum operational loop

current for the DAA, and the DCV[1:0] bits adjust the

DCT pin voltage, which affects the TIP/RING voltage of

the DAA. These bits permit important trade-offs for the

system designer. Increasing the TIP/RING voltage

provides more signal headroom, while decreasing the

TIP/RING voltage allows compliance to PTT standards

in low-voltage countries such as Japan. Increasing the

minimum operational loop current above 10 mA also

increases signal headroom and prevents degradation of

the signal level in low-voltage countries.

Finally, Australia has separate dc termination

requirements for line seizure versus line hold. Japan

mode may be used to satisfy both requirements.

However, if a higher transmit level for modem operation

is desired, switch to FCC mode 500 ms after the initial

off-hook. This satisfies the Australian dc termination

requirements.

1

Complex impedance for use in New

Zealand. [370 Ω + (620 Ω || 310 nF)]

Table 18. AC Termination Settings for the

Si3019 Line-Side Device

ACIM[3:0]

0000

AC Termination

600 Ω

900 Ω

0001

0010

270 Ω + (750 Ω || 150 nF) and 275 Ω

+ (780 Ω || 150 nF)

0011

220 Ω + (820 Ω || 120 nF) and

220 Ω + (820 Ω || 115 nF)

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

370 Ω + (620 Ω || 310 nF)

320 Ω + (1050 Ω || 230 nF)

370 Ω + (820 Ω || 110 nF)

275 Ω + (780 Ω || 115 nF)

120 Ω + (820 Ω || 110 nF)

350 Ω + (1000 Ω || 210 nF)

200 Ω + (680 Ω || 100 nF)

600 Ω + 2.16 µF

5.12. AC Termination

The Si3056 has four ac termination impedances with

the Si3018 line-side device and sixteen ac termination

impedances with the Si3019 line-side device. The ACT

and ACT2 bits select the ac impedance on the Si3018

line-side device. The ACIM[3:0] bits select the ac

impedance on the Si3019. The available ac termination

settings are listed for the line-side devices in Tables 17

and 18.

The most widely used ac terminations are available as

register options to satisfy various global PTT

requirements. The real 600 Ω impedance satisfies the

requirements of FCC part 68, JATE, and many other

countries. The 270 Ω+ (750 Ω || 150 nF) satisfies the

requirements of TBR21 (ACT = 0, ACT = 1, or ACIM

[3:0] = 0010).

900 Ω + 1 µF

900 Ω + 2.16 µF

600 Ω + 1 µF

Global complex impedance

28

Rev. 1.05

Si3056

Si3018/19/10

There are two selections that are useful for satisfying setting the RPOL bit (Register 14, bit 1). This pin is a

non-standard ac termination requirements. The 350 Ω + standard CMOS output. If multiple RGDT pins are

(1000 Ω || 210 nF) impedance selection is the ANSI/ connected to a single input, the combined pullup or

EIA/TIA 464 compromise impedance network for trunks. pulldown resistance should equal 4.7 kΩ.

The last ac termination selection, ACIM[3:0] = 1111, is

designed to satisfy minimum return loss requirements

for every country in the world that requires a complex

termination. For any of the ac termination settings, the

programmable hybrid can be used to further reduce

near-end echo. See “5.13.Transhybrid Balance” for

more details.

When the RFWE bit is 0, the RGDT pin is asserted

when the ring signal is positive, which results in an

output signal frequency equal to the actual ring

frequency. When the RFWE bit is 1, the RGDT pin is

asserted when the ring signal is positive or negative.

The output then appears to be twice the frequency of

the ring waveform.

The second method to monitor ring detection uses the

ring detect bits (RDTP, RDTN, and RDT). The RDTP

and RDTN behavior is based on the RNG1-RNG2

voltage. When the signal on RNG1-RNG2 is above the

positive ring threshold, the RDTP bit is set. When the

signal on RNG1-RNG2 is below the negative ring

threshold, the RDTN bit is set. When the signal on

RNG1-RNG2 is between these thresholds, neither bit is

set.

The RDT behavior is also based on the RNG1-RNG2

voltage. When the RFWE bit is 0, a positive ring signal

sets the RDT bit for a period of time. When the RFWE

bit is 1, a positive or negative ring signal sets the RDT

bit.

5.13. Transhybrid Balance

The Si3056 contains an on-chip analog hybrid that

performs the 2- to 4-wire conversion and near-end echo

cancellation. This hybrid circuit is adjusted for each ac

termination setting selected.

The Si3056 also offers a digital filter stage for additional

near-end echo cancellation. For each ac termination

setting selected, the eight programmable hybrid

registers (Registers 45-52) can be programmed with

coefficients to provide increased cancellation of real-

world line anomalies. This digital filter can produce

10 dB or greater of near-end echo cancellation in

addition to the echo cancellation provided by the analog

hybrid circuitry.

The RDT bit acts like a one shot. When a new ring

signal is detected, the one shot is reset. If no new ring

signals are detected prior to the one shot counter

reaching 0, then the RDT bit clears. The length of this

count is approximately 5 seconds. The RDT bit is reset

5.14. Ring Detection

The ring signal is resistively coupled from TIP and RING

to the RNG1 and RNG2 pins. The Si3056 supports

either full- or half-wave ring detection. With full-wave

ring detection, the designer can detect a polarity

reversal of the ring signal. See “5.21.Caller ID” on

page 32. The ring detection threshold is programmable

with the RT bit (Register 16, bit 0). The ring detector

output can be monitored in three ways. The first method

uses the RGDT pin. The second method uses the

register bits, RDTP, RDTN, and RDT (Register 5). The

final method uses the DTX output.

to

0 by an off-hook event. If the RDTM bit

(Register 3, bit 7) is set, a hardware interrupt occurs on

the AOUT/INT pin when RDT is triggered. This interrupt

can be cleared by writing to the RDTI bit

(Register 4, bit 7). When the RDI bit (Register 2, bit 2) is

set, an interrupt occurs on both the beginning and end

of the ring pulse. Ring validation may be enabled when

using the RDI bit.

The third method to monitor detection uses the DTX

data samples to transmit ring data. If the

communications link is active (PDL = 0) and the device

is not off-hook or in on-hook line monitor mode, the ring

data is presented on DTX. The waveform on DTX

depends on the state of the RFWE bit.

The ring detector mode is controlled by the RFWE bit

(Register 18, bit 1). When the RFWE bit is 0 (default

mode), the ring detector operates in half-wave rectifier

mode. In this mode, only positive ring signals are

detected. A positive ring signal is defined as a voltage

greater than the ring threshold across RNG1-RNG2.

Conversely, a negative ring signal is defined as a When RFWE is 0, DTX is –32768 (0x8000) while the

voltage less than the negative ring threshold across RNG1-RNG2 voltage is between the thresholds. When

RNG1-RNG2. When the RFWE bit is 1, the ring detector a ring is detected, DTX transitions to +32767 when the

operates in full-wave rectifier mode. In this mode, both ring signal is positive, then goes back to –32768 when

positive and negative ring signals are detected.

the ring is near 0 and negative. Thus a near square

wave is presented on DTX that swings from –32768 to

+32767 in cadence with the ring signal.

The first method to monitor ring detection output uses

the RGDT pin. When the RGDT pin is used, it defaults

to active low, but can be changed to active high by When RFWE is 1, DTX sits at approximately +1228

Rev. 1.05

29

Si3056

Si3018/19/10

while the RNG1-RNG2 voltage is between the ꢀ Delay period between when the ring signal is

thresholds. When the ring becomes positive, DTX

transitions to +32767. When the ring signal goes near 0,

DTX remains near 1228. As the ring becomes negative,

the DTX transitions to –32768. This repeats in cadence

with the ring signal.

validated and when a valid ring signal is indicated to

accommodate distinctive ringing.

The RNGV bit (Register 24, bit 7) enables or disables

the ring validation feature in normal operating mode and

low-power sleep mode.

To observe the ring signal on DTX, watch the MSB of

the data. The MSB toggles at the same frequency as

the ring signal independent of the ring detector mode.

This method is adequate for determining the ring

frequency.

Ring validation affects the behavior of the RDT status

bit, the RDTI interrupt, the INT pin, and the RGDT pin.

1. When ring validation is enabled, the status bit seen

in the RDT read-only bit (r5.2), represents the

detected envelope of the ring. The ring validation

parameters are configurable so that this envelope

may remain high throughout a distinctive-ring

sequence.

2. The RDTI interrupt fires when a validated ring

occurs. If RDI is zero (default), the interrupt occurs

on the rising edge of RDT. If RDI is set, the interrupt

occurs on both rising and falling edges of RDT.

5.15. Ring Validation

This feature prevents false triggering of a ring detection

by validating the ring frequency. Invalid signals, such as

a line voltage change when a parallel handset goes off-

hook, pulse dialing, or a high-voltage line test are

ignored. Ring validation can be enabled during normal

operation and in low power sleep mode. The external

MCLK signal is required in low power sleep mode for

ring validation.

3. The INT pin follows the RDTI bit with configurable

polarity.

The RGDT pin can be configured to follow the ringing

signal envelope detected by the ring validation circuit by

setting RFWE to 0. If RFWE is set to 1, the RGDT pin

follows an unqualified ring detect one-shot signal

initiated by a ring-threshold crossing and terminated by

a fixed counter timeout of approximately 5 seconds.

(This information is shown in Register 18).

The ring validation circuit operates by calculating the

time between alternating crossings of positive and

negative ring thresholds to validate that the ring

frequency is within tolerance. High and low frequency

tolerances are programmable in the RAS[5:0] and

RMX[5:0] fields. The RCC[2:0] bits define how long the

ring signal must be within tolerance.

Once the duration of the ring frequency is validated by

the RCC bits, the circuitry stops checking for frequency

tolerance and begins checking for the end of the ring

signal, which is defined by a lack of additional threshold

crossings for a period of time configured by the

RTO[3:0] bits. When the ring frequency is first validated,

a timer defined by the RDLY[2:0] bits is started. If the

RDLY[2:0] timer expires before the ring timeout, then

the ring is validated and a valid ring is indicated. If the

ring timeout expires before the RDLY[2:0] timer, a valid

ring is not indicated.

5.16. Ringer Impedance and Threshold

The ring detector in many DAAs is ac coupled to the line

with a large 1 µF, 250 V decoupling capacitor. The ring

detector on the Si3056 is resistively coupled to the line.

This produces a high ringer impedance to the line of

approximately 20 MΩ to meet the majority of country

PTT specifications, including FCC and TBR21.

Several countries including Poland, and South Africa,

may require a maximum ringer impedance that can be

met with an internally synthesized impedance by setting

the RZ bit (Register 16, bit 1).

Ring validation requires five parameters:

Some countries also specify ringer thresholds

differently. The RT bit (Register 16, bit 0) selects

between two different ringer thresholds: 15 V ±10% and

21.5 V ±10%. These two settings satisfy ringer

threshold requirements worldwide. The thresholds are

set so that a ring signal is guaranteed to not be detected

below the minimum, and a ring signal is guaranteed to

be detected above the maximum.

ꢀ

Timeout parameter to place a lower limit on the

frequency of the ring signal on the RAS[5:0] bits

(Register 24). This is measured by calculating the

time between crossings of positive and negative ring

thresholds.

Minimum count to place an upper limit on the

frequency on the RMX[5:0] bits (Register 22).

Time interval over which the ring signal must be the

correct frequency on the RCC[2:0] bits (Register 23).

Timeout period that defines when the ring pulse has

ended based on the most recent ring threshold

crossing.

ꢀ

30

Rev. 1.05

Si3056

Si3018/19/10

enough to excessively reduce the line-derived power

5.17. Pulse Dialing and Spark Quenching

supply of the line-side device.

Pulse dialing results from going off- and on-hook to

generate make and break pulses. The nominal rate is

10 pulses per second. Some countries have strict

specifications for pulse fidelity that include make and

break times, make resistance, and rise and fall times. In

a traditional solid-state dc holding circuit, there are

many problems in meeting these requirements.

The OVL bit (Register 19) can be polled following a

billing tone detection. The OVL bit indicates that the

billing tone has passed when it returns to 0. The BTD

and ROV bits are sticky, and must be written to 0 to be

reset. After the billing tone passes, the DAA initiates an

auto-calibration sequence that must complete before

data can be transmitted or received.

Certain line events, such as an off-hook event on a

parallel phone or a polarity reversal, can trigger the ROV

or the BTD bits. Look for multiple events before

qualifying if billing tones are present. After the billing

tone passes, the DAA initiates an auto-calibration

sequence that must complete before data can be

transmitted or received.

Although the DAA remains off-hook during a billing tone

event, the received data from the line is corrupted when

a large billing tone occurs. If the user wishes to receive

data through a billing tone, an external LC filter must be

added. A manufacturer can provide this filter to users in

the form of a dongle that connects on the phone line

before the DAA. This prevents the manufacturer from

having to include a costly LC filter to support multiple

countries and customers.

The Si3056 dc holding circuit actively controls the on-

hook and off-hook transients to maintain pulse dialing

fidelity.

Spark quenching requirements in countries such as

Italy, the Netherlands, South Africa, and Australia deal

with the on-hook transition during pulse dialing. These

tests provide an inductive dc feed resulting in a large

voltage spike. This spike is caused by the line

inductance and the sudden decrease in current through

the loop when going on-hook. The traditional solution to

the problem is to put a parallel resistive capacitor (RC)

shunt across the hookswitch relay. However, the

capacitor required is large (~1 µF, 250 V) and relatively

expensive. In the Si3056, loop current can be controlled

to achieve three distinct on-hook speeds to pass spark

quenching tests without additional BOM components.

Through settings of four bits in three registers, OHS

(Register 16), OHS2 (Register 31), SQ1 and SQ0 Alternatively, when a billing tone is detected, the system

(Register 59), a slow ramp down of loop current can be software notifies the user that a billing tone has

achieved which induces a delay between the time OH occurred. Notification prompts the user to contact the

bit is cleared and the time the DAA actually goes on- telephone company to disable billing tones or to

hook.

purchase an external LC filter.

Disturbance on the line other than billing tones can also

cause a receive overload. Some conditions may result in

a loop current collapse to a level below the minimum

required operating current of the DAA. When this occurs,

the dropout detect bit (DOD) is set, and an interrupt will

be generated if the dropout detect interrupt mask bit

(DODM) is set.

To ensure proper operation of the DAA during pulse

dialing, disable the automatic resistor calibration that is

performed each time the DAA enters the off-hook state

by setting the RCALD bit (Register 25, bit 5).

5.18. Billing Tone Protection and Receive

Overload

“Billing tones” or “metering pulses” generated by the

Central Office can cause modem connection difficulties.

The billing tone is typically either a 12 or 16 kHz signal

and is sometimes used in Germany, Switzerland, and

South Africa. Depending on line conditions, the billing

tone might be large enough to cause major errors in the

line data. The Si3056 chipset can provide feedback

indicating the beginning and end of a billing tone.

5.19. Billing Tone Filter (Optional)

To operate without degradation during billing tones in

Germany, Switzerland, and South Africa, requires an

external LC notch filter. The Si3056 can remain off-hook

during a billing tone event, but line data is lost in the

presence of large billing tone signals. The notch filter

design requires two notches, one at 12 kHz and one at

16 kHz. Because these components are expensive and

few countries utilize billing tones, this filter is typically

placed in an external dongle or added as a population

option for these countries. Figure 22 shows an example

billing tone filter.

Billing tone detection is enabled with the BTE bit

(Register 17, bit 2). Billing tones less than 1.1 V

on

PK

the line are filtered out by the low pass digital filter on

the Si3056. The ROV bit is set when a line signal is

greater than 1.1 V , indicating a receive overload

PK

condition. The BTD bit is set when a billing tone is large

Rev. 1.05

31

Si3056

Si3018/19/10

5.21. Caller ID

C1

C2

The Si3056 can pass caller ID data from the phone line

to a caller ID decoder connected to the serial port.

5.21.1. Type I Caller ID

Type I Caller ID sends the CID data while the phone is

L1

on-hook.

TIP

In systems where the caller ID data is passed on the

phone line between the first and second rings, utilize the

following method to capture the caller ID data:

1. After identifying a ring signal using one of the

methods described in "5.14.Ring Detection" on page

29, determine when the first ring is complete.

To

From

Line

L2

C3

DAA

RING

2. Assert the ONHM bit (Register 5, bit 3) to enable

caller ID data detection. The caller ID data passed

across the RNG 1/2 pins is presented to the host via

the SDO pin.

Figure 22. Billing Tone Filter

L1 must carry the entire loop current. The series

resistance of the inductors is important to achieve a

narrow and deep notch. This design has more than

25 dB of attenuation at both 12 kHz and 16 kHz.

3. Clear the ONHM bit after the caller ID data is

received.

In systems where the caller ID data is preceded by a

line polarity (battery) reversal, use the following method

to capture the caller ID data:

Table 19. Component Values—Optional Billing

Tone Filters

1. Enable full wave rectified ring detection (RFWE,

Symbol

C1,C2

C3

Value

Register 18, bit 1).

0.027 µF, 50 V, ±10%

2. Monitor the RDTP and RDTN register bits (or the

POLI bit) to identify whether a polarity reversal or

ring signal has occurred. A polarity reversal trips

either the RDTP or RDTN ring detection bits, and

thus the full-wave ring detector must be used to

distinguish a polarity reversal from a ring. The lowest

specified ring frequency is 15 Hz; therefore, if a

battery reversal occurs, the DSP should wait a

minimum of 40 ms to verify that the event observed

is a battery reversal and not a ring signal. This time

is greater than half the period of the longest ring

signal. If another edge is detected during this 40 ms

pause, this event is characterized as a ring signal

and not a battery reversal.

0.01 µF, 250 V, ±10%

L1

3.3 mH, >120 mA, <10 Ω, ±10%

10 mH, >40 mA, <10 Ω, ±10%

L2

The billing tone filter affects the ac termination and

return loss. The global complex ac termination

(ACIM = 1111) passes global return loss specifications

with and without the billing tone filter by at least 3 dB.

5.20. On-Hook Line Monitor

The on-hook line monitor mode allows the Si3056 to

receive line activity when in an on-hook state. A low-

power ADC located on the line-side device digitizes the

signal passed across the RNG1/2 pins and then sends

the signal digitally across the communications link to the

host. This mode is typically used to detect caller ID data

and is enabled by setting the ONHM bit (Register 5,

bit 3). Caller ID data can be gained up or attenuated

using the receive gain control bits in registers 39 and

41.

3. Assert the ONHM bit (Register 5, bit 3) to enable the

caller ID data detection. The caller ID data passed

across the RNG 1/2 pins is presented to the host via

the SDO pin.

4. Clear the ONHM bit after the caller ID data is

received.

5.21.2. Type II Caller ID

Type II Caller ID sends the CID data while the phone is

off-hook and is often referred to as caller ID/call waiting

(CID/CW). To receive the CID data while off-hook, use

the following procedure (see Figure 23):

1. The Caller Alert Signal (CAS) tone is sent from the

Central Office (CO) and is digitized along with the

32

Rev. 1.05

Si3056

Si3018/19/10

line data. The host processor must detect the

presence of this tone.

2. The DAA must then check for another parallel device

on the same line. This is accomplished by briefly

going on-hook, measuring the line voltage, and then

returning to an off-hook state.

f. Set the OH bit to 1 (or drive the OFHK pin to the

active state) to return to an off-hook state. After

returning to an off-hook state and waiting 8 ms

for the off-hook counter, normal data

transmission and reception can proceed. If a

non-compliant parallel device is present, then a

reply tone is not sent by the host tone generator

and the CO does not proceed with sending the

CID data. If all devices on the line are Type II CID

compliant, then the host must mute its upstream

data output to avoid propagation of its reply tone

and the subsequent CID data. After muting its

upstream data output, the host processor should

then return an acknowledgement (ACK) tone to

the CO to request the transmission of the CID

data.

a. Set the CALD bit (Register 17, bit 5) to disable

the calibration that automatically occurs when

going off-hook.

b. Set the RCALD bit (Register 25, bit 5) to disable

the resistor calibration from occurring when

going off-hook.

c. Set the FOH[1:0] bits (Register 31, bits 6:5) to 11

to reduce the off-hook counter time to 8 ms.

d. Clear the OH bit (or drive the OFHK pin to the

inactive state) to put the DAA in an on-hook

state. The RXM bit (Register 19, bit 3) may also

be set to mute the receive path.

3. The CO then responds with the CID data and the

host processor unmutes the upstream data output

and continues with normal operation.

e. Read the LVS bits to determine the state of the

4. The muting of the upstream data path by the host

processor mutes the handset in a telephone

application so the user cannot hear the

line.

If the LVS bits read the typical on-hook line

voltage, then no parallel devices are active on

the line and CID data reception can be

continued.

acknowledgement tone and CID data being sent.

5. The CALD and RCALD bits can be cleared to re-

enable the automatic calibration when going off-

hook. The FOH[1:0] bits also can be programmed to

01 to restore the default off-hook counter time.

Because of the nature of the low-power ADC, the data

presented on SDO could have up to a 10% dc offset.

The caller ID decoder must either use a high pass or a

band pass filter to accurately retrieve the caller ID data.

If the LVS bits read well below the typical on-

hook line voltage, then one or more devices are

present and active on the same line that are not

compliant with Type II CID. Do not continue CID

data reception.

Rev. 1.05

33

Si3056

Si3018/19/10

2

3

4

1

Off-Hook Counter

and Calibration

(402.75 ms nominally)

CAS Tone

Received

LINE

Off-Hook Counter

(8 ms)

On-Hook

Off-Hook

On-Hook

Off-Hook

Ack

FOH[1] Bit

FOH[0] Bit

RCALD Bit

CALD Bit

OH Bit⁶

Notes:

1. The off-hook counter and calibrations prevent transmission or reception of data for 402.75 ms (default) for the line

voltage to settle.

2. The caller alert signal (CAS) tone transmits from the CO to signal an incoming call.

3. The device is taken on-hook to read the line voltage in the LVS bits to detect parallel handsets. In this mode, no data

is transmitted on the SDO pin.

4. When the device returns off-hook, the normal off-hook counter is reduced to 8 ms. If the CALD and RCALD bits are

set, then the automatic calibrations are not performed.

5. After allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. If CID data

reception is required, send the appropriate signal to the CO at this time.

6. This example uses the OH bit to put the Si3056 into an off-hook state. The OFHK pin can also be used to accomplish

this. To use the OFHK pin instead of the OH bit, simply enable the OHE bit (Register 5, bit 1) and drive the OFHK pin

low during the preceding sequence. This has the same effect as setting the OH bit.

Figure 23. Implementing Type II Caller ID on the Si3056

34

Rev. 1.05

Si3056

Si3018/19/10

5.22. Overload Detection

5.23. Gain Control

The Si3056 can be programmed to detect an overload The Si3056 supports different gain and attenuation

condition that exceeds the normal operating power settings depending on the line-side device being used.

range of the DAA circuit. To use the overload detection For both devices, gains of 0, 3, 6, 9, and 12 dB can be

feature, the following steps should be followed:

selected for the receive path with the ARX[2:0] bits. The

receive path can also be muted with the RXM bit.

Attenuations of 0, 3, 6, 9, and 12 dB can also be

selected for the transmit path with the ATX[2:0] bits. The

transmit path also can be muted with the TXM bit

(Register 15).

When using the Si3019 line-side device, the Si3056

provides even more flexible gain and attenuation

settings. The TXG2 and RXG2 bits (registers 38–39)

enable gain or attenuation in 1 dB increments up to

15 dB for the transmit and receive paths. The TGA2 and

RGA2 bits select either gain or attenuation for these

registers. The TXG3 and RXG3 bits (registers 40–41)

enable gain or attenuation in 0.1 dB increments up to

1.5 dB for the transmit and receive paths. The TGA3

and RGA3 bits select either gain or attenuation for these

registers. These additional gain/attenuation registers

are active only when the ARX[2:0] and ATX[2:0] bits are

set to all 0s.

1. Set the OH bit (Register 5, bit 0) to go off-hook, and

wait 25 ms to allow line transients to settle.

2. Enable overload detection by then setting the OPE

bit high (Register 17, bit 3).

If the DAA then senses an overload situation, it

automatically presents an 800 Ω impedance to the line

to reduce the hookswitch current. At this time, the DAA

also sets the OPD bit (Register 19, bit 0) to indicate that

an overload condition exists. The line current detector

within the DAA has a threshold that is dependant upon

the ILIM bit (Register 26). When ILIM = 0, the overload

detection threshold equals 160 mA. When ILIM = 1, the

overload detection threshold equals 60 mA. The OPE

bit should always be cleared before going off-hook.

DAC

ACT

TX

Analog

Hybrid

To

Link

CO

Si3056

ADC

Figure 24. Line-Side Device Signal Flow Diagram

IIRE

TXG3

TXG2

Digital

TXA2

SDI

TXA3

Filter

1 dB

Attenuation

Steps

1 dB

Gain

0.1 dB

Gain/ATT

Steps

To

Digital

Hybrid

Line-side

Device

Link

0.1 dB

1 dB

Gain

Gain/ATT

Steps

Attenuation

Steps

IIRE

Digital

Filter

RXG3

RXA3

RXG2

RXA2

SDO

Figure 25. Si3056 Signal Flow Diagram

Rev. 1.05

35

Si3056

Si3018/19/10

N (Register 8) and M (Register 9) are 8-bit unsigned

values. F is the frequency of the clock provided to

5.24. Filter Selection

MCLK

the MCLK pin.

The Si3056 supports additional filter selections for the

receive and transmit signals as defined in Table 11 and

Table 12 on page 15. The IIRE bit (Register 16, bit 4)

selects between the IIR and FIR filters. The IIR filter

Table 20 lists several standard crystal oscillator rates

that can be supplied to MCLK. This list represents a

sample of MCLK frequency choices. Many others are

possible.

provides

a

shorter, but non-linear, group delay

alternative to the default FIR filter and only operates

with an 8 kHz sample rate. Also, on the Si3019 line-side After PLL1 is programmed, the SRC[3:0] bits can

device, the FILT bit (Register 31, bit 1) selects a –3 dB achieve the standard modem sampling rates with a

low frequency pole of 5 Hz when cleared and 200 Hz single write to Register 7. See "Register 7.Sample Rate

when set. The FILT bit affects the receive path only.

Control" on page 54.

When programming the registers of the clock generator,

the order of register writes is important. For PLL1

updates, N (Register 8, bits 7:0) must be written first,

then immediately followed by a write to M (Register 9,

bits 7:0).

The values shown in Table 20 satisfy the preceding

equation. However, when programming the registers for

N and M, the value placed in these registers must be

one less than the value calculated from the equations.

For example, with an MCLK of 46.08 MHz, the values

placed in the N and M registers are 0x0Dh and 0x1Fh,

respectively.

5.25. Clock Generation

The Si3056 has an on-chip clock generator. Using a

single MCLK input frequency, the Si3056 generates all

the desired standard modem sample rates.

The clock generator consists of two phase-locked loops

(PLL1 and PLL2) that achieve the desired sample

frequencies. Figure 26 illustrates the clock generator.

The architecture of the dual PLL scheme provides fast

lock time on initial start-up, fast lock time when

changing modem sample rates, high noise immunity,

and can change modem sample rates with a single

register write. Many MCLK frequencies between

1 and 60 MHz are supported. MCLK should be from a

clean source, preferably directly from a crystal with a

constant frequency and no dropped pulses.

In serial mode 2 (refer to the “5.26.Digital Interface”

section), the Si3056 operates as a slave device. The

clock generator is configured based on the SRC register

to generate the required internal clock frequencies. In

this mode, PLL2 is powered-down. For further details of

slave mode operation, see "5.27.Multiple Device

Support" on page 38.

Table 20. MCLK Examples

MCLK (MHz)

1.8432

N

3

1

M

160

24

16

12

32

256

80

8

4.0960

6.1440

8.1920

9.2160

1

3

10.3680

11.0592

12.288

27

9

5.25.1. Programming the Clock Generator

As shown in Figure 26, PLL1 must output a clock equal

to 98.304 MHz (F

). The F

is determined by

BASE

1

programming the following registers:

14.7456

18.4320

24.5760

25.8048

44.2368

46.0800

47.9232

56.0000

3

20

16

4

80

20

32

80

36

ꢀ

Register 8: PLL1 N[7:0] divider.

Register 9: PLL1 M[7:0] divider.

ꢀ

The main design consideration is the generation of a

base frequency, defined as follows:

1

21

9

F

_MCLK× M

----------------------------

F

=

= 98.304 MHz

BASE

N

15

39

35

36

Rev. 1.05

Si3056

Si3018/19/10

5.25.2. PLL Lock Times

for the required initial sample rate, typically 7200 Hz.

Rate changes are made by writing to SRC[3:0]

(Register 7, bits 3:0).

The Si3056 changes sample rates quickly. However,

lock time varies based on the programming of the clock

generator. The following relationships describe the The final design consideration for the clock generator is

boundaries on PLL locking time:

the update rate of PLL1. The following criteria must be

satisfied for the PLLs to remain stable:

PLL1 lock time < 1 ms

PLL2 lock time 100 µs to 1 ms

®

F

For

modem

designs,

Silicon

Laboratories

MCLK

-------------------

F

=

≥ 144 kHz

UP1

recommends that PLL1 be programmed during

initialization. No further programming of PLL1 is

necessary. The SRC[3:0] register can be programmed

N

where F

is shown in Figure 26.

UP1

1

0

SCLK

F_UP1

98.304 MHz

MCLK

DIV

PLL1

DIV

3

32.768 MHz

DIV

N2

PLL2

DIV

16

8-bit

DIV

M2

DIV

8-bit

Slave

0

1

0

1

N1

M1

Decoder

SRATE

Figure 26. Update Rate of PLL1

In serial mode 0 or 1, the Si3056 operates as a master,

where the master clock (MCLK) is an input, the serial

data clock (SCLK) is an output, and the frame sync

signal (FSYNC) is an output. The MCLK frequency and

the value of the sample rate control registers 7, 8, and 9

determine the sample rate (Fs). The serial port clock,

SCLK, runs at 256 bits per frame, where the frame rate

is equivalent to the sample rate. See "5.25.Clock

Generation" on page 36 for details on programming

sample rates.

5.26. Digital Interface

The Si3056 has two serial interface modes that support

most standard modem DSPs. The M0 and M1 mode

pins select the interface mode. The key difference

between these two serial modes is the operation of the

FSYNC signal. Table 21 summarizes the serial mode

definitions.

Table 21. Serial Modes

The Si3056 transfers 16- or 15-bit telephony data in the

primary timeslot and 16-bit control data in the secondary

timeslot. Figures 27 and 28 show the relative timing of

the serial frames. Primary frames occur at the frame

rate and are always present. To minimize overhead in

the external DSP, secondary frames are present only

when requested.

Mode M1 M0

Description

FSYNC frames data

0

1

2

3

0 0

0 1

1 0

1 1

FSYNC pulse starts data frame

Slave mode

Reserved

Two methods exist for requesting a secondary frame to

transfer control information. The default powerup mode

The digital interface consists of a single, synchronous uses the LSB of the 16-bit transmit (TX) data word as a

serial link that communicates both telephony and flag to request a secondary transfer. Only 15-bit TX data

control data.

is transferred, which results in a small loss of SNR but

Rev. 1.05

37

Si3056

Si3018/19/10

provides software control of the secondary frames. As frame communication must be requested via software in

an alternative method, the FC pin can serve as a the LSB of the transmit (TX) data word.

hardware flag for requesting a secondary frame. The

external DSP can turn on the 16-bit TX mode by setting

the SB bit (Register 1, bit 0). In the 16-bit TX mode, the

hardware FC pin must be used to request secondary

transfers.

Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be

supported on the serial bus. For each slave, the Si3056

generates an FSYNC to the DSP. In daisy-chain mode,

the polarity of the ring signal can be controlled by bit 1

(RPOL). When RPOL = 1, the ring detect signal (now an

Figures 29 and 30 illustrate the secondary frame read output on the FC/RGDT pin) is active high.

cycle and write cycle, respectively. During a read cycle,

the R/W bit is high and the 7-bit address field contains

the address of the register to be read. The contents of

the 8-bit control register are placed on the SDO signal.

During a write cycle, the R/W bit is low and the 7-bit

address field contains the address of the register to be

written. The 8-bit data to be written immediately follows

the address on SDI. Only one register can be read or

written during each secondary frame. See "6.Control

Registers" on page 48 for the register addresses and

functions.

The Si3056 supports a variety of codecs and additional

Si3056s. The type of slave codec(s) used is set by the

SSEL[1:0] bits (Register 14, bits 4:3) and determines

the type of signalling used in the LSB of SDO. This

assists the host in isolating which data stream is the

master and which is the slave. If the LSB is used for

signalling, the master device has a unique setting

relative to the slave devices. The DSP can use this

information to determine which FSYNC marks the

beginning of a sequence of data transfers.

The delayed frame sync (FSD) of each device is

supplied as the FSYNC of each subsequent slave

device in the daisy chain. The master Si3056 generates

an FSYNC signal for each device every 16 or 32 SLCK

periods. The delay period is set by FSD (Register 14,

bit 2). Figure 31 on page 43 and Figure 34 on page 46

show the relative timing for daisy chaining operation.

Primary communication frames occur in sequence,

followed by secondary communication frames, if

requested. When writing/reading the master device via

a secondary frame, all secondary frames of the slave

devices also must be written. When writing/reading a

slave device via a secondary frame, the secondary

frames of the master and all other slaves must be

written also. “No operation” writes/reads to secondary

In serial mode 2, the Si3056 operates as a slave device,

where MCLK is an input, SCLK is a no connect, and

FSYNC is an input. In addition, the RGDT/FSD/M1 pin

operates as a delayed frame sync (FSD) and the FC/

RGDT pin operates as ring detect (RGDT). In this

mode, FC operation is not supported. For details on

operating the Si3056 as

a

slave device, see

“5.27.Multiple Device Support” .

5.27. Multiple Device Support

The Si3056 supports the operation of up to seven

additional devices on a single serial interface. Figure 35

shows the typical connection of the Si3056 and one

additional serial voice codec (Si3000).

The Si3056 must be the master in this configuration. frames are accomplished by writing/reading a 0 value to

Configure the secondary codec as a slave device with address 0.

the master’s SCLK used as the MCLK input to the

codec, and the master’s frame sync delay signal (FSD)

used as the codec’s FSYNC input. On powerup, the

Si3056 master does not detect the additional codec on

the serial bus. The FC/RGDT pin is an input, operating

as the hardware control for secondary frames, and the

RGDT/FSD/M1 pin is an output, operating as the active

low ring detection signal. Program the master device for

master/slave mode before enabling the isolation link,

because a ring signal causes a false transition to the

slave device’s FSYNC.

Register 14 provides the necessary control bits to

configure the Si3056 for master/slave operation. Bit 0

(DCE) sets the Si3056 in master/slave mode, also

referred to as daisy-chain mode. When the DCE bit is

set, the FC/RGDT pin becomes the ring detect output

and the RGDT/FSD/M1 pin becomes the frame sync

delay output. When using multiple devices, secondary

If FSD is set for 16 SCLK periods between FSYNCs,

only serial mode 1 can be used. In addition, the slave

devices must delay the tri-state to active transition of

their SDO sufficiently from the rising edge of SCLK to

avoid bus contention.

The Si3056 supports the operation of up to eight Si3056

devices on a single serial bus. The master Si3056 must

be configured in serial mode 1. Configure the slave(s)

Si3056 in serial mode 2. Figure 36 on page 47 shows a

typical master/slave connection using three Si3056

devices.

When in serial mode 2, FSYNC becomes an input,

RGDT/FSD/M1 becomes the delay frame sync output,

and FC/RGDT becomes the ring detection output. The

serial interface runs at the MCLK input frequency fed

from a master device (such as a master Si3056's SCLK

output). To achieve the proper sampling frequency, the

38

Rev. 1.05

Si3056

Si3018/19/10

SRC[3:0] bits (Register 7, bits 3:0) must be The Si3056 also supports an additional powerdown

programmed with the proper sample rate value before mode. When both the PDN (Register 6, bit 3) and PDL

the sampled line data is valid. The SCLK pin of the (Register 6, bit 4) bits are set, the chipset enters a

slave is a no connect in this configuration.

complete powerdown mode and draws negligible

current (deep sleep mode). Turn off the PLL2 before

entering deep sleep mode (i.e., set Register 9 to 0 and

then Register 6 to 0x18). In this mode, the Si3056 is

non-functional. Normal operation is restored by the

same process for taking the DAA out of sleep mode.

The delay between FSYNC input and delayed frame

sync output (RGDT/FSD/M1) is 16 SCLK periods. The

RGDT/FSD/M1 output has a waveform identical to the

FSYNC signal in serial mode 0. In addition, the LSB of

SDO is set to 0 by default for all devices in serial

mode 2.

5.29. Calibration

5.28. Power Management

The Si3056 initiates two auto-calibrations by default

when the device goes off-hook or experiences a loss in

line power. A 17 ms resistor calibration is performed to

allow circuitry internal to the DAA to adjust to the exact

line conditions present at that time. This resistor

calibration can be disabled by setting the RCALD bit

(Register 25, bit 5). A 256 ms ADC calibration is also

performed to remove offsets that might be present in the

on-chip A/D converter which could affect the A/D

dynamic range. The ADC auto-calibration is initiated

after the DAA dc termination stabilizes, and the resistor

calibration completes. Because large variations in line

conditions and line card behavior exist, it could be

beneficial to use manual calibration instead of auto-

calibration.

The Si3056 supports four basic power management

operation modes. The modes are normal operation,

reset operation, sleep mode, and full powerdown mode.

PDN and PDL bits (Register 6) control the power

management modes.

On powerup, or following a reset, the Si3056 is in reset

operation. The PDL bit is set, and the PDN bit is

cleared. The Si3056 is operational, except for the

isolation link. No communication between the Si3056

and line-side device can occur during reset operation.

Bits associated with the line-side device are not valid in

this mode.

In typical applications, the DAA will predominantly be

operated in normal mode. In this mode, the PDL and

PDN bits are cleared. The Si3056 is operational and the

isolation link is passing information between the Si3056

and the line-side device.

Execute manual ADC calibration as close as possible to

256 ms before valid transmit/receive data is expected.

Take the following steps to implement manual ADC

calibration:

The Si3056 supports a low-power sleep mode to

support ring validation and wake-on-ring features. The

clock generator registers 7, 8, and 9 must be

1. The CALD (auto-calibration disable—Register 17) bit

must be set to 1.

programmed with valid, non-zero values and the PDL 2. The MCAL (manual calibration) bit must be toggled

bit must be clear before enabling sleep mode. The PDN

bit must then be set. When the Si3056 is in sleep mode

the MCLK signal must remain active. In low-power

sleep mode with MCLK active, the Si3056 is non-

functional except for the isolation link and the RGDT

signal. To take the Si3056 out of sleep mode, pulse the

reset pin (RESET) low.

to 1 and then 0 to begin and complete the

calibration.

3. The calibration is completed in 256 ms.

5.30. In-Circuit Testing

With the Si3056’s advanced design the designer can

determine system functionality during production line

In summary, the powerdown/up sequence for sleep tests, and during support for end-user diagnostics. Four

mode is as follows:

loopback modes allow thorough coverage of system

components. Four of the test modes require a line-side

power source. Although a standard phone line can be

used, the test circuit in Figure 1 on page 6 is adequate.

In addition, an off-hook sequence must be performed to

connect the power source to the line-side device.

For the start-up loopback test mode, line-side power is

not necessary and no off-hook sequence is required.

The start-up test mode is enabled by default. When the

PDL bit (Register 6, bit 4) is set (the default case), the

line-side is in a powerdown mode and the DSP-side is

in a digital loop-back mode. Data received on SDI

1. Ensure that Registers 7, 8, and 9 have valid non-

zero values, and ensure the PDL bit (Register 6, bit

4) is cleared.

2. Set the PDN bit (Register 6, bit 3).

3. The device is now in sleep mode. MCLK must stay

active.

4. To exit sleep mode, reset the Si3056 by pulsing the

RESET pin.

5. Program registers to desired settings.

Rev. 1.05

39

Si3056

Si3018/19/10

passes through the internal filters and transmitted on When the HBE bit is cleared, this causes a dc offset that

SDO which introduces approximately 0.9 dB of affects the signal swing of the transmit signal. Silicon

®

attenuation on the SDI signal received. The group delay Laboratories recommends that the transmit signal be

of both transmit and receive filters exists between SDI 12 dB lower than normal transmit levels. A lower level

and SDO. Clearing the PDL bit disables this mode and eliminates clipping from the dc offset that results from

the SDO data is switched to the receive data from the disabling the hybrid. It is assumed in this test that the

line-side. When the PDL bit is cleared, the FDT bit line ac impedance is nominally 600 Ω.

(Register 12, bit 6) becomes active, indicating the

successful communication between the line-side and

DSP-side. This can be used to verify that the isolation

link is operational.

The digital data loop-back mode offers a way to input

data on the SDI pin and have the identical data be

output on the SDO pin by bypassing the transmit and

receive filters. Setting the DDL bit (Register 10, bit 0)

enables this mode. No line-side power or off-hook

Note: All test modes are mutually exclusive. If more than one

test mode is enabled concurrently, the results are

unpredictable.

5.31. Exception Handling

The Si3056 provides several mechanisms to determine

if an error occurs during operation. Through the

secondary frames of the serial link, the controlling

systems can read several status bits.

sequence is required for this mode. The digital data The bit of highest importance is the frame detect bit

loopback mode is useful to verify communication (FDT, Register 12, bit 6), which indicates that the

between the host processor/DSP and the DAA.

system-side (Si3056) and line-side devices are

communicating.

The remaining test modes require an off-hook sequence

to operate. The following sequence describes the off- During normal operation, the FDT bit can be checked

hook procedure required for the following test modes:

1. Powerup or reset.

before reading bits for information about the line-side. If

FDT is not set, the following bits related to the line-side

are invalid—RDT, RDTN, RDTP, LCS[4:0], LSID[1:0],

REVB[3:0], LCS2[7:0], LVS[7:0], ROV, BTD, DOD, and

OVL; the RGDT operation is also non-functional.

2. Program the clock generator to the chosen sample

rate.

3. Enable line-side by clearing the PDL bit.

4. Issue an off-hook command.

5. Delay 402.75 ms to allow calibration to occur.

6. Set the desired test mode.

In the communications link loopback mode, the host

sends a digital input test pattern on SDI and receives

that digital test pattern back on SDO. To enable this

mode, set the IDL bit (Register 1, bit 1). In this mode,

the communication link is tested. The digital stream is

delivered across the isolation capacitors, C1 and C2 of

Figure 16 on page 17, to the line-side device and

returned across the same interface. In this mode, the

0.9 dB attenuation and filter group delays also exist.

Following Powerup and reset, the FDT bit is not set

because the PDL bit (Register 6 bit 4) defaults to 1. The

communications link does not operate and no

information about the line-side can be determined. The

user must program the clock generator to a valid

configuration for the system and clear the PDL bit to

activate the communications link. As the system- and

line-side devices are establishing communication, the

system-side device does not generate FSYNC signals.

Establishing communication takes less than 10 ms.

Therefore, if the controlling DSP serial interface is

interrupt driven based on the FSYNC signal, the

controlling DSP does not require a special delay loop to

wait for this event to complete.

The final testing mode, internal analog loopback, allows

the system to test the operation of the transmit and

receive paths through the line-side device and the

external components shown in Figure 16 on page 17. In

this test mode, the host provides a digital test waveform

on SDI. This data passes across the communications

link, is transmitted to and received from the line, passes

back across the communications link, and is presented

to the host on SDO. To enable this mode, clear the HBE

bit (Register 2, bit 1).

The FDT bit also can indicate if the line-side device

executes an off-hook request successfully. If the line-

side device is not connected to a phone line, the FDT bit

remains cleared. The controlling DSP must provide

sufficient time for the line-side to execute the off-hook

request. The maximum time for FDT to be valid

following an off-hook request is 10 ms. If the FDT bit is

high, the LCS[4:0] bits indicate the amount of loop

current flowing. If the FDT fails to be set following an off-

hook request, the PDL bit (Register 6) must be set high

for at least 1 ms to reset the line-side.

40

Rev. 1.05

Si3056

Si3018/19/10

5.32. Revision Identification

With the Si3056 the system designer can determine the revision of the Si3056 and/or the line-side device. The

REVA[3:0] bits (Register 11, bits 3:0) identify the revision of the Si3056. The REVB[3:0] bits (Register 13, bits 3:0)

identify the revision of the line-side device. Table 22 lists revision values for all devices and might contain future

revisions not yet in existence.

Table 22. Revision Values

Revision

Si3056

0001

0010

0011

0100

0101

0110

Si3018

0001

0010

0011

0100

0101

0110

Si3019

0001

0010

0011

0100

0101

0110

Si3010

0001

0010

0011

0100

0101

0110

A

B

C

D

E

F

Communications Frame 1 (CF1)

Secondary

(CF2)

Primary

FSYNC

FC

0

D15 –D1 D0 = 1 (Software FC Bit)

D15 –D1 D0 = 0 (Software FC Bit)

XMT Data

Secondary

XMT Data

SDI

Data

Secondary

Data

RCV Data

SDO

16 SCLKS

128 SCLKS

256 SCLKS

Figure 27. Software FC/RGDT Secondary Request

Rev. 1.05

41

Si3056

Si3018/19/10

Communications Frame 1 (CF1)

(CF2)

Primary

Secondary

Primary

FSYNC

FC

0

D15–D0

Secondary

Data

XMT Data

RCV Data

SDI

Secondary

Data

RCV Data

SDO

16 SCLKS

128 SCLKS

256 SCLKS

Figure 28. Hardware FC/RGDT Secondary Request

FSYNC

(mode 0)

FSYNC

(mode 1)

D15 D14 D13 D12 D11 D10 D9 D8 D7

D0

1

A

SDI

R/W

D7 D6 D5 D4 D3 D2 D1 D0

D

SDO

Figure 29. Secondary Communication Data Format—Read Cycle

42

Rev. 1.05

Si3056

Si3018/19/10

FSYNC

(mode 0)

FSYNC

(mode 1)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

A

D

SDI

R/W

SDO

Figure 30. Secondary Communication Data Format—Write Cycle

Master

Slave 1

Serial Mode 1

Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1

Serial Mode 2

Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1

Primary Frame (Data)

Secondary Frame (Control)

128 SCLKs

Master FSYNC

32 SCLKs

Master FSD/

Slave1 FSYNC

SDI [0]

SDI [15..1]

1

Master

Slave1

Master

Slave1

SDO [0]

SDO[15..1]

1

0

Master

Slave1

Master

Slave1

Comments

Primary frames with secondary frame requested via SDI[0] = 1

Figure 31. Daisy Chaining of a Single Slave (Pulse FSD)

Rev. 1.05

43

Si3056

Si3018/19/10

Master

Slave 1

Serial Mode 1

Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1

Serial Mode 2

Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1

Primary Frame (Data)

Secondary Frame (Control)

128 SCLKs

Master FSYNC

Master FSD/

Slave1 FSYNC

16 SCLKs

SDI [0]

SDI [15..1]

1

Master

Slave1

Master

Slave1

SDO [0]

SDO[15..1]

1

0

Master

Slave1

Master

Slave1

Comments

Primary frames with secondary frame requested via SDI[0] = 1

Figure 32. Daisy Chaining of a Single Slave (Frame FSD)

44

Rev. 1.05

Si3056

Si3018/19/10

Rev. 1.05

45

Si3056

Si3018/19/10

Master

Serial Mode 0

Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1

Slave 1

Serial Mode 2

Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1

Primary Frame (Data)

Secondary Frame (Control)

128 SCLKs

16 SCLKs

Master FSYNC

Master FSD/

Slave1 FSYNC

SDI [0]

SDI [15..1]

1

Master

Slave1

Master

Slave1

SD0 [0]

SD0 [15..1]

1

0

Master

Slave1

Master

Slave1

Comments

Primary frames with secondary frame requested via SDI[0] = 1

Figure 34. Daisy Chaining with Framed FSYNC and Framed FSD

MCLK

Host

SCLK

Si3056

MCLK

SCLK

SDI

SDO

SDI

FSYNC

INT0

FC/RGDT

RGDT/FSD/M1

VCC

M0

47 kΩ

+5 V

47 kΩ

Si3000

SCLK

MCLK

FSYNC

SDI

SDO

Voice

Codec

Figure 35. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem)

46

Rev. 1.05

Si3056

Si3018/19/10

MCLK

Host

SCLK

Si3056—Master

MCLK

SCLK

SDI

SDO

SDI

SDO

FSYNC

INTO

FC/RGDT

RGDT/FSD/M1

VCC

NC

M0

47 kΩ

Si3056—Slave 1

MCLK

SCLK

FSYNC

SDI

SDO

VCC

47 kΩ

RGDT/FSD/M1

M0

Si3056—Slave 2

MCLK

NC SCLK

FSYNC

SDI

SDO

VCC

47 kΩ

RGDT/FSD/M1

M0

Figure 36. Typical Connection for Multiple DAAS

Rev. 1.05

47

Si3056

Si3018/19/10

6. Control Registers

Table 23. Register Summary

Register

1

Name

Bit 7

SR

Bit 6

Bit 5

Bit 4

Bit 3

PWME

Bit 2

Bit 1

IDL

Bit 0

SB

Control 1

PWMM[1:0]

2

3

4

5

Control 2

Interrupt Mask

Interrupt Source

DAA Control 1

INTE

RDTM

RDTI

INTP

ROVM

ROVI

WDTEN

BTDM

BTDI

OPOL

PDL

RDI

LCSOM

LCSOI

RDT

HBE

RXE

POLM

POLI

OH

FDTM

FDTI

RDTP

DODM

DODI

ONHM

PDN

DLCSM

DLCSI

OHE

RDTN

6

DAA Control 2

7

8

Sample Rate Control

PLL Divide N

SRC[3:0]

N[7:0]

9

PLL Divide M

M[7:0]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32–37

38

39

40

41

42

43

DAA Control 3

DDL

DCE

System-Side and Line-Side Revision

Line-Side Device Status

Line-Side Device Revision

Serial Interface Control

TX/RX Gain Control 1

International Control 1

International Control 2

International Control 3

International Control 4

Call Progress Rx Attenuation

Call Progress Tx Attenuation

Ring Validation Control 1

Ring Validation Control 2

Ring Validation Control 3

Resistor Calibration

DC Termination Control

Reserved

Loop Current Status

Line Voltage Status

AC Termination Control

DAA Control 4

Reserved

TX Gain Control 2

RX Gain Control 2

TX Gain Control 3

RX Gain Control 3

Reserved

Line Current/Voltage Threshold

Interrupt

LSID[3:0]

FDT

0

REVA[3:0]

LCS[4:0]

REVB[3:0]

SSEL[1:0]

NSLV[2:0]

FSD

RPOL

ARX[2:0]

RZ

TXM

ACT2²

CALZ

ATX[2:0]

ACT²

RXM

OHS

IIRE

RT

BTD

MCAL

CALD

OPE

BTE

OVL

ROV

RFWE

DOD

OPD

ARM[7:0]

ATM[7:0]

RDLY[1:0]

RDLY[2]

RNGV

RMX[5:0]

RAS[5:0]

RTO[3:0]

RCC[2:0]

RCALS

RCALM

RCALD

MINI[1:0]

RCAL[3:0]

ILIM

DCV[1:0]

DCR

LCS2[7:0]

LVS[7:0]

FULL2¹

ACIM[3:0]¹

FILT¹

FULL¹

FOH[1:0]

OHS2

LVFD¹

TGA2¹

RGA2¹

TGA3¹

RGA3¹

TXG2[3:0]¹

RXG2[3:0]¹

TXG3[3:0]¹

RXG3[3:0]¹

CVT[7:0]¹

CVI¹

HYB1–8[7:0]

44

Line Current/Voltage Threshold

Interrupt Control

Programmable Hybrid Register 1–8

Reserved

CVS¹

CVM¹

GCE

CVP¹

45–52

53–58

59

TB3

SQ1

SQ0

Spark Quenching Control

RG1

Notes:

1. Bit is available for Si3019 line-side device only.

2. Bit is available for Si3010 and Si3018 line-side device only.

48

Rev. 1.05

Si3056

Si3018/19/10

Register 1. Control 1

Bit

D7

SR

D6

D5

D4

D3

D2

D1

IDL

R/W

D0

SB

Name

Type

PWMM[1:0]

R/W

PWME

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

SR

Software Reset.

0 = Enables the DAA for normal operation.

1 = Sets all registers to their reset value.

Note: Bit automatically clears after being set.

6

Reserved Read returns zero.

5:4 PWMM[1:0] Pulse Width Modulation Mode.

Used to select the type of signal output on the call progress AOUT pin.

00 = PWM output is clocked at 16.384 MHz as a delta-sigma data stream. A local density of

1s and 0s tracks the combined transmit and receive signals.

01 = Balanced conventional PWM output signal has high and low portions of the modulated

pulse that are centered on the 16 kHz sample clock.

10 = Conventional PWM output signal returns to logic 0 at regular 32 kHz intervals and rises

at a time in the 32 kHz period proportional to its instantaneous amplitude.

11 = Reserved.

3

PWME

Pulse Width Modulation Enable.

Sums the transmit and receive audio paths and presents it as a CMOS digital-level output of

PWM data. Use the circuit in “Figure 18. AOUT PWM Circuit for Call Progress” .

0 = Pulse width modulation signal for AOUT disabled.

1 = Pulse width modulation signal for call progress analog output (AOUT) enabled.

2

1

Reserved Read returns zero.

IDL

Isolation Digital Loopback.

0 = Digital loopback across the isolation barrier is disabled.

1 = Enables digital loopback mode across the isolation barrier. The line-side device must be

enabled and off hook before setting this mode. This data path includes the TX and RX filters.

0

SB

Serial Digital Interface Mode.

0 = Operation is in 15-bit mode, and the LSB of the data field indicates that a secondary

frame is required.

1 = The serial port is operating in 16-bit mode and requires a secondary frame sync signal,

FC, to initiate control data reads/writes.

Rev. 1.05

49

Si3056

Si3018/19/10

Register 2. Control 2

Bit

D7

D6

D5

D4

WDTEN

R/W

D3

D2

RDI

R/W

D1

D0

Name

Type

INTE

R/W

INTP

R/W

HBE

R/W

RXE

R/W

Reset settings = 0000_0011

Bit

Name

Function

7

INTE

Interrupt Pin Enable.

0 = The AOUT/INT pin functions as an analog output for call progress monitoring purposes.

1 = The AOUT/INT pin functions as a hardware interrupt pin.

6

INTP

Interrupt Polarity Select.

0 = The AOUT/INT pin, when used in hardware interrupt mode, is active low.

1 = The AOUT/INT pin, when used in hardware interrupt mode, is active high.

5

4

Reserved Returns to zero.

WDTEN Watchdog Timer Enable.

When set, this bit can only be cleared by a hardware reset. The watchdog timer monitors

register accesses. If no register accesses occur within a 4 second window, the DAA is put into

an on-hook state. A write of a DAA register restarts the watchdog timer counter. If the

watchdog timer times out, the OH and OHE bits are cleared, placing the DAA into an on-hook

state. Setting the OH bit or setting the OHE bit and asserting the OFHK pin places the DAA

back into an off-hook state.

0 = Watchdog timer disabled.

1 = Watchdog timer enabled.

3

2

Reserved Returns to zero.

RDI

Ring Detect Interrupt Mode.

This bit operates in conjunction with the RDTM and RDTI bits. This bit is selected if one or two

interrupts are generated for every ring burst.

0 = An interrupt is generated at the beginning of every ring burst.

1 = An interrupt is generated at the beginning and end of every ring burst. The interrupt at the

beginning of the ring burst must be serviced (by writing a 0 to the RDTI bit) before the end of

the ring burst for both interrupts to occur.

1

0

HBE

RXE

Hybrid Enable.

0 = Disconnects hybrid in transmit path.

1 = Connects hybrid in transmit path.

Receive Enable.

0 = Receive path disabled.

1 = Enables receive path.

50

Rev. 1.05

Si3056

Si3018/19/10

Register 3. Interrupt Mask

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name RDTM ROVM FDTM BTDM DODM LCSOM DLCSM POLM

Type

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

RDTM

Ring Detect Mask.

0 = A ring signal does not cause an interrupt on the AOUT/INT pin.

1 = A ring signal causes an interrupt on the AOUT/INT pin.

6

5

ROVM

FDTM

Receive Overload Mask.

0 = A receive overload does not cause an interrupt on the AOUT/INT pin.

1 = A receive overload causes an interrupt on the AOUT/INT pin.

Frame Detect Mask.

0 = The communications link achieving frame lock does not cause an interrupt on the AOUT/

INT pin.

1 = The communications link achieving frame lock causes an interrupt on the AOUT/INT pin.

4

3

2

1

0

BTDM

DODM

Billing Tone Detect Mask.

0 = A detected billing tone does not cause an interrupt on the AOUT/INT pin.

1 = A detected billing tone causes an interrupt on the AOUT/INT pin.

Drop Out Detect Mask.

0 = A line supply dropout does not cause an interrupt on the AOUT/INT pin.

1 = A line supply dropout causes an interrupt on the AOUT/INT pin.

LCSOM Loop Current Sense Overload Mask.

0 = An interrupt does not occur when the LCS bits are all 1s.

1 = An interrupt occurs when the LCS bits are all 1s.

DLCSM Delta Loop Current Sense Mask.

0 = An interrupt does not occur when the LCS bits change.

1 = An interrupt does occur when the LCS bits change.

POLM

Polarity Reversal Detect Mask.

Generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity

of TIP and RING was switched.

0 = A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin.

1 = A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin.

Rev. 1.05

51

Si3056

Si3018/19/10

Register 4. Interrupt Source

Bit

Name

Type

D7

RDTI

R/W

D6

ROVI

R/W

D5

FDTI

R/W

D4

BTDI

R/W

D3

DODI LCSOI DLCSI

R/W R/W R/W

D2

D1

D0

POLI

R/W

Reset settings = 0000_0000

Bit Name

Function

7

RDTI Ring Detect Interrupt.

0 = A ring signal is not occurring.

1 = A ring signal is detected. If the RDTM (Register 3) and INTE (Register 2) bits are set a hard-

ware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared. The RDI

bit (Register 2) determines if this bit is set only at the beginning of a ring pulse, or at the end of a

ring pulse as well. This bit should be cleared after clearing the PDL bit (Register 6) because pow-

ering up the line-side device may cause this interrupt to be triggered.

6

5

ROVI Receive Overload Interrupt.

0 = An excessive input level on the receive pin is not occurring.

1 = An excessive input level on the receive pin is detected. If the ROVM and INTE bits are set a

hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it. This bit is

identical in function to the ROV bit (Register 17). Clearing this bit also clears the ROV bit.

FDTI

BTDI

Frame Detect Interrupt.

0 = Frame detect is established on the communications link.

1 = This bit is set when the communications link does not have frame lock. If the FDTM and INTE

bits are set, a hardware interrupt occurs on the AOUT/INT pin. Once set, this bit must be written

to a 0 to be cleared.

4

3

Billing Tone Detect Interrupt.

0 = A billing tone has not occurred.

1 = A billing tone has been detected. If the BTDM and INTE bits are set, a hardware interrupt

occurs on the AOUT/INT pin. This bit must be written to 0 to clear it.

DODI Drop Out Detect Interrupt.

0 = The line-side power supply has not collapsed.

1 = The line-side power supply has collapsed (The DOD bit in Register 19 has fired). If the

DODM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be

written to 0 to be cleared. This bit should be cleared after clearing the PDL bit (Register 6)

because powering as the line-side device can cause this interrupt to be triggered.

2

LCSOI Loop Current Sense Overload Interrupt.

0 = The LCS bits have not reached max value (all ones).

1 = The LCS bits have reached max value. If the LCSOM bit (Register 3) and the INTE bit are

set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to be cleared.

LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent sit-

uation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI inter-

rupt fires, the OPD bit should be checked to determine if an overcurrent situation exists.

52

Rev. 1.05

Si3056

Si3018/19/10

Bit Name

Function

1

DLCSI Delta Loop Current Sense Interrupt

0 = The LCS bits have not changed value.

1 = The LCS bits have changed value; a hardware interrupt occurs on the AOUT/INT pin. This bit

must be written to a 0 to be cleared.

0

POLI

Polarity Reversal Detect Interrupt.

0 = Bit 7 of the LVS register does not change states.

1 = Bit 7 of the LVS register changes from a 0 to a 1, or from a 1 to a 0, indicating the polarity of

TIP and RING is switched. If the POLM and INTE bits are set, a hardware interrupt occurs on the

AOUT/INT pin. To clear the interrupt, write this bit to 0.

Register 5. DAA Control 1

Bit

Name

Type

D7

D6

RDTN RDTP OPOL ONHM

R/W R/W

D5

D4

D3

D2

RDT

R

D1

OHE

R/W

D0

OH

R/W

R

Reset settings = 0000_0000

Bit

7

Name

Reserved Read returns zero.

Function

6

RDTN

RDTP

OPOL

ONHM

Ring Detect Signal Negative.

0 = No negative ring signal is occurring.

1 = A negative ring signal is occurring.

Ring Detect Signal Positive.

0 = No positive ring signal is occurring.

1 = A positive ring signal is occurring.

Off-hook Polarity.

0 = Off-hook pin is active low.

1 = Off-hook pin is active high.

On-Hook Line Monitor.

0 = Normal on-hook mode.

5

4

3

1 = Enables low-power on-hook monitoring mode allowing the host to receive line activity

without going off-hook. This mode is used for caller-ID detection.

2

RDT

Ring Detect.

0 = Reset either 5 seconds after last positive ring is detected or when the system executes an

off-hook. Only a positive ring sets this bit when RFWE = 0. When RFWE = 1, either a positive

or negative ring sets this bit.

1 = Indicates a ring is occurring.

1

0

OHE

OH

Off-hook Pin Enable.

0 = Off-hook pin is ignored.

1 = Enables operation of the off-hook pin.

Off-Hook.

0 = Line-side device on-hook.

1 = Causes the line-side device to go off-hook. This bit operates independently of the OHE bit

and is a logic OR with the off-hook pin when enabled.

Rev. 1.05

53

Si3056

Si3018/19/10

Register 6. DAA Control 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

PDL

R/W

PDN

R/W

Reset settings = 0001_0000

Bit

7:5

4

Name

Reserved Read returns zero.

Function

PDL

Powerdown Line-Side Device.

0 = Normal operation. Program the clock generator before clearing this bit.

1 = Places the line-side device in lower power mode.

3

PDN

Powerdown System-Side Device.

0 = Normal operation.

1 = Powers down the system-side device. A pulse on RESET is required to restore normal

operation.

2:0

Reserved Read returns zero.

Register 7. Sample Rate Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

SRC[3:0]

R/W

Reset settings = 0000_0000

Bit Name

7:4 Reserved Read returns zero.

3:0 SRC[3:0] Sample Rate Control.

Function

Sets the sample rate of the line-side device.

0000 = 7200 Hz

0001 = 8000 Hz

0010 = 8229 Hz

0011 = 8400 Hz

0100 = 9000 Hz

0101 = 9600 Hz

0110 = 10286 Hz

0111 = 12000 Hz

1000 = 13714 Hz

1001 = 16000 Hz

1010–1111 = Reserved

54

Rev. 1.05

Si3056

Si3018/19/10

Register 8. PLL Divide N

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N[7:0]

R/W

Reset settings = 0000_0000 (serial mode 0, 1)

Reset settings = 0001_0011 (serial mode 2)

Bit

Name

Function

7:0

N[7:0]

PLL N Divider.

Contains the (value –1) for determining the output frequency on PLL1.

Register 9. PLL Divide M

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

M[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

M[7:0]

PLL M Divider.

Contains the (value –1) for determining the output frequency on PLL1.

Register 10. DAA Control 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DDL

R/W

Reset settings = 0000_0000

Bit Name

7:1 Reserved Read returns zero.

Function

0

DDL

Digital Data Loopback.

0 = Normal operation.

1 = Audio data received on SDI and loops it back out to SDO before the TX and RX filters.

Outputted data is identical to inputted data.

Rev. 1.05

55

Si3056

Si3018/19/10

Register 11. System-Side and Line-Side Device Revision

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

LSID[3:0]

REVA[3:0]

R

Reset settings = xxxx_xxxx

Bit

Name

LSID[3:0] Line-Side ID Bits.

Function

7:4

These four bits will always read one of the following values depending on which line-side

device is used.

Si3018

Si3019

Si3010

LSID[3:0]

0001

0011

0101

3:0 REVA[3:0] System-Side Revision.

Four-bit value indicating the revision of the system-side device.

Register 12. Line-Side Device Status

Bit

D7

D6

FDT

R

D5

D4

D3

D2

LCS[4:0]

R

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

7

Name

Reserved Read returns zero.

FDT Frame Detect.

Function

6

0 = Indicates the communications link has not established frame lock.

1 = Indicates the communications link frame lock is established.

5

Reserved Read returns zero.

4:0

LCS[4:0] Loop Current Sense.

5-bit value returning the loop current when the DAA is in an off-hook state.

00000 = Loop current is less than required for normal operation.

00100 = Minimum loop current for normal operation.

11111 = Loop current is >127 mA, and a current overload condition may exist.

56

Rev. 1.05

Si3056

Si3018/19/10

Register 13. Line-Side Device Revision

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

0

REVB[3:0]

R

Reset settings = xxxx_xxxx

Bit

7

Name

Reserved Read returns zero.

This bit always reads a zero.

Function

6

0

5:2 REVB[3:0] Line-Side Device Revision.

Four-bit value indicating the revision of the line-side device.

1:0 Reserved Read returns zero.

Rev. 1.05

57

Si3056

Si3018/19/10

Register 14. Serial Interface Control

Bit

D7

D6

NSLV[2:0]

R/W

D5

D4

SSEL[1:0]

R/W

D3

D2

D1

D0

Name

Type

FSD

R/W

RPOL

R/W

DCE

R/W

Reset settings = 0000_0000 (serial mode 0,1)

Reset settings = 0011_1101 (serial mode 2)

Bit

Name

Function

7:5 NSLV[2:0] Number of Slaves devices.

000 = 0 slaves. Redefines the FC/RGDT and RGDT/FSD pins.

001 = 1 slave device

010 = 2 slave devices

011 = 3 slave devices

100 = 4 slave devices (For four or more slave devices, the FSD bit MUST be set.)

101 = 5 slave devices

110 = 6 slave devices

111 = 7 slave devices

4:3 SSEL[1:0] Slave device select.

00 = 16-bit SDO receive data

01 = Reserved

10 = 15-bit SDO receive data, LSB = 1

11 = 15-bit SDO receive data, LSB = 0

2

FSD

Delayed Frame Sync Control.

0 = Sets the number of SCLK periods between frame syncs to 32.

1 = Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when

Si3056 devices are slaves. For the master Si3056, only serial mode 1 is allowed when this bit

is set.

1

0

RPOL

DCE

Ring Detect Polarity.

0 = The FC/RGDT pin (operating as ring detect) is active low.

1 = The FC/RGDT pin (operating as ring detect) is active high.

Daisy-Chain Enable.

0 = Daisy-chaining disabled.

1 = Enables the Si3056 to operate with slave devices on the same serial bus. The FC/RGDT

signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the

delayed frame sync signal. ALL other bits in this register are ignored if DCE = 0.

58

Rev. 1.05

Si3056

Si3018/19/10

Register 15. TX/RX Gain Control 1

Bit

D7

D6

D5

ATX[2:0]

R/W

D4

D3

D2

D1

ARX[2:0]

R/W

D0

Name

Type

TXM

R/W

RXM

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

TXM

Transmit Mute.

0 = Transmit signal is not muted.

1 = Mutes the transmit signal.

6:4

ATX[2:0] Analog Transmit Attenuation.

000 = 0 dB attenuation

001 = 3 dB attenuation

010 = 6 dB attenuation

011 = 9 dB attenuation

1xx = 12 dB attenuation

Note: Write these bits to zero when using the finer resolution transmit and receive gain/attenuation

registers 38–41 available only with the Si3019 line-side device.

3

RXM

Receive Mute.

0 = Receive signal is not muted.

1 = Mutes the receive signal.

2:0

ARX[2:0] Analog Receive Gain.

000 = 0 dB gain

001 = 3 dB gain

010 = 6 dB gain

011 = 9 dB gain

1xx = 12 dB gain

Note: Write these bits to zero when using the finer resolution transmit and receive gain/attenuation

registers 38–41 available only with the Si3019 line-side device.

Rev. 1.05

59

Si3056

Si3018/19/10

Register 16. International Control 1

Bit

D7

ACT2

RW

D6

D5

D4

D3

D2

D1

RZ

D0

RT

Name

Type

OHS

R/W

ACT

R/W

IIRE

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

ACT2

AC Termination Select 2 (Si3018 line-side device only).

Works with the ACT bit to select one of four ac terminations:

ACT2

ACT

AC Termination

0

1

0

1

0

1

Real, 600 Ω

Global complex impedance

Global complex impedance, except New Zealand

New Zealand complex impedance

The global complex impedance meets minimum return loss requirements in countries that require

a complex ac termination. For improved return loss performance, the other complex impedances

can be used.

6

OHS

On-Hook Speed.

This bit, in combination with the OHS2 bit (Register 31) and the SQ[1:0] bits (Register 59), sets the

amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured

from the time the OH bit is cleared until loop current equals zero.

OHS

OHS2

SQ[1:0]

00

Mean On-Hook Speed

0

1

0

1

X

Less than 0.5 ms

00

3 ms ±10% (meets ETSI standard)

26 ms ±10% (meets Australia spark quenching spec)

11

5

4

ACT

IIRE

AC Termination Select. (Si3018 line-side device only).

When the ACT2 bit is cleared, the ACT bit selects the following:

0 = Selects the real ac impedance (600 Ω)

1 = Selects the global complex impedance.

IIR Filter Enable.

0 = FIR filter enabled for transmit and receive filters. See Figures 7–10 on page 16.

1 = IIR filter enabled for transmit and receive filters. See Figures 11–16 on page 17.

3:2

1

Reserved Read returns zero.

RZ

Ringer Impedance.

0 = Maximum (high) ringer impedance.

1 = Synthesized ringer impedance enabled. See "5.16.Ringer Impedance and Threshold" on page

30.

0

RT

Ringer Threshold Select.

This bit is used to satisfy country requirements on ring detection. Signals below the lower level do

not generate a ring detection; signals above the upper level are guaranteed to generate a ring

detection.

RT

0

RT Lower level

13.5 V

RT Upper level

16.5 V

rms

1

19.35 V

23.65 V

rms

60

Rev. 1.05

Si3056

Si3018/19/10

Register 17. International Control 2

Bit

Name

Type

D7

CALZ MCAL CALD

R/W R/W R/W

D6

D5

D4

D3

OPE

R/W

D2

BTE

R/W

D1

ROV

R/W

D0

BTD

R

Reset settings = 0000_0000

Bit

7

Name

CALZ

Function

Clear ADC Calibration.

0 = Normal operation.

1 = Clears the existing calibration data. This bit must be written back to 0 after being set.

Manual ADC Calibration.

6

5

MCAL

CALD

0 = No calibration.

1 = Initiate manual ADC calibration.

ADC Auto-Calibration Disable.

0 = Enable auto-calibration.

1 = Disable auto-calibration.

4

3

Reserved Read returns zero.

OPE

Overload Protect Enable.

0 = Disabled.

1 = Enabled.

The OPE bit should always be cleared before going off-hook.

Billing Tone Detect Enable.

2

BTE

When set, the DAA can detect a billing tone signal on the line and maintain on off-hook state

through the billing tone. If a billing tone is detected, the BTD bit (Register 17) is set to indicate

the event. Writing this bit to zero clears the BTD bit.

0 = Billing tone detection disabled. The BDT bit is not function.

1 = Billing tone detection enabled. The BDT is functional.

Receive Overload.

This bit is set when the receive input has an excessive input level (i.e., receive pin goes below

ground). Writing a zero to this location clears this bit and the ROVI bit (Register 4, bit 6).

0 = Normal receive input level.

1 = Excessive receive input level.

Billing Tone Detected.

1

0

ROV

BTD

This bit is set if a billing tone is detected. Writing a zero to BTE clears this bit.

0 = No billing tone detected.

1 = Billing tone detected.

Rev. 1.05

61

Si3056

Si3018/19/10

Register 18. International Control 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RFWE

R/W

Reset settings = 0000_0000

Bit

7:2

1

Name

Reserved Read returns zero or one.

RFWE

Function

Ring Detector Full-Wave Rectifier Enable.

When RNGV (Register 24) is disabled, this bit controls the ring detector mode and the asser-

tion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow

the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect

one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter time-

out of approximately five seconds.

RNGV

RFWE

RGDT

0

1

0

1

0

1

Half-Wave

Full-Wave

Validated Ring Envelope

Ring Threshold Crossing One-Shot

0

Reserved Read returns zero or one.

62

Rev. 1.05

Si3056

Si3018/19/10

Register 19. International Control 4

Bit

D7

D6

D5

D4

D3

D2

OVL

R

D1

DOD

R

D0

OPD

R

Name

Type

Reset settings = 0000_0000

Bit Name

7:3 Reserved Read returns zero.

Function

2

1

OVL

Receive Overload Detect.

This bit has the same function as ROV in Register 17, but clears itself after the overload is

removed. See “5.18.Billing Tone Protection and Receive Overload” on page 31. This bit is

only masked by the off-hook counter and is not affected by the BTE bit.

0 = Normal receive input level.

1 = Excessive receive input level.

DOD

Recal/Dropout Detect.

When the line-side device is off-hook, it is powered from the line itself. This bit will read 1

when loop current is not flowing. For example, if the line-derived power supply collapses, such

as when the line is disconnected, this bit is set to 1. Additionally, when on-hook and the line-

side device is enabled, this bit is set to 1.

0 = Normal operation.

1 = Line supply dropout detected when off-hook.

0

OPD

Overload Protection Detect.

This bit is used to indicate that the DAA has detected a loop current overload. The detector fir-

ing threshold depends on the setting of the ILIM bit (Register 26).

OPD

ILIM

Overcurrent Threshold

Overcurrent Status

0

1

0

1

0

1

160 mA

60 mA

160 mA

60 mA

No overcurrent condition exists

An overcurrent condition has been detected

Rev. 1.05

63

Si3056

Si3018/19/10

Register 20. Call Progress Receive Attenuation

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

ARM[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

ARM[7:0]

AOUT Receive Path Attenuation.

When decremented from the default setting, these bits linearly attenuate the AOUT

receive path signal used for call progress monitoring. Setting the bits to all 0s mutes the

AOUT receive path.

Attenuation = 20 log(ARM[7:0]/64)

1111_1111 = +12 dB (gain)

0111_1111 = +6 dB (gain)

0100_0000 = 0 dB

0010_0000 = –6 dB (attenuation)

0001_0000 = –12 dB

.

0000_0000 = Mute

Register 21. Call Progress Transmit Attenuation

Bit

Name

Type

D7

D6

D5

D4

ATM[7:0]

R/W

D3

D2

D1

D0

Reset settings = 0000_0000

Bit

7:0

Name

ATM[7:0]

Function

AOUT Transmit Path Attenuation.

When decremented from the default settings, these bits linearly attenuate the AOUT trans-

mit path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT

transmit path.

Attenuation = 20 log(ATM[7:0]/64)

1111_1111 = +12 dB (gain)

0111_1111 = +6 dB (gain)

0100_0000 = 0 dB

0010_0000 = –6 dB (attenuation)

0001_0000 = –12 dB

.

0000_0000 = Mute

64

Rev. 1.05

Si3056

Si3018/19/10

Register 22. Ring Validation Control 1

Bit

D7

D6

D5

D4

D3

D2

RMX[5:0]

R/W

D1

D0

Name

Type

RDLY[1:0]

R/W

Reset settings = 1001_0110

Bit

Name

Function

7:6

RDLY[1:0]

Ring Delay Bits 1 and 0.

These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time

between when a ring signal is validated and when a valid ring signal is indicated.

RDLY[2]

RDLY[1:0]

Delay

0 ms

0

.

00

01

10

256 ms

512 ms

1

11

1792 ms

5:0

RMX[5:0]

Ring Assertion Maximum Count.

These bits set the maximum ring frequency for a valid ring signal within a 10% margin of

error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING

event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the

timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then

the frequency of the ring is too high and the ring is invalidated. The difference between

RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-

ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically

occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/

(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,

f_max], the following equation should be used:

1

--------------------------------------------

RMX[5:0] ≥ RAS[5:0] –

, RMX ≤ RAS

2 × f_max × 2 ms

To compensate for error margin and ensure a sufficient ring detection window, it is recom-

mended that the calculated value of RMX[5:0] be incremented by 1.

Rev. 1.05

65

Si3056

Si3018/19/10

Register 23. Ring Validation Control 2

Bit

D7

RDLY[2]

R/W

D6

D5

D4

D3

D2

D1

RCC[2:0]

R/W

D0

Name

Type

RTO[3:0]

R/W

Reset settings = 0010_1101

Bit

Name

Function

7

RDLY[2]

Ring Delay Bit 2.

This bit, in combination with the RDLY[1:0] bits (Register 22), set the amount of time

between when a ring signal is validated and when a valid ring signal is indicated.

RDLY[2]

RDLY[1:0]

Delay

0 ms

256 ms

512 ms

0

.

00

01

10

.

1

11

1792 ms

6:3

RTO[3:0]

Ring Timeout.

These bits set when a ring signal is determined to be over after the most recent ring thresh-

old crossing.

RTO[3:0]

Ring Timeout

80 ms

128 ms

256 ms

0000

0001

0010

.

1111

1920 ms

2:0

RCC[2:0]

Ring Confirmation Count.

These bits set the amount of time that the ring frequency must be within the tolerances set

by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal.

RCC[2:0]

000

Ring Confirmation Count Time

100 ms

150 ms

200 ms

256 ms

384 ms

512 ms

640 ms

1024 ms

001

010

011

100

101

110

111

66

Rev. 1.05

Si3056

Si3018/19/10

Register 24. Ring Validation Control 3

Bit

D7

D6

D5

D4

D3

RAS[5:0]

R/W

D2

D1

D0

Name

Type

RNGV

R/W

R

Reset settings = 0001_1001

Bit

Name

Function

7

RNGV

Ring Validation Enable.

0 = Ring validation feature is disabled.

1 = Ring validation feature is enabled in both normal operating mode and low-power

mode.

6

Reserved

RAS[5:0]

Reserved and may read either a 1 or 0.

5:0

Ring Assertion Time.

These bits set the minimum ring frequency for a valid ring signal within a 10% margin of