SI3014-FS [SILICON]
Telecom IC,;
| 型号： | SI3014-FS |
| 厂家： | 
SILICON |
| 描述： | Telecom IC, |
| 文件： | 总66页 (文件大小：1755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3034
3.3 V GLOBAL DIRECT ACCESS ARRANGEMENT
Features
Complete DAA includes the following:
Programmable line interface
Clock generation
z
z
z
z
AC termination
Pulse dialing support
Billing tone detection
Overload detection
DC termination
Ring detect threshold
Ringer impedance
3.3 or 5 V power supply
Direct interface to DSPs
84 dB dynamic range TX/RX
paths
Ordering Information
Daisy-chaining for up to eight
Integrated analog front end
See page 61.
devices
(AFE) and 2- to 4-wire hybrid
Greater than 3000 V isolation
Patented isolation technology
Integrated ring detector
Caller ID support
Pin Assignments
Si3021 (SOIC)
Lead-free/RoHS-compliant
Loop current monitor
packages available
1
2
3
4
5
6
7
8
MCLK
FSYNC
SCLK
OFHK
16
15
14
13
12
11
10
9
Applications
RGDT/FSD
M0
V.92 Modems
Set Top Boxes
Fax Machines
V
D
V
A
Voice Mail Systems
SDO
SDI
GND
C1A
M1
Description
FC/RGDT
RESET
AOUT
The Si3034 is an integrated direct access arrangement (DAA) that
provides a programmable line interface to meet global telephone line
interface requirements. Available in two 16-pin small outline packages, it
eliminates the need for an analog front end (AFE), isolation transformer,
relays, opto-isolators, and 2- to 4-wire hybrid. The Si3034 dramatically
reduces the number of discrete components and cost required to achieve
compliance with global regulatory requirements. The Si3034 interfaces
directly to standard modem DSPs.
Si3021 (TSSOP)
1
SDO
SDI
V
D
16
2
3
4
5
6
7
8
SCLK
15
14
13
12
11
10
9
FC/RGDT
RESET
AOUT
M1
FSYNC
MCLK
OFHK
RGDT/FSD
M0
C1A
Functional Block Diagram
GND
V
A
Si3014 (SOIC or TSSOP)
S i3021
S i3014
QE2
DCT
IGND
C1B
FILT2
FILT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M C L K
S C L K
R X
RX
F IL T
F IL T 2
R E F
D C T
V R E G
F S Y N C
S D I
D ig ita l
In te rfa ce
H yb rid
a n d
D C
REXT
REXT2
REF
S D O
RNG1
RNG2
QB
T e rm in a tio n
F C /R G D T
V R E G 2
R E X T
R E X T 2
Iso la tio n
In te rfa ce
Iso la tio n
In te rfa ce
VREG2
VREG
R G D T /F S D
O F H K
QE
R N G 1
R N G 2
Q B
C o n tro l
In te rfa ce
R in g D e te ct
O ff-H o o k
M O D E
R E S E T
Q E
Q E 2
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
A O U T
Rev. 2.02 8/05
Copyright © 2005 by Silicon Laboratories
Si3034
Si3034
2
Rev. 2.02
Si3034
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.2. On-Chip Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.3. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.5. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.6. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.7. DC Termination Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.8. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.9. Ringer Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.10. DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.11. Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.12. Billing Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.13. Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.14. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.15. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.16. Loop Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.17. Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.18. Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.19. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.20. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.21. Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.22. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.23. Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.24. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.25. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.26. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.27. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.28. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Appendix A—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Appendix B—CISPR22 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
7. Pin Descriptions: Si3021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
8. Pin Descriptions: Si3014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
9. Ordering Guide1,2,3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
10. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11. Package Outline: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Rev. 2.02
3
Si3034
1. Electrical Specifications
Table 1. Recommended Operating Conditions
1
2
2
Parameter
Symbol
Test Condition
Min
Typ
25
Max
Unit
°C
V
Ambient Temperature
Si3021 Supply Voltage, Analog
T
F-Grade or K-Grade
0
70
A
V
4.75
3.0
5.0
5.25
5.25
A
3
Si3021 Supply Voltage, Digital
V
3.3/5.0
V
D
Notes:
1. The Si3034 specifications are guaranteed when the typical application circuit (including component tolerance) and any
Si3021 and any Si3014 are used. See "2. Typical Application Schematic‚" on page 15.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. The digital supply, VD, can operate from either 3.3 V or 5.0 V. The Si3021 supports interface to 3.3 V logic when
operating from 3.3 V and applies to both the serial port and the digital signals RGDT/FSD, OFHK, RESET, M0, and M1.
4
Rev. 2.02
Si3034
Table 2. Loop Characteristics
(VD = 3.3 to 5.25 V, TA = 0 to 70 °C for F-Grade or K-Grade, See Figure 1)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Termination Voltage
V
V
V
V
V
V
V
V
I = 20 mA, ACT = 1
DCT = 11 (TBR21)
—
—
7.5
14.5
40
V
TR
TR
TR
TR
TR
TR
TR
TR
L
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
I = 42 mA, ACT 1
—
—
40
—
11
—
12
—
—
—
—
—
—
—
V
V
V
V
V
V
V
L
DCT 11 (TBR21)
I = 50 mA, ACT = 1
L
DCT = 11 (TBR21)
I = 60 mA, ACT = 1
—
L
DCT = 11 (TBR21)
I = 20 mA, ACT = 0
6.0
—
L
DCT = 01 (Japan)
I = 100 mA, ACT = 0
L
DCT = 01 (Japan)
I = 20 mA, ACT = 0
7.5
—
L
DCT = 10 (FCC)
I = 100 mA, ACT = 0
L
DCT = 10 (FCC)
On Hook Leakage Current
Operating Loop Current
Operating Loop Current
DC Ring Current
I
I
I
V
= –48V
TR
—
13
13
—
—
11
17
15
—
—
—
—
1
120
60
20
—
µA
mA
mA
µA
LK
LP
LP
FCC/Japan Modes
TBR21 Mode
w/o Caller ID
with Caller ID
RT = 0
—
—
DC Ring Current
450
—
µA
1
Ring Detect Voltage
V
V
22
33
68
0.2
—
V
RD
RD
RMS
RMS
1
Ring Detect Voltage
RT = 1
—
V
Ring Frequency
F
—
Hz
R
2
2
Ringer Equivalence Number
Ringer Equivalence Number
Notes:
REN
REN
w/o Caller ID
with Caller ID
—
0.8
1. The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected
above the maximum.
2. C15, R14, Z2, and Z3 not installed. See "5.9. Ringer Impedance‚" on page 24.
TIP
+
600 Ω
IL
VTR
Si3014
RING
10 µF
–
Figure 1. Test Circuit for Loop Characteristics
Rev. 2.02
5
Si3034
Table 3. DC Characteristics, VD = 5 V
(VD = 4.75 to 5.25 V, TA = 0 to 70 °C for F-Grade or K-Grade)
Parameter
Symbol
Test Condition
Min
3.5
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Power Supply Current, Analog
V
IH
V
—
0.8
—
V
IL
V
I = –2 mA
3.5
—
—
V
OH
O
V
I = 2 mA
—
0.4
10
V
OL
O
I
–10
—
—
µA
mA
mA
mA
mA
L
A
D
I
I
V pin
0.3
14
1.3
.04
1
A
1
Power Supply Current, Digital
V pin
—
18
D
1
Total Supply Current, Sleep Mode
I + I
PDN = 1, PDL = 0
PDN = 1, PDL = 1
—
2.5
0.5
A
D
1,2
Total Supply Current, Deep Sleep
I + I
—
A
D
Notes:
1. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
2. RGDT is not functional in this state.
Table 4. DC Characteristics, VD = 3.3 V
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for F-Grade or K-Grade)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Power Supply Current, Analog
V
IH
V
—
0.8
—
V
IL
V
I = –2 mA
2.4
—
—
V
OH
O
V
I = 2 mA
—
0.35
10
V
OL
O
I
–10
—
—
µA
mA
mA
mA
mA
V
L
A
D
1,2
I
I
V pin
0.3
9
1
A
3
Power Supply Current, Digital
Total Supply Current, Sleep Mode
V pin
—
12
D
3
I + I
PDN = 1, PDL = 0
PDN = 1, PDL = 1
Charge Pump On
—
1.2
.04
4.6
2.5
0.5
5.0
A
D
3,4
Total Supply Current, Deep Sleep
I + I
—
A
D
1,5
Power Supply Voltage, Analog
V
4.3
A
Notes:
1. Only a decoupling capacitor should be connected to VA when the charge pump is on.
2. There is no IA current consumption when the internal charge pump is enabled and only a decoupling capacitor is
connected to the VA pin.
3. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
4. RGDT is not functional in this state.
5. The charge pump is recommended to be used only when VD < 4.5 V. When the charge pump is not used, VA should be
applied to the device before VD is applied on power up if driven from separate supplies.
6
Rev. 2.02
Si3034
Table 5. AC Characteristics
(VD = 3.0 to 5.25 V, TA = 0 to 70 °C for F-Grade or K-Grade, see 16 on page 15)
Parameter
Symbol
Test Condition
Min
7.2
36
—
Typ
—
—
0
Max
Unit
1
Sample Rate
Fs
Fs = F
/5120
11.025 KHz
PLL2
1
z
PLL1 Output Clock Frequency
F
F
= F
M1/N1
58
—
—
—
—
—
MHz
Hz
PLL1
PLL1
MCLK
Transmit Frequency Response
Receive Frequency Response
Low –3 dBFS Corner
Low –3 dBFS Corner
—
5
Hz
2
Transmit Full Scale Level
V
—
1
V
PEAK
FS
FS
2,3
Receive Full Scale Level
V
—
1
V
PEAK
4
Dynamic Range
DR
ACT = 0, DCT = 10 (FCC)
—
82
dB
I = 100 mA
L
4
Dynamic Range
DR
ACT = 0, DCT = 01 (Japan)
—
—
—
—
—
—
83
84
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
I = 20 mA
L
4
Dynamic Range
DR
ACT = 1, DCT = 11(TBR21)
I = 60 mA
L
5
5
Transmit Total Harmonic Distortion
Transmit Total Harmonic Distortion
THD
THD
THD
THD
ACT = 0, DCT = 10 (FCC)
–85
–76
–74
–82
I = 100 mA
L
ACT = 0, DCT = 01 (Japan)
I = 20 mA
L
5
Receive Total Harmonic Distortion
ACT = 0, DCT = 01 (Japan)
I = 20 mA
L
5
Receive Total Harmonic Distortion
ACT = 1, DCT = 11 (TBR21)
I = 60 mA
L
Dynamic Range (call progress AOUT) DR
VIN = 1 kHz
VIN = 1 kHz
60
—
—
1.0
—
—
—
—
—
—
—
dB
%
AO
THD (call progress AOUT)
THD
AO
AOUT Full Scale Level
—
0.75 V
10
V
PP
D
AOUT Output Impedance
—
kΩ
dBFS
dB
Mute Level (call progress AOUT)
Dynamic Range (caller ID mode)
Caller ID Full Scale Level (0 dB gain)
–90
—
—
DR
VIN = 1 kHz, –13 dBFS
60
CID
V
—
0.8
V
PEAK
CID
Notes:
1. See 23 on page 28.
2. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.
3. Receive full scale level will produce –0.9 dBFS at SDO.
z
z
4. DR = 20 log |Vin| + 20 log (RMS signal/RMS noise). Measurement is 300 to 3400 Hz. Applies to both transmit and
receive paths. Vin = 1 KHz, –3 dBFS, Fs = 10300 Hz.
z
5. THD = 20 log (RMS distortion/RMS signal). Vin = 1 kHz, –3 dBFS, Fs = 10300 Hz.
Rev. 2.02
7
Si3034
Table 6. Absolute Maximum Ratings
Parameter
Symbol
Value
–0.5 to 6.0
±10
Unit
V
DC Supply Voltage
V
D
Input Current, Si3021 Digital Input Pins
Digital Input Voltage
I
mA
V
IN
V
–0.3 to (V + 0.3)
IND
D
Operating Temperature Range
Storage Temperature Range
T
–40 to 100
–65 to 150
°C
°C
A
T
STG
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 7. Switching Characteristics—General Inputs
(VD = 3.0 to 5.25 V, TA = 70 °C for F-Grade or K-Grade, CL = 20 pF)
1
Symbol
Min
Typ
Max
Unit
Parameter
Cycle Time, MCLK
MCLK Duty Cycle
Rise Time, MCLK
Fall Time, MCLK
MCLK Before RESET ↑
t
t
16.67
40
—
50
—
—
—
—
—
1000
60
5
ns
%
mc
dty
t
—
ns
r
t
—
5
ns
f
t
10
—
—
—
cycles
ns
mr
2
RESET Pulse Width
t
250
20
rl
3
M0, M1 Before RESET↑
t
ns
mxr
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times.
3. M0 and M1 are typically connected to VD or GND and should not be changed during normal operation.
tmc
tr
tf
VIH
VIL
MCLK
tmr
RESET
trl
M0, M1
tmxr
Figure 2. General Inputs Timing Diagram
8
Rev. 2.02
Si3034
Table 8. Switching Characteristics—Serial Interface (DCE = 0)
(VD = 3.0 to 5.25 V, TA = 70 °C for F-Grade or K-Grade, CL = 20 pF)
Parameter
Symbol
Min
354
—
Typ
Max
—
Unit
ns
%
Cycle time, SCLK
t
1/256 Fs
c
SCLK duty cycle
t
50
—
—
—
—
—
—
—
—
dty
Delay time, SCLK ↑ to FSYNC ↓
Delay time, SCLK ↑ to SDO valid
Delay time, SCLK ↑ to FSYNC ↑
Setup time, SDI before SCLK ↓
Hold time, SDI after SCLK ↓
Setup time, FC ↑ before SCLK ↑
Hold time, FC ↑ after SCLK ↑
t
—
10
20
10
—
ns
ns
ns
ns
ns
ns
ns
d1
d2
d3
t
—
t
—
t
25
20
40
40
su
t
—
h
t
t
—
sfc
—
hfc
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
tc
VOH
VOL
SCLK
td1
td3
FSYNC
(mode 0)
td3
FSYNC
(mode 1)
td2
16 Bit
SDO
D15
D15
D14
D14
D1
D1
D0
tsu
th
16 Bit
SDI
D0
tsfc
thfc
FC
Figure 3. Serial Interface Timing Diagram (DCE = 0)
Rev. 2.02
9
Si3034
Table 9. Switching Characteristics—Serial Interface (DCE = 1, FSD = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70 °C for F-Grade or K-Grade, CL = 20 pF)
1,2
Symbol
Min
Typ
Max
Unit
Parameter
Cycle Time, SCLK
t
354
—
1/256 Fs
50
—
—
10
10
ns
%
c
SCLK Duty Cycle
t
dty
Delay Time, SCLK ↑ to FSYNC ↑
Delay Time, SCLK ↑ to FSYNC ↓
Delay Time, SCLK ↑ to SDO valid
Delay Time, SCLK ↑ to SDO Hi-Z
Delay Time, SCLK ↑ to RGDT ↓
Delay Time, SCLK ↑ to RGDT ↑
Setup Time, SDO Before SCLK ↓
Hold Time, SDO After SCLK ↓
Setup Time, SDI Before SCLK
Hold Time, SDI After SCLK
Notes:
t
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d1
d2
d3
d4
d5
d6
t
—
—
t
t
t
t
0.25t – 20
—
0.25t + 20
c
c
—
—
—
25
20
25
20
—
20
20
20
—
—
—
—
—
—
t
—
su
t
—
h
t
—
su2
t
—
h2
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. Refer to the section "5.23. Multiple Device Support‚" on page 30 for functional details.
32 SCLKs
16 SCLKs
16 SCLKs
tc
SCLK
td1
td2
td2
FSYNC
(mode 1)
td5
td6
td5
FSYNC
(mode 0)
td3
tsu
D15
th
td4
SDO
(master)
D14
D13
D0
td3
SDO
(slave 1)
D15
td5
FSD
(Mode 0)
td2
FSD
(Mode 1)
tsu2
th2
D14
SDI
D15
D13
D0
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
10
Rev. 2.02
Si3034
Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = 1)
(VD = 3.0 to 5.25 V, TA = 70 °C for F-Grade or K-Grade, CL = 20 pF)
Parameter
Symbol
Min
354
—
Typ
1/256 Fs
50
Max
—
Unit
ns
Cycle Time, SCLK
t
c
SCLK Duty Cycle
t
—
%
dty
Delay Time, SCLK ↑ to FSYNC ↑
Delay Time, SCLK ↑ to FSYNC ↓
Delay Time, SCLK ↑ to SDO valid
Delay Time, SCLK ↑ to SDO Hi-Z
Delay Time, SCLK ↑ to RGDT ↓
Setup Time, SDO Before SCLK ↓
Hold Time, SDO After SCLK ↓
Setup Time, SDI Before SCLK
Hold Time, SDI After SCLK
Notes:
t
—
—
10
ns
d1
d2
d3
d4
d5
t
—
—
10
ns
t
t
t
0.25t – 20
—
0.25t + 20
ns
ns
ns
ns
ns
ns
ns
c
c
—
—
25
20
25
20
—
20
20
—
—
—
—
—
t
—
su
t
—
h
t
—
su2
t
—
h2
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. Refer to "5.23. Multiple Device Support‚" on page 30 for functional details.
tc
SCLK
td1
td2
FSYNC
(mode 1)
td3
tsu
th
td4
SDO
(master)
D15
D14
D13
D0
td3
D15
td5
SDO
(slave 1)
FSD
SDI
tsu2
th2
D14
D15
D1
D0
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
Rev. 2.02
11
Si3034
Table 11. Digital FIR Filter Characteristics—Transmit and Receive
(VD = 3.0 to 5.25 V, Sample Rate = 8 kHz, TA = 70 °C for F-Grade or K-Grade)
Parameter
Symbol
Min
0
Typ
—
Max
3.3
3.6
0.1
—
Unit
kHz
kHz
dB
Passband (0.1 dB)
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
F
(0.1 dB)
F
0
—
(3 dB)
–0.1
—
—
4.4
—
kHz
dB
Stopband Attenuation
Group Delay
–74
—
—
t
12/Fs
—
sec
gd
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 6, 7, 8, and 9.
Table 12. Digital IIR Filter Characteristics—Transmit and Receive
(VD = 3.0 to 5.25 V, Sample Rate = 8 kHz, TA = 70 °C for F-Grade or K-Grade)
Parameter
Symbol
Min
0
Typ
—
Max
3.6
0.2
—
Unit
kHz
dB
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
F
(3 dB)
–0.2
—
—
4.4
kHz
dB
Stopband Attenuation
Group Delay
–40
—
—
—
t
1.6/Fs
—
sec
gd
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 10, 11, 12, and 13. Figures 14 and 15 show
group delay versus input frequency.
12
Rev. 2.02
Si3034
Input Frequency—Hz
Input Frequency—Hz
Figure 6. FIR Receive Filter Response
Figure 8. FIR Transmit Filter Response
Input Frequency—Hz
Input Frequency—Hz
Figure 7. FIR Receive Filter Passband Ripple
Figure 9. FIR Transmit Filter Passband Ripple
For Figures 6–9, all filter plots apply to a sample rate of
Fs = 8 kHz. The filters scale with the sample rate as follows:
F(0.1 dB) = 0.4125 Fs
F(–3 dB) = 0.45 Fs
where Fs is the sample frequency.
For Figures 10–13, all filter plots apply to a sample rate of
Fs = 8 kHz. The filters scale with the sample rate as follows:
F(–3 dB) = 0.45 Fs
where Fs is the sample frequency.
Rev. 2.02
13
Si3034
Input Frequency (Hz)
Input Frequency (Hz)
Figure 10. IIR Receive Filter Response
Figure 13. IIR Transmit Filter Passband Ripple
Input Frequency (Hz)
Input Frequency (Hz)
Figure 14. IIR Receive Group Delay
Figure 11. IIR Receive Filter Passband Ripple
Input Frequency (Hz)
Input Frequency (Hz)
Figure 15. IIR Transmit Group Delay
Figure 12. IIR Transmit Filter Response
14
Rev. 2.02
Si3034
2. Typical Application Schematic
6
R 1
7
9
R 1
R 1
+
5
R 1
R 7
R 8
Rev. 2.02
15
Si3034
3. Bill of Materials
Table 13. Global Component Values
Component1
Value
Supplier(s)
2
C1,C4
150 pF, 3 kV, X7R,±20%
Not Installed
Novacap, Venkel, Johanson, Murata, Panasonic
C2,C11,C23,C28,C29,C31,C32
C3
C5
0.22 µF, 16 V, X7R,±20%
0.1 µF, 50 V, X7R/Elec/Tant, ±20%
0.1 µF, 16 V, X7R, ±20%
560 pF, 250 V, X7R, ±20%
10 nF, 250 V, X7R, ±20%
0.22 µF, 16 V, Tant, ±20%
0.47 µF, 16 V, X7R, ±20%
0.68 µF, 16 V, X7R/Elec/Tant, ±20%
3.9 nF, 16 V, X7R, ±20%
0.01 µF, 16 V, X7R, ±20%
1800 pF, 50 V, X7R, ±20%
1000 pF, 3 kV, X7R, ±10%
Not Installed
Novacap, Venkel, Johanson, Murata, Panasonic
C6,C10,C16
C7,C8
C9
Novacap, Johanson, Murata, Panasonic
Panasonic
C12
C13
C14
C18,C19
C20
C22
2
C24,C25
3
C30
4
D1,D2
Dual Diode, 300 V, 225 mA
BAV99 Dual Diode, 70 V, 350 mW
Ferrite Bead
Central Semiconductor
Diodes, Inc., OnSemiconductor, Fairchild
Murata
D3,D4
FB1,FB2
5
L1,L2
330 µH, DCR <3 Ω, 120 mA, ±10%
A42, NPN, 300 V
Taiyo Yuden, ACT, Transtek Magnetics, Cooper Electronics
OnSemiconductor, Fairchild
Q1,Q3
Q2
A92, PNP, 300 V
OnSemiconductor, Fairchild
6
Q4
BCP56T1, NPN, 60 V, 1/2 W
Sidactor, 275 V, 100 A
Not Installed
OnSemiconductor, Fairchild
RV1
Teccor, ST Microelectronics, Microsemi, TI
7
RV2
R1,R4,R21,R22,R23
R2
Not Installed
402 Ω, 1/16 W, ±1%
Not Installed
8
R3
R5
R6
36 kΩ, 1/16 W, ±5%
120 kΩ, 1/16 W, ±5%
4.87 kΩ, 1/4 W, ±1%
56 kΩ, 1/10 W, ±5%
10 kΩ, 1/16 W, ±1%
78.7 Ω, 1/16 W, ±1%
215 Ω, 1/16 W, ±1%
2.2 kΩ, 1/10 W, ±5%
150 Ω, 1/16 W, ±5%
10 Ω, 1/10 W, ±5%
Not Installed
9
R7,R8,R15,R16,R17,R19
R9,R10
R11
R12
R13
R18
R24
R27,R28
R29
R30
0 Ω, 1/10 W
U1
Si3021
Silicon Labs
Silicon Labs
U2
Si3014
Z1
Z4,Z5
Zener Diode, 43 V, 1/2 W
Zener Diode, 5.6 V, 1/2 W
Vishay, OnSemiconductor, Rohm
Diodes, Inc., OnSemiconductor, Fairchild
Notes:
1. The following reference designators were intentionally omitted: C15, C17, C21, C26, C27, R14, and R20.
2. X2/Y3 or Y2 class capacitors are used to comply with the Nordic requirements of EN60950 and may also be used to achieve higher surge immunity.
3. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, ±10%).
4. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.)
5. See Appendix B for additional considerations.
6. Q4 may require copper on board to meet 1/2 power requirement. (Contact transistor manufacturer for details.)
7. RV2 can be installed to improve performance from 2500 V to 3500 V for multiple longitudinal surges (270 V, MOV).
8. If the charge pump is not enabled (with the CPE bit in Register 6), VA must be 4.75 to 5.25 V. R3 can be installed with a 10 Ω, 1/10 W, ±5% if V is also
D
4.75 to 5.25 V.
9. The R7, R8, R15 and R16, R17, R19 resistors may each be replaced with a single resistor of 1.62 kΩ, 3/4 W, ±1%.
16
Rev. 2.02
Si3034
Table 14. FCC Component Values—Si3035 Chipset
1
Value
Supplier(s)
Component
C1,C42
C2
150 pF, 3 kV, X7R,±20%
Not Installed
Novacap, Venkel, Johanson, Murata, Panasonic
C3
0.22 µF, 16 V, X7R, ±20%
1.0 µF, 16 V, Elec/Tant, ±20%
0.1 µF, 16 V, X7R, ±20%
15 nF, 250 V, X7R, ±20%
39 nF, 16 V, X7R, ±20%
Not Installed
C5
C6,C10,C16
C9,C28,C29
C11
Novacap, Johanson, Murata, Panasonic
C7,C8,C12,C13,C14
C18,C19,C20,C22,C233
C24,C25,C31,C322,4
1000 pF, 3 kV, X7R, ±10%
Novacap, Venkel, Johanson, Murata,
Panasonic
C305
D1,D26
D3,D4
FB1,FB2
L1,L2
Q1,Q3
Q2
Not Installed
Dual Diode, 300 V, 225 mA
BAV99 Dual Diode, 70 V, 350 mW
Ferrite Bead
Central Semiconductor
Diodes, Inc., OnSemiconductor, Fairchild
Murata
0 Ω, 1/10 W
A42, NPN, 300 V
A92, PNP, 300 V
OnSemiconductor, Fairchild
OnSemiconductor, Fairchild
Q4
Not Installed
RV1
Sidactor, 275 V, 100 A
240 V, MOV
Teccor, ST Microelectronics, Microsemi, TI
Panasonic
RV2
R1
51 Ω, 1/2 W, ±5%
15 Ω, 1/4 W, ±5%
Not Installed
R2
R37
R4,R18,R21
R5,R6
301 Ω, 1/10 W, ±1%
36 kΩ, 1/10 W, ±5%
R7,R8,R113,R12,R13,R15
Not Installed
R16,R17,R19,R24
R9,R10
R22,R23
R27,R28
R29
2 kΩ, 1/10 W, ±5%
20 kΩ, 1/10 W, ±5%
10 Ω, 1/10 W, ±5%
0 Ω, 1/10 W
R30
Not Installed
U1
Si3021
Silicon Labs
Silicon Labs
U2
Si3012
Z1
Zener Diode, 18 V
Zener Diode, 5.6 V, 1/2 W
Vishay, OnSemiconductor, Rohm
Diodes, Inc., OnSemiconductor, Fairchild
Z4,Z5
Notes:
1. The following reference designators were intentionally omitted: C15, C17, C21, C26, C27, R14, and R20.
2. X2/Y3 or Y2 class capacitors may also be used to achieve surge performance of 5 kV or better.
3. If JATE support is required using the Si3035 chipset, C23 should be populated with a 0.1 µF, 16 V, Tant/Elec/X7R,
±20%, and R11 should be populated with a 2.7 nF, 16 V, X7R, ±20% capacitor.
4. Alternate population option is C24, C25 (2200 pF, 3 kV, X7R, ±10% and C31, C32 not installed).
5. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, ±10%).
6. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.).
7. If the charge pump is not enabled (with the CPE bit in Register 6), VA must be 4.75 to 5.25 V. R3 can be installed with a
10 Ω, 1/10 W, ±5% if VD is also 4.75 to 5.25 V.
Rev. 2.02
17
Si3034
4. Analog Output
Figure 17 illustrates an optional application circuit to support the analog output capability of the Si3034 for call
progress monitoring purposes. The ARM bits in Register 6 allow the receive path to be attenuated by 0 dB, –6 dB,
or –12 dB. The ATM bits, which are also in Register 6, allow the transmit path to be attenuated by –20 dB, –26 dB,
or –32 dB. Both the transmit and receive paths can also be independently muted.
+5 V
C2
6
R3
3
2
C4
+
–
5
+
AOUT
C5
4
C1
C6
R1
C3
R2
Speaker
Figure 17. Optional Connection to AOUT for a Call Progress Speaker
Table 15. Component Values—Optional Connection to AOUT
‘
Symbol
Value
C1
2200 pF, 16 V, ±20%
0.1 µF, 16 V, ±20%
100 µF, 16 V, Elec. ±20%
820 pF, 16 V, ±20%
10 kΩ, 1/10 W, ±5%
10 Ω, 1/10 W, ±5%
47 kΩ, 1/10 W, ±5%
LM386
C2, C3, C5
C4
C6
R1
R2
R3
U1
18
Rev. 2.02
Si3034
Si3034 has been designed to meet the most stringent
worldwide requirements for out-of-band energy,
5. Functional Description
The Si3034 is an integrated direct access arrangement emissions, immunity, lightning surges, and safety.
(DAA) that provides a programmable line interface to Typical Si3034 designs implement a dual layout (see
meet global telephone line interface requirements. The Figure 16) capable of two population options:
device implements Silicon Laboratories’ proprietary
FCC Compliant Population—This population option
isolation technology which offers the highest level of
removes the external devices needed to support
integration by replacing an analog front end (AFE), an
non-FCC countries. The FCC/JATE DAA Si3035
isolation transformer, relays, opto-isolators, and a 2- to
chipset is used.
4-wire hybrid with two 16-pin small outline packages
Globally Compliant Population—This population
(SOIC or TSSOP).
option targets global DAA requirements. This Si3034
The Si3034 chipset can be fully programmed to meet
international requirements and is compliant with FCC,
TBR21, JATE, and various other country-specific PTT
specifications as shown in Table 16. In addition, the
international DAA chipset is populated, and the
external devices required for the FCC-only
population option are removed.
Table 16. Country Specific Register Settings
Register
Country
16
DCT[1:0]
10
17
18
OHS
0
ACT
0
RZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LIM[1:0] VOL[1:0]
Argentina
00
00
11
00
11
00
11
00
00
00
00
11
11
11
11
00
00
00
11
11
11
11
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
1
Australia
1
1
01
Austria
Bahrain
Belgium
0
0 or 1
0
11
0
10
0
0 or 1
0
11
1
Brazil
0
10
Bulgaria
Canada
Chile
0
1
11
0
0
10
0
0
10
1
China
0
0
01 or 10
10
Colombia
Croatia
Cyprus
0
0
0
0 or 1
0 or 1
0 or 1
0 or 1
0
11
0
11
Czech Republic
Denmark
0
11
0
11
Ecuador
0
10
1
Egypt
0
0 or 1
0
01
El Salvador
Finland
France
Germany
Greece
Guam
0
10
0
0 or 1
0 or 1
0 or 1
0 or 1
0
11
0
11
0
11
0
11
0
10
Note:
1. See "5.7. DC Termination Considerations‚" on page 23 for more information.
2. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Hungary, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Poland, Portugal, Romania, Slovakia,
Slovenia, Spain, Sweden, Switzerland, and the United Kingdom.
3. Supported for loop current ≥ 20 mA.
Rev. 2.02
19
Si3034
Table 16. Country Specific Register Settings (Continued)
Register
16
DCT[1:0]
10
11
17
18
Country
OHS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ACT
RZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LIM[1:0] VOL[1:0]
Hong Kong
Hungary
Iceland
India
0
00
11
11
00
00
11
11
11
00
00
00
00
11
11
11
00
00
11
00
11
11
00
11
11
00
00
00
00
11
11
11
00
00
00
11
11
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0 or 1
0 or 1
11
0
10
10
11
Indonesia
Ireland
Israel
0
0 or 1
0 or 1
11
Italy
0 or 1
11
1
Japan
0
01
01
10
10
11
1
Jordan
0
1
Kazakhstan
Kuwait
0
0
Latvia
0 or 1
Lebanon
Luxembourg
Macao
0 or 1
11
0 or 1
11
0
10
01
11
1,3
Malaysia
0
Malta
0 or 1
Mexico
0
10
11
Morocco
Netherlands
New Zealand
Nigeria
0 or 1
0 or 1
11
1
10
11
0 or 1
Norway
0 or 1
11
1
Oman
0
01
01
10
01
11
1
Pakistan
0
Peru
0
1
Philippines
0
Poland
0 or 1
Portugal
Romania
0 or 1
11
0 or 1
11
1
Russia
0
0
0
0
0
10
10
10
11
Saudi Arabia
Singapore
Slovakia
Slovenia
Note:
11
1. See "5.7. DC Termination Considerations‚" on page 23 for more information.
2. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Hungary, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Poland, Portugal, Romania, Slovakia,
Slovenia, Spain, Sweden, Switzerland, and the United Kingdom.
3. Supported for loop current ≥ 20 mA.
20
Rev. 2.02
Si3034
Table 16. Country Specific Register Settings (Continued)
Register
Country
South Africa
16
DCT[1:0]
10
17
18
OHS
1
ACT
RZ
1
RT
0
LIM[1:0] VOL[1:0]
00
00
11
11
11
00
11
00
00
11
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
0
South Korea
Spain
0
10
0
0
0
0 or 1
0 or 1
0 or 1
0
11
0
0
Sweden
0
11
0
0
Switzerland
0
11
0
0
1
Taiwan
0
10
0
0
1,2
TBR21
0
0 or 1
0
11
0
0
1
Thailand
0
01
0
0
UAE
0
0
10
0
0
United Kingdom
USA
0
0 or 1
0
11
0
0
0
10
0
0
Yemen
Note:
0
0
10
0
0
1. See "5.7. DC Termination Considerations‚" on page 23 for more information.
2. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Hungary, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Poland, Portugal, Romania, Slovakia,
Slovenia, Spain, Sweden, Switzerland, and the United Kingdom.
3. Supported for loop current ≥ 20 mA.
5.1. Initialization
5.2. On-Chip Charge Pump
When the Si3034 is initially powered up, the RESET pin The Si3034 has an on-chip charge pump that can
should be asserted. When the RESET pin is produce the V supply needed by the patented
A
deasserted, the registers will have default values. This communication link. This on-chip power supply can be
reset condition guarantees the line-side chip (Si3014) is enabled by setting bit 7 in Register 6 to 1.
powered down with no possibility of loading the line (i.e.,
off-hook). An example initialization procedure is outlined
to ensure it is properly powered. If the on-chip charge
below:
Before enabling the line-side chip, care should be taken
pump is used to provide the V supply, R3 should not be
A
1. Program the PLLs with registers 7 to 9 (N1[7:0], M1[7:0],
N2[3:0], and M2[3:0]) to the appropriate divider ratios for
the supplied MCLK frequency and desired sample rate, as
defined in "5.21. Clock Generation Subsystem‚" on page
27.
populated. If the on-chip charge pump is not used, the
V
supply may be powered from the digital power
A
supply (V ). In this case, V should be at least 4.75 V,
D
D
and R3 should be populated. A separate 5 V power
supply may also be used for the V supply, in which
A
2. Wait until the PLLs are locked. This time is between
100 µs and 1 ms.
case, R3 should not be populated.
5.3. Isolation Barrier
3. Write an 80H into Register 6. This enables the charge
pump for the VA pin, powers up the line-side chip (Si3014),
and enables the AOUT for call progress monitoring.
The Si3034 achieves an isolation barrier through low-
cost, high-voltage capacitors in conjunction with Silicon
Laboratories’ proprietary signal processing techniques.
These techniques eliminate any signal degradation due
to capacitor mismatches, common mode interference, or
noise coupling. As shown in 16 on page 15, the C1, C4,
C24, and C25 capacitors isolate the Si3021 (DSP-side)
from the Si3014 (line-side). All transmit, receive, control,
ring detect, and caller ID data are communicated through
this barrier. Y2 class capacitors may be used for the
isolation barrier to achieve surge performance of 5 kV or
greater.
4. Set the desired line interface parameters (i.e., DCT[1:0],
ACT, OHS, RT, LIM[1:0], and VOL[1:0]) as defined by
"Country Specific Register Settings" shown in Table 16.
After this procedure is complete, the Si3034 is ready for
ring detection and off-hook.
Rev. 2.02
21
Si3034
The proprietary communications link is disabled by
default. To enable it, the PDL bit in Register 6 must be
cleared. No communication between the Si3021 and
Si3014 can occur until this bit is cleared. The clock
generator must be programmed to an acceptable
sample rate prior to clearing the PDL bit.
Figure 18. Japan Mode I/V Characteristics
FCC Mode (DCT[1:0] = 10 b), shown in Figure 19, is the
default dc termination mode and supports a transmit full
scale level of –1 dBm at TIP and RING. This mode
meets FCC requirements in addition to the requirements
of many other countries.
5.4. Off-Hook
The communication system generates an off-hook
command by applying logic 0 to the OFHK pin or by
setting the OH bit in Register 5. The OFHK pin must be
enabled by setting the OHE bit in Register 5. With
OFHK at logic 0, the system is in an off-hook state.
FCC DCT Mode
12
11
10
9
The off-hook state is used to seize the line for incoming/
outgoing calls and can also be used for pulse dialing.
With OFHK at logic 1, negligible dc current flows
through the hookswitch. When a logic 0 is applied to the
OFHK pin, the hookswitch transistor pair, Q1 & Q2, turn
on. This applies a termination impedance across TIP
and RING and causes dc loop current to flow. The
termination impedance has both an ac and dc
component.
8
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
When executing an off-hook sequence, the Si3034
requires 1548/Fs seconds to complete the off-hook and
provide phone-line data on the serial link. This includes
the 12/Fs filter group delay. If necessary, for the shortest
delay, a higher Fs may be established prior to executing
the off-hook, such as an Fs of 10.286 kHz. The delay
allows for line transients to settle prior to normal use.
Figure 19. FCC Mode I/V Characteristics
TBR21 Mode (DCT[1:0] = 11 b), shown in Figure 20,
provides current limiting, while maintaining a transmit
full scale level of –1 dBm at TIP and RING. In this mode,
the dc termination will current limit before reaching
60 mA.
5.5. DC Termination
TBR21 DCT Mode
45
The Si3034 has three programmable dc termination
modes which are selected with the DCT[1:0] bits in
Register 16.
40
35
30
25
Japan Mode (DCT[1:0] = 01 b), shown in Figure 18, is a
lower voltage mode and supports a transmit full scale
level of –2.71 dBm. Higher transmit levels for DTMF
dialing are also supported. See "5.10. DTMF Dialing‚"
on page 24. The low-voltage requirement is dictated by
countries, such as Japan and Malaysia.
20
15
10
5
Japan DCT Mode
10.5
.015
.055 .06
.02 .025 .03 .035 .04 .045 .05
Loop Current (A)
10
9.5
9
Figure 20. TBR21 Mode I/V Characteristics
8.5
8
5.6. AC Termination
The Si3034 has two ac termination impedances
selected with the ACT bit in Register 16.
7.5
7
6.5
6
5.5
ACT = 0 is a real, nominal 600 Ω termination, which
satisfies the impedance requirements of FCC part 68,
JATE, and other countries. This real impedance is set
by circuitry internal to the Si3034 as well as the resistor,
.01
.05 .06
.09 .1 .11
.07 .08
.02 .03 .04
Loop Current (A)
22
Rev. 2.02
Si3034
R2, connected to the REXT pin.
three ways. The first method uses the RGDT pin. The
second method uses the register bits (RDTP, RDTN,
and RDT) in Register 5. The final method uses the SDO
output.
ACT = 1 is a complex impedance which satisfies the
impedance requirements of Australia, New Zealand,
South Africa, TBR21, and some European NET4
countries such as the UK and Germany. This complex The DSP must detect the frequency of the ring signal in
impedance is set by circuitry internal to the Si3034 as order to distinguish a ring from pulse dialing by
well as the complex network formed by R12, R13, and telephone equipment connected in parallel.
C14 connected to the REXT2 pin.
The ring detector mode is controlled by the RFWE bit of
Register 18. When the RFWE bit is 0 (default mode),
5.7. DC Termination Considerations
the ring detector operates in half-wave rectifier mode. In
Under certain line conditions, it may be beneficial to use
this mode, only positive ringing signals are detected. A
other dc termination modes not intended for a particular
positive ringing signal is defined as a voltage greater
world region. For instance, in countries that comply with
than the ring threshold across RNG1-RNG2. RNG1 and
the TBR21 standard, improved distortion characteristics
RNG2 are pins 5 and 6 of the Si3014. Conversely, a
can be seen for very low loop current lines by switching
negative ringing signal is defined as a voltage less than
to FCC mode. Thus, after going off-hook in TBR21
the negative ring threshold across RNG1-RNG2.
mode, the loop current monitor bits (LCS[3:0]) may be
When the RFWE bit is 1, the ring detector operates in
used to measure the loop current, and if LCS[3:0] < 3, it
full-wave rectifier mode. In this mode, both positive and
is recommended that FCC mode be used.
negative ring signals are detected.
Additionally, for very low voltage countries, such as
When the RFWE bit is 0, the RGDT pin will toggle active
Japan and Malaysia, the following procedure may be
low when the ring signal is positive. When the RFWE bit
used to optimize distortion characteristics and maximize
is 1, the RGDT pin will toggle active low when the ring
transmit levels:
signal is positive or negative. This makes the ring signal
1. When first going off-hook, use the Japan mode with the
appear to be twice the frequency of the ringing
VOL bits (Register 18, bits 4:3) set to 01.
waveform.
2. Measure the loop current using the LCS[3:0] bits.
The second method uses the ring detect bits (RDTP,
RDTW, and RDT). The RDTP and RDTN behavior is
based on the RNG1-RNG2 voltage. Whenever the
signal, RNG1-RNG2, is above the positive ring
threshold, the RDTP bit is set. Whenever the signal,
RNG1-RNG2, is below the negative ring threshold, the
RDTN bit is set. When the signal, RNG1-RNG2, is
between these thresholds, neither bit is set.
3. If LCS[3:0]] ≤ 2, maintain the current settings and proceed
with normal operation.
4. If LCS[3:0] ≥ 3, switch to FCC mode, set the VOL bit to 0,
and proceed with normal operation.
Note: A single decision of dc termination mode following off-
hook is appropriate for most applications. However,
during PTT testing, a false dc termination I/V curve
may be generated if the dc I/V curve is determined fol-
lowing a single off-hook event.
The RDT behavior is also based on the RNG1-RNG2
voltage. When the RFWE bit is a 0 or a 1, a positive
ringing signal will set the RDT bit for a period of time.
The RDT bit will not be set for a negative ringing signal.
Finally, Australia has separate dc termination
requirements for line seizure versus line hold. Japan
mode may be used to satisfy both requirements.
However, if a higher transmit level for modem operation
is desired, switch to FCC mode 500 ms after the initial
off-hook. This will satisfy the Australian dc termination
requirements.
The RDT bit acts as a one shot. Whenever a new ring
signal is detected, the one shot is reset. If no new ring
signals are detected prior to the one shot counter
counting down to zero, the RDT bit will return to zero.
The length of this count (in seconds) is 65536 divided
by the sample rate. The RDT will also be reset to zero
by an off-hook event.
5.8. Ring Detection
The ring signal is capacitively coupled from TIP and
RING to the RNG1 and RNG2 pins. The Si3034 The third method uses the serial communication
supports either full- or half-wave ring detection. With interface to transmit ring data. If the isolation capacitor
full-wave ring detection, the designer can detect a is active (PDL = 0) and the device is not off-hook or not
polarity reversal as well as the ring signal. See “5.15. in on-hook line monitor mode, the ring data will be
Caller ID” on page 26. The ring detection threshold is presented on SDO. The waveform on SDO depends on
programmable with the RT bit in Register 16.
the state of the RFWE bit.
The ring detector output can be monitored in one of When the RFWE bit is 0, SDO will be –32768 (0x8000)
Rev. 2.02
23
Si3034
while the RNG1-RNG2 voltage is between the Higher DTMF levels may also be achieved if the
thresholds. When a ring is detected, SDO will transition amplitude is increased and the peaks of the DTMF
to +32767 while the ring signal is positive, then go back signal are clipped at digital full scale (as opposed to
to –32768 while the ring is near zero and negative. wrapping). Clipping the signal will produce some
Thus, a near square wave is presented on SDO that distortion and intermodulation of the signal. Generally,
swings from –32768 to +32767 in cadence with the ring somewhat increased distortion (between 10–20%) is
signal.
acceptable during DTMF signaling. Several dB higher
DTMF levels can be achieved with this technique,
compared with a digital full scale peak signal.
When the RFWE bit is 1, SDO will sit at approximately
+1228 while the RNG1-RNG2 voltage is between the
thresholds. When the ring goes positive, SDO will
transition to +32767. When the ring signal goes near
zero, SDO will remain near 1228. Then, as the ring
goes negative, the SDO will transition to –32768. This
will repeat in cadence with the ring signal.
5.11. Pulse Dialing
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have very tight
specifications for pulse fidelity, including make and
break times, make resistance, and rise and fall times. In
a traditional, solid-state, dc holding circuit, there are a
number of issues in meeting these requirements.
The best way to observe the ring signal on SDO is
simply to observe the MSB of the data. The MSB will
toggle in cadence with the ring signal independent of
the ring detector mode. This is adequate information for
determining the ring frequency. The MSB of SDO will
toggle at the same frequency as the ring signal.
The Si3034 dc holding circuit has active control of the
on-hook and off-hook transients to maintain pulse
dialing fidelity.
5.9. Ringer Impedance
Spark quenching requirements in countries, such as
The ring detector in many DAAs is ac coupled to the line Italy, the Netherlands, South Africa, and Australia, deal
with a large, 1 µF, 250 V decoupling capacitor. The ring with the on-hook transition during pulse dialing. These
detector on the Si3034 is also capacitively coupled to tests provide an inductive dc feed resulting in a large
the line, but it is designed to use smaller, less expensive voltage spike. This spike is caused by the line
capacitors (C7, C8). Inherently, this network produces a inductance and the sudden decrease in current through
high ringer impedance to the line of approximately 800 the loop when going on-hook. The traditional way of
to 900 kΩ. This value meets the majority of country PTT dealing with this problem is to put a parallel RC shunt
specifications, including FCC and TBR21.
across the hookswitch relay. The capacitor is large
(~1 µF, 250 V) and relatively expensive. In the Si3034,
the OHS bit in Register 16 can be used to slowly ramp
down the loop current to pass these tests without
requiring additional components.
Several countries including Poland, South Africa, and
Slovenia, require a maximum ringer impedance that can
be met with an internally-synthesized impedance by
setting the RZ bit in Register 16.
5.12. Billing Tone Detection
5.10. DTMF Dialing
"Billing tones" or "Metering Pulses" generated by the
central office can cause modem connection difficulties.
The billing tone is typically either a 12 KHz or 16 KHz
signal and is sometimes used in Germany, Switzerland,
and South Africa. Depending on line conditions, the
billing tone may be large enough to cause major errors
related to the modem data. The Si3034 chipset has a
feature which allows the device to provide feedback as
to whether a billing tone has occurred and when it ends.
In TBR21 dc termination mode, the DIAL bit in
Register 18 should be set during DTMF dialing if the
LCS[3:0] bits are less than 6. Setting this bit increases
headroom for large signals. This bit should not be used
during normal operation or if the LCS[3:0] bits are
greater than 5.
In Japan dc termination mode, the Si3021 device
attenuates the transmit output by 1.7 dB to meet
headroom requirements. This attenuation can be
removed when DTMF dialing is desired in this mode.
When in the FCC dc termination mode, the FJM bit in
Register 18 will enable the Japan dc termination mode
without the 1.7 dB attenuation. Increased distortion may
be observed, which is acceptable during DTMF dialing.
After DTMF dialing is complete, the attenuation should
be enabled by setting the Japan dc termination mode
DCT[1:0] = 01b. The FJM bit has no effect in Japan dc
termination mode.
Billing tone detection is enabled by setting the BTE bit
(Register 17, bit 2). Billing tones less than 1.1 V
on
PK
the line will be filtered out by the low-pass digital filter on
the Si3034. The ROV bit is set when a line signal is
greater than 1.1 V , indicating a receive overload
PK
condition. The BTD bit is set when a line signal (billing
tone) is large enough to excessively reduce the line-
derived power supply of the line-side device (Si3014).
When the BTD bit is set, the dc termination is changed
24
Rev. 2.02
Si3034
to an 800 Ω dc impedance. This ensures minimum line A modem manufacturer can provide this filter to users in
voltage levels even in the presence of billing tones.
the form of a dongle that connects on the phone line
before the DAA. This keeps the manufacturer from
having to include a costly LC filter internal to the modem
when it may only be necessary to support a few
countries/customers.
The OVL bit (Register 19) should be monitored (polled)
following a billing tone detection. When the OVL bit
returns to 0 (indicating that the billing tone has passed),
the BTE bit should be written to 0 to return the dc
termination to its original state. It will take approximately Alternatively, when a billing tone is detected, the system
one second to return to normal dc operating conditions. software may notify the user that a billing tone has
The BTD and ROV bits are sticky, and they must be occurred. This notification can be used to prompt the
written to 0 to be reset. After the BTE, ROV, and BTD user to contact the telephone company and have the
bits are all cleared, the BTE bit can be set to reenable billing tones disabled or to purchase an external LC filter.
billing tone detection.
5.13. Billing Tone Filter (Optional)
Certain line events, such as an off-hook event on a
In order to operate without degradation during billing
parallel phone or a polarity reversal, may trigger the
tones in Germany, Switzerland, and South Africa, an
ROV or the BTD bits, after which the billing tone detector
external LC notch filter is required. (The Si3034 can
must be reset. The user should look for multiple events
remain off-hook during a billing tone event, but modem
before qualifying whether billing tones are actually
data will be lost in the presence of large billing tone
present.
signals.) The notch filter design requires two notches,
Although the DAA will remain off-hook during a billing
one at 12 KHz and one at 16 KHz. Because these
tone event, the received data from the line will be
components are fairly expensive and few countries
corrupted when a large billing tone occurs. If the user
supply billing tone support, this filter is typically placed
wishes to receive data through a billing tone, an external
in an external dongle or added as a population option
LC filter must be added.
for these countries. Figure 21 shows an example of a
billing tone filter.
L1 must carry the entire loop current. The series
resistance of the inductors is important to achieve a
narrow and deep notch. This design has more than
25 dB of attenuation at both 12 KHz and 16 KHz.
C1
C2
L1
TIP
L2
To
From Line
DAA
C3
RING
Figure 21. Billing Tone Filter
Rev. 2.02
25
Si3034
SQLH bit (Register 18, bit 0) for a period of at least
1 ms. This resets the ac coupling network on the ring
input in preparation for the caller ID data. The SQLH bit
is then cleared, and the ONHM (Register 5, bit 3)
should be asserted to enable the caller ID data to be
passed to the DSP and presented on SDO. This bit
enables a low-power ADC (approximately 450 µA is
drawn from the line) that digitizes the signal passed
across the RNG1/2 pins. This signal is passed across
the isolation capacitor link to the DSP. The ONHM bit
should be cleared after the caller ID data is received
and prior to the second ring.
Table 17. Component Values—Optional Billing
Tone Filters
Symbol
C1,C2
C3
Value
0.027 µF, 50 V, ±10%
0.01 µF, 250 V, ±10%
L1
3.3 mH, >120 mA, <10 Ω, ±10%
10 mH, >40 mA, <10 Ω, ±10%
L2
The billing tone filter effects the ac termination and
return loss. The current complex ac termination will
pass worldwide return loss specifications both with and
without the billing tone filter by at least 3 dB. The ac
termination is optimized for frequency response and
hybrid cancellation, while having greater than 4 dB of
margin with or without the dongle for South Africa,
Australia, TBR21, German, and Swiss country-specific
specifications.
In systems where the caller ID data is preceded by a
line polarity (battery) reversal, the following method
should be used to capture the caller ID data. The
Si3034 supports both full- and half-wave rectified ring
detection. Because a polarity reversal will trip either the
RDTP or RDTN ring detection bits, the user must
distinguish between a polarity reversal and a ring. This
is accomplished using the full-wave ring detector in the
device. The lowest specified ring frequency is 15 Hz;
therefore, if a battery reversal occurs, the DSP should
wait a minimum of 40 ms to verify that the event
observed is a battery reversal and not a ring signal. This
time is greater than half the period of the longest ring
signal. If another edge is detected during this 40 ms
pause, this event is characterized as a ring signal and
not a battery reversal. If it is a battery reversal, the DSP
should set the SQLH bit (Register 18, bit 0) for a period
of at least 1 ms. This resets the ac coupling network on
the ring input in preparation for the caller ID data. The
5.14. On-Hook Line Monitor
The Si3034 allows the user to receive line activity when
in an on-hook state. The ONHM bit in Register 5
enables a low-power ADC that digitizes the signal
passed across the RNG1/2 pins. This signal is passed
across the isolation capacitor link to the DSP. A current
of approximately 450 µA is drawn from the line when
this bit is activated. This mode is typically used to detect
caller ID data. (See the “26 Caller ID” section.)
The on-hook line monitor can also be used to detect SQLH bit is then cleared, and the OHNM bit (Register 5,
whether a phone line is physically connected to the bit 3) should be asserted to enable the caller ID data to
Si3014. If a line is present and the ONHM bit is set, be passed to the DSP and presented on SDO. The
SDO will have a near zero value, and the LCS[3:0] bits ONHM bit should be cleared after the DSP has received
will read 1111b. Due to the nature of the low-power the caller ID data.
ADC, the data presented on SDO could have up to a
10% dc offset.
Due to the nature of the low-power ADC, the data
presented on SDO will have up to a 10% dc offset. The
If no line is connected, the output of SDO will move caller ID decoder must either use a high pass or band
towards a negative full scale value (–32768). The value pass filter to accurately retrieve the caller ID data.
is guaranteed to be at least 89% of negative full scale.
5.16. Loop Current Monitor
In addition, the LCS[3:0] bits will be zero.
It is desirable to have a measurement of the loop
current being drawn from the line to determine if a
5.15. Caller ID
The Si3034 provides the designer with the ability to telephone line is connected or if another telephone has
pass caller ID data from the phone line to a caller ID picked up.
decoder connected to the serial port.
When the system is in an off-hook state, the LCS[3:0]
In systems where the caller ID data is passed on the bits in Register 12 indicate the dc loop current. An
phone line between the first and second rings, the LCS[3:0] value of zero means the loop current is less
following method should be utilized to capture the caller than required for normal operation. When adequate
ID data. The RDTP and RDTN register bits should be loop current is available, the detector has 6 mA steps
monitored to determine the completion of the first ring. with a built-in hysteresis of 2 mA to provide stable
After completion of the first ring, the DSP should set the LCS[3:0] values when near a transition. The LCS[3:0]
26
Rev. 2.02
Si3034
value is a rough approximation of the loop current, and application circuit. In the configuration shown, the
the designer is advised to use this value in a relative LM386 provides a gain of 26 dB. Additional gain
means rather than an absolute value. A typical LCS[3:0] adjustments may be made by varying the voltage
transfer function is shown in Figure 22.
divider created by R1 and R3.
5.19. Gain Control
15
10
The Si3034 supports multiple receive gain and transmit
attenuation settings in Register 15. The receive path
can support gains of 0, 3, 6, 9, and 12 dB, as selected
with the ARX[2:0] bits. The receive path can also be
muted with the RXM bit. The transmit path can support
attenuations of 0, 3, 6, 9, and 12 dB, as selected with
the ATX[2:0] bits. The transmit path can also be muted
with the TXM bit.
LCS
BIT
5
0
The gain control bits ARXB and ATXB in Register 13 are
provided for firmware backwards compatibility with the
Si3032 and Si3035 chipsets. These bits should be set to
zero if the ARX[2:0] and ATX[2:0] in Register 15 are
used.
0
6
12 18 24 30 36 42 48 54 60 66 72 78 84 90 96
Loop Current (mA)
155
Figure 22. Typical LCS[3:0] Transfer Function
This feature enables the host processor to detect
whether an additional line has “picked up” while the
modem is transferring information. In the case of a
second phone going off-hook, the loop current falls
approximately 50% and is reflected in the value of the
LCS[3:0] bits.
5.20. Filter Selection
The Si3021 supports additional filter selections for the
receive and transmit signals as defined in Table 11 and
Table 12 on page 12. The IIRE bit in Register 16 selects
between the IIR and FIR filters. The IIR filter provides a
lower non-linear group delay than the default FIR filter.
5.17. Overload Detection
The Si3034 can detect if an overload condition is
present that may damage the DAA circuit. The DAA
may be damaged if excessive line voltage or loop
current is sustained.
5.21. Clock Generation Subsystem
The Si3034 contains an on-chip clock generator. Using
a single MCLK input frequency, the Si3034 can
generate all the desired standard modem sample rates,
as well as the common 11.025 kHz rate for audio
playback.
In FCC and Japan dc termination modes, an LCS[3:0]
value of 1111b means the loop current is greater than
155 mA indicating the DAA is drawing excessive loop
current.
The clock generator consists of two phase-locked loops,
PLL1 and PLL2, which achieve the desired sample
frequencies. 23 on page 28 illustrates the clock
generator. The architecture of the dual PLL scheme
allows for fast lock time on initial start-up, fast lock time
when changing modem sample rates, high noise
immunity, and the ability to change modem sample
rates with a single register write. A large number of
MCLK frequencies between 1 MHz and 60 MHz are
supported. MCLK should be from a clean source,
preferably directly from a crystal with a constant
frequency and no dropped pulses.
In TBR21 mode, 120 mA of loop current is not possible
due to the current limit circuit. In this dc termination
mode, an LCS[3:0] value of 1000b (8 decimal) or
greater indicates an excessive loop current condition.
5.18. Analog Output
The Si3034 supports an analog output (AOUT) for
driving the call progress speaker found with most of
today’s modems. AOUT is an analog signal that is
comprised of a mix of the transmit and receive signals.
The receive portion of this mixed signal has a 0 dB gain,
while the transmit signal has a gain of –20 dB.
In serial mode 2, the Si3021 operates as a slave device.
The clock generator is configured (by default) to set the
SCLK output equal to the MCLK input. The net effect is
that the clock generator multiplies the MCLK input by
20. For further details of slave mode operation, refer to
"5.23. Multiple Device Support‚" on page 30.
The transmit and receive signals of the AOUT signal
have independent controls found in Register 6. The
ATM[1:0] bits control the transmit portion, while the
ARM[1:0] bits control the receive portion. The bits only
affect the AOUT signal; they do not affect the modem
data. 17 on page 18 illustrates a recommended
Rev. 2.02
27
Si3034
5.21.1. Programming the Clock Generator
only take effect when N2 and M2 are written.
As noted in Figure 23, the clock generator must output a The values shown in Table 18 and Table 19 satisfy the
z
clock equal to 1024 Fs, where Fs is the desired equations above. However, when programming the
z
sample rate. The 1024 Fs clock is determined through registers for N1, M1, N2, and M2, the value placed in
programming of the following registers:
these registers must be one less than the value
calculated from the equations. For example, for
CGM = 0 with an MCLK of 48.0 MHz, the values placed
in the N1 and M1 registers would be 0x7C and 0x5F,
respectively. If CGM = 1, a non-zero value must be
programmed to Register 9 in order for the 16/25 ratio to
take effect.
Register 7: PLL1 N1[7:0] divider.
Register 8: PLL1 M1[7:0] divider.
Register 9: PLL2 N2[3:0] and M2[3:0] dividers.
Register 10: CGM Clock Generation Mode.
The main design consideration is the generation of a
base frequency, defined as follows:
5.21.2. PLL Lock Times
F
⋅ M1
The Si3034 changes sample rates very quickly.
However, lock time will vary based on the programming
of the clock generator. The major factor contributing to
PLL lock time is the CGM bit. When the CGM bit is used
(set to 1), PLL2 will lock more slowly than when CGM is
0. The following relationships describe the boundaries
on PLL locking time:
MCLK
--------------------------------
= 36.864MHz (CGM = 0)
F
=
=
BASE
N1
F
⋅ M1 ⋅ 16
MCLK
-------------------------------------------
F
= 36.864MHz (CGM = 1)
BASE
N1 ⋅ 25
N1 (Register 7) and M1 (Register 8) are 8-bit unsigned
values. F is the frequency of the clock provided to
the MCLK pin. Table 18 on page 29 lists several
standard crystal oscillator rates that could be supplied to
MCLK. This list simply represents a sample of MCLK
frequency choices. Many more are possible.
PLL1 lock time < 1 ms (CGM = 0,1)
PLL2 lock time 100 µs to 1 ms (CGM = 0)
PLL2 lock time <1 ms (CGM = 1)
MCLK
For modem designs, it is recommended that PLL1 be
programmed
during
initialization.
No
further
programming of PLL1 is necessary. The CGM bit and
PLL2 can be programmed for the desired initial sample
rate, typically 7200 Hz. All further sample rate changes
are made by simply writing to Register 9 to update
PLL2.
After PLL1 and the CGM bit have been programmed,
PLL2 can be used to achieve all the standard modem
sampling rates with a single write to Register 9. These
standard sample rates are shown in Table 19. The
values for N2 and M2 (Register 9) are shown in
Table 19. N2 and M2 are 4-bit unsigned values.
The final design consideration for the clock generator is
the update rate of PLL1. The following criteria must be
satisfied in order for the PLLs to remain stable:
When programming the registers of the clock generator,
the order of register writes is important. For PLL1
updates, N1 (Register 7) must always be written first,
immediately followed by a write to M1 (Register 8). For
PLL2, the CGM bit must be set as desired prior to
writing N2 and M2 (Register 9). Changes to the CGM bit
F
MCLK
-------------------
F
=
≥ 144 KHz
UP1
N1
Where F
is shown in Figure 23.
UP1
FUP1
FPLL1
FUP2
FPLL2
DIV
25
1
0
DIV N1
8 bits
DIV N2
4 bits
MCLK
DIV
5
PLL1
PLL2
1024·Fs
0
1
DIV M1
8 bits
DIV M2
4 bits
DIV
16
CGM
Bit
Figure 23. Clock Generation Subsystem
28
Rev. 2.02
Si3034
common audio rate of 11.025 kHz. The restrictions and
equations above still apply; however, a more generic
relationship between MCLK and Fs (the desired sample
rate) is needed. The following equation describes this
relationship:
Table 18. MCLK Examples
MCLK (MHz)
1.8432
N1
1
M1
20
72
9
CGM
0
4.0000
5
1
M1 ⋅ M2
N1 ⋅ N2
5 ⋅ 1024 ⋅ Fs
--------------------
--------------------------------
= ratio ⋅
4.0960
1
0
MCLK
5.0688
11
5
80
48
6
0
where Fs is the sample frequency, ratio = 1 for CGM = 0
and ratio = 25/16 for CGM = 1. All other symbols are
shown in Figure 23.
6.0000
1
6.1440
1
0
8.1920
32
1
225
4
1
By knowing the MCLK frequency and desired sample
rate, the values for the M1, N1, M2, and N2 registers
can be determined. When determining these values,
remember to consider the range for each register as
well as the minimum update rate for the first PLL.
9.2160
0
10.0000
10.3680
11.0592
12.288
25
9
144
32
10
3
1
0
3
0
The values determined for M1, N1, M2, and N2 must be
adjusted by –1 when determining the value written to
the respective registers. This is due to internal logic,
which adds 1 to the value stored in the register. This
addition allows the user to write a 0 value in any of the
registers and the effective “divide by” is 1. A special
case occurs when both M1 and N1 and/or M2 and N2
are programmed with a 0 value. When Mx and Nx are
both zero, the corresponding PLLx is bypassed. If M2
and N2 are set to 0, the ratio of 25/16 is eliminated and
cannot be used in the above equation. In this condition,
the CGM bit has no effect.
1
0
14.7456
16.0000
18.4320
24.5760
25.8048
33.8688
44.2368
46.0800
47.9232
48.0000
56.0000
60.0000
2
5
0
5
18
2
1
1
0
2
3
0
7
10
160
125
4
0
147
96
5
0
1
0
13
125
35
25
10
96
36
24
0
5.22. Digital Interface
0
The Si3034 has two serial interface modes that support
most standard modem DSPs. The M0 and M1 mode
pins select the interface mode. The key difference
between these two serial modes is the operation of the
FSYNC signal. Table 20 summarizes the serial mode
definitions.
1
1
Table 19. N2, M2 Values (CGM = 0,1)
Fs (Hz)
7200
8000
8229
8400
9000
9600
10286
N2
2
M2
2
Table 20. Serial Modes
Mode M1 M0
Description
9
10
8
0
1
2
3
0 0 FSYNC frames data
7
6
7
0 1 FSYNC pulse starts data frame
1 0 Slave mode
4
5
3
4
1 1 Reserved
7
10
The digital interface consists of a single synchronous
serial link that communicates both telephony and
control data.
5.21.3. Setting Generic Sample Rates
The clock generation description focuses on the
common modem sample rates. An application may
require a sample rate not listed in Table 19, such as the
In Serial mode 0 or 1, the Si3021 operates as a master,
where the master clock (MCLK) is an input, the serial
Rev. 2.02
29
Si3034
data clock (SCLK) is an output, and the frame sync
signal (FSYNC) is an output. The MCLK frequency and
the value of the sample rate control registers 7, 8, 9 and
10 determine the sample rate (Fs). The serial port clock,
SCLK, runs at 256 bits per frame, where the frame rate
is equivalent to the sample rate. Refer to "5.21. Clock
Generation Subsystem‚" on page 27 for more details on
programming sample rates.
5.23. Multiple Device Support
The Si3034 supports the operation of up to seven
additional devices on a single serial interface. Figure 32
shows the typical connection of the Si3034 and one
additional serial voice codec (Si3000).
The Si3034 must be the master in this configuration.
The secondary codec should be configured as a slave
device with SCLK and FSYNC as inputs. Upon power
up, the Si3034 master will be unaware of the additional
codec on the serial bus. The FC/RGDT pin is an input
operating as the hardware control for secondary frames,
and the RGDT/FSD pin is an output operating as the
active low ring detection signal. The master device
should be programmed for master/slave mode prior to
enabling the isolation capacitor link because a ring
signal would cause a false transition to the slave
device’s FSYNC.
The Si3034 transfers 16-bit or 15-bit telephony data in
the primary timeslot and 16-bit control data in the
secondary timeslot. Figure 24 and 25 on page 34 show
the relative timing of the serial frames. Primary frames
occur at the frame rate and are always present. To
minimize overhead in the external DSP, secondary
frames are present only when requested.
Two methods exist for transferring control information in
the secondary frame. The default power-up mode uses
the LSB of the 16-bit transmit (TX) data word as a flag to
request a secondary transfer. In this mode, only 15-bit
TX data is transferred, resulting in a loss of SNR but
allowing software control of the secondary frames. As
an alternative method, the FC pin can serve as a
hardware flag for requesting a secondary frame. The
external DSP can turn on the 16-bit TX mode by setting
the SB bit in Register 1. In the 16-bit TX mode, the
hardware FC pin must be used to request secondary
transfers.
Register 14 provides the necessary control bits to
configure the Si3034 for master/slave operation. Bit 0
(DCE) sets the Si3034 in master/slave mode, also
referred to as daisy-chain mode. When the DCE bit is
set, the FC/RGDT pin becomes the ring detect output,
and the RGDT/FSD pin becomes the frame sync delay
output.
Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be
supported on the serial bus. For each slave, the Si3034
will generate a FSYNC to the DSP. In daisy-chain mode,
the polarity of the ring signal can be controlled by bit 1
(RPOL). When RPOL = 1, the ring detect signal (now
output on the FC/RGDT pin) is active high.
Figure 26 and Figure 27 illustrate the secondary frame
read cycle and write cycle, respectively. During a read
cycle, the R/W bit is high, and the 5-bit address field
contains the address of the register to be read. The
contents of the 8-bit control register are placed on the
SDO signal. During a write cycle, the R/W bit is low, and
the 5-bit address field contains the address of the
register to be written. The 8-bit data to be written
immediately follows the address on SDI. Only one
register can be read or written during each secondary
frame. See "6. Control Registers‚" on page 41 for the
register addresses and functions.
The Si3034 supports a variety of codecs as well as
additional Si3034s. The type of slave codec(s) used is
set by bits 4:3 (SSEL1:SSEL0). These bits determine
the type of signalling used in the LSB of SDO. This
assists the DSP in isolating which data stream is the
master and which is the slave. If the LSB is used for
signalling, the master device will have a unique setting
relative to the slave devices. The DSP can use this
information to determine which FSYNC marks the
beginning of a sequence of data transfers.
In serial mode 2, the Si3021 operates as a slave device
where the MCLK is an input, the SCLK is a no connect
(except for the master device for which it is an output),
and the FSYNC is an input. In addition, the RGDT/FSD
pin operates as a delayed frame sync (FSD), and the
FC/RGDT pin operates as ring detect (RGDT). Note
that in this mode, FC operation is not supported. For
further details on operating the Si3021 as a slave
device, refer to “30 Multiple Device Support”.
The delayed frame sync (FSD) of each device is
supplied as the FSYNC of each subsequent slave
device in the daisy chain. The master Si3034 will
generate an FSYNC signal for each device every 16 or
32 SLCK periods. The delay period is set by
Register 14, bit 2 (FSD). Figures 28–31 show the
relative timing for daisy chaining operation.
30
Rev. 2.02
Si3034
Note that primary communication frames occur in isolation capacitor link is passing information between
sequence, followed by secondary communication the Si3021 and the Si3014. The clock generator must
frames, if requested. When writing/reading the master be programmed to a valid sample rate prior to entering
device via a secondary frame, all secondary frames of this mode.
the slave devices must be written as well. When writing/
The Si3034 supports a low-power sleep mode. This
reading a slave device via a secondary frame, the
mode supports the popular wake-up-on-ring feature of
secondary frames of the master and all other slaves
many modems. The clock generator registers, 7, 8, and
must be written as well. "No operation" writes/reads to
9, must be programmed with valid non-zero values prior
secondary frames are accomplished by writing/reading
to enabling sleep mode. Then, the PDN bit must be set
and the PDL bit cleared. When the Si3034 is in sleep
a zero value to address zero.
If FSD is set for 16 SCLK periods between FSYNCs, mode, the MCLK signal may be stopped or remain
only serial mode 1 can be used. In addition, the slave active, but it must be active before waking up the
devices must delay the tri-state to active transition of Si3034. The Si3021 is non-functional except for the
their SDO sufficiently from the rising edge of SCLK to isolation capacitor and RGDT signal. To take the Si3034
avoid bus contention.
out of sleep mode, pulse the reset pin (RESET) low.
The Si3034 supports the operation of up to eight Si3034 In summary, the power down/up sequence for sleep
devices on a single serial bus. The master Si3034 must mode is as follows:
be configured in serial mode 1. The slave(s) Si3034 is
configured in serial mode 2. 33 on page 40 shows a
typical master/slave connection using three Si3034
devices.
1. Registers 7, 8, and 9 must have valid non-zero values.
2. Set the PDN bit (Register 6, bit 3) and clear the PDL bit
(Register 6, bit 4).
3. MCLK may stay active or stop.
When in serial mode 2, FSYNC becomes an input,
RGDT/FSD becomes the delay frame sync output, and
FC/RGDT becomes the ring detection output. In
addition, the internal PLLs are fixed to a “multiply by
20”. This provides the desired sample rate when the
master’s SCLK is provided to the slave’s MCLK. Note
that the SCLK of the slave is a no connect in this
configuration.
4. Restore MCLK before initiating the power-up sequence.
5. Reset the Si3034 using RESET pin (after MCLK is
present).
6. Program registers to desired settings.
The Si3034 also supports an additional power-down
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) are set, the chipset enters a complete
power-down mode and draws negligible current (deep
sleep mode). PLL2 should be turned off prior to entering
deep sleep mode (i.e., set Register 9 to 0 and then
Register 6 to 0x18). In this mode, the RGDT pin does
not function. Normal operation may be restored using
the same process for taking the chipset out of sleep
mode.
The delay between FSYNC input and delayed frame
sync output (RGDT/FSD) will be 16 SCLK periods. The
RGDT/FSD output has a waveform identical to the
FSYNC signal in serial mode 0. In addition, the LSB of
SDO is set to zero by default for all devices in serial
mode 2.
5.24. Power Management
5.25. Calibration
The Si3034 supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full power down
mode. The power management modes are controlled by
the PDN and PDL bits in Register 6.
The Si3034 initiates an auto-calibration by default
whenever the device goes off-hook or experiences a
loss in line power. Calibration is used to remove any
offsets that may be present in the on-chip A/D converter
which could affect the A/D dynamic range. Auto-
calibration is typically initiated after the DAA dc
termination stabilizes and takes 512/Fs seconds to
complete. Due to the large variation in line conditions
and line card behavior that can be presented to the
DAA, it may be beneficial to use manual calibration in
lieu of auto-calibration.
Upon power up or following a reset, the Si3034 is in
reset operation. In this mode, the PDL bit is set, while
the PDN bit is cleared. The Si3021 is fully-operational
except for the isolation capacitor link. No
communication between the Si3021 and Si3014 can
occur during reset operation. Any bits associated with
the Si3014 are not valid in this mode.
Manual calibration should be executed as close to 512/
Fs seconds before valid transmit/receive data is
expected.
The most common mode of operation is normal
operation. In this mode, the PDL and PDN bits are
cleared. The Si3021 is fully-operational, and the
The following steps should be taken to implement
Rev. 2.02
31
Si3034
manual calibration:
0.9 dB attenuation and filter group delays also exist.
1. The CALD (auto-calibration disable—Register 17) bit must
be set to 1.
The analog loopback mode allows an external device to
drive a signal on the telephone line into the Si3034 line-
side device and have it driven back out onto the line.
This mode allows testing of external components
connecting the RJ-11 jack (TIP and RING) to the
Si3014. To enable this mode, set the AL bit in
Register 2.
2. The MCAL (manual calibration) bit must be toggled to one
and then zero to begin and complete the calibration.
3. The calibration will be completed in 512/Fs seconds.
5.26. In-Circuit Testing
The Si3034’s advanced design provides the modem
manufacturer with increased ability to determine system
functionality during production line tests, as well as
support for end-user diagnostics. Four loopback modes
exist allowing increased coverage of system
components. For three of the test modes, a line-side
power source is needed. While a standard phone line
can be used, the test circuit in 1 on page 5 is adequate.
In addition, an off-hook sequence must be performed to
connect the power source to the line-side chip.
The final testing mode, internal analog loopback, allows
the system to test the basic operation of the transmit
and receive paths on the line-side chip and the external
components in 16 on page 15. In this test mode, the
data pump provides a digital test waveform on SDI. This
data is passed across the isolation barrier, transmitted
to and received from the line, passed back across the
isolation barrier, and presented to the data pump on
SDO. To enable this mode, clear the HBE bit in
Register 2.
For the start-up test mode, no line-side power is
necessary and no off-hook sequence is required. The
start-up test mode is enabled by default. When the PDL
bit (Register 6, bit 4) is set (the default case), the line
side is in a power-down mode and the DSP side is in a
digital loop-back mode. In this mode, data received on
SDI is passed through the internal filters and transmitted
on SDO. This path will introduce approximately 0.9 dB
of attenuation on the SDI signal received. The group
delay of both transmit and receive filters will exist
between SDI and SDO. Clearing the PDL bit disables
this mode and the SDO data is switched to the receive
data from the line side. When PDL is cleared the FDT
bit (Register 12, bit 6) will become active, indicating the
successful communication between the line side and
DSP side. This can be used to verify that the isolation
capacitor is operational.
When the HBE bit is cleared, this will cause a dc offset,
which affects the signal swing of the transmit signal. In
this test mode, it is recommended that the transmit
signal be 12 dB lower than normal transmit levels. This
lower level will eliminate clipping caused by the dc
offset, which results from disabling the hybrid. In this
test, it is assumed that the line ac impedance is
nominally 600 Ω.
Note: All test modes are mutually exclusive. If more than one
test mode is enabled concurrently, the results are
unpredictable.
5.27. Exception Handling
The Si3034 provides several mechanisms to determine
if an error occurs during operation. Through the
secondary frames of the serial link, the controlling DSP
can read several status bits. The bit of highest
importance is the frame detect bit (FDT, Register 12,
bit 6). This bit indicates that the DSP-side (Si3021) and
line-side (Si3014) devices are communicating. During
normal operation, the FDT bit can be checked before
reading any bits that indicate information about the line
side. If FDT is not set, the following bits related to the
line-side are invalid: RDT, RDTN, RDTP, LCS[3:0],
CBID, REVB[3:0], CTRO, and OVL. The RGDT
operation will also be non-functional.
The remaining test modes require an off-hook sequence
to operate. The following sequence defines the off-hook
requirement:
1. Power up or reset.
2. Program clock generator to desired sample rate.
3. Enable line-side by clearing PDL bit.
4. Issue off-hook.
5. Delay 1548/Fs sec to allow calibration to occur.
6. Set desired test mode.
Following power-up and reset, the FDT bit is not set
because the PDL bit (Register 6, bit 4) defaults to 1. In
this state, the isolation capacitor link is not operating,
and no information about the line-side can be
determined. The user must program the clock generator
to a valid configuration for the system and clear the PDL
bit to activate the isolation capacitor link. While the DSP
and line side are establishing communication, the DSP-
side does not generate FSYNC signals. Establishing
The isolation capacitor digital loopback mode allows the
data pump to provide a digital input test pattern on SDI
and receive that digital test pattern back on SDO. To
enable this mode, set the DL bit in Register 1. In this
mode, the isolation barrier is actually being tested. The
digital stream is delivered across the isolation capacitor,
C1 of 16 on page 15, to the line-side device and
returned across the same barrier. In this mode, the
32
Rev. 2.02
Si3034
communication will take less than 10 ms. Therefore, if
the controlling DSP serial interface is interrupt driven,
based on the FSYNC signal, the controlling DSP does
not require a special delay loop to wait for this event to
complete.
The FDT bit can also indicate if the line-side executes
an off-hook request successfully. If the line-side is not
connected to a phone line (i.e., the user fails to connect
a phone line to the modem), the FDT bit remains
cleared. The controlling DSP must allow sufficient time
for the line-side to execute the off-hook request. The
maximum time for FDT to be valid following an off-hook
request is 10 ms. If the FDT is high, the LCS[3:0] bits
indicate the amount of loop current flowing. If the FDT
fails to be set following an off-hook request, the PDL bit
in Register 6 must be set high for at least 1 ms to reset
the line side.
Another useful bit is the communication link error (CLE)
bit (Register 12, bit 7). The CLE bit indicates a time-out
error for the isolation capacitor link following a change
to either PLL1 or PLL2. When the CLE bit is set, the
DSP-side chip has failed to receive verification from the
line-side that the clock change has been accepted in an
expected period of time (less than 10 ms). This
condition indicates a severe error in programming the
clock generator or possibly a defective line-side chip.
5.28. Revision Identification
The Si3034 provides the system designer the ability to
determine the revision of the Si3021 and/or the Si3014.
The REVA[3:0] bits in Register 11 identify the revision of
the Si3021. The REVB[3:0] and CBID bits in Register 13
identify the revision of the Si3014.
‘
Table 21. Revision Values
Revision
Si3021
1000
Si3014
0001
0010
0011
A
B
C
1001
1010
Rev. 2.02
33
Si3034
Communications Frame 1 (CF1)
(CF2)
Secondary
Primary
Primary
FSYNC
FC
0
D15 –D1 D0 = 1 (Software FC Bit)
D15 –D1 D0 = 0 (Software FC Bit)
XMT Data
Secondary
XMT Data
SDI
Data
Secondary
Data
RCV Data
RCV Data
SDO
16 SCLKS
128 SCLKS
256 SCLKS
Figure 24. Software FC/RGDT Secondary Request
Communications Frame 1 (CF1)
(CF2)
Primary
Secondary
Primary
FSYNC
FC
0
D15–D0
Secondary
Data
XMT Data
XMT Data
SDI
Secondary
Data
RCV Data
RCV Data
SDO
16 SCLKS
128 SCLKS
256 SCLKS
Figure 25. Hardware FC/RGDT Secondary Request
34
Rev. 2.02
Si3034
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9 D8 D7
D0
0
0
1
A
A
A
A
A
SDI
R/W
D7 D6 D5
D4 D3 D2 D1 D0
D
D
D
D
D
D
D
D
SDO
Figure 26. Secondary Communication Data Format—Read Cycle
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D4 D3 D2 D1 D0
0
0
0
A
A
A
A
A
D
D
D
D
D
D
D
D
SDI
R/W
SDO
Figure 27. Secondary Communication Data Format—Write Cycle
Rev. 2.02
35
Si3034
Master
Slave 1
Serial Mode 1
Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
Master FSYNC
32 SCLKs
32 SCLKs
Master FSD/
Slave1 FSYNC
SDI [0]
SDI [15..1]
1
1
Master
Master
Slave1
Slave1
Master
Slave1
SDO [0]
SDO[15..1]
1
0
Master
Master
Slave1
Slave1
Master
Slave1
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 28. Daisy Chaining of a Single Slave (Pulse FSD)
Master
Slave 1
Serial Mode 1
Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
Master FSYNC
Master FSD/
Slave1 FSYNC
16 SCLKs
16 SCLKs
16 SCLKs
16 SCLKs
SDI [0]
SDI [15..1]
1
1
Master
Master
Slave1
Slave1
Master
Slave1
SDO [0]
SDO[15..1]
1
0
Master
Master
Slave1
Slave1
Master
Slave1
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 29. Daisy Chaining of a Single Slave (Frame FSD)
36
Rev. 2.02
Si3034
Rev. 2.02
37
Si3034
Master
Slave 1
Serial Mode 0
Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
16 SCLKs
Master FSYNC
Master FSD/
Slave1 FSYNC
1
1
Master
Master
Slave1
Slave1
SDI [0]
SDI [15..1]
Master
Slave1
SDO [0]
SDO [15..1]
1
0
Master
Master
Slave1
Slave1
Master
Slave1
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 31. Daisy Chaining with Framed FSYNC and Framed FSD
38
Rev. 2.02
Si3034
MCLK
DSP
Si3021
MCLK
SCLK
SCLK
SDI
SDO
SDI
SDO
FSYNC
FSYNC
INT0
FC/RGDT
VCC
RGDT/FSD
M0
M1
+5 V
47 kΩ
47 kΩ
47 kΩ
Si3000
SCLK
MCLK
FSYNC
SDI
SDO
Voice
Codec
Figure 32. Typical Connection for Master/Slave Operation
(e.g, Data/Fax/Voice Modem)
Rev. 2.02
39
Si3034
MCLK
DSP
Si3021–Master
MCLK
SCLK
SDI
SCLK
SDO
SDI
SDO
FSYNC
FSYNC
INT0
FC/RGDT
RGDT/FSD
VCC
M1
M0
47 kΩ
47 kΩ
Si3021–Slave 1
MCLK
SCLK
FSYNC
SDI
SDO
RGDT/FSD
VCC
M1
M0
Si3021–Slave 2
MCLK
SCLK
FSYNC
SDI
SDO
RGDT/FSD
VCC
M1
M0
Figure 33. Typical Connection for Multiple Si3034s
40
Rev. 2.02
Si3034
6. Control Registers
Note: Any register not listed here is reserved and should not be written.
Table 22. Register Summary
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DL
Bit 0
SB
1
2
3
4
5
6
7
8
9
Control 1
SR
Control 2
AL
HBE
RXE
Reserved
Reserved
DAA Control 1
DAA Control 2
PLL1 Divide N1
PLL1 Divide M1
RDTN
RDTP
OPOL ONHM
PDL PDN
N1[7:0]
RDT
OHE
OH
CPE
ATM[1] ARM[1]
ATM[0] ARM[0]
M1[7:0]
PLL2 Divide/Multiply N2/
M2
N2[3:0]
M2[3:0]
10
11
12
13
14
15
16
17
18
19
PLL Control
CGM
Chip A Revision
REVA[3:0]
LCS[3:0]
ARXB
Line Side Status
CLE
TXM
FDT
CBID
Chip B Revision
REVB[3:0]
SSEL[1:0]
ATXB
DCE
Daisy Chain Control
TX/RX Gain Control
International Control 1
International Control 2
International Control 3
International Control 4
NSLV[2:0]
ATX[2:0]
FSD
RPOL
ARX[2:0]
RZ
RXM
DCT[1:0]
OHS
MCAL
DIAL
ACT
CALD
FJM
IIRE
RT
LIM[1:0]
VOL[1:0]
BTE
ROV
BTD
RFWE SQLH
OVL
Rev. 2.02
41
Si3034
Register 1. Control 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name SR
Type R/W
DL
SB
R/W R/W
Reset settings = 0000_0000
Bit
Name
Function
7
SR
Software Reset.
0 = Enables chip for normal operation.
1 = Sets all registers to their reset value.
Note: Bit will automatically clear after being set.
6:2 Reserved Read returns zero.
1
0
DL
SB
Isolation Digital Loopback.
0 = Digital loopback across the isolation barrier disabled.
1 = Enables digital loopback mode across the isolation barrier. The line-side must be enabled
prior to setting this mode.
Serial Digital Interface Mode.
0 = Operation is in 15-bit mode, and the LSB of the data field indicates whether a secondary
frame is required.
1 = The serial port is operating in 16-bit mode and requires use of the secondary frame sync
signal (FC) to initiate control data reads/writes.
Register 2. Control 2
Bit
D7
D6
D5
D4
D3
AL
D2
D1
D0
Name
Type
HBE RXE
R/W R/W
R/W
Reset settings = 0000_0011
Bit
Name
Function
7:4 Reserved Read returns zero.
3
AL
Analog Loopback.
0 = Analog loopback mode disabled.
1 = Enables external analog loopback mode.
Reserved Read returns zero.
2
1
HBE
Hybrid Enable.
0 = Disconnects hybrid in transmit path.
1 = Connects hybrid in transmit path.
0
RXE
Receive Enable.
0 = Receive path disabled.
1 = Enables receive path.
42
Rev. 2.02
Si3034
Register 3. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit Name
Function
7:0 Reserved Read returns zero.
Register 4. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0 Reserved Read returns zero.
Rev. 2.02
43
Si3034
Register 5. DAA Control 1
Bit
D7
D6
RDTN RDTP OPOL ONHM RDT
R/W R/W
D5
D4
D3
D2
D1
D0
OH
Name
Type
OHE
R/W
R
R
R
R/W
Reset settings = 0000_0000
Bit
7
Name
Reserved Read returns zero.
Function
6
RDTN
RDTP
OPOL
ONHM
Ring Detect Signal Negative.
0 = No negative ring signal is occurring.
1 = A negative ring signal is occurring.
5
4
3
Ring Detect Signal Positive.
0 = No positive ring signal is occurring.
1 = A positive ring signal is occurring.
Off-Hook Polarity.
0 = Off-hook pin is active low.
1 = Off-hook pin is active high.
On-Hook Line Monitor.
0 = Normal on-hook mode.
1 = Enables low-power monitoring mode allowing the DSP to receive line activity without
going off-hook. This mode is used for caller-ID detection.
2
RDT
Ring Detect.
0 = Reset either 4.5–9 seconds after last positive ring is detected or when the system exe-
cutes an off-hook.
1 = Indicates a ring is occurring.
1
0
OHE
OH
Off-Hook Pin Enable.
0 = Off-hook pin is ignored.
1 = Enables the operation of the off-hook pin.
Off-Hook.
0 = Line-side device is on-hook.
1 = Causes the line-side chip to go off-hook. This bit operates independently of the OHE bit
and is a logic OR with the off-hook pin when enabled.
44
Rev. 2.02
Si3034
Register 6. DAA Control 2
Bit
Name CPE ATM[1] ARM[1] PDL
Type R/W R/W R/W R/W
Reset settings = 0111_0000
D7
D6
D5
D4
D3
D2
D1
D0
PDN
R/W
ATM[0] ARM[0]
R/W
R/W
Bit
Name
Function
7
CPE
Charge Pump Enable.
0 = Charge pump is disabled.
1 = Charge pump is enabled.
If the charge pump is not to be enabled, R3 must be installed with 10 Ω, 1/10 W and V must
D
be between 4.75 and 5.25 V.
6,1
5,0
ATM[1:0] AOUT Transmit Path Level Control.
00 = –20 dB transmit path attenuation for call progress AOUT pin only.
01 = –32 dB transmit path attenuation for call progress AOUT pin only.
10 = Mutes transmit path for call progress AOUT pin only.
11 = –26 dB transmit path attenuation for call progress AOUT pin only.
ARM[1:0] AOUT Receive Path Level Control.
00 = 0 dB receive path attenuation for call progress AOUT pin only.
01 = –12 dB receive path attenuation for call progress AOUT pin only.
10 = Mutes receive path for call progress AOUT pin only.
11 = –6 dB receive path attenuation for call progress AOUT pin only.
4
3
2
PDL
PDN
Power Down Line-Side Chip.
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the Si3014 in lower power mode.
Power Down.
0 = Normal operation.
1 = Powers down the Si3021. A pulse on RESET is required to restore normal operation.
Reserved Read returns zero.
Register 7. PLL1 Divide N1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N1
R/W
Reset settings = 0000_0000 (serial mode 0, 1, 2)
Bit
Name
Function
7:0
N1[7:0]
PLL N1 Divider.
Contains the (value – 1) for determining the output frequency on PLL1.
Rev. 2.02
45
Si3034
Register 8. PLL1 Multiply M1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
M1
R/W
Reset settings = 0000_0000 (serial mode 0, 1)
Reset settings = 0001_0011 (serial mode 2)
Bit
Name
Function
7:0
M1[7:0]
PLL1 M1 Multiplier.
Contains the (value – 1) for determining the output frequency on PLL1.
Register 9. PLL2 Divide/Multiply N2/M2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N2
R/W
M2
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:4
N2[3:0]
PLL2 N2 Divider.
Contains the (value – 1) for determining the output frequency on PLL2.
3:0
M2[3:0]
PLL2 M2 Multiplier.
Contains the (value – 1) for determining the output frequency on PLL2.
Register 10. PLL Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CGM
R/W
Reset settings = 0000_0000
Bit
7:1
0
Name
reserved Read returns zero.
CGM Clock Generation Mode.
Function
0 = No additional ratio is applied to the PLL and faster lock times are possible.
1 = A 25/16 ratio is applied to the PLL allowing for a more flexible choice of MCLK frequencies
while slowing down the PLL lock time.
46
Rev. 2.02
Si3034
Register 11. Chip A Revision
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
REVA[3:0]
R
Reset settings = N/A
Bit Name
Function
7:4 Reserved Read returns zero.
3:0 REVA[3:0] Chip A Revision.
Four-bit value indicating the revision of the Si3021 (DSP-side) chip.
Register 12. Line-Side Status
Bit
Name CLE FDT
Type R/W
Reset settings = N/A
D7
D6
D5
D4
D3
D2
D1
D0
LCS[3:0]
R
R
Bit
Name
Function
Communications (Isolation Capacitor link) Error.
7
CLE
0 = Isolation capacitor communication link between the Si3021 and the Si3014 is operating
correctly.
1 = Indicates a communication problem between the Si3021 and the Si3014. When it goes
high, it remains high until a logic 0 is written to it.
6
FDT
Frame Detect.
0 = Indicates isolation capacitor link has not established frame lock.
1 = Indicates isolation capacitor link frame lock has been established.
5:4 Reserved Read returns zero.
3:0 LCS[3:0] Loop Current Sense.
Four-bit value returning the loop current in 6 mA increments.
0 = Loop current < 0.4 mA typical.
1111 = Loop current > 155 mA typical. See "5.16. Loop Current Monitor‚" on page 26.
Rev. 2.02
47
Si3034
Register 13. Chip B Revision
Bit
D7
D6
CBID
R
D5
D4
D3
D2
D1
D0
ARXB ATXB
R/W R/W
Name
Type
REVB[3:0]
R
Reset settings = N/A
Bit
7
Name
Reserved Read returns zero.
CBID Chip B ID.
Function
6
0 = Indicates the line-side is domestic only.
1 = Indicates the line-side has international support.
5:2 REVB[3:0] Chip B Revision.
Four-bit value indicating the revision of the Si3014 (line-side) chip.
Receive Gain.
1
ARXB
0 = 0 dB gain is applied to the receive path.
1 = A 6 dB gain is applied to the receive path.
Note: This bit is for Si3032 backwards compatibility. The Si3034 has additional receive gain settings
ARX[2:0] in Register 15. ARXB should be set to 0 if the settings in Register 15 are used.
0
ATXB
Transmit Attenuation.
0 = 0 dB gain is applied to the transmit path.
1 = A 3 dB attenuation is applied to the transmit path.
Note: This bit is for Si3032 backwards compatibility. The Si3034 has additional transmit gain settings
ATX[2:0] in Register 15. ATXB should be set to 0 if the settings in Register 15 are used.
48
Rev. 2.02
Si3034
Register 14. Daisy Chain Control
Bit
D7
D6
NSLV[2:0]
R/W
D5
D4
SSEL[1:0]
R/W
D3
D2
D1
D0
Name
Type
FSD
R/W
RPOL
R/W
DCE
R/W
Reset settings = 0000_0010 (serial mode 0,1)
Reset settings = 0011_1111 (serial mode 2)
Bit
Name
Function
7:5 NSLV[2:0] Number of Slave Devices.
000 = 0 slaves. Simply redefines the FC/RGDT and RGDT/FSD pins.
001 = 1 slave device
010 = 2 slave devices
011 = 3 slave devices
100 = 4 slave devices (For four or more slave devices, the FSD bit MUST be set.)
101 = 5 slave devices
110 = 6 slave devices
111 = 7 slave devices
4:3 SSEL[1:0] Slave Device Select.
00 = 16-bit SDO receive data
01 = Reserved
10 = 15-bit SDO receive data. LSB = 1 for the Si3034 device.
11 = 15-bit SDO receive data. LSB = 0 for the Si3034 device.
2
FSD
Delayed Frame Sync Control.
0 = Sets the number of SCLK periods between frame syncs to 32.
1 = Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when
Si3034 devices are slaves. For the master Si3034, only serial mode 1 is allowed in this case.
1
0
RPOL
DCE
Ring Detect Polarity.
0 = The FC/RGDT pin (operating as ring detect) is active low.
1 = The FC/RGDT pin (operating as ring detect) is active high.
Daisy-Chain Enable.
0 = Daisy-chaining disabled.
1 = Enables the Si3034 to operate with slave devices on the same serial bus. The FC/RGDT
signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the
delayed frame sync signal. ALL other bits in this register are ignored if DCE = 0.
Rev. 2.02
49
Si3034
Register 15. TX/RX Gain Control
Bit
D7
D6
D5
ATX[2:0]
R/W
D4
D3
D2
D1
ARX[2:0]
R/W
D0
Name TXM
Type R/W
RXM
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
TXM
Transmit Mute.
0 = Transmit signal is not muted.
1 = Mutes the transmit signal.
6:4
ATX[2:0] Analog Transmit Attenuation.
000 = 0 dB attenuation
001 = 3 dB attenuation
010 = 6 dB attenuation
011 = 9 dB attenuation
1xx = 12 dB attenuation
Note: Register 13 ATXB bit must be 0 if these bits are used.
3
RXM
Receive Mute.
0 = Receive signal is not muted.
1 = Mutes the receive signal.
2:0
ARX[2:0] Analog Receive Gain.
000 = 0 dB gain
001 = 3 dB gain
010 = 6 dB gain
011 = 9 dB gain
1xx = 12 dB gain
Note: Register 13 ARXB bit must be 0 if these bits are used.
50
Rev. 2.02
Si3034
Register 16. International Control 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
OHS ACT IIRE
R/W R/W R/W
DCT[1:0]
R/W
RZ
RT
R/W R/W
Reset settings = 0000_1000
Bit
7
Name
Function
Reserved Read returns zero.
6
OHS
ACT
IIRE
On-Hook Speed.
0 = The Si3034 will execute a fast on-hook.
1 = The Si3034 will execute a slow, controlled on-hook.
5
4
AC Termination Select.
0 = Selects the real impedance.
1 = Selects the complex impedance.
IIR Filter Enable.
0 = FIR filter enabled for transmit and receive filters. (See Figures 6–9 on page 13.)
1 = IIR filter enabled for transmit and receive filters. (See Figures 10–15 on page 14.)
3:2
DCT[1:0] DC Termination Select.
00 = Reserved
01 = Japan Mode. Low voltage mode. (Transmit level = –3 dBm).
10 = FCC Mode. Standard voltage mode. (Transmit level = –1 dBm).
11 = TBR21 Mode. Current limiting mode. (Transmit level = –1 dBm).
1
0
RZ
RT
Ringer Impedance.
0 = Maximum (high) ringer impedance.
1 = Synthesized ringer impedance. C15, R14, Z2, and Z3 must not be installed when setting
this bit. See "5.9. Ringer Impedance‚" on page 24.
Ringer Threshold Select.
Used to satisfy country requirements on ring detection. Signals below the lower level will not
generate a ring detection; signals above the upper level are guaranteed to generate a ring
detection.
0 = 11 to 22 V
1 = 17 to 33 V
RMS
RMS
Rev. 2.02
51
Si3034
Register 17. International Control 2
Bit
D7
D6
MCAL CALD
R/W R/W
D5
D4
LIM[1:0]
R/W
D3
D2
D1
D0
Name
Type
BTE ROV BTD
R/W R/W R/W
Reset settings = 0000_0000
Bit
7
Name
Function
Reserved Must be zero.
6
MCAL
CALD
Manual Calibration.
0 = No calibration.
1 = Initiate calibration.
5
4:3
2
Auto-Calibration Disable.
0 = Auto-calibration enabled.
1 = Auto-calibration disabled.
LIM[1:0] Current Limit.
00 = All other modes.
11 = TBR21 mode.
BTE
Billing Tone Detect Enable.
0 = Billing tone detection disabled.
1 = Billing tone detection enabled.
When set, the Si3034 can detect a billing tone signal on the line and maintain off-hook
through the billing tone. If a billing tone is detected, the BTD bit in Register 17 will be set to
indicate the event.
1
0
ROV
BTD
Receive Overload.
0 = Normal receive input level.
1 = Excessive receive input level.
This bit is set if the BTE bit in Register 17 is enabled and the RX pin has an excessive input
level. This bit is cleared by writing a 0 to this location.
Billing Tone Detected.
0 = No billing tone detected.
1 = Billing tone detected.
This bit will be set if the BTE bit in Register 17 is enabled and a billing tone is detected. This
bit is cleared by writing a 0 to this location.
52
Rev. 2.02
Si3034
Register 18. International Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
RFWE SQLH
R/W R/W
D0
Name
Type
DIAL FJM
R/W R/W
VOL[1:0]
R/W
Reset settings = 0000_0000
Bit
7
Name
Reserved Read returns zero.
Function
6
DIAL
DTMF Dialing Mode.
This bit should be set during DTMF dialing in TBR21 mode if LCS[3:0] < 6.
0 = Normal operation.
1 = Increase headroom for DTMF dialing.
5
FJM
Force Japan DC Termination Mode.
0 = Normal Gain.
1 = When Register 16, DCT[1:0], is set to 10b (FCC mode), setting this bit will force Japan dc
termination mode while allowing for a transmit level of –1 dBm. See “5.10. DTMF Dialing” on
page 24.
4:3
VOL[1:0] Line Voltage Adjust.
When set, this bit will adjust the TIP-RING line voltage. Lowering this voltage will improve
margin in low voltage countries. Raising this voltage may improve distortion performance.
00 = Normal
01 = –0.125 V
10 = 0.25 V
11 = 0.125 V
2
1
Reserved Read returns zero.
RFWE
Ring Detector Full Wave Rectifier Enable.
When set, the ring detection circuitry provides full-wave rectification. This will affect the RGDT
pin as well as the data stream presented on SDO during ring detection.
0 = Half Wave.
1 = Full Wave.
0
SQLH
Ring Detect Network Squelch.
This bit must be set, then cleared after at least 1 ms, following a polarity reversal or ring signal
detection. It is used to quickly recover the offset on the RNG1/2 pins after a polarity reversal
or ring signal.
0 = Normal operation.
1 = Squelch function is enabled.
Rev. 2.02
53
Si3034
Register 19. International Control 4
Bit
D7
D6
D5
D4
D3
D2
OVL
R
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Reserved Read may return zero or one.
Function
7
6:3 Reserved Read returns zero.
2
OVL
Overload Detected.
0 = Normal receive input level.
1 = Excessive receive input level.
This bit has the same function as ROV in Register 17, but will clear itself after the overload
has been removed. See “5.12. Billing Tone Detection” on page 25. This bit is only functional
when the BTE bit in Register 17 is enabled.
1:0 Reserved Read returns zero.
54
Rev. 2.02
Si3034
APPENDIX A—UL1950 3RD EDITION
Although designs using the Si3034 comply with UL1950 The bottom schematic of Figure 34 shows the
3rd Edition and pass all overcurrent and overvoltage configuration in which the ferrite beads (FB1, FB2) are
tests, there are still several issues to consider.
on the protected side of the sidactor (RV1). For this
design, the ferrite beads can be rated at 200 mA.
Figure 34 shows two designs that can pass the UL1950
overvoltage tests, as well as electromagnetic emissions. In a cost optimized design, it is important to remember
The top schematic of Figure 34 shows the configuration that compliance to UL1950 does not always require
in which the ferrite beads (FB1, FB2) are on the overvoltage tests. It is best to plan ahead and know
unprotected side of the sidactor (RV1). For this which overvoltage tests will apply to your system.
configuration, the current rating of the ferrite beads System-level elements in the construction, such as fire
needs to be 6 A. However, the higher current ferrite enclosure and spacing requirements, need to be
beads are less effective in reducing electromagnetic considered during the design stages. Consult with your
emissions.
professional testing agency during the design of the
product to determine which tests apply to your system.
C24
75 Ω @ 100 MHz, 6 A
1.25 A
FB1
TIP
RV1
75 Ω @ 100 MHz, 6 A
FB2
RING
C25
C24
600 Ω @ 100 MHz, 200 mA
FB1
1.25 A
TIP
RV1
FB2
RING
600 Ω @ 100 MHz, 200 mA
C25
Figure 34. Circuits that Pass all UL1950 Overvoltage Tests
Rev. 2.02
55
Si3034
APPENDIX B—CISPR22 COMPLIANCE
Various countries are expected to adopt the IEC The direct current resistance (DCR) of the listed
CISPR22 standard over the next few years. For inductors is an important consideration. If the DCR of
example, the European Union (EU) has adopted a the inductors used is less than 3 Ω each, country PTT
standard entitled EN55022, which is based on the specifications that require 300 Ω or less of dc resistance
CISPR22 standard. EN55022 is now part of the EU’s at TIP and RING with 20 mA of loop current can be
EMC Directive, and compliance is expected to be satisfied with the Japan dc termination mode. If the
required starting in 2003. Adherence to this standard DCR of the inductors is at or slightly above 3 Ω, the low
will be necessary to display the CE mark on designs voltage termination mode may need to be used to
intended for sale in the EU. The typical schematic and satisfy the 300 Ω dc resistance requirement at 20 mA of
global bill of materials (BOM) (see Figure 16 and loop current. In all cases, "5.7. DC Termination
Table 13) contained in this data sheet are designed to Considerations‚" on page 23 should be followed.
be compliant to the CISPR22 standard.
If compliance with the CISPR22 standard and certain
If smaller inductors are desired, a notch filter may be other country PTT requirements are not desired, L1 and
used and compliance to CISPR22 still achieved. As L2 may be removed. If these inductors are removed,
shown in Figure 35, a series capacitor-resistor in C24 and C25 should be increased to 2200 pF, and C9
parallel with L1 and L2 forms the simple notch filter. should be changed to 22 nF, 250 V. With these
Table 23 shows corresponding values used for C24, changes, PTT compliance in the following countries will
C25, C38, C39, L1, L2, R31, and R32.
not be achieved: India (I/Fax-03/03 standard), Taiwan
(ID0001 standard), Chile (Decree No. 220 1981
standard), and Argentina (CNC-St2-44.01 standard).
C38
R31
For questions concerning compliance to CISPR22 or
other relevant standards, contact a Silicon Laboratories
technical representative.
L1
FB1
TIP
C24
To
DAA
C39
R32
L2
FB2
RING
C25
Figure 35. Notch Filter for CISPR22
Compliance
Table 23. Notch Filter Component Values
C24/C25
C38/C39
L1/L2
R31/
R32
1000 pF
33 pF, 50 V
150 µH, DCR
< 3 W,
680 Ω,
1/10 W
I > 120 mA
56
Rev. 2.02
Si3034
7. Pin Descriptions: Si3021
Si3021 (SOIC)
Si3021 (TSSOP)
MCLK
1
OFHK
1
SDO
SDI
V
D
16
16
FSYNC
RGDT/FSD
M0
2
SCLK
2
15
15
SCLK
FC/RGDT
RESET
AOUT
M1
FSYNC
MCLK
OFHK
RGDT/FSD
M0
3
4
5
6
7
8
3
4
5
6
7
8
14
13
12
11
10
9
14
13
12
11
10
9
V
V
A
D
SDO
SDI
GND
C1A
M1
FC/RGDT
RESET
C1A
AOUT
GND
V
A
Table 24. Si3021 Pin Descriptions
SOIC TSSOP
Pin Name
Description
Pin #
Pin #
1
13
MCLK
Master Clock Input.
High-speed master clock input. Generally supplied by the system crystal
clock or modem/DSP.
2
14
FSYNC
SCLK
Frame Sync Output.
Data framing signal that is used to indicate the start and stop of a
communication/data frame.
3
4
15
16
Serial Port Bit Clock Output.
Controls the serial data on SDO and latches the data on SDI.
V
Digital Supply Voltage.
D
Provides the digital supply voltage to the Si3021, nominally either 5 V or
3.3 V.
5
6
1
2
SDO
SDI
Serial Port Data Output.
Serial communication data that is provided by the Si3021 to the modem/DSP.
Serial Port Data Input.
Serial communication and control data generated by the modem/DSP and
presented as an input to the Si3021.
7
3
FC/RGDT
Secondary Transfer Request Input/Ring Detect Output.
An optional signal to instruct the Si3021 that control data is being requested
in a secondary frame. When daisy chain is enabled, this pin becomes the
ring detect output. Produces an active low rectified version of the ring signal.
8
9
4
5
RESET
AOUT
Reset Input.
An active low input used to reset all control registers to a defined, initialized
state. Also used to bring the Si3034 out of sleep mode.
Analog Speaker Output.
Provides an analog output signal for driving a call progress speaker.
Rev. 2.02
57
Si3034
Table 24. Si3021 Pin Descriptions (Continued)
SOIC TSSOP
Pin Name
Description
Pin #
Pin #
10
6
M1
Mode Select 1 Input.
The second of two mode select pins that is used to select the operation of the
serial port/DSP interface.
11
7
C1A
GND
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor C1. Used to communicated
with the line-side device.
12
13
8
9
Ground.
Connects to the system digital ground.
V
Analog Supply Voltage.
A
Provides the analog supply voltage for the Si3021, nominally 5 V. This supply
is typically generated internally with an on-chip charge pump set through a
control register.
14
15
10
11
M0
Mode Select 0 Input.
The first of two mode select pins that is used to select the operation of the
serial port/DSP interface.
RGDT/FSD
Ring Detect/Delayed Frame Sync Output.
Output signal that indicates the status of a ring signal. Produces an active low
rectified version of the ring signal. When daisy chain is enabled, this signal
becomes a delayed frame sync to drive a slave device.
16
12
OFHK
Off-Hook Input.
An active low input control signal that provides a termination across TIP and
RING for line seizing and pulse dialing.
58
Rev. 2.02
Si3034
8. Pin Descriptions: Si3014
Si3014 (SOIC or TSSOP)
QE2
DCT
IGND
C1B
FILT2
FILT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RX
REXT
REXT2
REF
RNG1
RNG2
QB
VREG2
VREG
QE
Table 25. 3014 Pin Descriptions
(SOIC or
TSSOP)
Pin Name
Description
Pin #
1
QE2
DCT
Transistor Emitter 2.
Connects to the emitter of Q4.
2
3
4
5
DC Termination.
Provides dc termination to the telephone network.
IGND
C1B
Isolated Ground.
Connects to ground on the line-side interface. Also connects to capacitor C2.
Isolation Capacitor 1B.
Connects to one side of isolation capacitor C1.
RNG1
Ring 1.
Connects through a capacitor to the TIP lead of the telephone line. Provides the
ring and caller ID signals to the Si3034.
6
RNG2
Ring 2.
Connects through a capacitor to the RING lead of the telephone line. Provides the
ring and caller ID signals to the Si3034.
7
8
9
QB
QE
Transistor Base.
Connects to the base of transistor Q3.
Transistor Emitter.
Connects to the emitter of transistor Q3.
VREG
Voltage Regulator.
Connects to an external capacitor to provide bypassing for an internal power sup-
ply.
10
11
VREG2
REF
Voltage Regulator 2.
Connects to an external capacitor to provide bypassing for an internal power sup-
ply.
Reference.
Connects to an external resistor to provide a high accuracy reference current.
Rev. 2.02
59
Si3034
Table 25. 3014 Pin Descriptions (Continued)
Description
(SOIC or
TSSOP)
Pin Name
Pin #
12
REXT2
REXT
RX
External Resistor 2.
Sets the complex ac termination impedance.
13
14
15
16
External Resistor.
Sets the real ac termination impedance.
Receive Input.
Serves as the receive side input from the telephone network.
FILT
Filter.
Provides filtering for the dc termination circuits.
FILT2
Filter 2.
Provides filtering for the bias circuits.
60
Rev. 2.02
Si3034
9. Ordering Guide1,2,3
System Side
Package
Part Number
Si3021-X-ZS#
Si3021-X-ZT#
Si3021-X-FS#
Si3021-X-FT#
Lead-Free
Yes
Temp Range
0 to 70 °C
0 to 70 °C
0 to 70 °C
0 to 70 °C
SOIC-16
TSSOP-16
SOIC-16
Yes
Yes
TSSOP-16
Yes
Line Side
Part Number
Si3014-X-FS
Si3014-X-FT
Notes:
Package
SOIC-16
Lead-Free
Yes
Temp Range
0 to 70 °C
TSSOP-16
Yes
0 to 70 °C
1. “X” denotes product revision.
2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
3. “#” denotes customer-specific bond ID.
Rev. 2.02
61
Si3034
10. Package Outline: 16-Pin SOIC
Figure 36 illustrates the package details for the Si3014 and the Si2493 16-pin packaging option. Table 26 lists the
values for the dimensions shown in the illustration.
16
9
h
bbb B
E
H
-B-
θ
1
8
L
B
aaa C A B
Detail F
-A-
D
C
A
-C-
A1
e
See Detail F
γ
Approximate device weight is 152 mg.
Seating Plane
Figure 36. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 26. Package Diagram Dimensions
Millimeters
Symbol
Min
1.35
.10
Max
1.75
.25
A
A1
B
.33
.51
C
.19
.25
D
E
9.80
3.80
10.00
4.00
e
1.27 BSC
H
h
5.80
.25
6.20
.50
L
.40
1.27
γ
0.10
θ
0º
8º
aaa
bbb
0.25
0.25
62
Rev. 2.02
Si3034
11. Package Outline: 16-Pin TSSOP
Figure 37 illustrates the package details for the Si3024 and Si3014. Table 27 lists the values for the dimensions
shown in the illustration.
16
B
E1
E
θ1
L
ddd
C B A
e
1
2
3
Detail G
A
D
c
A
b
C
bbb M C B A
A1
See Detail G
Figure 37. 16-Pin Thin Small Shrink Outline Package (TSSOP)
Table 27. Package Diagram Dimensions
Symbol
Millimeters
Nom
—
Min
—
Max
1.20
0.15
0.30
0.20
5.10
A
A1
b
0.05
0.19
0.09
4.90
—
—
c
—
D
5.00
e
0.65 BSC
6.40 BSC
4.40
E
E1
L
4.30
0.45
0°
4.50
0.75
8°
0.60
θ1
bbb
ddd
—
0.10
0.20
Rev. 2.02
63
Si3034
Revision 1.2 to Revision 2.0
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Typical Application Circuit was updated.
Updated schematic and BOM.
Added Appendix B.
Corrected transmit frequency response specification
C24, C25 value changed from 470 pF to 1000 pF
and C31, C32 were added in Table 13 and Table 14.
In Table 14, the tolerance was also changed from
20% to 10%.
to 0 Hz typical.
Updated “27 Overload Detection” section text
concerning CTR21 mode.
Removed CTRO bit (Register 19, bit 7).
Power Supply Voltage, Analog maximum changed
Revision 2.0 to Revision 2.01
from 4.75 V to 5.00 V in Table 4.
Last paragraph updated in “31 Power
Table 16 updated.
Management”text section.
“56 Appendix B—CISPR22 Compliance” updated.
Revision 1.1 to Revision 1.2
The “Ringer Impedance Network” figure and the
“Component Values—Optional Ringer Impedance
Network” table were deleted from the “24 Ringer
Impedance”section as well as a paragraph
discussing Czech Republic designs.
Added TSSOP pinout and package drawing.
Added note to Table 2.
Amended numbers in Table 3.
Amended numbers in Table 4.
Amended note #4 in Table 5.
Amended numbers in Table 7.
Replaced Figure 4.
The “Dongle Applications Circuit” figure was deleted.
Revision 2.01 to Revision 2.02
Added support for lead-free/RoHS-compliant
packages and updated lead-free part numbers (page
1 features and Ordering Guide).
Updated Analog Output text.
Added China to Table 16.
Updated footnotes in BOM (no changes in schematic
Added “On-Chip Charge Pump” section.
Added “DC Termination Considerations” section.
or BOM component values).
Updated Table 16 on page 19 and footnote 2 to list
Figure 16, “Typical Application Circuit for the Dual
several countries adopting TBR21.
Design Si3034 and Si3035,” on page 15 updated.
Updated SOIC and TSSOP package drawings and
Table 13, “Global Component Values,” on page 16
dimensions tables.
(BOM) updated.
Table 14, “FCC Component Values—Si3035
Chipset,” on page 17 (BOM) updated.
64
Rev. 2.02
Si3034
NOTES:
Rev. 2.02
65
Si3034
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
66
Rev. 2.02
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