SI3015 [SILICON]
V.22BIS ISOMODEM CHIPSET WITH ERROR CORRECTION; 的V.22bis ISOmodem调制解调器芯片组纠错
| 型号： | SI3015 |
| 厂家： | 
SILICON |
| 描述： | V.22BIS ISOMODEM CHIPSET WITH ERROR CORRECTION |
| 文件： | 总68页 (文件大小：739K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si2403
V.22BIS ISOMODEM® CHIPSET WITH ERROR CORRECTION
Features
ꢀ Data modem formats
ꢀ Integrated DAA
ꢁ
ꢁ
ꢁ
ITU-T, Bell
ꢁOver 5000 V capacitive isolation
300 bps up to 2400 bps
V.42, MNP2-4
ꢁParallel phone detect
ꢁGlobally-compliant line interface
ꢁOvercurrent detection
ꢀ Caller ID decode
ꢀ 3.3 V power
ꢀ No external ROM or RAM required
ꢀ UART with flow control
ꢀ AT command set support
ꢀ Fast connect
ꢀ Parallel interface
ꢀ Call progress support
ꢀ Firmware upgradeable
Ordering Information
This data sheet is valid only for
those chipset combinations listed
on page 63.
Applications
ꢀ Set-top boxes
ꢀ E-mail terminals
ꢀ Point-of-sale terminals
ꢀ Digital video recorders
ꢀ Security systems
ꢀ Remote monitoring
Pin Assignments
Description
Si2403
24
23
22
21
CLKIN/XTALI
EECLK/D5
1
2
3
The Si2403 is a complete, ITU-V.22bis-compliant, 2400 bps modem
chipset with integrated direct access arrangement (DAA) that provides a
programmable line interface to meet global telephone line requirements
with a single design. Available in two small packages, it eliminates the
need for a separate DSP data pump, external RAM and ROM, modem
controller, codec, isolation transformer, relays, opto-isolators, and 2- to 4-
wire hybrid. The ISOmodem® chipset is ideal for embedded modem
applications due to its small board space, low power consumption, and
global compliance.
XTALO
DCD/D4
ESC/D3
CLKOUT/EECS/A0
D6
VD3.3
GND
C1A
4
5
ISOB
VD3.3
GND
20
19
6
7
8
9
VDA
18
17
RTS/D7
VDB
16
15
14
EESD/D2
RI/D1
RXD/RD
10
11
12
TXD/WR
CTS/CS
INT/D0
AOUT/INT
13
RESET
Functional Block Diagram
Si3015
CLKIN/XTALI
CLKOUT
XTALO
1
2
3
4
QE2
DCT
16
FILT2
PLL
Clocking
15
FILT
RAM/ROM
Data Bus
IGND
C1B
RX
14
13
RXD
TXD
CTS
RTS
DCD
ESC
RI
REXT
REXT2
REF
RNG1
RNG2
12
11
5
6
7
Serial
Interface
QB
QE
10
9
C1A
VREG2
VREG
8
DAA
Interface
Microcontroller
DSP
To Phone
Line
INT
AOUT
ISOB
CS
WR
RD
Patents pending
Parallel
Interface
A0
D0-D7
RESET
Rev. 1.2 8/06
Copyright © 2006 by Silicon Laboratories
Si2403
Si2403
2
Rev. 1.2
Si2403
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3. Bill of Materials: Si2403 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3. Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4. Command Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.5. Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.6. Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.7. Clocking/Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.8. Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.9. Wire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.10. Caller ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.11. Parallel Phone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.12. Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.13. Global Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.14. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.15. EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.16. AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.17. Extended AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. S-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6. User-Access Registers (U-Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6.1. Bit-Mapped U-Register Detail (Defaults in Bold) . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
7. Parallel Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
8. Pin Descriptions: Si2403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
9. Pin Descriptions: Si3015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11. Package Outline: 24-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
12. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Rev. 1.2
3
Si2403
1. Electrical Specifications
Table 1. Recommended Operating Conditions
1
2
2
Symbol
Test Condition
Typ
Unit
Parameter
Min
Max
70
Ambient Temperature
Si2403 Supply Voltage, Digital
Notes:
T
K-Grade, F-Grade
0
25
°C
V
A
3
V
3.0
3.3
3.6
D
1. The Si2403 specifications are guaranteed when the typical application circuit (including component tolerance) and any
Si2403 and any Si3015 are used. See "Typical Application Schematic" on page 11.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. The digital supply, VD, operates from 3.0 to 3.6 V. The Si2403 interface supports 5 V logic (CLKIN/XTALI supports 3.3 V
logic only).
4
Rev. 1.2
Si2403
Table 2. DAA Loop Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1
DC Termination Voltage
V
V
V
V
V
V
V
V
I
I = 20 mA, ACT = 1
—
—
7.5
14.5
40
V
TR
TR
TR
TR
TR
TR
TR
TR
L
DCT = 11 (CTR21)
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
I = 42 mA, ACT = 1
DCT = 11 (CTR21)
—
—
40
—
9
—
—
—
—
—
—
—
V
V
V
V
V
V
V
L
I = 50 mA, ACT = 1
DCT = 11 (CTR21)
L
I = 60 mA, ACT = 1
DCT = 11 (CTR21)
—
L
I = 20 mA, ACT = 0
DCT = 01 (Japan)
6.0
—
L
I = 100 mA, ACT = 0
DCT = 01 (Japan)
L
I = 20 mA, ACT = 0
DCT = 10 (FCC)
—
9
7.5
—
L
I = 100 mA, ACT = 0
L
DCT = 10 (FCC)
On-Hook Leakage Current
Operating Loop Current
Operating Loop Current
V
= –48 V
TR
—
13
13
—
—
—
—
—
7
120
60
7
μA
mA
mA
µA
LK
LP
LP
I
I
FCC/Japan Modes
CTR21
2
DC Ring Current
DC flowing through
ring detection circuitry
3
Ring Detect Voltage
V
V
RT = 0
RT = 1
11
17
15
—
—
—
—
—
22
33
68
0.2
V
V
RD
RD
rms
3
Ring Detect Voltage
rms
Ring Frequency
Ringer Equivalence Number
Notes:
F
Hz
R
4
REN
1. ACT = U67, bit 5; DCT = U67, bits 3:2; RT = U67, bit 0; RZ = U67, bit 1.
2. R25 and R26 installed.
3. The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected
above the maximum.
4. C15, R14, Z2, and Z3 not installed. RZ = 0.
Rev. 1.2
5
Si2403
TIP
+
600 Ω
Si3015
I
V
L
TR
10 µF
–
RING
Figure 1. Test Circuit for Loop Characteristics
Table 3. DC Characteristics, VD = 3.3 V
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
I = –2 mA
2.4
—
—
V
OH
O
V
I = 2 mA
—
0.35
10
V
OL
O
I
–10
50
—
µA
kΩ
L
Pullup Resistance Pins 3, 4, 9, 11,
13, 14, 16, 23, 24
R
100
200
PU
*
Total Supply Current
I
I
V
pin
D33
—
—
26
80
35
—
mA
D
D
*
Total Supply Current, Powerdown
PDN = 1
μA
*Note: All inputs at 0 or VD. All inputs held static except clock, and all outputs unloaded (Static IOUT = 0 mA).
6
Rev. 1.2
Si2403
Table 4. DAA AC Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade)
Parameter
Symbol
Fs
Test Condition
Min
Typ
Max
Unit
Sample Rate
—
—
—
—
—
—
—
9.6
—
—
—
—
—
—
—
kHz
MHz
Hz
Crystal Oscillator Frequency
Transmit Frequency Response
Receive Frequency Response
F
4.9152
XTL
Low –3 dBFS Corner
Low –3 dBFS Corner
5
5
Hz
1
Transmit Full Scale Level
V
1
V
PEAK
FS
FS
1
Receive Full Scale Level
V
1
V
PEAK
2,3,4
5
5
Dynamic Range
DR
ACT = 0, DCT = 10 (FCC)
82
dB
I = 100 mA
L
2,3,6
Dynamic Range
DR
ACT = 0, DCT = 01 (Japan)
—
—
—
—
—
—
83
84
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
I = 20 mA
L
2,3,4
Dynamic Range
DR
ACT = 1, DCT = 11(CTR21)
I = 60 mA
L
Transmit Total Harmonic
THD
THD
THD
ACT = 0, DCT = 10 (FCC)
–85
–76
–74
–82
4,7
Distortion
I = 100 mA
L
Transmit Total Harmonic
ACT = 0, DCT = 01 (Japan)
5,7
Distortion
I = 20 mA
L
Receive Total Harmonic
ACT = 0, DCT = 01 (Japan)
6,7
Distortion
I = 20 mA
L
Receive Total Harmonic
THD ACT = 1, DCT = 11 (CTR21)
4,7
Distortion
I = 60 mA
L
AOUT Dynamic Range
AOUT THD
VIN = 1 kHz
VIN = 1 kHz
—
—
—
—
40
40
—
—
—
—
dB
dB
AOUT Full-Scale Level
AOUT Mute Level
Notes:
0.7V
V
PP
DD
60
dB
1. Measured at TIP and RING with 600 Ω termination at 1 kHz.
2. DR = 20 x log |Vin| + 20 x log (RMS signal/RMS noise).
3. Measurement is 300 to 3400 Hz. Applies to transmit and receive paths.
4. Vin = 1 kHz, –3 dBFS, Fs = 10300 Hz.
5. ACT = U67, bit 5; DCT = U67, bits 3:2.
6. Vin = 1 kHz, –6 dBFS, Fs = 10300 Hz.
7. THD = 20 x log (RMS distortion/RMS signal).
Rev. 1.2
7
Si2403
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
4.1
Unit
V
DC Supply Voltage
V
I
D
Input Current, Si2403 Digital Input Pins
Digital Input Voltage
±10
μA
V
IN
V
–0.3 to 5.3
IND
CLKIN/XTALI Input Voltage
Operating Temperature Range
Storage Temperature Range
V
–0.3 to (V + 0.3)
V
XIND
D
T
–10 to 100
–40 to 150
°C
°C
A
T
STG
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 6. Switching Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade)
Parameter
Symbol
Min
2.4576
–1
Typ
Max
39.3216
1
Unit
CLKOUT Output Clock Frequency
—
MHz
Baud Rate Accuracy
CTS or RTS ↑ High to Start Bit↓
RESET ↓ to RESET ↑
RESET ↑ to 1st AT Command
Address Setup
t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
%
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BD
t
10
—
RTS
t
5.0
300
15
—
RS
t
—
AT
t
—
AS
AH
WL
Address Hold
t
0
—
WR Low Pulse Width
Write Data Setup Time
Write Cycle Time
t
50
—
t
20
—
WDSU
t
120
10
—
WC
Chip Select Setup
t
—
CSS
CSH
Chip Select Hold
t
0
—
RD Low Pulse Width
RD Low to Data Driven Time
Data Hold
t
50
—
RL
t
—
20
RLDD
t
10
—
DH
RD High to Hi-Z Time
Read Cycle Time
t
—
30
DZ
t
120
—
RC
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V
8
Rev. 1.2
Si2403
UART Time for Modem Receive Path (8N1 Mode)
8-Bit Data
Mode
R X
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
tRTS
tRTH
RTS
UART Timing for Modem Transmit Path (9N1 Mode with 9th Bit Escape)
9-Bit Data
Mode
T X
Start
D0
D1
D2
D3
D4
D5
D6
D7
ESC Stop
tRTS
tCTH
CTS
Figure 2. Asynchronous UART Serial Interface Timing Diagram
Rev. 1.2
9
Si2403
tCSS
tCSH
CS
A0
tAH
tAS
ADDRESS = 0 or 1
tRL
tRC
RD
tDZ
tRLDD
tDH
D[7:0]
VALID DATA
VALID DATA
tRLDD
Figure 3. Parallel Interface Read Timing
tCSS
tCSH
CS
tAH
tAS
ADDRESS = 0 or 1
A0
tW L
tW C
W R
tW DSU
tDH
D[7:0]
VALID DATA
VALID DATA
Figure 4. Parallel Interface Write Timing
10
Rev. 1.2
Si2403
2. Typical Application Schematic
6
R 1
7
9
R 1
R 1
+
5
R 1
R 7
R 8
Rev. 1.2
11
Si2403
3. Bill of Materials: Si2403 Chipset
Component
Value
Supplier(s)
1
C1,C4
150 pF, 3 kV, X7R, ±20%
0.22 µF, 16 V, X7R, ±20%
0.1 µF, 50 V, Elec/Tant, ±20%
0.1 µF, 16 V, X7R, ±20%
560 pF, 250 V, X7R, ±20%
22 nF, 250 V, X7R, ±20%
1.0 µF, 16 V, Tant, ±20%
Novacap, Venkel, Johanson, Murata, Panasonic
Novacap, Venkel, Johanson, Murata, Panasonic
Venkel, Johanson, Murata, Panasonic
Novacap, Venkel, Johanson, Murata
Novacap, Venkel, Johanson, Murata, Panasonic
Novacap, Venkel, Johanson, Murata, Panasonic
Venkel, Panasonic
C3,C13,C35,C36
2
C5
C6,C10,C16,C37
3
C7,C8
C9
C12
2
C14
0.68 µF, 16 V, X7R/Elec/Tant,
±20%
Novacap, Venkel, AUX, Murata, Panasonic
3
C18,C19
3.9 nF, 16 V, X7R, ±20%
0.01 µF, 16 V, X7R, ±20%
1800 pF, 50 V, X7R, ±20%
1000 pF, 3 kV, X7R, ±10%
33 pF, 16 V, NPO, ±5%
Novacap, Venkel, Johanson, Murata
Novacap, Venkel, Johanson, Murata
Not installed
C20
4
C22
1
C24,C25
Novacap, Venkel, Johanson, Murata, Panasonic
Novacap, Venkel, Johanson, Murata
Not Installed
C26,C27
4
C30
10 pF, 16 V, NPO, ±10%
47 pF, 16 V, X7R, ±10%
2,5
C38,C39
Venkel
6
D1,D2
Dual Diode, 300 V, 225 mA
BAV99 Dual Diode, 70 V, 350 mW
Central Semiconductor
1
D3,D4
Diodes Inc., OnSemiconductor, Fairchild
Murata
FB1,FB2
Ferrite Bead, 600 Ω, ±25%,
200 mA
2,5
L1,L2
68 μH, 120 mA, 4 Ω max, ±10%
A42, NPN, 300 V
Murata, Panasonic
Q1,Q3
Q2
OnSemiconductor, Fairchild, Zetex
OnSemiconductor, Fairchild, Zetex
OnSemiconductor, Fairchild
A92, PNP, 300 V
7
Q4
BCP56, NPN, 60 V, 1/2 W
Sidactor, 275 V, 100 A
RV1
Teccor, ST Microelectronics, Microsemi, TI
Notes:
1. The Si2403 design survives up to 3500 V longitudinal surges without R27, R28, D3, D4, Z4, and Z5. Adding the R27, R28, D3, D4, Z4,
and Z5 enhanced lightning options increases longitudinal surge survival to greater than 6600 V. The isolation capacitors, C1, C4, C24,
and C25, must also be rated to greater than the surge voltage. Y-class capacitors are recommended for highest surge survival.
2. For FCC-only designs, C14, C38, C39, R12, R13, R31, and R32 are not required (leave Si3015 pin 12 unconnected); L1 and L2 may
be replaced with a short; R2 may be ±5%; with Z1 rated at 18 V, C5 may be rated at 16 V; also see Note 9.
3. If the auto answer, ring detect, and caller ID features are not used, R9, R10, C7, and C8 may be removed.
4. C22 and C30 may provide an additional improvement in emissions/immunity, depending on design and layout. Population option
recommended. See “AN70: Si2456/Si2433/Si2414/Si2403 Modem Designer’s Guide” for details.
5. Compliance with EN55022 and/or CISPR-22 conductance disturbance tests requires the following: L1, L2, C38, C39, R31, and R32;
D1 and D2 must be 400 V rated, and RV2 must be populated. See also “EN55022 and CISPR-22 Compliance” in “AN70: Si2456/
Si2433/Si2414/Si2403 Modem Designer’s Guide”.
6. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.)
7. Q4 may require copper on board to meet 1/2 W power requirement. (Contact manufacturer for details.)
8. RV2 can be installed to improve performance for multiple longitudinal surges.
9. The R7, R8, R15, and R16, R17, R19 resistors may each be replaced with a single resistor of 1.78 kΩ, 3/4 W, ±1%. For FCC-only
designs, 1.78 kΩ, 1/16 W, ±5% resistors may be used.
10. If the parallel phone detection feature is not used, R25 and R26 may be removed.
11. To ensure compliance with ITU specifications, frequency tolerance must be less than 100 ppm including initial accuracy, 5-year aging,
0 to 70 °C, and capacitive loading. Crystals with 50 ppm initial accuracy typically satisfy this requirement.
12
Rev. 1.2
Si2403
Component
Value
Supplier(s)
5,8
RV2
270 V, MOV
Not Installed
2
R2
402 Ω, 1/16 W, ±1%
100 kΩ, 1/16 W, ±1%
120 kΩ, 1/16 W, ±5%
5.36 kΩ, 1/4 W, ±1%
56 kΩ, 1/10 W, ±5%
9.31 kΩ, 1/16 W, ±1%
78.7 Ω, 1/16 W, ±1%
215 Ω, 1/16 W, ±1%
2.2 kΩ, 1/10 W, ±5%
150 Ω, 1/16 W, ±5%
10 MΩ, 1/16 W, ±5%
10 Ω, 1/10 W, ±5%
470 Ω, 1/16 W, ±5%
Si2403
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Venkel, Panasonic
Silicon Labs
R5
R6
9
R7,R8,R15,R16,R17,R19
3
R9,R10
R11
2
R12
2
R13
R18
R24
10
R25, R26
1
R27, R28
2,5
R31, R32
U1
U2
Y1
Si3015
Silicon Labs
11
4.9152 MHz, 20 pF, 100 ppm ,
150 ESR
Not Installed
1
Z1
Zener Diode, 43 V, 1/2 W
Zener Diode, 5.6 V, 1/2 W
Vishay, OnSemiconductor, Rohm
Vishay, OnSemiconductor, Rohm
1
Z4,Z5
Notes:
1. The Si2403 design survives up to 3500 V longitudinal surges without R27, R28, D3, D4, Z4, and Z5. Adding the R27, R28, D3, D4, Z4,
and Z5 enhanced lightning options increases longitudinal surge survival to greater than 6600 V. The isolation capacitors, C1, C4, C24,
and C25, must also be rated to greater than the surge voltage. Y-class capacitors are recommended for highest surge survival.
2. For FCC-only designs, C14, C38, C39, R12, R13, R31, and R32 are not required (leave Si3015 pin 12 unconnected); L1 and L2 may
be replaced with a short; R2 may be ±5%; with Z1 rated at 18 V, C5 may be rated at 16 V; also see Note 9.
3. If the auto answer, ring detect, and caller ID features are not used, R9, R10, C7, and C8 may be removed.
4. C22 and C30 may provide an additional improvement in emissions/immunity, depending on design and layout. Population option
recommended. See “AN70: Si2456/Si2433/Si2414/Si2403 Modem Designer’s Guide” for details.
5. Compliance with EN55022 and/or CISPR-22 conductance disturbance tests requires the following: L1, L2, C38, C39, R31, and R32;
D1 and D2 must be 400 V rated, and RV2 must be populated. See also “EN55022 and CISPR-22 Compliance” in “AN70: Si2456/
Si2433/Si2414/Si2403 Modem Designer’s Guide”.
6. Several diode bridge configurations are acceptable (suppliers include General Semi., Diodes Inc.)
7. Q4 may require copper on board to meet 1/2 W power requirement. (Contact manufacturer for details.)
8. RV2 can be installed to improve performance for multiple longitudinal surges.
9. The R7, R8, R15, and R16, R17, R19 resistors may each be replaced with a single resistor of 1.78 kΩ, 3/4 W, ±1%. For FCC-only
designs, 1.78 kΩ, 1/16 W, ±5% resistors may be used.
10. If the parallel phone detection feature is not used, R25 and R26 may be removed.
11. To ensure compliance with ITU specifications, frequency tolerance must be less than 100 ppm including initial accuracy, 5-year aging,
0 to 70 °C, and capacitive loading. Crystals with 50 ppm initial accuracy typically satisfy this requirement.
Rev. 1.2
13
Si2403
Table 7. Protocol Characteristics
Item
Specification
Data Rate
ITU-T V.22bis
ITU-T V.22bis, V.23, or Bell 212A
ITU-T V.21
2400 bps
1200 bps
300 bps
300 bps
Bell 103
Data Format
Selectable 8, 9, 10, or 11 bits per character
Bit asynchronous
Compatibility
V.23, V.22bis, V.22, V.21, Bell 212A, and Bell 103
Operating Mode
Two-wire full-duplex
Switched network
Data Modulation
2400 bps
1200 bps
16-level QAM/600 Baud ±0.01%
4-level PSK/600 Baud ±0.01%
FSK 0–300 Baud ±0.01%
0 to 300 bps
Answer Tone
2100 Hz ±3 Hz
2225 Hz ±3 Hz
ITU-T V.22bis, V.22, and V.21 modes
Bell 212A and 103 modes
Transmit Carrier
ITU-T V.22, V.22bis/Bell 212A
Originate mode
Answer mode
1200 Hz ±0.5 Hz
2400 Hz ±1 Hz
ITU-T V.21
Mark (980 Hz ±12 Hz) Space (1180 Hz ±12 Hz)
Mark (1650 Hz ±12 Hz) Space (1850 Hz ±12 Hz)
Originate mode
Answer mode
Bell 103
Mark (1270 Hz ±12 Hz) Space (1070 Hz ±12 Hz)
Mark (2225 Hz ±12 Hz) Space (2025 Hz ±12 Hz)
Originate mode
Answer mode
Output Level
–9 dBm maximum
Permissive—Switched network
Receive Carrier
ITU-T V.22, V.22bis/Bell 212A
Originate mode
Answer mode
2400 Hz ±7 Hz
1200 Hz ±7 Hz
ITU-T V.21
Mark (1850 Hz ±12 Hz) Space (1650 Hz ±12 Hz)
Mark (1850 Hz ±12 Hz) Space (1650 Hz ±12 Hz)
Originate mode
Answer mode
Bell 103
Mark (2225 Hz ±12 Hz) Space (2025 Hz ±12 Hz)
Mark (1270 Hz ±12 Hz) Space (1070 Hz ±12 Hz)
Originate mode
Answer mode
14
Rev. 1.2
Si2403
Table 7. Protocol Characteristics (Continued)
Item
Specification
Carrier Detect (level for ITU-T V.22bis,
V.22, V.21, 212, 103) in Switched Network
Acquisition (–43 dBm)
Release (–48 dBm)
Hysteresis
2 dBm minimum
DTE Interface
EIA/TIA-232-E (ITU-T V.24/V.28/ISO 2110)
Automatic Adaptive
Line Equalization
Connection Options
Phone Types
Loss of Carrier in ITU-T V.22bis and lower
500 (rotary dial), 2500 (DTMF dial)
Pulse and Tone
Dialing
DTMF Output Level
Pulse Dial Ratio
Ring Cadence
Call Progress Monitor
Per Part 68
Make/Break: 39/61%
On 2 seconds; Off 4 seconds
BUSY
CONNECT (rate)
NO CARRIER
NO DIALTONE
OK
RING
RINGING
Rev. 1.2
15
Si2403
4.1. Digital Interface
4. Functional Description
The ISOmodem chipset digital I/O can be configured as
either a serial UART interface with flow control or as a
parallel 8-bit interface.
The ISOmodem® chipset is a complete embedded-
modem
chipset
with
integrated
direct-access
arrangement (DAA) that provides a programmable line
interface to meet global telephone line requirements.
Available in two small packages, this solution includes a
DSP data pump, a modem controller, on-chip RAM and
ROM, an analog front end (AFE), a DAA, and analog
output.
Selection of a serial or parallel I/O interface is
determined by the state of AOUT/INT (Si2403, pin 13)
during the rising edge of RESET. An internal pullup
resistor forces the default state to serial mode
operation. An external 10 kΩ pulldown resistor can be
connected to AOUT/INT to force selection of parallel
mode. Additionally, when selecting parallel mode, CS
should remain high until after the rising edge of RESET.
Configuration of pins 3, 4, 8–11, 13–16, and 22–24 is
determined by this interface selection.
The Si2403 accepts standard modem AT commands and
provides connect rates up to 2400 bps full-duplex over
the public switched telephone network (PSTN). The
Si2403 features a complete set of modem protocols
including all ITU-T standard formats up to 2400 bps.
4.2. Serial Interface
The Si2403 provides numerous additional features for
embedded modem applications. The modem includes full
caller ID detection and decoding for global standards.
Call progress is supported through echoing result codes
and is also programmable to meet global settings.
Because the Si2403 integrates the DAA, analog features,
such as parallel phone detect, overcurrent detection, and
global PTT compliance with a single design, are included.
The ISOmodem chipset supports data terminal
equipment (DTE) rates up to 307.2 kbps with the
standard serial UART format. Upon powerup, the UART
defaults to a 19.2 kbps baud rate. If a pulldown resistor
≤ 10 kΩ is placed between D2 (Si2403, pin 16) and
GND (Si2403, pin 6), the DTE rate is set by the
autobaud feature after reset.
This device is ideal for embedded modem applications
due to its small board space, low power consumption,
and global compliance. The Si2403 solution includes a
silicon DAA using Silicon Laboratories’ proprietary
capacitive isolation technology. This highly-integrated
DAA can be programmed to meet worldwide PTT
specifications for ac termination, dc termination, ringer
impedance, and ringer threshold. In addition, the Si2403
has been designed to meet the most stringent worldwide
requirements for out-of-band energy, billing-tone
immunity, lightning surges, and safety requirements.
The serial interface also provides a hardware pin, DCD
(data carrier detect), which remains low as long as the
Si2403 is connected.
The INT interrupt pin can be programmed to alert the
host of changes to the interrupts listed in I/O Control 0
(U70).
4.2.1. Autobaud
The ISOmodem chipset includes an automatic baud
rate detection feature that allows the host to start
transmitting data at any standard DTE rate from
300 bps to 307.2 kbps. This feature is enabled by
placing a pulldown resistor <10 kΩ between D2 (pin 16)
and GND.
The Si2403 is designed to be rapidly incorporated into
existing modem applications. The device interfaces
directly through either a serial UART to a microcontroller
or to a PC through a standard RS-232 transceiver. This
interface allows for PC evaluation of the modem
immediately upon powerup via the AT commands using
standard terminal software. The Si2403 also provides an
8-bit parallel port.
4.3. Parallel Interface
The parallel interface is an 8-bit data bus with a single
bit address. Figure 3 on page 10 shows the required
timing for the parallel interface.
If A0 = 0, the data bus represents a read/write to the
“Parallel Interface 0 (0x00)” register on page 57. If
A0 = 1, the data bus represents a read/write to the
“Parallel Interface 1 (0x01)” register on page 58).
The Si2403 solution requires only a few low-cost discrete
components to achieve global compliance. See "Typical
Application Schematic" on page 11.
16
Rev. 1.2
Si2403
4.4. Command Mode
4.7. Clocking/Low-Power Modes
Upon reset, the ISOmodem® chipset is in command
mode and accepts “AT” commands. An outgoing
modem call can be made using the “ATDT#” (tone dial)
or “ATDP#” (pulse dial) command after the device is
configured. If the handshake is successful, the modem
responds with the response codes detailed in Table 12
on page 32 and enters data mode.
The ISOmodem chipset contains an on-chip phase-
locked loop (PLL) and clock generator. Using either a
single crystal or master clock input, the Si2403 can
generate all the internal clocks required to support the
featured modem protocols. Either a 4.9152 MHz clock
(3.3 V max input—see Table 5 on page 8) on XTALI or a
4.9152 MHz crystal across XTALI and XTALO form the
master clock (±100 ppm max) for the Si2403. This clock
source is sent to an internal PLL that generates all
necessary internal system clocks including the DSP
clock. Figure 5 shows a block diagram of how the DSP
clock and the CLKOUT are derived.
4.5. Data Mode
The ISOmodem chipset is in data mode while it has a
connection to another modem or is in the process of
establishing a connection.
In command and data mode, the Si2403 operates in
asynchronous DTE mode only. Data protocols are
available to provide error correction to improve reliability
(V.42 and MNP2-4).
Using the S24 S-register, the Si2403 can be set to
automatically enter sleep mode after a pre-programmed
time of inactivity with either the DTE or the remote
modem. The sleep mode is entered after (S24) seconds
Each connection between two modems in data mode have passed since the TX FIFO has been empty. The
begins with a handshaking sequence. During that Si2403 remains in the sleep state until either a 1 to 0
sequence, the modems determine the line speed, data transition on TXD (serial mode) or a 1 to 0 transition on
protocol, and related parameters for the data link. CS (parallel mode) occurs.
Configuration through AT commands determines the
range of choices available to the modem during the
negotiation process.
Additionally, the Si2403 may be placed in a complete
Powerdown
mode.
Complete
powerdown
is
accomplished via U65[13] (PDN). Once the PDN bit is
written, the Si2403 completely powers down and can
only be powered back on via the RESET pin.
4.6. Fast Connect
The ISOmodem chipset supports a Fast Connect mode
of operation to reduce the time of a connect sequence
in originate mode. The Fast Connect modes can be
enabled for V.21, V.22, V.22bis, Bell103, and Bell212. In
addition, the Si2403 may be set to either default
asynchronous data communications equipment (DCE)
mode or a transparent HDLC synchronous mode.
A 78.6432 MHz/(R1 + 1) clock is produced on the
CLKOUT pin that may be used as an external system
clock. R1 may be programmed via U5E to any value
between 1 and 31 (default value = 31).
To internal clocking
78.6432 MHz
PLL
4.9152 MHz
CLKIN (pin 1)
÷ (R1 + 1)
CLKOUT
(pin 3)
1 < R1 < 31
Figure 5. DSP and CLKOUT Generation
Rev. 1.2
17
Si2403
This allows the host to avoid interrupting another phone
call when the phone line is already in use and to
intelligently handle an interruption when the Si2403 is
using the phone line.
4.8. Error Correction
The ISOmodem® chipset can employ error-correction
(reliable) protocols to ensure error-free delivery of
asynchronous data sent between the host and the
remote end. The Si2403 supports V.42 and MNP2-4
4.11.1. On-Hook Line-in-Use Detection
error correction protocols. V.42 (LAPM) is most When the ISOmodem chipset is sharing the telephone
commonly used and is enabled by default.
line with other devices, it is important that it not interrupt
a call in progress. To detect whether another device is
using the shared telephone line, the host can use the
4.9. Wire Mode
Wire mode is used to communicate with standard non- Si2403 to monitor the TIP-RING dc voltage with the
error correcting modems. When optioned with \N3, the LVCS (Line Voltage and Current Sense) register (U79,
ISOmodem chipset falls back to wire mode if it fails in bits 4:0). See Figure 6 on page 19. See also the %Vn
an attempt to negotiate a V.42 or MNP link with the commands for automatic line-in-use detection.
remote modem. Error correction is not active in wire
mode.
4.11.2. Off-Hook Intrusion Detection
When the ISOmodem chipset is off-hook, an algorithm is
implemented in the Si2403 to automatically monitor the
4.10. Caller ID Operation
TIP-RING loop current via the LVCS register. When the
The ISOmodem chipset supports full type 1 caller ID
Si2403 is off-hook, the LVCS register switches from
detection and decode for the US Bellcore, European
representing the TIP-RING voltage to representing the
ETSI, UK, and Japanese caller ID protocols. Caller ID is
TIP-RING current. (See Figure 7 on page 19.) Upon
enabled via the +VCID and +VCDT commands.
detecting an intrusion, the Si2403 alerts the host to the
condition via the INT pin.
4.11. Parallel Phone Detection
The ISOmodem chipset is able to detect when another
telephone, modem, or other device is using the phone
line.
18
Rev. 1.2
Si2403
30
25
20
15
LVCS
BITS
10
5
0
0
3
6
9
12 15 18 21 24 28 30 33 36 39 42 45 47 51 54 57 60 63 66 69 72 75 78 81 84 87
Loop Voltage (V)
100
Figure 6. Loop Voltage
Overload
30
25
20
15
10
5
CTR21 only
LVCS
BITS
0
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 87 90 93
140
Loop Current
(mA)
Figure 7. Loop Current
Rev. 1.2
19
Si2403
4.12. Overcurrent Detection
4.14. Firmware Upgrades
The ISOmodem® chipset includes an overcurrent The ISOmodem chipset contains an on-chip program
detection feature that measures the loop current at a ROM that includes the firmware required for the
programmable time after the Si2403 goes off-hook. This features listed in this data sheet. In addition, the Si2403
allows the Si2403 to detect if it is connected to an contains on-chip program RAM to accommodate minor
improper telephone line. The overcurrent detection changes to the ROM firmware. This allows Silicon Labs
feature may be enabled by setting the OCDM bit (U70, to provide future firmware updates to optimize the
bit 11). OHT (U77, bits 8:0) sets the delay after off-hook characteristics of new modem designs and those
until the loop current is measured.
already deployed in the field. See AN70 for further
information.
4.13. Global Operation
4.15. EEPROM Interface
The ISOmodem chipset contains an integrated silicon
direct-access arrangement (Silicon DAA) that provides The ISOmodem chipset supports an optional serial
a programmable line interface to meet international peripheral interface (SPI) bus serial EEPROM. The
telephone line interface requirements. “AN70: Si2456/ EEPROM must support SPI mode 3 with a 16-bit
Si2433/Si2414/Si2403 Modem Designer’s Guide” gives (8 kbit – 64 kbit range) address. Upon powerup, if a
the DAA register settings required to meet international pulldown resistor ≤10 kΩ is placed between D6 (Si2403,
PTT standards.
pin 4) and GND, the Si2403 attempts to detect an
EEPROM. An installed EEPROM may contain custom
default settings, firmware upgrades, and/or user-defined
AT command macros for use in custom AT commands
or country codes.
Additionally, the user-access registers (via the AT:U and
AT:R commands) may be programmed for country-
specific settings, such as dial tone, ring, ringback, and
busy tone. See AN70 for complete details.
4.16. AT Commands
At powerup, the Si2403 is in the AT command mode. In
command mode, the modem monitors the input (serial
or parallel) checking constantly for a valid command.
(AT commands are described in Table 8.)
20
Rev. 1.2
Si2403
Table 8. Basic AT Command Set (Command Defaults in Bold)
Action
Command
$
A
Display AT command mode settings.
Answer incoming call.
A/
Re-execute last command. This is the only command not preceded by “AT” or followed by a
<CR>.
Dn
Dial
The dial command, which may be followed by one or more dial command modifiers, manually
dials a phone number:
Modifier
! or &
, or <
;
Function
Flash hook switch for FHT (U4F) ms (default: 500 ms)
Pause before continuing for S8 seconds (default: 2 seconds)
Return to AT command mode after verifying dialtone and dial-
ing any digits.
G
Telephone voting mode. This modifier, intended for use in
Japan, enables a special dial-in voting mode that may be
used with certain automated voting systems. When this modi-
fier is placed anywhere in the dial string (e.g. ATDG), the
Si2403 will dial the phone number and wait S7 seconds (60
by default) to detect a busy tone. When the busy tone is
detected, the Si2403 will report whether or not a polarity
reversal occurs between the time the last digit is dialed and
the detection of the busy tone. The Si2403 will report either
“POLARITY REVERSAL” or “NO POLARITY REVERSAL”. It
is not possible to establish a modem connection when using
this command.
P
T
Pulse (rotary) dialing—pulse digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
Tone (DTMF) dialing—DTMF digits: *, #, A, B, C, D, 0, 1, 2, 3,
4, 5, 6, 7, 8, 9.
W
Wait for dial tone before continuing for S14 seconds (default:
12 seconds). Blind dialing modes X0, X1, and X3 do not
affect the W command.
If the DOP bit (U7A, bit 7) is set, the “ATDTW” command will
cause the Si2403 to pause dialing and either report an “OK” if
a dialtone is detected or “NO DIALTONE” if a dial tone is not
detected.
En
E0
E1
Hn
H0
H1
In
Local DTE echo
Disable
Enable
Hook switch.
Go on-hook (hang up modem).
Go off-hook.
Identification and checksum.
Rev. 1.2
21
Si2403
Table 8. Basic AT Command Set (Command Defaults in Bold) (Continued)
Command
Action
I0
Display Si2403 revision code.
B: Revision B
C: Revision C, etc.
I1
I3
Display Si2403 firmware revision code (numeric).
Display line-side revision code.
15F = Si3015 Revision F
I6
I7
Display the Si2403 model number.
“2403” = Si2403
Diagnostic Results 1. See “AN70: Si2456/Si2433/Si2414/Si2403 Modem Designer’s Guide” for
details.
I8
Mn
M0
M1
M2
M3
On
O0
O1
O2
Qn
Q0
Q1
R
Diagnostic Results 2. See AN70 for details.
Speaker operation (via AOUT).
Speaker is always off.
Speaker is on while dialing and handshaking; off in Data mode.
Speaker is always on.
Speaker is off while dialing; on during handshaking and retraining.
Return to Data mode from command mode operation.
Return to Data mode.
Return to Data mode and perform a full retrain (at any speed except 300 bps).
Return to Data mode and perform rate renegotiation.
Response mode.
Enable result codes (see Table 12 on page 32)
Disable result codes (enable quiet mode).
Initiate V.23 reversal.
Sn
S-register operation (see Table 13 on page 33).
List contents of all S registers.
S$
Sn?
Sn=x
Vn
Display contents of S-register n.
Set S-register n to value x (where n and x are decimal values).
Result code type (see Table 12 on page 32).
Numeric result codes.
V0
V1
Verbal result codes
Xn
Call Progress Monitor (CPM)—This command controls which CPM signals are monitored and
reported to the host from the Si2403. (See Table 12 on page 32.)
X0
Basic results; disable CPM—Blind dial (does not wait for dial tone). CONNECT message does
not include speed.
X1
X2
Extended results; disable CPM—Blind dial. CONNECT message includes speed.
Extended results and detect dial tone only—Add dial tone detection to X1 mode. Does not blind
dial.
X3
Extended results and detect busy only—Add busy tone detection to X1 mode.
X4
Extended results, full CPM—Full CPM enabled, CONNECT message includes speed.
22
Rev. 1.2
Si2403
Table 8. Basic AT Command Set (Command Defaults in Bold) (Continued)
Command
Action
X5
Extended results—Full CPM enabled including ringback detection. Adds ringback detection to
X4 mode.
Yn
Long space disconnect—Modem hangs up after 1.5 seconds or more of continuous space while
on-line.
Y0
Y1
Z
Disable.
Enable.
Hard Reset—This command is functionally equivalent to pulsing the RESET pin low. (See t in
AT
Table 6 on page 8.)
:E
:I
Read from serial EEPROM.
Interrupt Read—This command causes the Si2403 to report the lower 8 bits of the interrupt reg-
ister I/O Control 0 (U70). The CID, OCD, PPD, and RI bits are also cleared, and the INT pin (INT
bit in parallel mode) is deactivated on this read.
:M
:P
Write to serial EEPROM.
Program RAM Write—This command is used to upload firmware supplied by Silicon Labs to the
Si2403. The format for this command is AT:Paaaa,xxxx,yyyy,.... where aaaa is the first address in
hexadecimal, and xxxx,yyyy,.... is data in hexadecimal. Only one :P command is allowed per AT
command line. No other commands can be concatenated in the :P command line. This com-
mand is only for use with special files provided by Silicon Laboratories. Do not attempt to use this
command for any other purpose. Use &T6 to display checksum for patch verification.
:R
:U
User-Access Register Read—This command allows the user to read from the user-access regis-
ters. (See pages 35–53.) The format is “AT:Raa”, where
aa = user-access address in hexadecimal.
The “AT:R” command causes all the U- registers to be displayed.
User-Access Register Write—This command allows the user to write to the 16-bit user-access
registers. (See page 35.) The format is “AT:Uaa,xxxx,yyyy,zzzz,...” where
aa = user-access address in hexadecimal.
xxxx = data in hexadecimal to be written to location aa.
yyyy = data in hexadecimal to be written to location (aa + 1).
zzzz = data in hexadecimal to be written to location (aa + 2).
etc.
Rev. 1.2
23
Si2403
Table 8. Basic AT Command Set (Command Defaults in Bold) (Continued)
Command
Action
+GCI = X
Country settings - Automatically configure all registers for a particular country.
X
Country
0
Japan
9
A
Australia
Austria
F
Belgium
Brazil
16
1B
20
26
27
2E
31
35
3C
3D
42
46
50
51
53
57
58
59
61
69
6C
73
7B
7E
82
87
89
8A
8B
9C
9F
A0
A5
A6
B8
B4
B5
FE
Bulgaria
Canada
China
Columbia
Czech Republic
Denmark
Ecuador
Finland
France
Germany
Greece
Hong Kong
Hungary
India
Ireland
Israel
Italy
South Korea
Luxembourg
Malaysia
Mexico
Netherlands
New Zealand
Norway
Paraguay
Philippines
Poland
Portugal
Singapore
South Africa
Spain
Sweden
Switzerland
Russia
United Kingdom
United States
Taiwan
Note: U-registers are configured to Silicon Laboratories’ recommended values. Changes may be made by
writing individual registers after sending the AT+GCI command. Several countries use the same
configurations as the United Kingdom and the United States. Refer to “AN93: Modem Designer’s
Guide” for details.
+GCI = ?
+GCI?
List all possible country code settings.
List current country code setting (response is: + GCI:<setting>)
24
Rev. 1.2
Si2403
Table 8. Basic AT Command Set (Command Defaults in Bold) (Continued)
Command
Action
+VCDT = X
Caller ID Type.
X
0
1
2
3
Mode
After ring only
Always on
UK
Japan
+VCID = X
Caller ID Enable.
X
0
1
2
Mode
Off
On—formatted
On—raw data format
Rev. 1.2
25
Si2403
4.17. Extended AT Commands
The extended AT commands are supported by the Si2403 and are described in Tables 9 through 11.
Table 9. Extended AT& Command Set (Command Defaults in Bold)
Command
Action
&$
Display AT& current settings.
ESC (pin 22) is not used.
&D0
&D1
&D2
ESC (pin 22) escapes to command mode from data mode if also enabled by HES U70, bit 15.
ESC (pin 22) assertion during a modem connection causes the modem to go on-hook and return to
command mode.
&D3
&Gn
ESC (pin 22) assertion causes ATZ command (reset and return OK result code).
Line connection rate limit—This command sets an upper limit on the line speed that the Si2403 can
connect. Note that the &Hn commands may limit the line speed as well (&Gn not used for &H0 or
&H1). Not all modulations support rates given by &G. Any improper setting will be ignored.
&G3
&G4
&Hn
1200 bps max
2400 bps max
Switched network handshake mode—&Hn commands must be on a separate command line from
ATD, ATA, or ATO commands.
&H6
&H7
&H8
&H9
&H10
&H11
&Pn
&P0
&P1
&Tn
ITU-T V.22bis only (2400 bps or 1200 bps)
ITU-T V.22 only (1200 bps)
Bell 212 only (1200 bps)
Bell 103 only (300 bps)
ITU-T V.21 only (300 bps)
V.23 (1200/75 bps)
Japan pulse dialing
Configure Si2403 for 10 pulse-per-second pulse dialing. For Japan.
Configure Si2403 for 20 pulse-per-second pulse dialing. For Japan.
Test Mode
&T0
Cancel Test Mode (Escape to command mode to issue AT&T0). This command will also report the
number of bit errors encountered on the previous &T4 test.
&T2
&T3
Initiate ITU-T V.54 (ANALOOP) test. Modulation set by &H AT command. Test loop is through the
DSP (Si2403 device) only. The Si2403 echoes data from TX pin (Register 0 in parallel mode) back
to RX pin (Register 0 in parallel mode).
Initiate ITU-T V.54 (ANALOOP) test. Modulation set by &H AT command. Test loop is through the
DSP (Si2403), DAA interface section (Si2403), isolation interface (Si3015), and analog hybrid circuit
(Si3015). Si2403 echoes data from TX pin (Register 0 in parallel mode) back to RX pin (Register 0 in
parallel mode). Phone line termination required as in Figure 1. To test only the link operation, the
hybrid and AFE codec can be removed from the test loop by setting the DL bit (U62, bit 1).
&T4
Initiate transmit as originating modem with automatic data generation. Modulation, data rate, and
symbol rate are set by &H, &G, and S41. Data pattern is set by the S40 register. Continues until the
ATH command is sent after an escape into command mode. Data is also demodulated as in
ANALOOP, and any bit errors are counted to be displayed after the test using &T0.
26
Rev. 1.2
Si2403
Table 9. Extended AT& Command Set (Command Defaults in Bold) (Continued)
Command
Action
&T5
Initiate transmit as answering modem with automatic data generation. Modulation, data rate, and
symbol rate are set by &H, &G, and S41. Data pattern is set by the S40 register. Continues until the
ATH command is sent after an escape into command mode. Data is also demodulated as in
ANALOOP, and any bit errors are counted to be displayed after the test using &T0.
&T6
Compute checksum for firmware-upgradeable section of program memory. If no firmware upgrade is
installed, &T6 returns 0xDE5C.
&Xn
&X0
&X1
Automatic determination of telephone line type.
Abort &x1 or &x2 command.
Automatic determination of telephone line type.
Result code: WXYZn
W:
X:
Y:
Z:
n:
0 = line supports DTMF dialing.
1 = line is pulse dial only.
0 = line supports 20 pps dialing.
1 = line supports 10 pps dialing only.
0 = extension network present (PBX).
1 = outside line (PSTN) connected directly.
0 = continuous dialtone.
1 = make-break dialtone.
0–9 (number required for outside line if Y = 0).
&X2
Same as &X1, but Y result (PBX) is not tested.
Y2A
Produce a constant answer tone (ITU-T) and return to command mode. The answer tone continues
until the ATH command is received or the S7 timer expires.
*
Rev. 1.2
27
Si2403
Table 10. Extended AT% Command Set (Command Defaults in Bold)
Action
Command
%$
Display AT% command settings.
%B
Report blacklist. See also S42 register.
Answer mode
%On
%O1
%O2
%Vn
Si2403 will auto-answer a call in answer mode
Si2403 will auto-answer a call in originate mode
Automatic Line Status Detection.
After the %V1 and %V2 commands are issued, the Si2403 will automatically check the telephone
connection for whether or not a line is present. If a line is present, the Si2403 will automatically
check if the line is already in use. Finally, the Si2403 will check line status both before going off-hook
and again before dialing. %V1 uses the fixed method, and %V2 uses the adaptive method. %V0
(default) disables this feature.
%V0
Disable automatic line-in-use detection.
%V1
Automatic Line Status Detection - Fixed Method.
Description: Before going off-hook with the ATD, ATO, or ATA commands, the Si2403 compares the
line voltage (via LVCS) to registers NOLN (U83) and LIUS (U84):
Loop Voltage Action
0 ≤ LVCS ≤ NOLNReport “NO LINE” and remain on-hook.
NOLN ≤ LVCS ≤ LIUSReport “LINE IN USE” and remain on-hook.
LIUS ≤ LCVS Go off-hook and establish a modem connection.
Once the call has begun, the off-hook intrusion algorithm (described in "Off-Hook Intrusion Detec-
tion" on page 18) operates normally. In addition, the Si2403 will report “NO LINE” if the telephone
line is completely disconnected. If the HOI bit (U77, bit 11) is set, “LINE IN USE” is reported upon
intrusion.
%V2
Automatic Line Status Detection - Adaptive Method.
Description: Before going off-hook with the ATD, ATO, or ATA commands, the Si2403 compares the
line voltage (via LVCS) to the NLIU (U85) register:
Loop Voltage Action
0 ≤ LVCS ≤ (0.0625 x NLIU)Report “NO LINE” and remain on-hook.
(0.0625 x NLIU) < LVCS ≤ (0.85 x NLIU)Report “LINE IN USE” and remain on-hook.
(0.85 x NLIU) < LCVSGo off-hook and establish a modem connection.
The NLIU register is updated every 1 ms with the minimum non-zero value of LVCS in the last
30 ms. This allows the Si2403 to eliminate errors due to 50/60 Hz interference and also adapt to rel-
atively slow change in the on-hook dc reference value on the telephone line. This algorithm does not
allow any non-zero values for NLIU below 0x0007. The host may also initialize NLIU prior to issuing
the %V2 command. Once the call has begun, the off-hook intrusion algorithm (described in "Off-
Hook Intrusion Detection" on page 18) operates normally. In addition, the Si2403 will report “NO
LINE” if the telephone line is completely disconnected. If the HOI (U77, bit 11) bit is set, “LINE IN
USE” is reported upon intrusion.
28
Rev. 1.2
Si2403
Table 11. Extended AT\ Command Set (Command Defaults in Bold)
Command
\$
Action
Display AT\ command settings.
\Bn
Character length will be automatically set in autobaud mode.
1
\B0
6N1—six data bits, no parity, one stop bit, one start bit, eight bits total (\N0 only)
1
\B1
7N1—seven data bits, no parity, one stop bit, one start bit, nine bits total (\N0 only)
7P1—seven data bits, parity optioned by \P, one stop bit, one start bit, 10 bits total
8N1—eight data bits, no parity, one stop bit, one start bit, 10 bits total
\B2
\B3
\B5
8P1—eight data bits, parity optioned by \P, one stop bit, one start bit, 11 bits total (\N0 only)
\B6
8X1—eight data bits, one escape bit, one stop bit, one start bit, 11 bits total (enables ninth-bit
escape mode)
\Nn
\N0
\N2
Asynchronous protocol
Wire mode (no error correction)
MNP reliable mode. The Si2403 attempts to connect with the MNP protocol. If unsuccessful, the call
is dropped.
\N3
\N4
\N5
V.42 auto-reliable—The Si2403 attempts to connect with the V.42 protocol. If unsuccessful,
the MNP protocol is attempted. If unsuccessful, wire mode is attempted.
V.42 (LAPM) reliable mode (or drop call)—Same as \N3 except that the Si2403 drops the call
instead of connecting in MNP or wire mode.
V.42 and MNP reliable mode - The Si2403 attempts to connect with V.42. If unsuccessful, MNP is
attempted. If MNP is unsuccessful, the call is dropped.
\Pn
\P0
\P1
\P2
\P3
\Qn
\Q0
Parity type will be automatically set in autobaud mode.
Even
1
Space
Odd
1
Mark
Modem-to-DTE flow control
Disable all flow control—Note that this may only be used if the DTE speed and the VF speed are
guaranteed to match throughout the call.
\Q2
Use CTS only
Notes:
1. When in autobaud mode, \B0, \B1, and \P1 will not be detected automatically. The combination of \B2 and \P3 will be
detected. This is compatible with seven data bits, no parity, two stop bits. Seven data bits, no parity, one stop bit may be
forced by sending AT\T17\B1.
2. The autobaud feature does not detect this rate.
3. Default is \T16 if a pulldown is connected to pin 16; otherwise, the default is \T9.
Rev. 1.2
29
Si2403
Table 11. Extended AT\ Command Set (Command Defaults in Bold) (Continued)
Command
\Q3
Action
Use RTS/CTS
\Q4
Use XON/XOFF flow control for modem-to-DTE interface. Does not enable modem-to-modem flow
control.
\Tn
DTE rate - Change DTE rate. When changing rates, the result code “OK” is sent at the old DTE rate.
All options except \T16 lock the DTE to the given rate, and subsequent commands must be sent at
this rate. When \T16 is used (or at reset when pin 16 is pulled down), automatic bandrate detection
is used for subsequent commands.
\T0
\T1
300 bps
600 bps
\T2
1200 bps
2400 bps
4800 bps
7200 bps
9600 bps
\T3
\T4
\T5
\T6
2
\T7
12.0 kbps
\T8
14.4 kbps
3
\T9
19.2 kbps
\T10
\T11
\T12
\T13
\T14
\T15
\T16
\T17
Notes:
38.4 kbps
57.6 kbps
115.2 kbps
230.4 kbps
2
245.760 kbps
307.200 kbps
3
Autobaud on
Autobaud off; lock at current baud rate.
1. When in autobaud mode, \B0, \B1, and \P1 will not be detected automatically. The combination of \B2 and \P3 will be
detected. This is compatible with seven data bits, no parity, two stop bits. Seven data bits, no parity, one stop bit may be
forced by sending AT\T17\B1.
2. The autobaud feature does not detect this rate.
3. Default is \T16 if a pulldown is connected to pin 16; otherwise, the default is \T9.
30
Rev. 1.2
Si2403
Table 11. Extended AT\ Command Set (Command Defaults in Bold) (Continued)
Command
Action
\U
Serial mode—causes a low pulse (25 ms) on RI and DCD. INT to be the inverse of ESC. RTS to be
the inverse of CTS.
Parallel mode—causes a low pulse (25 ms) on INT.
This command terminates with a RESET.
\Vn
\V0
Connect message type
Report connect message and protocol message
Report connect message only (exclude protocol message)
Report connect and protocol message with both upstream and downstream connect rates.
\V2
\V4
*Note:
Notes:
1. When in autobaud mode, \B0, \B1, and \P1 will not be detected automatically. The combination of \B2 and \P3 will be
detected. This is compatible with seven data bits, no parity, two stop bits. Seven data bits, no parity, one stop bit may be
forced by sending AT\T17\B1.
2. The autobaud feature does not detect this rate.
3. Default is \T16 if a pulldown is connected to pin 16; otherwise, the default is \T9.
Rev. 1.2
31
Si2403
Table 12. Result Codes1
Verbal Response
2
Meaning
X0
X1
X2
X3
X4
X5
Numeric
0
1
Command was successful OK
X
X
X
X
X
X
X
X
X
X
X
X
Link established at 300 bps CONNECT
or higher
2
3
Incoming ring detected
Link dropped
RING
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NO CARRIER
ERROR
4
Command failed
5
Link establish at 1200
Dial tone not present
Line busy
CONNECT 1200
NO DIALTONE
BUSY
6
7
X
9
Ringback detected
Link established at 2400
Caller ID mark detected
RINGING
10
30
31
32
CONNECT 2400
CIDM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hookswitch flash detected FLASH
UK CID State Tone Alert
Signal detected
STAS
3
33
40
Overcurrent condition
Blacklist is full
X
X
X
X
X
X
X
X
X
X
X
X
X
BLACKLIST FULL (enabled
via S42 register)
41
42
43
44
45
Attempted number is black- BLACKLISTED (enabled via
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
listed.
S42 register)
No phone line present
NO LINE (enabled via %Vn
commands)
Telephone line is in use
LINE IN USE (enabled via
%Vn commands)
A polarity reversal was
detected
POLARITY REVERSAL
(enabled via G modifier)
A polarity reversal was NOT NO POLARITY REVERSAL
detected
(enabled via G modifier)
PROTOCOL: NONE
CONNECT 75
70
75
77
80
No protocol
Set with \V command.
Link established at 75
V.42 protocol
MNP2 protocol
X
X
X
X
X
PROTOCOL: V42
Set with \V command.
Set with \V command.
PROTOCOL:
ALTERNATE, + CLASS 2
81
82
MNP3 protocol
MNP4 protocol
PROTOCOL:
ALTERNATE, + CLASS 3
Set with \V command.
Set with \V command.
PROTOCOL:
ALTERNATE, + CLASS 4
102
DTMF dial attempted on a
pulse dial only line
UNOBTAINABLE NUMBER
X
X
X
X
X
X
Notes:
1. The connect messages shown in this table are sent when link negotiation is complete.
2. Numeric result codes are of the format: Result code <CR>.
3. X is the only verbal response code that does not follow the <CR><LF>Result Code<CR><LF> standard. There is no
leading <CR><LF>.
32
Rev. 1.2
Si2403
5. S-Registers
The S command allows reading (Sn?) or writing (Sn=x) the S-registers. The S-registers store values for functions
that, typically, are rarely changed, such as timers or counters, and the ASCII values of control characters, such as
carriage return. Table 13 summarizes the S-register set.
Table 13. S-Register Descriptions
Definition
S-Register
(Decimal)
Function
Default
(Decimal)
Range
Units
0
Automatic answer—Number of rings the Si2403 must
detect before answering a call. 0 disables auto answer.
0
0–255
Rings
1
2
3
4
5
6
Ring counter.
0
0–255
0–255
0–255
0–255
0–255
0–255
Rings
ASCII
ESC code character.
Carriage return character.
Linefeed character.
Backspace character.
43 (+)
13 (CR)
10 (LF)
08 (BS)
02
ASCII
ASCII
ASCII
Dial tone wait timer—Number of seconds the Si2403
waits before blind dialing. Only applicable if blind dial-
ing is enabled (X0, X1, X3).
seconds
7
Carrier wait timer—Number of seconds the Si2403
waits for carrier before timing out. This register also
sets the number of seconds the modem waits for ring-
back when originating a call before hanging up. This
register also sets the number of seconds the answer
80
0–255
seconds
tone will continue while using the AT Y2A command.
*
8
9
Dial pause timer for , and < dial command modifiers.
02
06
0–255
1–255
seconds
Carrier presence timer—Time after a loss of carrier
that a carrier must be detected before reactivating
DCD. S9 is referred to as “carrier loss debounce time.”
0.1 seconds
10
Carrier loss timer—Time the carrier must be lost
before the Si2403 disconnects. Setting 255 disables
disconnect entirely. If S10 is less than S9, even a
momentary loss of carrier causes a disconnect.
14
1–255
0.1 seconds
12
14
24
Escape code guard timer—Minimum guard time
required before and after “+++” for the Si2403 to rec-
ognize a valid escape sequence.
50
12
0
1–255
0–255
0–255
0.02 seconds
seconds
Wait for dial tone delay value (in relation to the W dial
modifier). Starts when “W” is executed in the dial
string.
Sleep Inactivity Time—Sets the time that the modem
operates in normal power mode with no activity on the
serial port, parallel port, or telephone line before enter-
ing low-power sleep mode. This feature is disabled if
the timer is set to 0.
seconds
Rev. 1.2
33
Si2403
Table 13. S-Register Descriptions (Continued)
Definition
S-Register
(Decimal)
Function
Default
(Decimal)
Range
Units
30
Disconnect Activity Timer—Sets the length of time that
the modem stays online before disconnecting with no
activity on the serial port, parallel port, or telephone
line (Ring, hookswitch flash, or caller ID). This feature
is disabled if set to 0.
0
0–255
minutes
38
Hang Up Delay Time—Maximum delay between
receipt of ATH0 command and hang up. If time out
occurs before all data can be sent, the NO CARRIER
(3) result code is sent (operates in V.42 mode only).
“OK” response is sent if all data is transmitted before
timeout. S38 = 255 disables timeout and modem dis-
connects only if data is successfully sent or carrier is
lost.
20
0–255
seconds
40
42
Data Pattern - Data pattern generated during &T4 and
&T5 transmit tests.
0 – All spaces (0s)
1 – All marks (1s)
2 – Random data
0
0–2
0–1
—
—
Blacklisting - The Si2403 will not dial the same number 0 (disabled)
more than three times in three minutes. An attempt to
dial a fourth time within three minutes will result in a
“BLACKLISTED” result code. If the blacklist memory is
full, any dial to a new number will result in a “BLACK-
LIST FULL” result code. Numbers are added to the
blacklist only if the modem connection fails. The %B
command will list the numbers on the blacklists.
0: disabled
1: enabled
43
Dial Attempts to Blacklist.
4
0–4
—
When blacklisting is enabled with S42, this value con-
trols the number of dial attempts that will result in a
number being blacklisted.
44
50
Blacklist Timer.
Period during which blacklisting is active
180
3
0–255
0–255
seconds
seconds
Minimum On-Hook Time—Modem will remain on-hook
for S50 seconds. Any attempt to go off-hook will be
delayed until this timer expires.
51
Number to start checking for an outside line on a PBX.
1
0–9
—
34
Rev. 1.2
Si2403
6. User-Access Registers (U-Registers)
The :U AT command is used to write these 16-bit U-registers, and the :R command is used to read them. U-
registers are identified by a hexidecimal (hex) address.
Table 14. U-Register Descriptions
Register
U00
U01
U02
U03
U04
U05
U06
U07
U08
U09
U0A
U0B
U0C
U0D
U0E
U0F
U10
U11
Name Description
Default
0x0800
0x0000
0x0000
0x0000
0x0000
0x00A0
0x6EF1
0xC4F4
0xC000
0x0000
0x00A0
0x78B0
0xC305
0x4000
0xB50A
0x0400
0x70D2
0xC830
0x4000
0x80E2
0x0009
0x00A0
0x0070
DT1A0 DT1 registers set the coefficients for stage 1 of the Dial Tone Detect filter.
Default is for FCC countries. See “AN70: Si2456/Si2433/Si2414/Si2403
DT1B1
Modem Designer’s Guide” for other country settings.
DT1B2
DT1A2
DT1A1
DT2A0 Dial tone detect filters stage 2 biquad coefficients.
DT2B1
DT2B2
DT2A2
DT2A1
DT3A0 Dial tone detect filters stage 3 biquad coefficients.
DT3B1
DT3B2
DT3A2
DT3A1
DT4A0 Dial tone detect filters stage 4 biquad coefficients.
DT4B1
DT4B2
DT4A2
DT4A1
U12
U13
U14
U15
U16
DTK
Dial tone detect filter output scaler.
DTON Dial tone detect ON threshold.
DTOF Dial tone detect OFF threshold.
Rev. 1.2
35
Si2403
Table 14. U-Register Descriptions (Continued)
Register
Name Description
Default
0x0800
0x0000
0x0000
0x0000
0x0000
0x00A0
0x6EF1
0xC4F4
0xC000
0x0000
0x00A0
0x78B0
0xC305
0x4000
0xB50A
0x0400
0x70D2
0xC830
0x4000
0x80E2
0x0009
0x00A0
0x0070
0x0870
0x25F8
0x0438
0x4650
0xEF10
0x1200
0x1B58
U17
U18
U19
U1A
U1B
U1C
U1D
U1E
U1F
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U2A
U2B
U2C
U2D
U2E
U2F
U30
U31
U32
U33
U34
BT1A0 BT1 registers set the coefficients for stage 1 of the Busy Tone Detect filter.
Default is for FCC countries. See AN70 for other country settings.
BT1B1
BT1B2
BT1A2
BT1A1
BT2A0 Busy tone detect filter stage 2 biquad coefficients.
BT2B1
BT2B2
BT2A2
BT2A1
BT3A0 Busy tone detect filter stage 3 biquad coefficients.
BT3B1
BT3B2
BT3A2
BT3A1
BT4A0 Busy tone detect filter stage 4 biquad coefficients.
BT4B1
BT4B2
BT4A2
BT4A1
BTK
Busy tone detect filter output scaler.
BTON Busy tone detect ON threshold.
BTOF Busy tone detect OFF threshold.
BMTT Busy cadence minimum total time in seconds multiplied by 7200.
BDLT Busy cadence delta in seconds multiplied by 7200.
BMOT Busy cadence minimum on time in seconds multiplied by 7200.
RMTT Ringback cadence minimum total time in seconds multiplied by 7200.
RDLT Ringback cadence delta in seconds multiplied by 7200.
RMOT Ringback cadence minimum on time in seconds multiplied by 7200.
DTWD Window to look for dialtone in seconds multiplied by 1000.
36
Rev. 1.2
Si2403
Table 14. U-Register Descriptions (Continued)
Register
U35
U37
U38
U39
U3A
U3B
U3C
U3D
U3E
U3F
U40
U42
U43
Name Description
DMOT Minimum dialtone on time in seconds multiplied by 7200.
Default
0x2D00
0x000A
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x003D
0x0027
0x0320
0x09B0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Number of pulses to dial 0.
Number of pulses to dial 1.
Number of pulses to dial 2.
Number of pulses to dial 3.
Number of pulses to dial 4.
Number of pulses to dial 5.
Number of pulses to dial 6.
Number of pulses to dial 7.
Number of pulses to dial 8.
Number of pulses to dial 9.
PDBT Pulse dial break time (ms units).
PDMT Pulse dial make time (ms units).
U45
U46
PDIT
Pulse dial interdigit time (ms units).
DTPL DTMF power level—16-bit format is 0x0(H)(L)0 where H is the
(–)dBm level of the high-frequency DTMF tone, and L is the (–)dBm level of
the low-frequency DTMF tone. Note that twist may be specified here.
U47
U48
U49
DTNT DTMF on time (ms units).
DTFT DTMF off time (ms units).
0x0064
0x0064
RGFH Ring frequency high—Maximum frequency ring to be considered a valid ring.
RGFH = 2400/(maximum ring frequency).
0x0022
U4A
RGFD Ring delta
0x007A
1
1
⎛
⎝
⎞
⎠
⎛
⎝
⎞
⎠
----------------------------------------------
-----------------------------------------------
RGFD = 2400Hz ×
–
min ring freq (Hz)
max ring freq (Hz)
U4B
U4C
U4D
U4E
RGMN Ring cadence minimum ON time in seconds multiplied by 2400.
RGNX Ring cadence maximum total time in seconds multiplied by 2400.
MOD1 This is a bit-mapped register.
0x0258
0x6720
0x0000
0x0000
PRDD Pre-dial delay-time after ATD command that modem waits to dial (ms units).
The Si2403 stays on-hook during this time.
U4F
U50
FHT
Flash Hook Time. Time corresponding with “!” or “&” dial modifier that the
Si2403 goes on-hook during a flash hook (ms units).
0x01F4
0x015E
LCDN Loop current debounce on time (ms units).
Rev. 1.2
37
Si2403
Table 14. U-Register Descriptions (Continued)
Register
U51
Name Description
Default
0x00C8
0x0000
LCDF Loop current debounce off time (ms units).
U52
XMTL Transmit level (1 dB units)—Sets the modem data pump transmitter level.
Default level of 0 corresponds to –9.85 dBm.
Transmit level = –(9.85 + XMTL) dBm. Range = –9.85 to –48.
U53
U62
U65
U66
U67
U68
U69
U6A
U6E
U6F
U70
U76
U77
U78
U79
U7A
U7C
U7D
U83
MOD2 This is a bit-mapped register.
DAAC1 This is a bit-mapped register.
DAAC4 This is a bit-mapped register.
DAAC5 This is a bit-mapped register.
0x0000
0x0804
0x00E0
0x0049
0x0008
0x0000
0x0006
n/a
ITC1
ITC2
ITC3
ITC4
CK1
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
This is a bit-mapped register.
0x1F20
0x00FF
0x2700
0x3240
0x401E
0x0000
PTMR This is a bit-mapped register.
IO0 This is a bit-mapped register.
GEN1 This is a bit-mapped register.
GEN2 This is a bit-mapped register.
GEN3 This is a bit-mapped register.
GEN4 This is a bit-mapped register.
GENA This is a bit-mapped register.
GENC This is a bit-mapped register.
GEND This is a bit-mapped register.
0x0000
0x0000
0x0000
0x0001
NOLN No-Line threshold. If %V1 is set, NOLN sets the threshold for determination of
line present vs. line not present.
U84
U85
LIUS
Line-in-use threshold. If %V1 is set, LIUS sets the threshold for determination
of line in use vs. line not in use.
0x0007
0x0000
NLIU
Line-in-use/No line threshold. If %V2 is set, NLIU sets the threshold reference
for the adaptive algorithm (see %V2).
38
Rev. 1.2
Si2403
Table 15. Bit-Mapped U-Register Summary
Reg. Name Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
Bit
5
Bit Bit Bit Bit Bit
15
14
13
12
11
10
9
8
7
6
4
3
2
1
0
TOCT
NHFP NHFD CLPD
FTP SPDM
GT18
GT55
CTE
LLC
LCN
U4D MOD1
U53 MOD2
U62 DAAC1
U65 DAAC4
U66 DAAC5
REV
FOH
DL
PWM PWMG PDN
PDL
FDT
OFF
OHS
ACT
FJM
DCT[1:0]
BTE
RZ
RT
U67
U68
U69
ITC1
ITC2
ITC3
LIM
ROV
BTD
DIAL
VOL
FLVM MODE
OVL
U6A ITC4
U6E CK1
U6F PTME
U70 IO0
R1[4:0]
PTMR[7:0]
HES
TES
CIDM OCDM PPDM
RIM DCDM
FACL
CID
OCD
PPD
RI
DCD
OHSR[6:0]
HOI
DCL[2:0]
ACL[4:0]
U76 GEN1
U77 GEN2
U78 GEN3
U79 GEN4
U7A GENA
U7C GENC
IST[3:0]
AOC
OHT[8:0]
IB[1:0]
IS[7:0]
LVCS[4:0]
DOP
ADD
HDLC FAST
RIGPO
RIG-
POEN
LVFF
LLV AUSDC
ATZD
FDP
U7D GEND
Rev. 1.2
39
Si2403
6.1. Bit-Mapped U-Register Detail (Defaults in Bold)
U4D MOD1
Bit D15 D14 D13 D12
D11
D10 D9 D8
D7
D6
D5
D4
D3
D2 D1
D0
Name
Type
TOCT
R/W
NHFP NHFD CLPD
R/W R/W R/W
FTP SPDM
GT18 GT55 CTE
R/W R/W R/W
LLC LCN
R/W R/W
R/W R/W
Reset settings = 0x0000
Bit
15
14
Name
Reserved Read returns zero.
Function
TOCT
Turn Off Calling Tone.
0 = Disable.
1 = Enable.
13
12
Reserved Read returns zero.
NHFP
NHFD
CLPD
No Hook Flash Pulse.
0 = Disable.
1 = Enable.
11
10
No Hook Flash Dial.
0 = Disable.
1 = Enable.
Check Loop Current Before Dialing.
0 = Ignore.
1 = Check.
9
8
Reserved Read returns zero.
FTP
Force Tone or Pulse.
0 = Disable.
1 = Enable.
7
SPDM
Skip Pulse Dial Modifier.
0 = No.
1 = Yes.
6
5
Reserved Read returns zero.
GT18
GT55
CTE
1800 Hz Guard Tone Enable.
0 = Disable.
1 = Enable.
4
3
2
550 Hz Guard Tone Enable.
0 = Disable.
1 = Enable.
Calling Tone Enable.
0 = Disable.
1 = Enable.
Reserved Read returns zero.
40
Rev. 1.2
Si2403
Bit
Name
Function
1
LLC
Low Loop Current Detect (required for CTR21).
0 = Disabled.
1 = Enabled.
0
LCN
Loop Current Needed.
0 = No.
1 = Yes.
U53 MOD2
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name REV
Type R/W
Reset settings = 0x0000
Bit
Name
Function
15
REV
V.23 Reversing.
0 = Disable.
1 = Enable.
14:0
Reserved Read returns zero.
U62 DAAC1
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
FOH DL
R/W R/W
Reset settings = 0x0804
Bit
15:12 Reserved Must be set to 0.
11 Reserved Must be set to 1.
10:3 Reserved Must be set to 0.
Name
Function
2
FOH
Fast Off-Hook.
0 = Automatic Calibration Time set to 426 ms
1 = Automatic Calibration Time set to 106 ms
1
DL
Isolation Digital Loopback (see the AT&T commands).
0 = Loopback occurs beyond the isolation interface, out to and including the analog
hybrid circuit.
1 = Enables digital loopback mode across isolation barrier only.
0
Reserved Must be set to 0.
Rev. 1.2
41
Si2403
U65 DAAC4
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PWM PWMG PDN
PDL
R/W
Name
Type
R/W
R/W
R/W
Reset settings = 0x00E0
Bit
Name
Function
15
PWM
PWM Mode.
0 = Normal. Classic PWM output waveform.
1 = Scrambled mode. Low-distortion mode if used with output circuit shown in “AN70: Si2456/
Si2433/Si2414/Si2403 Modem Designer’s Guide”.
14
13
PWMG
PDN
PWM Gain.
0 = No gain.
1 = 6 dB gain applied to AOUT.
Powerdown.
Completely powerdown the Si2403 and Si3015. Once set to 1, the Si2403 must be reset to
power on.
0 = Normal.
1 = Powerdown.
12:8 Reserved Read returns zero.
7:5 Reserved
PDL*
Must not change in a read-modify-write.
4
Powerdown Line-Side Chip.
0 = Normal operation.
1 = Places the Si3015 in powerdown mode.
3:0 Reserved
Must not change in a read-modify-write.
*Note: Typically used only for board-level debug.
42
Rev. 1.2
Si2403
U66 DAAC5
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
FDT
R
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0x0049
Bit
15:7 Reserved Read returns zero.
FDT* Frame Detect.
Name
Function
6
0 = Indicates isolation link has not established frame lock.
1 = Indicates isolation link frame lock has been established.
5:4 Reserved Read returns zero.
3:0 Reserved Do not modify.
*Note: Typically used only for board-level debug.
Rev. 1.2
43
Si2403
U67 ITC1
Bit
D15 D14 D13 D12 D11 D10 D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
OFF OHS ACT
R/W R/W R/W
DCT[1:0]
R/W
RZ
RT
R/W R/W
Reset settings = 0x0008
Bit
Name
Function
15:8 Reserved Read returns zero.
7
OFF
DC Termination Off.
0 = Normal operation. The OFF bit must always be set to 0 when on-hook.
1 = DC termination disabled and the device presents an 800 Ω dc impedance to the line,
which is used to enhance operation with an off-hook parallel phone.
6
5
OHS
ACT
On-Hook Speed.
0 = The Si2403 will execute a fast on-hook.
1 = The Si2403 will execute a slow controlled on-hook.
AC Termination Select.
0 = Selects the real impedance.
1 = Selects the complex impedance.
4
Reserved Read returns zero.
3:2
DCT[1:0] DC Termination Select.
00 = Low-voltage mode (Transmit level = –13.85 dBm).
01 = Japan mode (Transmit level = –11.85 dBm).
10 = FCC mode. Standard voltage mode (Transmit level = –9.85 dBm).
11 = CTR21 mode. Current limiting mode (Transmit level = –9.85 dBm).
1
0
RZ
RT
Ringer Impedance.
0 = Maximum (high) ringer impedance.
1 = Synthesize ringer impedance. C15, R14, Z2, and Z3 must not be installed when setting
this bit. See the “Ringer Impedance” section in “AN70: Si2456/Si2433/Si2414/Si2403 Modem
Designer’s Guide”.
Ringer Threshold Select.
Used to satisfy country requirements on ring detection. Signals below the lower level do not
generate a ring detection; signals above the upper level are guaranteed to generate a ring
detection.
0 = 11 to 22 V
.
rms
1 = 17 to 33 V
.
rms
44
Rev. 1.2
Si2403
U68 ITC2
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
LIM
R/W
D3
D2
D1
D0
Name
Type
BTE ROV BTD
R/W R/W R/W
Reset settings = 0x0000
Bit Name
Function
15:8 Reserved
7:5 Reserved
Read returns zero.
Do not modify.
4
LIM
Current Limit.
0 = All other modes.
1 = CTR21 mode.
3
2
Reserved
BTE
Do not modify.
Billing Tone Protect Enable.
0 = Disabled.
1 = Enabled.
When set, the DAA responds automatically to a collapse of the line-derived power supply dur-
ing a billing tone event. When off-hook, if BTE = 1 and BTD goes high, the dc termination is
released (800 Ω presented to line). If BTE and RIM (U70, bit 9) are set, an RI (U70, bit 1)
interrupt also occurs when BTD goes high.
1
0
ROV
BTD
Receive Overload.
The bit is set when the receive input (i.e., receive pin goes below ground) has an excessive
input level. This bit is cleared by writing a 0 to this location.
0 = Normal receive input level.
1 = Excessive receive input level.
Billing Tone Detected.
This bit is set if a billing tone is detected. This bit is cleared by writing a 0 to this location.
0 = No billing tone.
1 = Billing tone detected.
Rev. 1.2
45
Si2403
U69 ITC3
Bit
D15 D14 D13 D12 D11 D10 D9 D8
D7
D6
DIAL FJM VOL FLVM MODE
R/W R/W R/W R/W R/W
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0x0006
Bit
Name
Function
15:8 Reserved
Read returns zero.
7
6
Reserved
DIAL
Do not modify. Must be set to zero.
DTMF Dialing Mode.
This bit should be set during DTMF dialing in CTR21 mode if LVCS < 12.
0 = Normal operation.
1 = Increase headroom for DTMF dialing.
5
4
3
2
FJM
VOL
Force Japan DC Termination Mode.
0 = Normal Gain.
1 = When DCT = 2 (FCC mode), setting this bit forces Japan dc termination mode while allow-
ing for a transmit level of –1 dBm. See the “DTMF Dialing” section in “AN70: Si2456/Si2433/
Si2414/Si2403 Modem Designer’s Guide”.
Line Voltage Adjust.
When set, this bit adjusts the TIP-RING line voltage. Lowering this voltage improves margin in
low-voltage countries. Raising this voltage may improve large-signal distortion performance.
0 = Normal operation.
1 = Lower DCT voltage.
FLVM
MODE
Force Low Voltage Mode.
When DCT (U67, bits 3:2) = 10 (FCC mode), setting FLVM forces the low-voltage mode (see
DCT = 00) while allowing for a transmit level of –1 dBm.
0 = Disable.
1 = Enable.
Mode.
This bit enables on-hook line monitoring. It is automatically set while on-hook and cleared
while off-hook.
1:0 Reserved Do not modify.
46
Rev. 1.2
Si2403
U6A ITC4
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
OVL
R
D1
D0
Name
Type
Reset settings = N/A
Bit
15:3 Reserved
OVL
Name
Function
Read returns zero.
2
Overload Detected.
This bit has the same function as ROV but clears itself after the overload has been removed.
See the “Billing Tone Detection” section in “AN70: Si2456/Si2433/Si2414/Si2403 Modem
Designer’s Guide”. This bit is not affected by the BTE bit.
1:0 Reserved Do not modify.
U6E CK1
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
R1[4:0]
R/W
R/W
Reset settings = 0x1F20
Bit
Name
Function
15:13 Reserved Do not modify.
12:8
7:0
R1*[4:0] R1
CLKOUT Divider
0
R1
CLKOUT off.
R1 + 1 (default R1 = 31; 2.4576 MHz). R1 = 31 required for proper codec
interface operation.
Reserved Do not modify.
Note: See Figure 5 on page 17.
Rev. 1.2
47
Si2403
U6F PTMR
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PTMR[7:0]
R/W
Reset settings = 0x00FF
Bit
Name
Function
15:8 Reserved Do not modify
7:0 PTMR[7:0] Parallel Port Receive FIFO Interrupt Timer (msec units). See “AN70: Si2456/Si2433/Si2414/
Si2403 Modem Designer’s Guide” for more details.
48
Rev. 1.2
Si2403
U70 IO0
Bit
D15 D14 D13 D12
D11
D10
D9
D8
D7 D6 D5 D4
D3
D2
D1
D0
Name HES
Type R/W
TES CIDM OCDM PPDM RIM DCDM
CID OCD PPD RI DCD
R/W R/W R/W R/W R/W
R/W R/W
R/W
R/W R/W R/W
Reset settings = 0x2700
Bit
Name
Function
15
HES
Hardware Escape Pin.
0 = Disable.
1 = Enable.
14
13
Reserved Read returns zero.
TES
CIDM
OCDM
Enable “+++” Escape.
0 = Disable.
1 = Enable.
12
11
Caller ID Mask.
0 = Change in CID will not affect INT.
1 = A low-to-high transition in CID activates INT.
Overcurrent Detect Mask.
0 = Change in OCD does not affect INT. (“X” result code is not generated in command
mode.)
1 = A low-to-high transition in OCD will activate INT. (“X” result code is generated in command
mode.)
10
9
PPDM
RIM
Parallel Phone Detect Mask.
0 = Change in PPD does not affect INT.
1 = A low-to-high transition in PPD will activate INT.
Ring Indicator.
0 = Change in RI does not affect INT.
1 = A low-to-high transition in RI activates INT.
8
DCDM
Data Carrier Detect Mask.
0 = Change in DCD does not affect INT.
1 = A high-to-low transition in DCD (U70, bit 0), which indicates loss of carrier, activates
INT.
7
Reserved Must be set to zero.
6:5 Reserved Read returns zero.
4
3
2
1
CID
OCD
PPD
RI
Caller ID (sticky).
Caller ID preamble has been detected; data will soon follow. Clears on :I read.
Overcurrent Detect (sticky).
Overcurrent condition has occurred. Clears on :I read.
Parallel Phone Detect (sticky).
Parallel phone detected since last off-hook event. Clears on :I read.
Ring Indicator.
Active high bit when the Si2403 is on-hook indicates ring event has occurred. Clears on :I
read.
0
DCD
Data Carrier Detect (status).
Active high bit indicates carrier detected (equivalent to inverse of DCD pin).
Rev. 1.2
49
Si2403
U76 GEN1
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
DCL[2:0]
R/W
D5
D4
D3
D2
ACL[4:0]
R/W
D1
D0
Name
Type
OHSR[6:0]
R/W
FACL
R/W
Reset settings = 0x3240
Bit
Name
Function
15:9 OHSR[6:0] Off-Hook Sample Rate (40 ms units)
Sets the sample rate for the off-hook intrusion algorithms (1 second default).
8
FACL
Force ACL.
0 = While off-hook, ACL is automatically updated with LVCS.
1 = While off-hook, ACL does not change from the value written to it while on-hook.
7:5
4:0
DCL[2:0] Differential Current Level (3 mA units).
Sets the differential level between ACL and LVCS that will trigger an off-hook PPD interrupt
(default = 2).
ACL[4:0] Absolute Current Level (3 mA units, see Figure 7 on page 19).
ACL represents the value of LVCS current when the Si2403 is off-hook and all parallel
phones are on-hook. If ACL = 0, it is ignored by the off-hook intrusion algorithm.The Si2403
will also write ACL with the contents of LVCS before an intrusion and before going on-hook
(default = 0).
50
Rev. 1.2
Si2403
U77 GEN2
Bit
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
OHT[8:0]
R/W
D3
D2
D1
D0
Name
Type
IST[3:0]
R/W
HOI
R/W
AOC
R/W
Reset settings = 0x401E
Bit
Name
IST[3:0] Intrusion Settling Time (250 ms units).
Function
15:12
Delay between the time the Si2403 goes off-hook and the time the off-hook intrusion algo-
rithm begins. Default is 1 s.
11
HOI
Hang-Up On Intrusion.
0 = Si2403 will not automatically hang up when an off-hook PPD interrupt occurs.
1 = Si2403 automatically hangs up on a PPD interrupt. If %Vn commands are set, HOI also
causes the “LINE IN USE” result code upon PPD interrupt.
10
9
Reserved Read returns zero.
AOC
Overcurrent Detection.
Enable Overcurrent Detection.
0 = Disable.
1 = Enable.
Note: AOC may falsely detect an overcurrent condition in the presence of line reversals or other
transients. Therefore, this feature should not be used in applications or locations, such as
Japan, where line reversals are common or may be expected.
8:0
OHT[8:0] Off-Hook Time (1 ms units).
Time before LVCS is checked for overcurrent condition after going off-hook (30 ms default).
Rev. 1.2
51
Si2403
U78 GEN3
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
IS[7:0]
R/W
D3
D2
D1
D0
Name
Type
IB[1:0]
R/W
Reset settings = 0x0000
Bit
Name
Function
15:14
IB[1:0]
Intrusion Blocking.
Defines the method used to block the off-hook intrusion algorithm from operation after dialing
has begun.
0 = No intrusion blocking.
1 = Intrusion disabled from start of dial to end of dial.
2 = Intrusion disabled from start of dial to IS register time-out.
3 = Intrusion disabled from start of dial to connect (“CONNECT XXX”, “NO DIALTONE”, or
“NO CARRIER”).
13:8 Reserved
7:0 IS[7:0]
Read returns zero.
Intrusion Suspend (500 ms units).
When IB = 2, this register sets the length of time, starting when dialing begins, that the off-
hook intrusion algorithm is blocked (suspended) (default = 00000000 ).
b
52
Rev. 1.2
Si2403
U79 GEN4
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
LVCS[4:0]
R
D1
D0
Name
Type
Bit
Name
Function
15:5 Reserved
4:0 LVCS[4:0] Line Voltage Current Sense.
Read returns zero.
Represents either the line voltage, loop current, or on-hook line monitor depending on the
state of the MODE, OFHK, and ONHM bits.
On-Hook Voltage Monitor (2.75 V/bit ±20%) (see Figure 6 on page 19).
00000 = No line connected.
00001 = Minimum line voltage (V
= 3.0 V ± 0.5 V).
MIN
11111 = Maximum line voltage (87 V ± 20%).
The line voltage monitor full scale may be modified by changing R5 as follows:
V
= V
+ 4.2 (10M + R5 + 1.6k)/(R5 +1.6k)/5
MIN
MAX
U69[2] (MODE) must be set to 1 before reading LVCS while the Si2403 is on-hook. See
b
MODE on page 46.
U69[2] (MODE) must be disabled (MODE = 0 ) before the Si2403 can go off-hook, dial, or
b
answer a call.
Off-Hook Loop Current Monitor (3 mA/bit) (see Figure 7 on page 19).
00000 = No loop current.
00001 = Minimum loop current.
11110 = Maximum loop current.
11111 = Loop current is excessive (overload).
Overload > 140 mA in all modes except CTR21
Overload > 54 mA in CTR21 mode
Rev. 1.2
53
Si2403
U7A GENA
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
HDLC FAST
R/W R/W
D0
Name
DOP ADD
R/W R/W
Type
Reset settings = 0x0000
Bit
Name
Function
15:8 Reserved Read returns to zero.
7
6
DOP
ADD
Dial or Pulse.
0 = Normal ATDTW operation
1 = Use ATDTW for Pulse/Tone Dial Detection (see also ATDW command)
Adaptive Dialing.
1 = Enable
0 = Disable
Attempt DTMF dial, then fall back to pulse dialing if unsuccessful. First digit is dialed as
DTMF. If a dialtone is still present after two seconds, the Si2403 will redial the first digit and
remaining digits as pulse. If a dialtone is not present after two seconds, the Si2403 will dial
the remaining digits as DTMF.
5:2
1
Reserved Read returns to zero.
HDLC
Synchronous Mode.*
0 = Normal asynchronous mode.
1 = Transparent HDLC mode.
0
FAST
Fast Connect.*
0 = Normal modem handshake timing per ITU/Bellcore standards.
1 = Fast connect modem handshake timing.
*Note: When V22HD, HDLC, or FAST bits are set, \N0 (wire mode) must be used.
54
Rev. 1.2
Si2403
U7C GENC
Bit
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D4
D3
D2
D1
D0
RIGPO
RIGPOEN
Name
R
R/W
Type
Reset settings = 0x0000
Bit
Name
Function
15:5 Reserved Reads returns to zero.
4
RIGPO
RI.
RI (pin 15), follows this bit when RIGPIOEN = 1 .
b
3:1
0
Reserved Reads returns to zero.
RIGPOEN 0 = RI indicates valid ring signal (Normal ring-indicator mode).
1 = RI (Pin 15) can be used as a general-purpose output and follows U7C[4] (RIGPO).
Rev. 1.2
55
Si2403
U7D GEND
Bit
D15 D14 D13 D12 D11 D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
LVFE
R/W
LLV AUSDC
ATZD FDP
R/W R/W
Name
R/W
R/W
Type
Reset settings = 0x0000
Bit Name
15:14 Reserved Reads returns to zero.
Function
13
LVFE
LVCS Filter Enable.
0 = Normal operation
1 = Enables optional filtering on LVCS to mitigate the effect of 50/60 Hz noise on tip/ring volt-
age.
12:11 Reserved Read returns zero.
10
LLV
0 = Normal operation.
1 = Enables an optional algorithm for countries, such as Japan and Malaysia, with low loop
voltage. Also set U67[3:2] (DCT) = 00 , U69[4] VOL = 1 , and U52 = 0x0002 before going off-
b
b
hook. When the modem goes off-hook, it samples LVCS and changes DCT and VOL as nec-
essary to maximize transmit levels and optimize distortion.
9
AUSDC 0 = Normal operation.
1 = Causes the modem to go off-hook in Japan mode and then revert to FCC mode after
500 ms. This allows the modem to meet the Australian line seizure requirements while allow-
ing the maximum transmit power (optional for Australia and when DCT = 01 ).
b
8:2
1
Reserved Reads returns to zero.
ATZD
ATZ Disable.
0 = ATZ functions normally.
1 = Disable ATZ command. This may be used to ensure modem settings are not lost in some
systems.
0
FDP
FSK Data Processing.
0 = FSK data processing stops when carrier is lost.
1 = FSK data processing continued for 2 bytes after carrier is lost.
56
Rev. 1.2
Si2403
7. Parallel Interface Registers
Parallel Interface 0 (0x00)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TX/RX
R/W
Reset settings = 0x00
Bit
Name
Function
7:0
TX/RX
Parallel Interface Transmit/Receive.
This register functions similarly to the serial port TX pin on writes to the parallel port, and sim-
ilarly to the serial port RX pin on reads from the parallel port.
Rev. 1.2
57
Si2403
Parallel Interface 1 (0x01)
Bit
D7
RXF
R
D6
TXE
R
D5
REM
R
D4
D3
INT
R
D2
D1
D0
CTS
R
Name
Type
INTM
R/W
ESC
R/W
RTS
R/W
Reset settings = 0110_0011
Bit
Name
Function
7
RXF
Receive FIFO Almost Full (status).
0 = Receive FIFO (12 deep) contains three or more empty locations (RXF ≤ 9). The host can
clear the RXF interrupt without emptying the RX FIFO by writing a 0 to the RXF bit. This will
disable the RXF interrupt until the host has emptied the FIFO.
1 = Receive FIFO contains two or fewer empty locations (RXF ≥ 10).
6
5
TXE
Transmit FIFO Almost Empty (status).
0 = Transmit FIFO (14 deep) contains three or more characters (TXF ≥ 3).
1 = Transmit FIFO contains two or fewer characters (TXF ≤ 2). TXE interrupt will not trigger if
the CTS bit is inactive. Therefore, the host does not need to poll CTS while waiting for trans-
mit FIFO to empty. TXE can be cleared by writing it to 0.
REM
Receive FIFO Empty.
0 = Receive FIFO has valid data.
1 = Receive FIFO empty.
Note: If the interim timer (see PTMR - U6F, bits 7:0) set by PTMR expires, it will cause an interrupt. This
interrupt will not set RXF, TXE, or INT. The interrupt handler on the host should then verify that
REM = 0 and begin to empty the receive FIFO (Parallel Interface 0 register) until REM = 1.
4
3
INTM
INT
Interrupt Mask.
0 = In parallel mode, the INT pin is triggered by a rising edge on RXF or TXE only (default).
1 = In parallel mode, the INT pin is triggered by a rising edge on RXF, TXE, or INT.
Interrupt.
0 = No interrupt has occurred.
1 = Indicates that an interrupt (CID, OCD, PPD, RI, or DCD from U70) has occurred. This bit is
cleared via the AT:I command.
2
1
ESC
RTS
Escape.
Operation of this bit in parallel mode is functionally-equivalent to the ESC pin in serial mode.
Request-to-Send.
Operation of this bit in parallel mode is functionally equivalent to the RTS pin in serial mode.
Use of the CTS and RTS bits (as opposed to the TXE and RXF bits) allows the flow control
between the host and the Si2403 to operate 1 byte at a time rather than in blocks.
0
CTS
Clear-to-Send.
Operation of this bit in parallel mode is functionally-equivalent to the CTS pin in serial mode.
Use of the CTS and RTS bits (as opposed to the TXE and RXF bits) allows the flow control
between the host and the Si2403 to operate 1 byte at a time, rather than in blocks.
58
Rev. 1.2
Si2403
8. Pin Descriptions: Si2403
24
23
22
21
CLKIN/XTALI
XTALO
EECLK/D5
1
2
3
DCD/D4
ESC/D3
CLKOUT/EECS/A0
D6
VD3.3
GND
C1A
4
5
ISOB
VD3.3
GND
20
19
6
7
8
9
VDA
18
17
RTS/D7
VDB
16
15
14
EESD/D2
RI/D1
RXD/RD
TXD/WR
CTS/CS
10
11
12
INT/D0
AOUT/INT
13
RESET
Pin #
Pin Name
Description
1
CLKIN/XTALI
Clock Input/Crystal Oscillator Pin.
This pin provides support for parallel-resonant, AT-cut crystals. XTALI also acts
as an input in the event that an external clock source is used in place of a crystal.
A 4.9152 MHz crystal or 4.9152 MHz clock is required.
2
3
XTALO
Crystal Oscillator Pin.
This pin provides support for parallel-resonant AT-cut crystals. XTALO serves as
the output of the crystal amplifier.
CLKOUT/EECS/A0 Clock Output/EEPROM Chip Select/Address Bit 0.
Clock output in serial mode. Active low read/write enable for SPI EEPROM in
serial mode when pin 4 is pulled low during powerup. Address Enable in parallel
mode.
4
D6
VD3.3
Data Bit.
Bidirectional parallel bus data bit 6 in parallel mode.
5, 19
6, 18
7,17
8
Digital Supply Voltage.
Provides the 3.3 V digital supply voltage to the Si2403.
GND
Ground.
Connects to the system digital ground.
VDA, VDB
RTS/D7
Digital Rail.
Pin provides decoupling for the internal power supplies.
Request-to-Send/Data Bit.
Request-to-send (for flow control) in serial mode. Bidirectional parallel bus data
bit 7 in parallel mode.
9
RXD/RD
Receive Data/Read Enable.
Data output to DTE RXD pin in serial mode. Active low read enable pin in parallel
mode.
Rev. 1.2
59
Si2403
Pin #
Pin Name
Description
10
TXD/WR
Transmit Data/Write Enable.
Data input from DTE TXD pin in serial mode. Active low write-enable pin in paral-
lel mode.
11
12
CTS/CS
RESET
Clear-to-Send/Chip Select.
Active low clear-to-send (for flow control) in serial mode. Active low chip select in
parallel mode.
Reset Input.
An active low input that is used to reset all control registers to a defined initialized
state.
13
14
AOUT/INT
INT/D0
Analog Output/Interrupt Output.
Analog output in serial mode. Active low interrupt output in parallel mode.
Interrupt Output/Data Bit.
Active low interrupt output in serial mode. Bidirectional parallel bus data bit 0 in
parallel mode.
15
16
RI/D1
Ring Indicator/Data Bit.
The RI on (active low) indicates the presence of an ON segment of a ring signal
on the telephone line. Bidirectional parallel bus data bit 1 in parallel mode.
EESD/D2
EEPROM Serial Data Input/Output/Data Bit.
Bidirectional Input/Output to SPI EEPROM in serial mode. Bidirectional parallel
bus data bit 2 in parallel mode.
20
21
22
ISOB
C1A
Bias Voltage.
This pin provides decoupling for the power supply.
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor, C1.
ESC/D3
Escape/Data Bit.
Hardware escape in serial mode. Bidirectional parallel bus data bit 3 in parallel
mode.
23
24
DCD/D4
Carrier Detect/Data Bit.
Active low-carrier detect in serial mode. Bidirectional parallel bus data bit 4 in par-
allel mode.
EECLK/D5
EEPROM Clock/Data Bit.
Clock output for SPI EEPROM in serial mode. Bidirectional parallel bus data bit 5
in parallel mode.
60
Rev. 1.2
Si2403
9. Pin Descriptions: Si3015
1
2
3
4
QE2
DCT
IGND
C1B
16
15
FILT2
FILT
RX
14
13
REXT
REXT2
RNG1
RNG2
12
11
5
6
7
REF
QB
QE
10
9
VREG2
VREG
8
Pin #
Pin Name
Description
1
QE2
Transistor Emitter 2.
Connects to the emitter of Q4.
2
3
4
5
DCT
IGND
C1B
DC Termination.
Provides dc termination to the telephone network.
Isolated Ground.
Connects to ground on the line-side interface. Also connects to capacitor C2.
Isolation Capacitor 1B.
Connects to one side of isolation capacitor C1.
RNG1
Ring 1.
Connects through a capacitor to the TIP lead of the telephone line. Provides the ring
and caller ID signals to the modem.
6
RNG2
Ring 2.
Connects through a capacitor to the RING lead of the telephone line. Provides the ring
and caller ID signals to the modem.
7
8
QB
QE
Transistor Base.
Connects to the base of transistor Q3.
Transistor Emitter.
Connects to the emitter of transistor Q3.
9
VREG
VREG2
REF
Voltage Regulator.
Connects to an external capacitor to provide bypassing for an internal power supply.
10
11
12
Voltage Regulator 2.
Connects to an external capacitor to provide bypassing for an internal power supply.
Reference.
Connects to an external resistor to provide a high-accuracy reference current.
REXT2
External Resistor 2.
Sets the complex ac termination impedance.
Rev. 1.2
61
Si2403
Pin #
Pin Name
Description
13
REXT
External Resistor.
Sets the real ac termination impedance.
14
15
16
RX
Receive Input.
Serves as the receive side input from the telephone network.
FILT
FILT2
Filter.
Provides filtering for the dc termination circuits.
Filter 2.
Provides filtering for the bias circuits.
62
Rev. 1.2
Si2403
10. Ordering Guide
Chipset
Si2403
Si2403
Description
Digital
Line
Temperature
Commercial
Si2403-KT
Si2403-FT
Si3015-KS
Si3015-F-FS
0 to 70 °C
0 to 70 °C
Commercial Pb-free
Rev. 1.2
63
Si2403
11. Package Outline: 24-Pin TSSOP
Figure 8 illustrates the package details for the Si2403. Table 16 lists the values for the dimensions shown in the
illustration.
E
H
θ
L
B
D
A
e
A1
C
γ
Approximate device weight is 115.7 mg.
Figure 8. 24-Pin Thin Shrink Small Outline Package (TSSOP)
Table 16. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
1.20
0.15
0.30
0.20
7.90
4.50
Typical*
A
A1
B
3
3
0.05
0.19
0.09
7.70
C
3
D
E
e
H
L
θ
4.30
0.65 BSC
6.40 BSC
0.45
0°
0.75
8°
3
γ
0.10
*Note: To guarantee coplanarity (γ), the
parameters marked “Typical” may be
exceeded.
64
Rev. 1.2
Si2403
12. Package Outline: 16-Pin SOIC
Figure 9 illustrates the package details for the Si3015. Table 17 lists the values for the dimensions shown in the
illustration.
16
9
8
h
E
H
0.010
GAUGE PLANE
θ
1
L
B
Detail F
D
C
A
A1
e
See Detail F
γ
Seating Plane
Figure 9. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 17. Package Diagram Dimensions
Millimeters
Symbol
Typical*
Min
Max
A
A1
B
C
D
E
e
1.35
1.75
3
3
.10
.33
.25
.51
.19
.25
3
9.80
3.80
1.27 BSC
5.80
.25
10.00
4.00
—
H
h
6.20
.50
L
.40
1.27
0.10
8º
γ
—
θ
0º
3
*Note: Typical parameters are for information
purposes only.
Rev. 1.2
65
Si2403
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
ꢀ Updated "Functional Block Diagram" on page 1.
ꢀ Updated Table 6 on page 8.
ꢀ Expanded “+GCI country codes” in Table 8 on page 21.
ꢀ Updated S-registers S43 and S44 in Table 13 on page 33.
ꢀ Updated default register value for U66.
ꢀ Updated U-register U7D.
Revision 1.1 to Revision 1.2
ꢀ Updated "Ordering Guide" on page 63.
ꢀ Updated Table 8 on page 21.
ꢁ Updated description of I3 command.
66
Rev. 1.2
Si2403
NOTES:
Rev. 1.2
67
Si2403
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: ISOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and ISOmodem are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
68
Rev. 1.2
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