SI3050-E1-GMR [SILICON]
Consumer Circuit, QFN-24;
| 型号： | SI3050-E1-GMR |
| 厂家： | 
SILICON |
| 描述： | Consumer Circuit, QFN-24 商用集成电路 |
| 文件： | 总128页 (文件大小：2742K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3050+Si3011/18/19
PROGRAMMABLE VOICE DAA SOLUTIONS
Features
PCM highway data interface
TIP/RING polarity detection
Integrated codec and 2- to 4-wire
analog hybrid
µ-law/A-law companding
SPI control interface
GCI interface
80 dB dynamic range TX/RX
Line voltage monitor
Loop current monitor
+6 dBm or +3.2 dBm TX/RX level
mode
Parallel handset detection
3 µA on-hook line monitor current
Overload detection
Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
Programmable digital hybrid for
near-end echo reduction
Polarity reversal detection
Programmable digital gain in 0.1 dB
increments
Integrated ring detector
Type I and II caller ID support
Pulse dialing support
3.3 V power supply
Daisy-chaining for up to 16 devices
Greater than 5000 V isolation
Patented isolation technology
Ground start and loop start support
Available in Pb-free RoHS-compliant
packages
Ordering Information
See page 106.
Applications
DSL IADs
VoIP gateways
PBX and IP-PBX systems
Voice mail systems
DECT base stations
Package Options
Si3050
Description
CS
FSYNC
PCKLK
DTX
1
2
3
4
5
6
18
17
16
15
14
13
GND
VDD
VA
The Si3050+Si3011/18/19 Voice DAA chipset provides a highly-programmable
and globally-compliant foreign exchange office (FXO) analog interface. The
solution implements Silicon Laboratories' patented isolation capacitor technology,
which eliminates the need for costly isolation transformers, relays, or
opto-isolators, while providing superior surge immunity for robust field
performance. The Voice DAA is available as a chipset, a system-side device
(Si3050) paired with a line-side device (Si3011/18/19). The Si3050 is available in
a 20-pin TSSOP or a 24-pin QFN. The Si3011/18/19 is available in a 16-pin
TSSOP, a 16-pin SOIC, or a 20-pin QFN and requires minimal external
components. The Si3050 interfaces directly to standard telephony PCM
interfaces.
Si3050
Top View
C1A
DRX
C2A
GND
RGDT
RESET
Si3011/18/19
Functional Block Diagram
1
2
20
19
18
17 16
15 DCT3
Si3050
Si3018/19
NC
RX
IB
CS
SCLK
RX
Control
Data
Interface
3
4
14
13
QB
SDI
IB
SC
DCT
VREG
IGND
PAD
Hybrid, AC
and DC
Terminations
SDO
SDI THRU
QE2
C1B
C2B
VREG2
DCT2
PCLK
DTX
Isolation
Interface
Isolation
Interface
Line
Data
Interface
5
6
12 SC
11 NC
DCT3
DRX
7
8
9
10
RNG1
RNG2
QB
QE
QE2
FSYNC
Ring Detect
Off-Hook
RGDT
RG
Control
Logic
TGD
TGDE
RESET
AOUT/INT
US Patent# 5,870,046
US Patent# 6,061,009
Rev. 1.5 10/11
Copyright © 2011 by Silicon Laboratories
Si3050 + Si3011/18/19
Si3050 + Si3011/18/19
2
Rev. 1.5
Si3050 + Si3011/18/19
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. AOUT PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.1. Line-Side Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.2. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.3. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.4. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.5. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.6. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.7. In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.8. Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.9. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.10. Transmit/Receive Full-Scale Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.11. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.12. Line Voltage/Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.13. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.14. Ground Start Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.15. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.16. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.17. AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.18. Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.19. Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.20. Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.21. Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.22. Receive Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.23. Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.24. On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.25. Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.26. Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.27. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.28. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.29. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.30. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.31. Communication Interface Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.32. PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
5.33. Companding in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.34. 16 kHz Sampling Operation in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.35. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.36. GCI Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Rev. 1.5
3
Si3050 + Si3011/18/19
5.37. Companding in GCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.38. 16 kHz Sampling Operation in GCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.39. Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.40. Summary of Monitor Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.41. Device Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.42. Command Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.43. Register Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.44. SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.45. Receive SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.46. Transmit SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
7. Pin Descriptions: Si3011/18/19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
9. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10. Package Outline: 20-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
10.1. PCB Land Pattern: Si3050 TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
11. Package Outline: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12. PCB Land Pattern: Si3050 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
13. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
13.1. PCB Land Pattern: Si3011/18/19 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14. Package Outline: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
14.1. PCB Land Pattern: Si3011/18/19 TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
15. Package Outline: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
16. PCB Land Pattern: Si3011/18/19 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Silicon Labs Si3050 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
4
Rev. 1.5
Si3050 + Si3011/18/19
1. Electrical Specifications
Table 1. Recommended Operating Conditions and Thermal Information
1
2
2
Symbol
Test Condition
F-Grade
Typ
25
Unit
°C
Parameter
Min
Max
70
85
3.6
—
0
Ambient Temperature
T
A
G-Grade
–40
3.0
—
25
Si3050 Supply Voltage, Digital
V
3.3
77
V
D
SOIC-16
TSSOP-16
QFN-20
JA
3
Thermal Resistance (Si3011/18/19)
—
89
—
°C/W
°C/W
—
120
84
—
TSSOP-20
QFN-24
—
—
JA
3
Thermal Resistance (Si3050)
—
67
—
Notes:
1. The Si3050 specifications are guaranteed when the typical application circuit (including component tolerance) and any
Si3050 and any Si3011/18/19 are used. See "2. Typical Application Schematic" on page 17 for the typical application
circuit.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. Operation above 125 °C junction temperature may degrade device reliability.
Rev. 1.5
5
Si3050 + Si3011/18/19
Table 2. Loop Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, see Figure 1 on page 6)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Termination Voltage
V
V
V
V
V
V
V
I = 20 mA, ILIM = 0
DCV = 00, MINI = 11, DCR = 0
—
—
6.0
V
TR
TR
TR
TR
TR
TR
TR
L
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
I = 120 mA, ILIM = 0
9
—
—
—
—
—
—
—
7.5
—
V
V
V
V
V
V
L
DCV = 00, MINI = 11, DCR = 0
I = 20 mA, ILIM = 0
—
9
L
DCV = 11, MINI = 00, DCR = 0
I = 120 mA, ILIM = 0
L
DCV = 11, MINI = 00, DCR = 0
I = 20 mA, ILIM = 1
—
40
—
7.5
—
L
DCV = 11, MINI = 00, DCR = 0
I = 60 mA, ILIM = 1
L
DCV = 11, MINI = 00, DCR = 0
I = 50 mA, ILIM = 1
40
L
DCV = 11, MINI = 00, DCR = 0
On-Hook Leakage Current
Operating Loop Current
Operating Loop Current
DC Ring Current
I
I
I
V
= –48 V
TR
—
10
10
—
—
—
5
120
60
3
µA
mA
mA
µA
LK
LP
LP
MINI = 00, ILIM = 0
MINI = 00, ILIM = 1
—
dc current flowing through ring
detection circuitry
1.5
*
Ring Detect Voltage
V
V
V
RT2 = 0, RT = 0
RT2 = 0, RT = 1
RT2 = 1, RT = 1
13.5
19.35
40.5
13
15
21.5
45
16.5
23.65
49.5
68
V
V
V
RD
RD
RD
rms
rms
rms
*
Ring Detect Voltage
*
Ring Detect Voltage
Ring Frequency
F
—
Hz
R
Ringer Equivalence Number
REN
—
—
0.2
*Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected
above the maximum.
TIP
+
600
IL
Si3011/18/19
VTR
10F
–
RING
Figure 1. Test Circuit for Loop Characteristics
6
Rev. 1.5
Si3050 + Si3011/18/19
Table 3. DC Characteristics, VD = 3.0 to 3.6 V
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
1
High Level Input Voltage
V
IH
1
Low Level Input Voltage
V
—
0.8
—
V
IL
High Level Output Voltage
Low Level Output Voltage
AOUT High Level Voltage
AOUT Low Level Voltage
Input Leakage Current
V
I = –2 mA
2.4
—
—
V
OH
O
V
I = 2 mA
—
0.35
—
V
OL
O
V
I = 10 mA
2.4
—
—
V
AH
O
V
I = 10 mA
—
0.35
10
V
AL
O
I
–10
—
—
µA
mA
mA
mA
L
2
Power Supply Current, Digital
I
V pin
8.5
5.0
1.3
10
D
D
2
Total Supply Current, Sleep Mode
I
PDN = 1, PDL = 0
PDN = 1, PDL = 1
—
6.0
1.5
D
D
2,3
Total Supply Current, Deep Sleep
I
—
Notes:
1. VIH/VIL do not apply to C1A/C2A.
2. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
3. RGDT is not functional in this state.
Rev. 1.5
7
Si3050 + Si3011/18/19
Table 4. AC Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, Fs = 8000 Hz, see "2. Typical Application Schematic" on page 17)
Parameter
Symbol
Fs
Test Condition
Min
8
Typ
—
Max
16
8192
—
Unit
kHz
kHz
Hz
Sample Rate
PCLK Input Frequency
Receive Frequency Response
Receive Frequency Response
PCLK
256
—
—
—
—
—
—
—
—
—
—
Low –3 dBFS Corner, FILT = 0
Low –3 dBFS Corner, FILT = 1
FULL = 0 (0 dBm)
5
200
1.1
1.58
2.16
1.1
1.58
2.16
80
—
Hz
V
V
—
V
FS
FS
PEAK
PEAK
PEAK
PEAK
PEAK
1
2
Transmit Full-Scale Level
FULL = 1 (+3.2 dBm)
—
V
V
V
V
V
2
FULL2 = 1 (+6.0 dBm)
—
FULL = 0 (0 dBm)
—
1,3
2
Receive Full-Scale Level
FULL = 1 (+3.2 dBm)
—
2
FULL2 = 1 (+6.0 dBm)
—
PEAK
DR
DR
ILIM = 0, DCV = 11, MINI=00
—
dB
4,5,6
Dynamic Range
DCR = 0, I = 100 mA
L
ILIM = 0, DCV = 00, MINI=11
—
—
—
—
—
—
80
80
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
4,5,6
Dynamic Range
DCR = 0, I = 20 mA
L
DR
ILIM = 1, DCV = 11, MINI=00
4,5,6
Dynamic Range
DCR = 0, I = 50 mA
L
THD
THD
THD
THD
ILIM = 0, DCV = 11, MINI=00
–72
–78
–78
–78
Transmit Total Harmonic
6,7
Distortion
DCR = 0, I = 100 mA
L
ILIM = 0, DCV = 00, MINI=11
Transmit Total Harmonic
6,7
Distortion
DCR = 0, I = 20 mA
L
ILIM = 0, DCV = 00, MINI=11
Receive Total Harmonic
6,7
Distortion
DCR = 0, I = 20 mA
L
ILIM = 1,DCV = 11, MINI=00
Receive Total Harmonic
6,7
Distortion
DCR = 0, I = 50 mA
L
Notes:
1. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1 on page 6.
2. With FULL = 1, the transmit and receive full-scale level of +3.2 dBm can be achieved with a 600 ac termination.
While the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV
into all reference impedances. With FULL2 = 1, the transmit and receive full-scale level of +6.0 dBm can be achieved
with a 600 termination. In this mode, the DAA will transmit and receive +1.5 dBV into all reference impedances.
3. Receive full-scale level produces –0.9 dBFS at DTX.
4. DR = 20 x log (RMS VFS/RMS Vin) + 20 x log (RMS Vin/RMS noise). The RMS noise measurement excludes
harmonics. Here, VFS is the 0 dBm full-scale level per Note 1 above.
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin = 1 kHz, –3 dBFS.
7. THD = 20 x log (RMS distortion/RMS signal).
8. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log (RMS VIN/RMS noise). VCID is the 1.5 V full-scale level with the
enhanced caller ID circuit. With the typical CID circuit, the VCID full-scale level is 6 V peak, and the DRCID decreases to
50 dB.
9. Refer to Tables 10–11 for relative gain accuracy characteristics (passband ripple).
10. Analog hybrid only. ZACIM controlled by ACIM in Register 30.
8
Rev. 1.5
Si3050 + Si3011/18/19
Table 4. AC Characteristics (Continued)
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, Fs = 8000 Hz, see "2. Typical Application Schematic" on page 17)
Parameter
Symbol
DR
Test Condition
Min
—
Typ
62
1.5
0
Max
—
Unit
8
Dynamic Range (Caller ID mode)
VIN = 1 kHz, –13 dBFS
dB
CID
8
Caller ID Full-Scale Level
V
—
—
V
PEAK
CID
2-W to DTX,
TXG2, RXG2, TXG3,
and RXG3 = 0000
–0.5
0.5
dB
6,9
Gain Accuracy
10
Transhybrid Balance
300–3.4 kHz, ZACIM = ZLINE
1 kHz, ZACIM = ZLINE
20
—
25
—
30
—
—
—
—
dB
dB
dB
10
Transhybrid Balance
300–3.4 kHz, all ac
terminations
Two-Wire Return Loss
Two-Wire Return Loss
1 kHz, all ac terminations
—
32
—
dB
Notes:
1. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1 on page 6.
2. With FULL = 1, the transmit and receive full-scale level of +3.2 dBm can be achieved with a 600 ac termination.
While the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV
into all reference impedances. With FULL2 = 1, the transmit and receive full-scale level of +6.0 dBm can be achieved
with a 600 termination. In this mode, the DAA will transmit and receive +1.5 dBV into all reference impedances.
3. Receive full-scale level produces –0.9 dBFS at DTX.
4. DR = 20 x log (RMS VFS/RMS Vin) + 20 x log (RMS Vin/RMS noise). The RMS noise measurement excludes
harmonics. Here, VFS is the 0 dBm full-scale level per Note 1 above.
5. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.
6. Vin = 1 kHz, –3 dBFS.
7. THD = 20 x log (RMS distortion/RMS signal).
8. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log (RMS VIN/RMS noise). VCID is the 1.5 V full-scale level with the
enhanced caller ID circuit. With the typical CID circuit, the VCID full-scale level is 6 V peak, and the DRCID decreases to
50 dB.
9. Refer to Tables 10–11 for relative gain accuracy characteristics (passband ripple).
10. Analog hybrid only. ZACIM controlled by ACIM in Register 30.
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
–0.5 to 3.6
±10
Unit
V
DC Supply Voltage
V
D
Input Current, Si3050 Digital Input Pins
Digital Input Voltage
I
mA
V
IN
V
–0.3 to (V + 0.3)
IND
D
Ambient Operating Temperature Range
Storage Temperature Range
T
–40 to 100
–65 to 150
°C
°C
A
T
STG
Note: Permanent device damage can occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods might affect device reliability.
Rev. 1.5
9
Si3050 + Si3011/18/19
Table 6. Switching Characteristics—General Inputs
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
1
Symbol
Min
Typ
Max
Unit
Parameter
Cycle Time, PCLK
PCLK Duty Cycle
PCLK Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
PCLK Before RESET
t
0.12207
40
—
50
—
—
—
—
—
—
—
3.90625
s
%
p
t
60
2
dty
t
—
ns
jitter
t
—
25
25
—
—
—
25
ns
r
t
—
ns
f
2
t
10
cycles
ns
mr
3
RESET Pulse Width
t
250
20
rl
CS, SCLK Before RESET
Rise Time, Reset
Notes:
t
ns
mxr
t
—
ns
r
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC/PCLK relationship must be fixed after RESET
3. The minimum RESET pulse width is the greater of 250 ns or 10 PCLK cycle times.
tr
tp
tf
VIH
VIL
PCLK
RESET
tmr
trl
CS, SCLK
tmxr
Figure 2. General Inputs Timing Diagram
10
Rev. 1.5
Si3050 + Si3011/18/19
Table 7. Switching Characteristics—Serial Peripheral Interface
(VIO = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter*
Test
Conditions
Symbol
Min
Typ
Max
Unit
Cycle Time SCLK
t
61.03
—
—
—
—
—
—
—
25
25
20
20
ns
ns
ns
ns
ns
c
Rise Time, SCLK
t
r
Fall Time, SCLK
t
—
f
Delay Time, SCLK Fall to SDO Active
t
t
—
d1
d2
Delay Time, SCLK Fall to SDO
Transition
—
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
t
—
25
20
25
20
220
—
—
—
—
—
—
—
6
20
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
d3
t
su1
Hold Time, SCLK to CS Rise
t
h1
Setup Time, SDI to SCLK Rise
Hold Time, SCLK Rise to SDI Transition
Delay time between chip selects
Propagation Delay, SDI to SDITHRU
t
su2
t
h2
t
cs
*Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
tr
t
f
tc
SCLK
CS
tsu1
th1
tcs
tsu2
th2
SDI
td2
td3
td1
SDO
Figure 3. SPI Timing Diagram
Rev. 1.5
11
Si3050 + Si3011/18/19
Table 8. Switching Characteristics—PCM Highway Serial Interface
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
1
Test
Conditions
Parameter
Symbol
Min
Typ
Max
Units
Cycle Time PCLK
Valid PCLK Inputs
tp
122
—
3906
ns
—
—
—
—
—
—
—
—
256
512
768
1.024
1.536
2.048
4.096
8.192
—
—
—
—
—
—
—
—
kHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
FSYNC Period2
tfp
tdty
tjitter
tjitter
tr
—
40
—
—
—
—
—
—
—
25
20
25
20
125
50
—
—
—
—
—
—
—
—
—
—
—
—
60
2
s
%
PCLK Duty Cycle
PCLK Jitter-Tolerance
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FSYNC Jitter Tolerance
±120
25
25
20
20
20
—
Rise Time, PCLK
Fall Time, PCLK
tf
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
Delay Time, PCLK Rise to DTX Tri-State3
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
Notes:
td1
td2
td3
tsu1
th1
tsu2
th2
—
—
—
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and fall
times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC must be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.
tp
PCLK
th1
tfp
tsu1
FSYNC
tsu2
th2
DRX
DTX
td1
td3
td2
Figure 4. PCM Highway Interface Timing Diagram (RXS = TXS = 1)
12
Rev. 1.5
Si3050 + Si3011/18/19
Table 9. Switching Characteristics—GCI Highway Serial Interface
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
1
Test
Conditions
Parameter
Symbol
Min
Typ
Max
Units
Cycle Time PCLK (Single Clocking Mode)
Cycle Time PCLK (Double Clocking Mode)
Valid PCLK Inputs
t
t
—
—
488
244
—
—
ns
ns
p
p
—
—
2.048
4.096
—
—
MHz
MHz
2
FSYNC Period
t
—
40
—
—
—
—
—
—
—
25
20
25
20
125
50
—
—
—
—
—
—
—
—
—
—
—
—
60
2
µs
%
fp
PCLK Duty Cycle
t
dty
PCLK Jitter Tolerance
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
jitter
jitter
FSYNC Jitter Tolerance
Rise Time, PCLK
±120
25
25
20
20
20
—
t
r
Fall Time, PCLK
t
f
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
t
t
t
d1
d2
d3
3
Delay Time, PCLK Rise to DTX Tri-State
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
Notes:
t
su1
t
—
h1
t
—
su2
t
—
h2
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and fall
times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC must be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.
tr
tf
tp
PCLK
th1
t su1
tfp
FSYNC
DRX
t su2
t
h2
t d1
t d2
td3
DTX
Figure 5. GCI Highway Interface Timing Diagram (1x PCLK Mode)
Rev. 1.5
13
Si3050 + Si3011/18/19
tr
tf
PCLK
tfp
th1
tsu2
FSYNC
tsu2
th2
DRX
td2
td1
td3
DTX
Figure 6. GCI Highway Interface Timing Diagram (2x PCLK Mode)
Table 10. Digital FIR Filter Characteristics—Transmit and Receive
(VD = 3.0 to 3.6 V, Sample Rate = 8 kHz, TA = 0 to 70 °C)
Parameter
Symbol
Min
0
Typ
—
Max
3.3
3.6
0.1
—
Unit
kHz
kHz
dB
Passband (0.1 dB)
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
F
(0.1 dB)
F
0
—
(3 dB)
–0.1
—
—
4.4
—
kHz
dB
Stopband Attenuation
Group Delay
–74
—
—
t
12/Fs
—
s
gd
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10.
Table 11. Digital IIR Filter Characteristics—Transmit and Receive
(VD = 3.0 to 3.6 V, Sample Rate = 8 kHz, TA = 0 to 70 °C)
Parameter
Symbol
Min
0
Typ
—
Max
3.6
0.2
—
Unit
kHz
dB
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
F
(3 dB)
–0.2
—
—
4.4
kHz
dB
Stopband Attenuation
Group Delay
–40
—
—
—
t
1.6/Fs
—
s
gd
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 11, 12, 13, and 14. Figures 15 and 16 show
group delay versus input frequency.
14
Rev. 1.5
Si3050 + Si3011/18/19
Figure 7. FIR Receive Filter Response
Figure 9. FIR Transmit Filter Response
Figure 8. FIR Receive Filter Passband Ripple
Figure 10. FIR Transmit Filter Passband Ripple
For Figures 7–10, all filter plots apply to a sample rate of
Fs = 8 kHz.
For Figures 11–14, all filter plots apply to a sample rate of
Fs = 8 kHz.
Rev. 1.5
15
Si3050 + Si3011/18/19
Figure 11. IIR Receive Filter Response
Figure 12. IIR Receive Filter Passband Ripple
Figure 13. IIR Transmit Filter Response
Figure 14. IIR Transmit Filter Passband Ripple
Figure 15. IIR Receive Group Delay
Figure 16. IIR Transmit Group Delay
16
Rev. 1.5
Si3050 + Si3011/18/19
2. Typical Application Schematic
Rev. 1.5
17
Si3050 + Si3011/18/19
N D I G
E P A D
E P A D
E P A D
4 7 K
N I
N I
R 5 3
R 5 2
4 7 K
18
Rev. 1.5
Si3050 + Si3011/18/19
3. Bill of Materials
Component
Value
Supplier(s)
C1, C2
33 pF, Y2, X7R, ±20%
Panasonic, Murata, Vishay
1
C3
3.9 nF, 250 V, X7R, ±20%
1.0 µF, 50 V, Elec/Tant, ±20%
0.1 µF, 16 V, X7R, ±20%
Venkel, SMEC
Panasonic
C4
C5, C6, C50, C51
C7
Venkel, SMEC
Venkel, SMEC
Panasonic, Murata, Vishay
Venkel, SMEC
Venkel, SMEC
Diodes Inc.
2.7 nF, 50 V, X7R, ±20%
C8, C9
680 pF, Y2, X7R, ±10%
C10
0.01 µF, 16 V, X7R, ±20%
1
C30, C31
120 pF, 250 V, X7R, ±10%
Dual Diode, 225 mA, 300 V, (MMBD3004S)
2
D1, D2
FB1, FB2, FB203, FB204
Ferrite Bead, BLM18AG601SN1
NPN, 300 V, MMBTA42
PNP, 300 V, MMBTA92
NPN, 80 V, 330 mW, MMBTA06
Sidactor, 275 V, 100 A
1.07 k, 1/2 W, 1%
150 , 1/16 W, 5%
Murata
Q1, Q3
Q2
OnSemi, Fairchild, Diodes Inc.
OnSemi, Fairchild, Diodes Inc.
Central OnSemi, Fairchild
Teccor, Diodes Inc., Shindengen
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Venkel, SMEC, Panasonic
Silicon Labs
Q4, Q5
RV1
R1
R2
R3
3.65 k, 1/2 W, 1%
2.49 k, 1/2 W, 1%
100 k, 1/16 W, 5%
Not Installed, 20 M, 1/8 W, 5%
1 M, 1/16 W, 1%
R4
R5, R6
1
R7, R8
R9
R10
536 , 1/4 W, 1%
R11
73.2 , 1/2 W, 1%
R12, R13
56.2 , 1/16 W, 1%
15 M, 1/8 W, 5%
1
R30, R32
1
R31, R33
5.1 M, 1/8 W, 5%
R52, R53
U1
4.7 k, 1/16 W, 5%
Si3050
U2
Si3011/8/19
Silicon Labs
Z1
Zener Diode, 43 V, 1/2 W
General Semi, On Semi, Diodes Inc.
Notes:
1. R7–R8 may be substituted for R30–R33 and C30–C31 for lower cost, but reduced CID performance.
2. Several diode bridge configurations are acceptable. Parts, such as a single HD04, a DF-04S, or four 1N4004 diodes,
may be used (suppliers include General Semiconductor, Diodes Inc., etc.).
Rev. 1.5
19
Si3050 + Si3011/18/19
4. AOUT PWM Output
Table 12. Component Values—AOUT PWM
Figure 19 illustrates an optional circuit to support the
pulse width modulation (PWM) output capability of the
Si3050 for call progress monitoring purposes. To enable
this mode, the INTE bit (Register 2) should be set to 0,
the PWME bit (Register 1) set to 1, and the PWMM bits
(Register 2) set to 00.
Component
LS1
Value
Supplier
Intervox
Fairchild
Speaker BRT1209PF-06
NPN KSP13
Q6
C41
0.1 µF, 16 V, X7R, ±20% Venkel, SMEC
Venkel, SMEC,
R41
150 1/10 W, ±5%
+5VA
Panasonic
LS1
Registers 20 and 21 allow the receive and transmit
paths to be attenuated linearly. When these registers
are set to all 0s, the transmit and receive paths are
muted. These registers affect the call progress output
only and do not affect transmit and receive operations
on the telephone line.
R41
Q6
AOUT
C41
The PWMM[1:0] bits (Register 1, bits 5:4) select one of
three different PWM output modes for the AOUT signal,
including a delta-sigma data stream, a 32 kHz return to
0 PWM output, and a balanced 32 kHz PWM output.
Figure 19. AOUT PWM Circuit for Call Progress
20
Rev. 1.5
Si3050 + Si3011/18/19
5. Functional Description
Si3050
Si3018/19
CS
RX
IB
SC
DCT
SCLK
SDI
Control
Data
Interface
Hybrid, AC
and DC
Terminations
SDO
SDI THRU
VREG
VREG2
DCT2
PCLK
DTX
Isolation
Interface
Isolation
Interface
Line
Data
DCT3
DRX
Interface
RNG1
RNG2
QB
QE
QE2
FSYNC
Ring Detect
Off-Hook
RGDT
RG
Control
Logic
TGD
TGDE
RESET
AOUT/INT
Figure 20. Si3050 + Si3011/18/19 Functional Block Diagram
The Si3050 is an integrated direct access arrangement 5.1.1. Si3011
(DAA) providing a programmable line interface that
meets global telephone line requirements. The Si3050
implements Silicon Laboratories’ patented isolation
capacitor technology, which offers the highest level of
integration by replacing an analog front end (AFE), an
isolation transformer, relays, opto-isolators, and a 2- to
4-wire hybrid with two highly-integrated ICs.
TBR-21 and FCC-compliant line-side device.
Selectable dc terminations.
Two selectable ac terminations to increase return loss
and trans-hybrid loss performance.
+6 dBm TX/RX level mode (600 )
5.1.2. Si3018
Globally-compliant line-side device—targets global
DAA requirements for voice applications. This
line-side device supports both FCC-compliant
countries and non-FCC-compliant countries.
Selectable dc terminations.
Four selectable ac terminations to increase return loss
and trans-hybrid loss performance.
The Si3050 DAA is fully software programmable to meet
global requirements and is compliant with FCC, TBR21,
JATE, and other country-specific PTT specifications as
shown in Table 13. In addition, the Si3050 meets the
most stringent global requirements for out-of-band
energy, emissions, immunity, high-voltage surges, and
safety, including FCC Parts 15 and 68, EN55022,
EN55024, and many other standards.
+6 dBm TX/RX level mode (600 )
5.1.3. Si3019
5.1. Line-Side Device Support
Globally-compliant, enhanced features line-side
device—targets global DAA requirements for voice
applications.
Three different line-side devices are available for use
with the Si3050 system-side device. The Si3011
line-side device only supports DC terminations
compliant with TBR21 and FCC-compliant countries.
Selectable dc terminations
Sixteen selectable ac terminations to further increase
return loss and trans-hybrid loss performance.
Line voltage monitoring in on- and off-hook modes to
enable line in-use/parallel handset detection.
Programmable line current / voltage threshold interrupt.
Polarity reversal interrupt.
+3.2 dBm TX/RX level mode (600 )
+6 dBm TX/RX level mode (600 )
Higher resolution (1.1 mA/bit) loop current
measurement.
The Si3018 and Si3019 line-side devices are globally
compliant, have a selectable 5 Hz or 200 Hz RX
high-pass filter pole, and offer a –16.5 to 13.5 dB digital
gain/attenuation adjustment in 0.1dB increments for the
transmit and receive paths.
Rev. 1.5
21
Si3050 + Si3011/18/19
Table 13. Country-specific Register Settings
Register
Country
16
OHS
0
31
OHS2
0
16
RZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
RT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
26
ILIM
0
26
26
30
DCV[1:0] MINI[1:0] ACIM[3:0]
Argentina
11
01
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
00
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0000
0011
0010
0010
0010
0001
0011
0000
0000
1010
0000
0010
0010
0010
0010
0000
0010
0000
0010
0010
0010
0010
0000
0000
0010
0010
0000
0000
1
Australia
Austria
Bahrain
Belgium
Brazil
1
0
0
0
1
1
0
1
1
0
1
1
0
0
0
Bulgaria
Canada
Chile
0
1
1
0
0
0
0
0
0
China
0
0
0
Colombia
Croatia
0
0
0
0
1
1
Cyprus
0
1
1
Czech Republic
Denmark
Ecuador
Egypt
0
1
1
0
1
1
0
0
0
0
1
1
El Salvador
Finland
0
0
0
0
1
1
France
0
1
1
Germany
Greece
0
1
1
0
1
1
Guam
0
0
0
Hong Kong
Hungary
Iceland
0
0
0
0
1
1
0
1
1
India
0
0
0
Indonesia
Note:
0
0
0
1. See "5.16. DC Termination" on page 31 for DCV and MINI settings.
2. Supported for loop current 20 mA.
3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
22
Rev. 1.5
Si3050 + Si3011/18/19
Table 13. Country-specific Register Settings (Continued)
Register
Country
16
OHS
0
31
OHS2
1
16
RZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
RT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
26
ILIM
1
26
26
30
DCV[1:0] MINI[1:0] ACIM[3:0]
Ireland
11
11
11
10
01
11
11
11
11
11
11
01
11
11
11
11
11
11
11
01
01
11
01
11
11
11
11
11
11
00
00
00
01
01
00
00
00
00
00
00
01
00
00
00
00
00
00
00
01
01
00
01
00
00
00
00
00
00
0010
0010
0010
0000
0000
0000
0000
0010
0010
0010
0000
0000
0010
0000
0010
0010
0100
0010
0010
0000
0000
0000
0000
0010
0010
0010
0000
0000
0000
Israel
0
1
1
Italy
0
1
1
Japan
0
0
0
Jordan
Kazakhstan
Kuwait
0
0
0
0
0
0
0
0
0
Latvia
0
1
1
Lebanon
Luxembourg
Macao
0
1
1
0
1
1
0
0
0
2
Malaysia
0
0
0
Malta
0
1
1
Mexico
0
0
0
Morocco
Netherlands
New Zealand
Nigeria
0
1
1
0
1
1
0
0
0
0
1
1
Norway
0
1
1
Oman
0
0
0
Pakistan
Peru
0
0
0
0
0
0
Philippines
Poland
0
0
0
0
1
1
Portugal
Romania
Russia
0
1
1
0
1
1
0
0
0
Saudi Arabia
Singapore
Note:
0
0
0
0
0
0
1. See "5.16. DC Termination" on page 31 for DCV and MINI settings.
2. Supported for loop current 20 mA.
3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
Rev. 1.5
23
Si3050 + Si3011/18/19
Table 13. Country-specific Register Settings (Continued)
Register
Country
16
OHS
0
31
16
RZ
0
16
RT
0
26
ILIM
1
26
26
30
OHS2
DCV[1:0] MINI[1:0] ACIM[3:0]
Slovakia
1
1
0
0
1
1
1
0
0
0
0
1
0
0
11
11
11
11
11
11
11
11
11
01
11
11
11
11
00
00
00
00
00
00
00
00
00
01
00
00
00
00
0010
0010
0011
0000
0010
0010
0010
0000
0010
0000
0000
0101
0000
0000
Slovenia
South Africa
South Korea
Spain
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
Sweden
0
0
0
1
Switzerland
Taiwan
0
0
0
1
0
0
0
0
3
TBR21
0
0
0
1
Thailand
UAE
0
0
0
0
0
0
0
0
United Kingdom
USA
0
0
0
1
0
0
0
0
Yemen
0
0
0
0
Note:
1. See "5.16. DC Termination" on page 31 for DCV and MINI settings.
2. Supported for loop current 20 mA.
3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece,
Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the
United Kingdom.
24
Rev. 1.5
Si3050 + Si3011/18/19
The communications link is disabled by default. To
enable it, the PDL bit (Register 6, bit 4) must be
cleared. No communication between the Si3050 and
Si3018/19 can occur until this bit is cleared. Allow the
PLL to lock to the PCLK and FSYNC input signals
before clearing the PDL bit.
5.2. Power Supplies
The Si3050 operates from a 3.3 V power supply. The
Si3050 input pins require 3.3 V CMOS signal levels. If
support of 5 V signal levels is necessary, a level shifter
is required. The Si3011/18/19 derives its power from
two sources: the Si3050 and the telephone line. The
Si3050 supplies power over the patented isolation
capacitor link between the two devices, allowing the
line-side device to communicate with the Si3050 while
on-hook, and perform other on-hook functions such as
line voltage monitoring. When off-hook, the line-side
device also derives power from the line current supplied
from the telephone line. This feature is exclusive to
DAAs from Silicon Labs and allows the most
cost-effective implementation for a DAA while still
maintaining robust performance over all line conditions.
5.5. Power Management
The Si3050 supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
The power management modes are controlled by the
PDN and PDL bits (Register 6).
On powerup, or following a reset, the Si3050 is in reset
operation. The PDL bit is set, and the PDN bit is
cleared. The Si3050 is operational, except for the
communications link. No communication between the
Si3050 and line-side device (Si3011/18/19) can occur
during reset operation. Bits associated with the line-side
device are invalid in this mode.
5.3. Initialization
Each time the Si3050 is powered up, assert the RESET
pin. When the RESET pin is deasserted, the registers
have default values to guarantee the line-side device In typical applications, the DAA will predominantly be
(Si3011/18/19) is powered down without the possibility operated in normal mode. In normal mode, the PDL and
of loading the line (i.e., off-hook). An example PDN bits are cleared. The DAA is operational and the
initialization procedure follows:
communications link passes information between the
Si3050 and the Si3011/18/19.
1. Power up and de-assert RESET.
The Si3050 supports a low-power sleep mode that
supports ring validation and wake-up-on-ring features.
To enable the sleep mode, the PDN bit must be set.
When the Si3050 is in sleep mode, the PCLK signal
must remain active. In low-power sleep mode, the
Si3050 is non-functional except for the communications
link and the RGDT signal. To take the Si3050 out of
sleep mode, pulse the reset pin (RESET) low.
2. Wait until the PLL is locked. This time is less than
1 ms from the application of PCLK.
3. Enable PCM (Register 33) or GCI (Register 42)
mode.
4. Set the desired line interface parameters (i.e.,
DCV[1:0], MINI[1:0], ILIM, DCR, ACIM[3:0], OHS,
RT, RZ, TGA2, and TXG2[3:0]) shown in Table 13 on
page 22.
In summary, the powerdown/up sequence for sleep
mode is as follows:
5. Set the FULL (or FULL2) + IIRE bits as required.
6. Write a 0x00 into Register 6 to power up the
line-side device (Si3011/18/19).
1. Ensure the PDL bit (Register 6, bit 4) is cleared.
2. Set the PDN bit (Register 6, bit 3).
When this procedure is complete, the Si3011/18/19 is
ready for ring detection and off-hook operation.
3. The device is now in sleep mode. PCLK must remain
active.
5.4. Isolation Barrier
4. To exit sleep mode, reset the Si3050 by pulsing the
RESET pin.
The Si3050 achieves an isolation barrier through
low-cost, high-voltage capacitors in conjunction with 5. Program registers to desired settings.
Silicon Laboratories’ patented signal processing
The Si3050 also supports an additional Powerdown
techniques. Differential capacitive communication
eliminates signal degradation from capacitor
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) bits are set, the chipset enters a
complete powerdown mode and draws negligible
current (deep sleep mode). In this mode, the Si3050 is
non-functional. The RGDT pin does not function and the
Si3050 will not detect a ring. Normal operation can be
restored using the same process for taking the Si3050
out of sleep mode.
mismatches, common mode interference, or noise
coupling. As shown in the "2. Typical Application
Schematic" on page 17, the C1, C2, C8, and C9
capacitors isolate the Si3050 (system-side) from the
Si3011/18/19 (line-side). Transmit, receive, control, ring
detect, and caller ID data are passed across this barrier.
Rev. 1.5
25
Si3050 + Si3011/18/19
FDT bit (Register 12, bit 6) becomes active to indicate
that successful communication between the line side
and system side is established. This provides
verification that the communications link is operational.
5.6. Calibration
The Si3050 initiates two auto-calibrations by default
when the device goes off-hook or experiences a loss of
line power. A 17 ms resistor calibration is performed to
allow circuitry internal to the DAA to adjust to the exact
line conditions present at the time of going off-hook.
This resistor calibration can be disabled by setting the
The digital data loop-back mode offers a way to input
data on the DRX pin and have the identical data output
on the DTX pin through bypassing the transmit and
receive filters. Setting the DDL bit (Register 10, bit 0)
enables this mode, which provides an easy way to verify
communication between the host processor/DSP and
the DAA. No line-side power or off-hook sequence is
required for this mode.
RCALD bit (Register 25, bit 5).
A
256 ms ADC
calibration is also performed to remove offsets that
might be present in the on-chip A/D converter, which
could affect the A/D dynamic range. The ADC
auto-calibration is initiated after the DAA dc termination
stabilizes and the resistor calibration completes. Due to The remaining test modes require an off-hook sequence
the large variation in line conditions and line card to operate. The following sequence lists the off-hook
behavior presented to the DAA, it might be beneficial to requirements:
use manual ADC calibration instead of auto-calibration.
1. Powerup or reset.
Manual ADC calibration should be executed as close as
possible to 256 ms before valid transmit/receive data is
expected.
2. Allow the internal PLL to lock on PCLK and FSYNC.
3. Enable line-side by clearing PDL bit.
4. Issue an off-hook command.
The following steps should be taken to implement
manual ADC calibration:
5. Delay 402.75 ms for calibration to occur.
6. Set desired test mode.
1. The CALD bit (auto-calibration disable—Register 17) The communications link digital loopback mode allows
must be set to 1.
the host processor to provide a digital input test pattern
on DRX and receive that digital test pattern back on
DTX. To enable this mode, set the IDL bit (Register 1,
bit 1). The communications link is tested in this mode.
The digital stream is delivered across the isolation
capacitors, C1 and C2, of the "2. Typical Application
Schematic" on page 17, to the line-side device and
2. The MCAL bit (manual calibration) must be toggled
to one and then 0 to begin and complete the
calibration.
3. The calibration is completed in 256 ms.
5.7. In-Circuit Testing
The Si3050’s advanced design provides the designer returned across the same path. In this digital loopback
with an increased ability to determine system mode, the 0.9 dB attenuation and filter group delays
functionality during production line tests and support for also exist.
end-user diagnostics. Six loopback modes allow
The PCM analog loopback mode extends the signal
increased coverage of system components. For four of
path of the analog loopback mode. In this mode, an
the test modes, a line-side power source is needed.
analog signal is driven from the line into the line-side
While a standard phone line can be used, the test circuit
device. This analog signal is converted to digital data
in Figure 1 on page 6 is adequate. In addition, an
and then passed across the communications link to the
off-hook sequence must be performed to connect the
system-side device. The data passes through the
power source to the line-side device.
receive filter, through the transmit filter, and is then
For the start-up loopback test mode, no line-side power passed across the communications link and sent back
is necessary, and no off-hook sequence is required. The out onto the line as an analog signal. Set the PCML bit
start-up test mode is enabled by default. When the PDL (Register 33, bit 7) to enable this mode.
bit (Register 6, bit 4) is set (the default case), the line
With the final testing mode, internal analog loopback,
side is in a powerdown mode, and the system-side is in
the system can test the operation of the transmit and
a digital loopback mode. In this mode, data received on
receive paths on the line-side device and the external
DRX passes through the internal filters and is
components in the "2. Typical Application Schematic"
transmitted on DTX. This path introduces approximately
on page 17. The host provides a digital test waveform
0.9 dB of attenuation on the DRX signal received. The
on DRX. Data passes across the isolation barrier, is
group delay of both transmit and receive filters exists
transmitted to and received from the line, passes back
between DRX and DTX. Clearing the PDL bit disables
across the isolation barrier, and is presented to the host
this mode, and the DTX data switches to the receive
on DTX. Clear the HBE bit (Register 2, bit 1) to enable
data from the line side. When the PDL bit is cleared, the
this mode.
26
Rev. 1.5
Si3050 + Si3011/18/19
When the HBE bit is cleared, it produces a dc offset that mode (or 2x full scale) is enabled by setting the FULL2
affects the signal swing of the transmit signal. Silicon bit in Register 30. With FULL2 = 1, the full-scale signal
Laboratories recommends that the transmit signal be level increases to +6.0 dBm into a 600 load or
12 dB lower than normal transmit levels. A lower level 1.5 dBV into all reference impedances. The full-scale
eliminates clipping from the dc offset that results from and enhanced full-scale modes provide the ability to
disabling the hybrid. It is assumed in this test that the trade off TX power and TX distortion for a peak signal.
line ac impedance is nominally 600
By using the programmable digital gain registers in
conjunction with the enhanced full-scale signal level
mode, a specific power level (+3.2 dBm for example)
can be achieved across all ACT settings.
Note: All test modes are mutually exclusive. If more than one
test mode is enabled concurrently, the results are
unpredictable.
5.8. Exception Handling
5.11. Parallel Handset Detection
The Si3050 can determine if an error occurs during The Si3050 can detect a parallel handset going
operation. Through the secondary frames of the serial off-hook. When the Si3050 is off-hook, the loop current
link, the controlling DSP can read several status bits. can be monitored with the LCS or LCS2 bits. A
The bit of highest importance is the frame detect bit significant drop in loop current signals a parallel handset
(FDT, Register 12, bit 6) which indicates that the going off-hook. If a parallel handset going off-hook
system-side (Si3050) and line-side (Si3011, 3018 or causes the loop current to drop to 0, the LCS and LCS2
Si3019) devices are communicating. During normal bits will read all 0s. Additionally, the Drop-Out Detect
operation, the FDT bit can be checked before reading (DOD) bit will fire (and generate an interrupt if the
the bits that indicate information about the line side. If DODM bit is set) indicating that the line-derived power
FDT is not set, the following bits related to the line side supply has collapsed.
are invalid—RDT, RDTN, RDTP, LCS[4:0], LSID[1:0],
REVB[3:0], LVS[7:0], LCS2[7:0], ROV, BTD, DOD, and
when on- or off-hook to determine the line voltage.
OVL; the RGDT operation is also non-functional.
With the Si3019 line side, the LVS bits also can be read
Significant drops in line voltage can signal a parallel
Following powerup and reset, the FDT bit is not set handset. For the Si3050 to operate in parallel with
because the PDL bit (Register 6 bit 4) defaults to 1. In another handset, the parallel handset must have a
this state, the ISOcap is not operating and no sufficiently high dc termination to support two off-hook
information about the line side can be determined. The DAAs on the same line. Improved parallel handset
user must provide a valid PCLK and FSYNC to the operation can be achieved by changing the dc
system and clear the PDL bit to activate the ISOcap impedance from 50 to 800 and reducing the DCT
link. Communication with the line-side device takes less pin voltage with the DCV[1:0] bits.
than 10 ms to establish.
5.12. Line Voltage/Loop Current Sensing
5.9. Revision Identification
The Si3050 can measure loop current with either the
The Si3050 provides information to determine the Si3011, Si3018 or the Si3019 line-side device. The 5-bit
revision of the Si3050 and/or the Si3011/18/19. The LCS[4:0] register reports loop current measurements
REVA[3:0] bits (Register 11) identify the revision of the when off-hook. The Si3011 and Si3019 offer an
Si3050, where 0101b denotes revision E. The additional register to report loop current to a finer
REVB[3:0] bits (Register 13) identify the revision of the resolution (LCS2[7:0]). The Si3050 can only measure
line-side device, where 0110b denotes revision F.
line voltage when used with the Si3011 and Si3019
line-side devices. The LVS[7:0] register is available with
the Si3011 or Si3019, and monitors voltage both on and
5.10. Transmit/Receive Full-Scale Level
The Si3050 supports programmable maximum transmit off-hook. These registers can be used to help determine
and receive levels. The default signal level supported by the following line conditions:
the Si3050 is 0 dBm into a 600 load. Two additional
modes of operation offer increased transmit and receive
level capability to enable use of the DAA in applications
that require higher signal levels. The full-scale mode is
enabled by setting the FULL bit in Register 31. With
FULL = 1 (Si3019 only), the full-scale signal level
increases to +3.2 dBm into a 600 load or 1 dBV into
all reference impedances. The enhanced full-scale
When on-hook, detect if a line is connected.
When on-hook, detect if a parallel phone is off-hook.
When off-hook, detect if a parallel phone goes on or
off-hook.
Detect if enough loop current is available to operate.
When used in conjunction with the OPD bit, detect if
an overload condition exists. (See "5.26. Overload
Detection" on page 37.)
Rev. 1.5
27
Si3050 + Si3011/18/19
5.12.1. Line Voltage Measurement
register changes state. The edge-triggered interrupt is
cleared by writing 0 to the POLI bit (Register 4, bit 0).
The POLI bit is set each time bit 7 of the LVS register
changes state, and must be written to 0 to clear it. The
default state of the LVS register forces the LVS[7:0] bits
to 0 when the line voltage is 3 V or less. The LVFD bit
(Register 31, bit 0) disables this force-to-zero function
and allows the LVS register to display non-zero values
of 3 V and below. This register may display
unpredictable values at line voltages between 0 to 2 V.
At 0 V, the LVS register displays all 0s.
(Si3011 and Si3019 Line Side Devices Only)
The Si3050 reports line voltage with the LVS[7:0] bits
(Register 29) in both on- and off-hook states with a
resolution of 1 V per bit. The accuracy of these bits is
approximately ±10%. Bits 0 through 7 of this 8-bit
signed number indicate the value of the line voltage in
2s complement format. Bit 7 indicates the polarity of the
TIP/RING voltage.
If the INTE bit (Register 2, bit 7) and the POLM bit
(Register 3, bit 0) are set, a hardware interrupt is
generated on the AOUT/INT pin when Bit 7 of the LVS
Possible Overload
30
25
20
LCS
BITS
15
10
5
0
0
3.3 6.6 9.9 13.2 16.5 19.8 23.1 26.4 29.7 33 36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.1 62.7 66 69.3 72.6 75.9
79.2 82.5 85.8 89.1 92.4 95.7 99 102.3
127
Loop Current (mA)
Figure 21. Typical Loop Current LCS Transfer Function (ILIM = 0)
28
Rev. 1.5
Si3050 + Si3011/18/19
5.12.2. Loop Current Measurement
With the OH bit at logic 0, negligible dc current flows
through the hookswitch. When a logic 1 is written to the
OH bit, the hookswitch transistor pair, Q1 and Q2, turn
on. A termination impedance across TIP and RING is
applied and causes dc loop current to flow. The
termination impedance has both an ac and a dc
component.
When the Si3050 is off-hook, the LCS[4:0] bits measure
loop current in 3.3 mA/bit resolution. With the LCS[4:0]
bits, a user can detect another phone going off-hook by
monitoring the dc loop current. The line current sense
transfer function is shown in Figure 21 and is detailed in
Table 14. The LCS and LCS2 bits report loop current
down to the minimum operating loop current for the Several events occur in the DAA when the OH bit is set.
DAA. Below this threshold, the reported value of loop There is a 250 µs latency for the off-hook command to
current is unpredictable. The minimum operating loop be communicated to the line-side device. When the
current of the DAA is set by the MINI[1:0] bits in line-side device goes off-hook, an off-hook counter
Register 26.
forces a delay to allow line transients to settle before
transmission or reception can occur. The off-hook
counter time is controlled by the FOH[1:0] bits
(Register 31, bits 6:5). The default setting for the
off-hook counter time is 128 ms, but can be adjusted up
to 512 ms or down to 64 or 8 ms.
When the LCS bits reach max value, the Loop Current
Sense Overload Interrupt bit (Register 4) fires. LCSOI
firing however, does not necessarily imply that an
overcurrent situation has occurred. An overcurrent
situation in the DAA is determined by the status of the
OPD bit (Register 19). After the LCSOI interrupt fires, After the off-hook counter expires, a resistor calibration
the OPD bit should be checked to determine if an is performed for 17 ms to allow the DAA internal
overcurrent situation exists. The OPD bit indicates an circuitry to adjust to the exact conditions present at the
overcurrent situation when loop current exceeds either time of going off-hook. This resistor calibration can be
160 mA (ILIM = 0) or 60 mA (ILIM = 1), depending on disabled by setting the RCALD bit (Register 25, bit 5).
the setting of the ILIM bit (Register 26).
After the resistor calibration is performed, an ADC
calibration is performed for 256 ms. This calibration
helps to remove offset in the A/D sampling the
Table 14. Loop Current Transfer Function
telephone line. ADC calibration can be disabled by
LCS[4:0]
Condition
setting the CALD bit (Register 17, bit 5). See "5.6.
Calibration" on page 26 for more information on
automatic and manual calibration.
00000 Insufficient line current for normal operation.
Use the DOD bit (Register 19, bit 1) to
determine if a line is still connected.
Silicon Laboratories recommends that the resistor and
the ADC calibrations not be disabled except when a fast
response is needed after going off-hook, such as when
responding to a Type II Caller-ID signal. See "5.25.
Caller ID" on page 36 for detailed information.
00100 Minimum line current for normal operation.
(MINI[1:0] = 01)
11111
Loop current may be excessive. Use the
OPD bit to determine if an overload condi-
tion exists.
To calculate the total time required to go off-hook and
start transmission or reception, include the digital filter
delay (typically 1.5 ms with the FIR filter) in the
calculation.
The LCS2 register also reports loop current in the
off-hook state. This register has a resolution of 1.1 mA
per bit.
5.14. Ground Start Support
5.13. Off-Hook
The Si3050 DAA supports loop-start applications by
default. It can also support ground-start applications
with the RG, TGD, and TGDE pins and the schematic
shown in Figure 22. The component values are listed in
Table 15.
The communication system generates an off-hook
command by setting the OH bit (Register 5, bit 0). This
off-hook state seizes the line for incoming/outgoing
calls. It also can be used for pulse dialing.
Rev. 1.5
29
Si3050 + Si3011/18/19
on RING and grounds TIP. This sets the TGD bit
(Register 32, bit 2). The DAA may then be taken
off-hook and the relay in series with RING opened (clear
the RG bit). The call continues as in loop-start mode.
VD
R106
TGDb
-24V
5.14.3. CO Requests Line Seizure
R105
In a normal on-hook state, the relay in series with TIP
should be closed, connecting the –24 V isolated supply.
The CO grounds TIP to request line seizure, causing
current to flow. The opto-isolator U3 (see Figure 22 on
page 30) detects this current and sets the TGD bit
(Register 32, bit 2). This bit remains high as long as
current is detected. The TGDI bit (Register 4, bit 1) is a
sticky bit, and remains high until cleared. A hardware
interrupt on the AOUT/INT can be made to occur when
TIP current begins to flow by enabling the TGDM bit
(Register 3, bit 1). Clear the interrupt by writing 0 to the
TGDI bit (Register 4 bit 1). The DAA may then be taken
off-hook and the call continued as in loop-start mode.
U3
1
2
4
3
1
2
4
3
Opto-Isolator
VD
R104
R102
R103
RL1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
TGDEb
RGb
TIP
RING
Opto-Relay
R101
5.15. Interrupts
The AOUT/INT pin can be used as a hardware interrupt
pin by setting the INTE bit (Register 2, bit 7). When this
bit is set, the analog output used for call progress
monitoring is not available. The default state of this
interrupt output pin is active low, but active high
operation can be enabled by setting the INTP bit
(Register 2, bit 6). This pin is an open-drain output
when the INTE bit is set and requires a 4.7 k pullup or
pulldown for correct operation. If multiple INT pins are
connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k Bits 7–0 in
Register 3 and bit 1 in Register 44 can be set to enable
hardware interrupt sources (bit 0 is available with the
Si3011 and Si3019 line-side devices only). When one or
more of these bits is set, the AOUT/INT pin goes into an
active state and stays active until the interrupts are
serviced. If more than one hardware interrupt is enabled
in Register 3, use software polling to determine the
cause of the interrupts. Register 4 and bit 3 of
Register 44 contain sticky interrupt flag bits. Clear these
bits after servicing the interrupt.
Figure 22. Typical Application Circuit for
Ground Start Support on the SI3050
Table 15. Component Values for the Ground
Start Support Schematic
Symbol
Value
Supplier(s)
R101
200 , 2 W, ±5%
Venkel, SMEC,
Panasonic
R102, R103,
R106
1 k, 1/10 W, ±5% Venkel, SMEC,
Panasonic
R104
1.5 k, 1/10 W, ±5% Venkel, SMEC,
Panasonic
R105
10 k, 1/2 W, ±5% Venkel, SMEC,
Panasonic
RL1
U3
AQW210S
PS2501L-1
Aromat, NEC
NEC, Fairchild
Registers 43 and 44 contain the line current/voltage
threshold interrupt. These line current/voltage registers
and interrupt are only available with the Si3011 and
Si3019 line-side devices. This interrupt is triggered
when the measured line voltage or current in the LVS or
LCS2 registers, as selected by the CVS bit
(Register 44, bit 2), crosses the threshold programmed
into the CVT[7:0] bits. With the CVP bit, the interrupt
can be programmed to occur when the measured value
rises above or falls below the threshold. Only the
magnitude of the measured value is used for
comparison to the threshold programmed into the
5.14.1. Ground Start Idle
Ensure the relay in series with TIP is closed by clearing
the TGOE bit (Register 32, bit 1). This enables the DAA
to sense if the CO grounds TIP. Set RG to 1
(Register 32, bit 0) so that no current flows through the
relay connecting RING to ground.
5.14.2. DAA Requests Line Seizure
With TGOE set to zero, seize the line by closing the
relay in series with RING (clear the RG bit,
Register 32, bit 0). The CO detects this current flowing
30
Rev. 1.5
Si3050 + Si3011/18/19
CVT[7:0] bits. Therefore, only positive numbers should The MINI[1:0] bits select the minimum operational loop
be used as a threshold.
current for the DAA, and the DCV[1:0] bits adjust the
DCT pin voltage, which affects the TIP/RING voltage of
the DAA. These bits allow important trade-offs to be
5.16. DC Termination
The DAA has programmable settings for the dc made between signal headroom and minimum
impedance, current limiting, minimum operational loop operational loop current. Increasing TIP/RING voltage
current and TIP/RING voltage. The dc impedance of the increases signal headroom, whereas decreasing the
DAA is normally represented with a 50 slope as TIP/RING voltage allows compliance to PTT standards
shown in Figure 23, but can be changed to an 800 in low-voltage countries, such as Japan. Increasing the
slope by setting the DCR bit. This higher dc termination minimum operational loop current above 10 mA also
presents a higher resistance to the line as loop current increases signal headroom and prevents degradation of
increases.
the signal level in low-voltage countries.
Finally, Australia has separate dc termination
requirements for line seizure versus line hold. Japan
mode (only available with the Si3018 or Si3019) may be
used to satisfy both requirements. However, if a higher
transmit level for modem operation is desired, switch to
FCC mode 500 ms after the initial off-hook. This
satisfies the Australian dc termination requirements.
FCC DCT Mode
12
11
10
9
5.17. AC Termination
8
The Si3050
+ Si3011 chipset provides two ac
termination impedances. The Si3050 + Si3018 chipset
provides four ac termination impedances. The
ACIM[3:0] bits in Register 30 are used to select the ac
impedance setting. The two available settings for the
Si3050 + Si3011 chipset are listed in Table 16. The four
available settings for the Si3018 are listed in Table 17. If
an ACIM[3:0] setting other than the four listed in
Table 16 or Table 17 is selected, the ac termination is
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
Figure 23. FCC Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 0
For applications requiring current limiting per the TBR21 forced to 600 (ACIM[3:0] = 0000). The programmable
standard, the ILIM bit may be set to select this mode. In digital hybrid can be used to further reduce near-end
this mode, the dc I/V curve is changed to a 2000 echo for each of the four listed ac termination settings.
slope above 40 mA, as shown in Figure 24. This allows See "5.28. Transhybrid Balance" on page 38 for details.
the DAA to operate with a 50 V, 230 feed, which is the
Table 16. AC Termination Settings for the
Si3011 Line-Side Device
maximum linefeed specified in the TBR21 standard.
TBR21 DCT Mode
45
ACIM[3:0]
0000
AC Termination
600
40
35
30
25
20
15
10
0001
210 + (750 || 150 nF) and 275 +
(780 || 150 nF)
5
.015 .02 .025 .03 .035 .04 .045 .05 .055 .06
Loop Current (A)
Figure 24. TBR21 Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 1
Rev. 1.5
31
Si3050 + Si3011/18/19
Table 17. AC Termination Settings for the
Si3018 Line-Side Device
Table 18. AC Termination Settings for the
Si3019 Line-Side Device
ACIM[3:0]
0000
AC Termination
ACIM[3:0]
0000
AC Termination
600
600
900
0011
220 + (820 || 120 nF) and 220 +
(820 || 115 nF)
0001
0010
270 + (750 || 150 nF) and
275 + (780 || 150 nF)
0100
1111
370 + (620 || 310 nF)
Global complex impedance
0011
220 + (820 || 120 nF) and 220
+ (820 || 115 nF)
The Si3019 provides sixteen ac termination
impedances when used with the Si3050. The ACIM[3:0]
bits in Register 30 are used to select the ac impedance
setting on the Si3019. The sixteen available settings for
the Si3019 are listed in Table 18.
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
370 + (620 || 310 nF)
320 + (1050 || 230 nF)
370 + (820 || 110 nF)
275 + (780 || 115 nF)
120 + (820 || 110 nF)
350 + (1000 || 210 nF)
200 + (680 || 100 nF)
600 + 2.16 µF
The most widely used ac terminations are available as
register options to satisfy various global PTT
requirements. The real 600 impedance satisfies the
requirements of FCC Part 68, JATE, and other country
requirements. The 270 + (750 || 150 nF) satisfies
the requirements of TBR21.
There are two selections useful for satisfying
non-standard ac termination requirements. The
350 + (1000 || 210 nF) impedance selection in
Register 30 is the ANSI/EIA/TIA 464 compromise
impedance network for trunks. The last ac termination
selection, ACIM[3:0] = 1111, is designed to satisfy
minimum return loss requirements for every country that
requires a complex termination. By selecting this
setting, the system is ensured to meet minimum PTT
requirements.
900 + 1 µF
900 + 2.16 µF
600 + 1 µF
Global complex impedance
For each of the sixteen ac termination settings, the
programmable digital hybrid can be used to further
reduce near-end echo. See "5.28. Transhybrid Balance"
on page 38 for details.
32
Rev. 1.5
Si3050 + Si3011/18/19
The RDT behavior is also based on the RNG1-RNG2
voltage. When the RFWE bit is 0, a positive ring signal
sets the RDT bit for a period of time. When the RFWE
bit is 1, a positive or negative ring signal sets the RDT
bit.
5.18. Ring Detection
The ring signal is resistively coupled from TIP and RING
to the RNG1 and RNG2 pins. The Si3050 supports
either full- or half-wave ring detection. With full-wave
ring detection, the designer can detect a polarity
reversal of the ring signal. See “5.25.Caller ID” on
page 36. The ring detection threshold is programmable
with the RT bit (Register 16, bit 0) and RT2 bit
(Register 17, bit 4). The ring detector output can be
monitored in three ways. The first method uses the
RGDT pin. The second method uses the register bits,
RDTP, RDTN, and RDT (Register 5). The final method
uses the DTX output.
The RDT bit acts like a one shot. When a new ring
signal is detected, the one shot is reset. If no new ring
signals are detected prior to the one shot counter
reaching 0, then the RDT bit clears. The length of this
count is approximately 5 seconds. The RDT bit is reset
to
0 by an off-hook event. If the RDTM bit
(Register 3, bit 7) is set, a hardware interrupt occurs on
the AOUT/INT pin when RDT is triggered. This interrupt
can be cleared by writing to the RDTI bit
(Register 4, bit 7). When the RDI bit (Register 2, bit 2) is
set, an interrupt occurs on both the beginning and end
of the ring pulse as defined by the RTO bits
(Register 23, bits 6:3). Ring validation may be enabled
when using the RDI bit.
The ring detector mode is controlled by the RFWE bit
(Register 18, bit 1). When the RFWE bit is 0 (default
mode), the ring detector operates in half-wave rectifier
mode. In this mode, only positive ring signals are
detected. A positive ring signal is defined as a voltage
greater than the ring threshold across RNG1-RNG2.
Conversely, a negative ring signal is defined as a
voltage less than the negative ring threshold across
RNG1-RNG2. When the RFWE bit is 1, the ring detector
operates in full-wave rectifier mode. In this mode, both
positive and negative ring signals are detected.
The third method to monitor detection uses the DTX
data samples to transmit ring data. If the ISOcap is
active (PDL=0) and the device is not off-hook or in
on-hook line monitor mode, the ring data is presented
on DTX. The waveform on DTX depends on the state of
the RFWE bit.
The first method to monitor ring detection output uses
the RGDT pin. When the RGDT pin is used, it defaults
to active low, but can be changed to active high by
setting the RPOL bit (Register 14, bit 1). This pin is an
open-drain output, and requires a 4.7 k pullup or
pulldown for correct operation. If multiple RGDT pins
are connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k
When RFWE is 0, DTX is –32768 (0x8000) while the
RNG1-RNG2 voltage is between the thresholds. When
a ring is detected, DTX transitions to +32767 when the
ring signal is positive, then goes back to –32768 when
the ring is near 0 and negative. Thus a near square
wave is presented on DTX that swings from –32768 to
+32767 in cadence with the ring signal.
When RFWE is 1, DTX sits at approximately +1228
while the RNG1-RNG2 voltage is between the
thresholds. When the ring becomes positive, DTX
transitions to +32767. When the ring signal goes near 0,
DTX remains near 1228. As the ring becomes negative,
the DTX transitions to –32768. This repeats in cadence
with the ring signal.
When the RFWE bit is 0, the RGDT pin is asserted
when the ring signal is positive, which results in an
output signal frequency equal to the actual ring
frequency. When the RFWE bit is 1, the RGDT pin is
asserted when the ring signal is positive or negative.
The output then appears to be twice the frequency of
the ring waveform.
To observe the ring signal on DTX, watch the MSB of
the data. The MSB toggles at the same frequency as
the ring signal independent of the ring detector mode.
This method is adequate for determining the ring
frequency.
The second method to monitor ring detection uses the
ring detect bits (RDTP, RDTN, and RDT). The RDTP
and RDTN behavior is based on the RNG1-RNG2
voltage. When the signal on RNG1-RNG2 is above the
positive ring threshold, the RDTP bit is set. When the
signal on RNG1-RNG2 is below the negative ring
threshold, the RDTN bit is set. When the signal on
RNG1-RNG2 is between these thresholds, neither bit is
set.
Rev. 1.5
33
Si3050 + Si3011/18/19
may remain high throughout a distinctive-ring
sequence.
5.19. Ring Validation
Ring validation prevents false triggering of a ring
detection by validating the ring parameters. Invalid
signals, such as a line-voltage change when a parallel
handset goes off-hook, pulse dialing, or a high-voltage
line test are ignored. Ring validation can be enabled
2. The RDTI interrupt fires when a validated ring
occurs. If RDI is zero (default), the interrupt occurs
on the rising edge of RDT. If RDI is set, the interrupt
occurs on both rising and falling edges of RDT.
during normal operation and in low-power sleep mode 3. The INT pin follows the RDTI bit with configurable
when a valid external PCLK signal is supplied. polarity.
The ring validation circuit operates by calculating the 4. The RGDT pin can be configured to follow the
time between alternating crossings of positive and
negative ring thresholds to validate that the ring
frequency is within tolerance. High and low frequency
tolerances are programmable in the RAS[5:0] and
RMX[5:0] fields. The RCC[2:0] bits define how long the
ring signal must be within tolerance.
ringing signal envelope detected by the ring
validation circuit by setting RFWE to 0. If RFWE is
set to 1, the RGDT pin follows an unqualified ring
detect one-shot signal initiated by a ring-threshold
crossing and terminated by a fixed counter timeout
of approximately 5 seconds. (This information is
shown in Register 18).
Once the duration of the ring frequency is validated by
the RCC bits, the circuitry stops checking for frequency
tolerance and begins checking for the end of the ring
signal, which is defined by a lack of additional threshold
crossings for a period of time configured by the
RTO[3:0] bits. When the ring frequency is first validated,
a timer defined by the RDLY[2:0] bits is started. If the
RDLY[2:0] timer expires before the ring timeout, then
the ring is validated and a valid ring is indicated. If the
ring timeout expires before the RDLY[2:0] timer, a valid
ring is not indicated.
5.20. Ringer Impedance and Threshold
The ring detector in a typical DAA is ac coupled to the
line with a large 1 F, 250 V decoupling capacitor. The
ring detector on the Si3011/18/19 is resistively coupled
to the line. This coupling produces a high ringer
impedance to the line of approximately 20 Mto meet
the majority of country PTT specifications including FCC
and TBR21.
Several countries including Poland, South Africa, and
Slovenia require a maximum ringer impedance that can
be met with an internally-synthesized impedance by
setting the RZ bit (Register 16). Certain countries also
specify ringer thresholds differently. The RT and RT2
bits (Register 16 and Register 17, respectively) select
between three different ringer thresholds: 15 V ±10%,
21 V ±10%, and 45 V ±10%. These three settings
enable satisfaction of global ringer threshold
requirements. Thresholds are set so that a ring signal is
guaranteed to not be detected below the minimum, and
a ring signal is guaranteed to be detected above the
Ring validation requires the following five parameters:
Timeout parameter to place a lower limit on the
frequency of the ring signal (the RAS[5:0] bits in
Register 24). The frequency is measured by
calculating the time between crossings of positive
and negative ring thresholds.
Minimum count to place an upper limit on the
frequency (the RMX[5:0] bits in Register 22).
Time interval over which the ring signal must be the
correct frequency (the RCC[2:0] bits in Register 23).
Timeout period that defines when the ring pulse has maximum.
ended based on the most recent ring threshold
5.21. Pulse Dialing and Spark Quenching
crossing.
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have strict
specifications for pulse fidelity including make and
break times, make resistance, and rise and fall times. In
a traditional, solid-state dc holding circuit, there are a
number of issues in meeting these requirements.
Delay period between when the ring signal is
validated and when a valid ring signal is indicated to
accommodate distinctive ringing.
The RNGV bit (Register 24, bit 7) enables or disables
the ring validation feature in both normal operating
mode and low-power sleep mode.
Ring validation affects the behavior of the RDT status
bit, the RDTI interrupt, the INT pin, and the RGDT pin.
The Si3050 dc holding circuit has active control of the
on- and off-hook transients to maintain pulse dialing
fidelity.
1. When ring validation is enabled, the status bit seen
in the RDT read-only bit (r5.2), represents the
detected envelope of the ring. The ring validation
parameters are configurable so that this envelope
Spark quenching requirements in countries, such as
Italy, the Netherlands, South Africa, and Australia, deal
34
Rev. 1.5
Si3050 + Si3011/18/19
with the on-hook transition during pulse dialing. These bits will be set. An external interrupt can optionally be
tests provide an inductive dc feed resulting in a large triggered by the DODI bit by setting the DODM and
voltage spike. This spike is caused by the line INTE bits.
inductance and the sudden decrease in current through
the loop when going on-hook. The traditional way of
5.23. Billing Tone Filter (Optional)
dealing with this problem is to put a parallel RC shunt Optionally, a billing tone filter may be inserted between
across the hookswitch relay. The capacitor is large the line and the voice DAA to minimize disruptions
(~1 µF, 250 V) and relatively expensive. In the Si3050, caused by large billing tones. The notch filter design
loop current can be controlled to achieve three distinct requires two notches, one at 12 kHz and one at 16 kHz.
on-hook speeds to pass spark quenching tests without Because these components are expensive and few
additional BOM components. Through the settings of countries utilize billing tones, this filter is typically placed
four bits in three registers, OHS (Register 16), OHS2 in an external dongle or added as a population option.
(Register 31), SQ0, and SQ1 (Register 59), a slow ramp Figure 25 shows a billing tone filter example. Table 19
down of loop current can be achieved which induces a gives the component values.
delay between the time the OH bit is cleared and the
time the DAA actually goes on-hook.
L1 must carry the entire loop current. The series
resistance of the inductors is important to achieve a
To ensure proper operation of the DAA during pulse narrow and deep notch. This design has more than
dialing, disable the automatic resistor calibration that is 25 dB of attenuation at both 12 kHz and 16 kHz.
performed each time the DAA enters the off-hook state
C1
by setting the RCALD bit (Register 25, bit 5).
5.22. Receive Overload Detection
C2
L1
The Voice DAA chipset is capable of monitoring and
reporting receive overload conditions on the line. Billing
tones, parallel phone off-hook events, polarity reversals
and other disturbances on the line may trigger multiple
levels of overload detection as described below.
TIP
From Line
RING
Transient events less than 1.1 V
on the line are
PK
filtered out by the low-pass digital filter on the Si3050 +
Si3011 and Si3050+Si3019. The ROV and ROVI bits
are set when the received signal is greater than 1.1
L2
To
DAA
C3
V
.
Both bits will continue to indicate an overload
PK
condition until a zero is written to clear. The OVL mirrors
the function of the ROV and ROVI bits but it
automatically clears after the overload condition has
been removed. When the OVL bit returns to 0, the DAA
initiates an auto-calibration sequence that must
complete before data can be transmitted. An external
interrupt can optionally be triggered by the ROVI bit by
setting the ROVM and INTE bits.
Figure 25. Billing Tone Filter
Table 19. Component Values—Optional Billing
Tone Filters
Component
Value
Certain events such as billing tones can be sufficiently
large to disrupt the line-derived power supply of the
Voice DAA line side device (Si3011, Si3018 or Si3019.)
To ensure that the device maintains the off-hook line
state during these events, the BTE bit should be set. If
such an event occurs while the BTE bit is set, the BTD
and BTDI bits will be asserted. A zero must be written to
the BTE bit to clear the BTD and BTDI bits. An external
interrupt can optionally be triggered by the BTDI bit by
setting the BTDM and INTE bits.
C1,C2
C3
0.027 µF, 50 V, ±10%
0.01 µF, 250 V, ±10%
L1
3.3 mH, >120 mA, <10 , ±10%
10 mH, >40 mA, <10 , ±10%
L2
The billing tone filter affects the DAA’s ac termination
and return loss. The global compromise complex ac
termination as selected by ACIM[3:0] = 1111 passes
global return loss specifications with and without the
billing tone filter by at least 3 dB. This ac termination is
optimized for frequency response and hybrid
In the event that a line disturbance causes the loop
current to collapse below the minimum required
operating current of the Voice DAA, the DOD and DODI
Rev. 1.5
35
Si3050 + Si3011/18/19
cancellation and has greater than 4 dB of margin with or 3. Assert the ONHM bit (Register 5, bit 3) to enable
without the dongle for South Africa, Australia, TBR21,
caller ID data detection. The caller ID data is passed
across the RNG 1/2 pins and presented to the host
via the DTX pin.
Germany,
and
Switzerland
country-specific
specifications.
4. Clear the ONHM bit after the caller ID data is
received.
5.24. On-Hook Line Monitor
The on-hook line monitor mode allows the Si3050 to
receive line activity when in an on-hook state. This
mode is typically used to detect caller ID data (see
“5.25.Caller ID”) and is enabled by setting the ONHM bit
(Register 5, bit 3). Caller ID data can be gained up or
attenuated using the receive gain control bits in
Registers 39 and 41.
5.25.2. Type II Caller ID (Si3011 and Si3019 Line-Side
Device Only)
Type II Caller ID sends the CID data while the phone is
off-hook. This mode is often referred to as caller ID/
call waiting (CID/CW). To receive the CID data when
off-hook, use the following procedure (also see
Figure 26):
5.25. Caller ID
1. The Caller Alert Signal (CAS) tone is sent from the
central office (CO) and is digitized along with the line
data. The host processor detects the presence of
this tone.
The Si3050 can pass caller ID data from the phone line
to a caller ID decoder connected to the DAA.
5.25.1. Type I Caller ID
2. The DAA must check if there is another parallel
device on the same line, which is accomplished by
briefly going on-hook, measuring the line voltage,
and returning to an off-hook state.
Type I Caller ID sends the CID data when the phone is
on-hook.
In systems where the caller ID data is passed on the
phone line between the first and second rings, utilize the
following method to capture the caller ID data:
a. Set the CALD bit (Register 17, bit 5) to disable
the calibration that automatically occurs when
going off-hook.
1. After identifying a ring signal using one of the
methods described in "5.18. Ring Detection" on
page 33, determine when the first ring is complete.
b. Set the RCALD bit (Register 25, bit 5) to disable
the resistor calibration that automatically occurs
when going off-hook
2. Assert the ONHM bit (Register 5, bit 3) to enable
caller ID data detection. The caller ID data is passed
across the RNG 1/2 pins and presented to the host
via the DTX pin.
c. Set the FOH[1:0] bits (Register 31 bits 6:5) to 11
to reduce the time period for the off-hook counter
to 8 ms allowing compliance to the Type II CID
timing requirements.
3. Clear the ONHM bit after the caller ID data is
received.
In systems where the caller ID data is preceded by a
line polarity (battery) reversal, use the following method
to capture the caller ID data:
d. Clear the OH bit (Register 5, bit 0). This puts the
DAA into an on-hook state. The RXM bit
(Register 15, bit 3) also can be set to mute the
receive path.
1. Enable full wave rectified ring detection (RFWE,
Register 18, bit 1).
e. Read the LVS bits to determine the state of the
line. If the LVS bits read the typical on-hook line
voltage, then there are no parallel devices active
on the line, and CID data reception can be
continued. If the LVS bits read well below the
typical on-hook line voltage, then there are one or
more devices present and active on the same line
that are not compliant with Type II CID. Do not
continue CID data reception.
2. Monitor the RDTP and RDTN register bits (or the
POLI bit with the Si3011 or Si3019 line-side) to
identify if a polarity reversal or a ring signal has
occurred. A polarity reversal trips either the RDTP or
RDTN ring detection bits, therefore the full-wave ring
detector must be used to distinguish a polarity
reversal from a ring. The lowest specified ring
frequency is 15 Hz; so, if a battery reversal occurs,
the DSP should wait a minimum of 40 ms to verify
that the event is a battery reversal and not a ring
signal. This time is greater than half the period of the
longest ring signal. If another edge is detected
during this 40 ms pause, this event is characterized
as a ring signal and not a battery reversal.
36
Rev. 1.5
Si3050 + Si3011/18/19
f. Set the OH bit to return to an off-hook state.
Immediately after returning to an off-hook state,
the off-hook counter must be allowed to expire.
This allows the line voltage to settle before
transmitting or receiving data. After 8 ms normal
data transmission and reception can begin. If a
non-compliant parallel device is present, then a
reply tone is not sent by the host tone generator
and the CO does not send the CID data. If all
devices on the line are Type II CID compliant,
then the host must mute its upstream data output
to avoid the propagation of its reply tone and the
subsequent CID data. When muting its upstream
data output, the host processor should return an
acknowledgement (ACK) tone to the CO
3. The CO then responds with CID data after receiving
the CID data, the host processor unmutes the
upstream data output and continues with normal
operation.
4. The muting of the upstream data path by the host
processor mutes the handset in a telephone
application so the user cannot hear the
acknowledgement tone and CID data being sent.
5. The CALD and the RCALD bits can be cleared to
re-enable the automatic calibrations when going
off-hook. The FOH[1:0] bits also can be programmed
to 01 to restore the default off-hook counter time.
Because of the nature of the low-power ADC, the data
presented on DTX can have up to a 10% dc offset. The
caller ID decoder must either use a high-pass or a
band-pass filter to accurately retrieve the caller ID data.
requesting transmission of CID data.
1
5
2
3
4
Off-Hook Counter
and Calibration
(402.75 ms nominally)
CAS Tone
Received
Off-Hook Counter
(8 ms)
LINE
On-Hook
Off-Hook
On-Hook
Off-Hook
Ack
FOH[1] Bit
FOH[0] Bit
RCALD Bit
CALD Bit
OH Bit
Notes:
1. The off-hook counter and calibrations prevent transmission or reception of data for 402.75 ms (default) for the line
voltage to settle.
2. The caller alert signal (CAS) tone transmits from the CO to signal an incoming call.
3. The device is taken on-hook to read the line voltage in the LVS bits to detect parallel handsets. In this mode, no data is
transmitted on the DTX pin.
4. When the device returns off-hook, the normal off-hook counter is reduced to 8 ms. If the CALD and RCALD bits are set,
then the automatic calibrations are not performed.
5. After allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. If CID data
reception is required, send the appropriate signal to the CO at this time.
Figure 26. Implementing Type II Caller ID on the Si3050+Si3011/19
presents an 800 impedance to the line to reduce the
hookswitch current. At this time, the DAA also sets the
OPD bit (Register 19, bit 0) to indicate that an overload
condition exists. The line current detector within the
DAA has a threshold that is dependent on the ILIM bit
(Register 26). When ILIM = 0, the overload detection
threshold equals 160 mA. When ILIM = 1, the overload
detection threshold equals 60 mA. The OPE bit should
always be cleared before going off-hook.
5.26. Overload Detection
The Si3050 can be programmed to detect an overload
condition that exceeds the normal operating power
range of the DAA circuit. To use the overload detection
feature, the following steps should be followed:
1. Set the OH bit (Register 5, bit 0) to go off-hook, and
wait 25 ms to allow line transients to settle.
2. Enable overload detection by then setting the OPE
bit (Register 17, bit 3).
If the DAA senses an overload situation it automatically
Rev. 1.5
37
Si3050 + Si3011/18/19
(Registers 40–41) enable gain or attenuation in 0.1 dB
increments up to 1.5 dB for the transmit and receive
paths. The TGA3 and RGA3 bits select either gain or
attenuation. The transmit and receive paths can be
individually muted with the TXM and RXM bits
(Register 15). The signal flow through the Si3050 and
the Si3011/18/19 is shown in Figures 27–28.
5.27. Gain Control
The Si3050 supports multiple levels of gain and
attenuation for the transmit and receive paths.
The TXG2 and RXG2 bits (Registers 38–39) enable
gain or attenuation in 1 dB increments for the transmit
and receive paths (up to 12 dB gain and 15 dB
attenuation). The TGA2 and RGA2 bits select either
gain or attenuation. The TXG3 and RXG3 bits
DAC
ACT
TX
Analog
Hybrid
To
Si3050
Link
CO
0.6 Hz
HPF
ADC
Figure 27. Si3011/18/19 Signal Flow Diagram
IIRE
Digital
Filter
TXG3
TXA3
TXG2
TXA2
1 dB
Attenuation
Steps
DRX
DTX
1 dB
Gain
Steps
0.1 dB
Gain/ATT
Steps
Digital
Hybrid
To
Si3011/18/19
Link
0.1 dB
1 dB
1 dB
Gain
Steps
Gain/ATT
Steps
Attenuation
Steps
IIRE
Digital
Filter
Selectable
200 Hz
HPF
RXG3
RXA3
RXG2
RXA2
Figure 28. Si3050 Signal Flow Diagram
Coefficients are 2s complement, where unity is
represented as binary 0100 0000b, the maximum value
as binary 0111 1111b, and the minimum value as binary
1000 000b. See AN84 for a more detailed description of
the digital hybrid and how to use it.
5.28. Transhybrid Balance
The Si3050 contains an on-chip analog hybrid that
performs the 2- to 4-wire conversion and near-end echo
cancellation. This hybrid circuit is adjusted for each ac
termination setting selected to achieve a minimum
transhybrid balance of 20 dB when the line impedance
matches the impedance set by ACIM.
The Si3050 also offers a digital hybrid stage for
additional near-end echo cancellation. For each ac
termination setting, the eight programmable hybrid
registers (Registers 45–52) can be programmed with
coefficients to increase cancellation of real-world line
impedances. This digital filter can produce 10 dB or
greater of near-end echo cancellation in addition to the
trans-hybrid loss from the analog hybrid circuitry.
38
Rev. 1.5
Si3050 + Si3011/18/19
increased to 16 kHz by setting the HSSM bit
(Register 7, bit 3). Regardless of the sample rate
frequency, the serial data communication rate of the
PCM and GCI highways remains 8 kHz. When the
16 kHz sample rate is selected, additional timeslots in
the PCM or GCI highway are used to transfer the
additional data.
5.29. Filter Selection
The Si3050 supports additional filter selections for the
receive and transmit signals as defined in Tables 10 and
11. The IIRE bit (Register 16, bit 4) selects between the
IIR and FIR filters. The IIR filter provides a shorter, but
non-linear, group delay alternative to the default FIR
filter, and only operates with an 8 kHz sample rate. The
FILT bit (Register 31, bit 1) selects
a –3 dB low
5.31. Communication Interface Mode
Selection
frequency pole of 5 Hz when cleared and a –3 dB low
frequency pole of 200 Hz (per EIA/TIA 464) when set.
The FILT bit affects the receive path only.
The Si3050 supports two communication interface
protocols:
5.30. Clock Generation
PCM/SPI mode where data and control information
transmission/reception occurs across separate
buses (PCM highway for data, and SPI port for
control).
The Si3050 generates the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz, 1.53 MHz, 2.048 MHz, 4.09 MHz, or
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined internally by the DAA and is
transferred into internal registers after a reset. These
internal registers are not accessible through register
reads or writes. Figure 29 shows the operation of the
Si3050 clock circuitry.
GCI mode where data and control information is
multiplexed and transmission/reception occurs
across the GCI highway bus.
A pin-strapping method (specifically, the state of SCLK
on power-up [reset]) is used to select between the two
communication interface protocols. Tables 19 and 20
specify how to select a communication mode, and how
the various pins are used in each mode.
The PLL clock synthesizer settles quickly after powerup.
However, the settling time depends on the PCLK
frequency and it can be approximately predicted by the
following equation:
When operating in PCM/SPI mode, the GCI control
register should not be written (i.e., Register 42 must
each remain set at 0000_0000 when using the PCM/
SPI highway mode). Similarly, when operating in GCI
highway mode the PCM registers should not be written
(i.e., Registers 33–37 must remain set to 0000_0000
when using the GCI highway mode).
T
= 64/F
PCLK
settle
For all valid PCLK frequencies listed above, the default
line sample rate is 8 kHz. This sample rate can be
N
PCLK
2
PFD
VCO
2
16.384 MHz
DIV M
Internal PLL
Register
Figure 29. PLL Clock Synthesizer
Rev. 1.5
39
Si3050 + Si3011/18/19
Table 20. PCM or GCI Highway Mode Selection
SCLK
SDI
Mode Selected
1
0
X
0
PCM Mode
GCI Mode,
B2 Channel used
GCI Mode,
0
1
B1 Channel used
Note: Values shown are the states of the pins at the rising edge of
RESET.
Table 21. Pin Functionality in PCM or GCI Highway Mode
Pin Name
PCM Mode
GCI Mode
SDI_THRU
SPI Data Throughput pin for Daisy Chaining
Operation (Connects to the SDI pin of the
subsequent device in the daisy chain)
Sub-frame
Selector, bit 2
SCLK
SDI
SPI Clock Input
SPI Serial Data Input
SPI Serial Data Output
PCM/GCI Mode Selector
B1/B2 Channel Selector
SDO
Sub-frame
Selector, bit 1
CS
SPI Chip Select
Sub-frame
Selector, bit 0
FSYNC
PCLK
DTX
PCM Frame Sync Input
PCM Input Clock
GCI Frame Sync Input
GCI Input Clock
PCM Data Transmit
PCM Data Receive
GCI Data Transmit
GCI Data Receive
DRX
Note: This table denotes pin functionality after the rising edge of RESET and mode selection.
5.32. PCM Highway
The Si3050 contains a flexible programmable interface for the transmission and reception of digital PCM samples.
PCM data transfer is controlled via the PCLK and FSYNC inputs, the PCM Transmit and Receive Start Count
registers (Registers 34–37), and the PCM Mode Select register (Register 33). The interface can be configured to
support from 4 to 128 8-bit timeslots in each frame, which corresponds to PCLK frequencies of 256 kHz to
8.192 MHz in power of 2 increments. Time slot assignment and data delay from FSYNC edge are handled via the
TXS and RXS registers. These 10-bit values are programmed with the number of PCLK cycles following the rising
edge of FSYNC until the data transfer begins. Because the Si3050 looks for the rising edge of FSYNC, both long
and short FSYNC pulse widths can be accommodated. A value of 0 in the PCM Transmit and Receive Start Count
registers signifies that the MSB of the data should occur in the same cycle as the rising edge of FSYNC.
40
Rev. 1.5
Si3050 + Si3011/18/19
By setting the correct starting point of the data, the Si3050 can operate with buses having multiple devices
requiring different time slots. The DTX pin is high impedance except during transmission of an 8-bit PCM sample.
DTX returns to high impedance either on the negative edge of PCLK during the LSB or on the positive edge of
PCLK following the LSB. This behavior is based on the setting of the TRI bit in the PCM Mode Select register.
Tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the
risk of driver contention. In addition to 8-bit data modes, a 16-bit linear mode is also provided. This mode can be
activated via the PCMF bits in the PCM Mode Select register. Double-clocked timing also is supported in which the
duration of a data bit is two PCLK cycles. This mode is activated via the PHCF bit in the PCM Mode Select register.
Setting the TXS or RXS registers greater than the number of PCLK cycles in a sample period stops data
transmission or reception. Figures 30–33 illustrate the usage of the PCM highway interface to adapt to common
PCM standards.
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18
PCLK_CNT
DRX
MSB
MSB
LSB
LSB
DTX
HI-Z
HI-Z
Figure 30. PCM Highway Transmission, Short FSYNC, Single Clock Cycle Delayed Transmission
(TXS = RXS = 0, PHCF = 0, TRI = 1)
Rev. 1.5
41
Si3050 + Si3011/18/19
PC LK
FSYN C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
P C LK _CN T
D R X
M SB
M SB
LSB
LSB
D TX
H I-Z
H I-Z
Figure 31. PCM Highway Transmission, Long FSYNC (TXS = RXS = 0, PHCF = 0, TRI = 1)
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PCLK_CNT
DRX
MSB
MSB
LSB
DTX
HI-Z
HI-Z
LSB
Figure 32. PCM Highway Transmission, Long FSYNC, Delayed Data Transfer
(TXS = RXS = 10, PHCF = 0, TRI = 1)
42
Rev. 1.5
Si3050 + Si3011/18/19
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PCLK_CNT
DRX
MSB
MSB
LSB
LSB
DTX
HI-Z
HI-Z
Figure 33. PCM Highway Double Clocked Transmission, Short FSYNC
(TXS = RXS = 0, PHCF = 1, TRI = 1)
Rev. 1.5
43
Si3050 + Si3011/18/19
5.33. Companding in PCM Mode
The Si3050 supports both µ-Law and A-Law companding formats in addition to 16-bit linear data. The 8-bit
companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and four step bits. µ-Law
is commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is selected
via the PCMF bits (Register 33). Table 22 on page 45 and Table 23 on page 46 define the µ-Law and A-Law
encoding formats. If linear mode is used the resulting 16-bit data is transmitted in two consecutive 8-bit PCM
highway timeslots as shown in Figure 34.
5.34. 16 kHz Sampling Operation in PCM Mode
The Si3050 can be configured to support a 16 kHz sampling rate and transmit the data on an 8 kHz PCM or GCI
highway bus. By setting the HSSM bit (Register 7, bit 3) to 1, the DAA changes its sampling rate, Fs, to 16 kHz if it
was originally configured for an 8 kHz sampling rate. If µ-law or A-law companding is used, the resulting 8-bit
samples are transmitted in two consecutive 8-bit PCM highway timeslots. If linear mode is used, the resulting 16-bit
samples are transmitted in four consecutive 8-bit PCM highway timeslots as shown in Figure 35.
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18
PCLK_CNT
DRX
MSB
MSB
LSB
LSB
DTX
HI-Z
Figure 34. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode
(TXS = RXS = 0, PHCF = 0, TRI = 1, PCMF = 11)
PCLK
FSYNC
PCLK_CNT
DRX
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37
MSB
MSB
LSB
DTX
HI-Z
HI-Z
LSB
Sample 1
Sample 2
Figure 35. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode
(TXS = RXS = 0, PHCF = 0, TRI = 1, PCMF = 11, HSSM = 1)
44
Rev. 1.5
Si3050 + Si3011/18/19
Table 22. µ-Law Encode-Decode Characteristics1,2
Segment #Intervals x Interval Size
Number
Value at Segment Endpoints Digital Code
Decode Level
8
16 x 256
8159
.
.
.
4319
4063
10000000b
10001111b
8031
4191
2079
1023
495
231
99
7
6
5
4
3
2
1
16 x 128
16 x 64
16 x 32
16 x 16
16 x 8
.
.
.
2143
2015
10011111b
10101111b
10111111b
11001111b
11011111b
11101111b
.
.
.
1055
991
.
.
.
511
479
.
.
.
239
223
.
.
.
103
95
16 x 4
.
.
.
35
31
33
15 x 2
.
.
.
3
1
0
__________________
1 x 1
11111110b
11111111b
2
0
Notes:
1. Characteristics are symmetrical about analog 0 with sign bit = 1 for negative analog values.
2. Digital code includes inversion of both sign and magnitude bits.
Rev. 1.5
45
Si3050 + Si3011/18/19
Table 23. A-Law Encode-Decode Characteristics1,2
Segment #Intervals x interval size
Number
Value at segment endpoints Digital Code
Decode Level
7
16 x 128
4096
3968
.
.
2143
2015
10101010b
10100101b
4032
2112
1056
528
264
132
66
6
16 x 64
16 x 32
16 x 16
16 x 8
.
.
.
1055
991
10110101b
10000101b
10010101b
11100101b
11110101b
11010101b
5
.
.
.
511
479
4
.
.
.
239
223
3
.
.
.
103
95
2
16 x 4
.
.
.
35
31
1
32 x 2
.
.
.
2
0
1
Notes:
1. Characteristics are symmetrical about analog 0 with sign bit = 1 for negative analog values.
2. Digital code includes inversion of all even numbered bits.
46
Rev. 1.5
Si3050 + Si3011/18/19
5.35. SPI Control Interface
The control interface to the Si3050 is a 4-wire interface modeled on commonly available micro-controller and serial
peripheral devices. The interface consists of four pins: clock (SCLK), chip select (CS), serial data input (SDI), and
serial data output (SDO). In addition, the Si3050 includes a serial data through output pin (SDITHRU) to support
daisy chain operation of up to 16 devices. The device can operate with 8-bit and 16-bit SPI controllers. Each SPI
operation consists of a control byte, an address byte (of which only the six LSBs are used internally), and either
one or two data bytes depending on the width of the controller. Bytes are transmitted MSB first.
There are a number of variations of usage on this four-wire interface as follows:
Continuous clocking. During continuous clocking, assertion of the CS pin controls the data transfers. The CS
pin must be asserted before the falling edge of SCLK on which the first bit of data is expected during a read
cycle, and must remain low for the duration of the 8-bit transfer (command/address or data), going high after the
last rising edge of SCLK after the transfer.
Clock only during transfer. The clock is active during the actual byte transfers only. Each byte transfer consists
of eight clock cycles in a return to 1 format.
SDI/SDO wired operation. Independent of the clocking options described, the SDI and SDO pins can be treated
as two separate lines or wired together if the master can tri-state its output during the data byte transfer of a
read operation.
The SPI state machine resets when the CS pin is asserted during an operation on an SCLK cycle that is not a
multiple of eight. This provides a mechanism for the controller to force the state machine to a known state in the
case where the controller and the device are not synchronized.
The control byte has the following structure and is presented on the SDI pin MSB first.
7
6
5
1
4
0
3
2
1
0
BRCT
R/W
CID[0]
CID[1]
CID[2]
CID[3]
The bits are defined as follows:
Indicates a broadcast operation that is intended for all devices in the daisy chain. This is only
valid for write operations as it causes contention on the SDO pin during a read.
7
6
BRCT
R/W
Read/Write Bit.
1 = Read operation.
0 = Write operation.
5
4
1
0
This bit must be 1 at all times.
This bit must be 0 at all times.
This field indicates the channel that is targeted by the operation. The 4-bit channel value is pro-
vided LSB first. The devices reside on the daisy chain such that device 0 is nearest to the con-
troller and device 15 is furthest away in the SDI/SDITHRU chain. See Figure 36.
As the CID information propagates down the daisy chain, each channel decrements the CID by
1. The device that receives a value of 0 in the CID field responds to the SPI transaction. See
Figure 37. If a broadcast to all devices connected to the chain is requested, the CID do not
decrement. In this case, the same 8- or 16-bit data is presented to all channels regardless of
the CID values.
3:0
CID[0:3]
Rev. 1.5
47
Si3050 + Si3011/18/19
SDO
SCLK
CS
SDI
SCLK
CPU
CS
Si3050 #1
Channel 0
SDITHRU
SDO
SDI
SDI
SCLK
CS
Si3050 #2
Channel 1
SDO
SDITHRU
SCLK
CS
SDI
Si3050 #16
Channel 15
SDITHRU
SDO
Figure 36. SPI Daisy Chain Control Architecture
SPI Control Byte
BRCT
1
1
1
1
1
0
0
0
0
0
CID[0]
CID[1]
CID[2]
CID[3]
R/W
0
0
0
0
0 or 1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
SDI0
SDI1
SDI2
SDI3
0 or 1
0 or 1
0 or 1
0
0
0 or 1
0 or 1
1
1
0
0
0
1
1
1
1
1
1
1
SDI14
SDI15
Figure 37. Sample SPI Control Byte to Access Channel 0
48
Rev. 1.5
Si3050 + Si3011/18/19
1
0
1
0
X
X
X
X
SDI0-15
Figure 38. Sample SPI Control Byte for Broadcast Mode (Write Only)
In Figure 37 the CID field is 0. As this field is decremented in LSB to MSB order, the value decrements for each SDI
down the line. The BRCT and R/W bits remain unchanged as the control word passes through the entire chain. A
unique CID is presented to each device, and the device receiving a CID value of 0 is the target of the operation
(channel 0 in this case). Figure 38 illustrates that in broadcast mode, all bits pass through the chain without
permutation.
CSB
SCLK
SDI
CONTROL
ADDRESS
DATA [7:0]
Hi-Z
SDO
Figure 39. Write Operation via an 8-bit SPI Port
CSB
SCLK
SDI
CONTROL
ADDRESS
XXXXXXXXXXXX
Data [7:0]
SDO
Figure 40. Read Operation via an 8-bit SPI Port
Figure 39 and Figure 40 illustrate WRITE and READ operations via an 8-bit SPI controller. Each of these
operations are performed as a 3-byte transfer. The CS pin is asserted between each byte. The CS pin must be
asserted before the first falling edge of SCLK after the DATA byte to indicate to the state machine that only one
byte should be transferred. The state of the SDI pin is ignored during the DATA byte of a read operation.
CSB
SCLK
SDI
CONTROL
ADDRESS
Data [7:0]
X X X X X X X X
Hi - Z
SDO
Figure 41. Write Operation via a 16-bit SPI Port
Rev. 1.5
49
Si3050 + Si3011/18/19
CSB
SCLK
X X X X X X X X
Data [7:0]
X X X X X X X X
Data [7:0]
SDI
CONTROL
ADDRESS
SDO
Same byte repeated twice.
Figure 42. Read Operation via a 16-bit SPI Port
Figures 41 and 42 illustrate WRITE and READ
operations via a 16-bit SPI controller. These operations
require a 4-byte transfer arranged as two 16-bit words.
The CS pin does not go high when the eighth bit of data
is received, which indicates to the SPI state machine
that eight more SCLK pulses follow to complete the
operation. In the case of a WRITE operation, the last
eight bits are ignored. In a read operation, the 8-bit data
value is repeated so that the data may be captured
during the last half of a data transfer if required by the
controller. The Si3050 autodetects the SPI mode (16-bit
or 8-bit mode).
Table 24. GCI Mode Sub-Frame Selection
SDI_THRU SDO CS
GCI Subframe 0 Selected
(Voice channels 1–2)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
GCI Subframe 1 Selected
(Voice channels 3–4)
GCI Subframe 2 Selected
(Voice channels 5–6)
GCI Subframe 3 Selected
(Voice channels 7–8)
5.36. GCI Highway
The Si3050 contains an alternate communication
interface to the SPI and PCM highway control and data
interface. The general circuit interface (GCI) can be
used for the transmission and reception of control and
data information onto a GCI highway bus. The PCM and
GCI highways are 4-wire interfaces and share the same
pins. The SPI control interface is not used as a
communication interface in the GCI highway mode, but
rather as hardwired channel selector pins.
GCI Subframe 4 Selected
(Voice channels 9–10)
GCI Subframe 5 Selected
(Voice channels 11–12)
GCI Subframe 6 Selected
(Voice channels 13–14)
GCI Subframe 7 Selected
(Voice channels 15–16)
When GCI mode is selected, the sub-frame selection
pins must be tied to the correct state to select one of
eight sub-frame timeslots in the GCI frame (Table 24).
These pins must remain in this state when the Si3050 is
operating. Selecting a particular subframe automatically
causes that individual Si3050 to transmit and receive on
the appropriate sub-frame in the GCI frame, which is
initiated by an FSYNC pulse. No more register settings
are needed to select which sub-frame a device uses,
and the sub-frame for a particular device cannot be
changed when in operation. Only one Si3050 DAA can
be assigned per sub-frame, which allows a total of eight
DAAs to be connected to the same GCI highway bus.
GCI mode supports a 1x and a 2x PCLK rate as shown
in Figures 5 and 6 on pages 13 and 14, respectively.
The PCLK rate is autodetected and no internal register
settings are needed to support either 1x or 2x PCLK
mode.
The GCI highway requires either a 2.048 or 4.096 MHz
clock frequency on the PCLK pin, and an 8 kHz frame
sync input on the FSYNC pin. The overall unit of data
used to communicate on the GCI highway is a frame,
which is 125 µs in length. Each frame is initiated by a
pulse on the FSYNC pin and the rising edge signifies
the beginning of the next frame. In 2x PCLK mode,
there are twice as many PCLK cycles during each
125 µs frame versus 1x PCLK mode. Each frame
consists of eight fixed timeslot sub-frames that are
assigned using the Sub-Frame Select pins as described
in Table 21 on page 40 (SDI_THRU, SDO, and CS).
Within each sub-frame are four channels (bytes) of
data, including the two voice data channels (B1 and
B2), one Monitor channel (M) for initialization and setup
of the device, and one Signaling and Control channel
50
Rev. 1.5
Si3050 + Si3011/18/19
(SC) for communicating status of the device and for used with a 16 kHz sample rate, the samples are
initiating commands. Within the SC channel are six transmitted in both the B1 and B2 channels of a single
Command/Indicate (C/I) bits and two handshaking bits subframe. If 16-bit linear mode is used, the resulting
(MR and MX). The C/I bits are used for status and 16-bit samples are transmitted in both the B1 and B2
command communication, whereas the handshaking channels of two consecutive subframes. In this case,
bits Monitor Receive (MR) and Monitor Transmit (MX) assign one DAA per two subframes.
are used for data exchanges in the Monitor channel.
5.39. Monitor Channel
Figure 43 illustrates the contents of a GCI highway
frame.
The Monitor channel is used for initialization and setup
of the Si3050. It also can be used for general
communication with the Si3050 by allowing read and
5.37. Companding in GCI Mode
The Si3050 supports µ-Law and A-Law companding write access to the Si3050’s registers. Use of the
formats in addition to 8-bit or 16-bit linear data. The 8-bit monitor channel requires manipulation of the MR and
companding schemes are described in "5.33. MX handshaking bits, located in bits 1 and 0 of the SC
Companding in PCM Mode" on page 44 and are shown channel described below. For purposes of this
in Table 22 and Table 23. If 16-bit linear mode is used, specification, “downstream” is identified to be the data
the resulting 16-bit samples are transmitted in both the sent by a host to the Si3050. “Upstream” is identified to
B1 and B2 channels of a single subframe. For proper be the data sent by the Si3050 to a host.
operation, select all Si3050 DAAs to use the B1 channel
with only one DAA per subframe.
Figure 43 illustrates the Monitor channel communication
protocol. For successful communication with the
Si3050, the transmitter should anticipate the falling
edge of the receiver’s acknowledgement. This also
maximizes communication speed. Because of the
5.38. 16 kHz Sampling Operation in GCI
Mode
The Si3050 can be configured to support a 16 kHz
sampling rate (as described in "5.34. 16 kHz Sampling
Operation in PCM Mode" on page 44) and transmit the
data on an 8 kHz GCI Highway bus. If 8-bit samples are
handshaking protocol required for successful
communication, the data transfer rate using the Monitor
channel is less than 8 kbytes/second.
125 s
FSYNC
SF0
SF1
SF2
SF3
SF4
SF5
SF6
SF7
Sub-Frame
8
8
8
B1
B2
M
C/I MR MX
0
1
2
6
1
1
Channel
SC Channel
Figure 43. Time-Multiplexed GCI Highway Frame Structure
Rev. 1.5
51
Si3050 + Si3011/18/19
1st Byte
2nd Byte
3rd Byte
MX
Transmitter
MX
MR
Receiver
MR
ACK
ACK
ACK
1st Byte
2nd Byte
3rd Byte
125 s
Figure 44. Monitor Handshake Timing
The Idle state is achieved by the MX and MR bits being held inactive (signal is high) for two or more frames. When
a transmission is initiated by a host device, an active state (signal is low) is present on the downstream MX bit. This
signals to the Si3050 that a transmission has begun on the Monitor channel and the Si3050 should begin accepting
data from host device. The Si3050, after reading the data on the Monitor channel, acknowledges the initial
transmission by placing the upstream MR bit in an active state. The data is received and the upstream MR
becomes active in the frame immediately following the downstream MX becoming active. The upstream MR then
remains active until either the next byte is received or an end of message is detected. The end of message is
signaled by the downstream MX being held inactive for two or more consecutive frames. Receipt of initial data is
signaled by the upstream MR bit’s transitioning from an inactive to an active state. Upon receiving
acknowledgement from the Si3050 that the initial data is received, the host device places the downstream MX bit in
the inactive state for one frame and then either transmit another byte by placing the downstream MX bit in an active
state again, or signal an end of message by leaving the downstream MX bit inactive for a second frame.
When the host is performing a write command, the host only manipulates the downstream MX bit, and the Si3050
only manipulates the upstream MR bit. If a read command is performed, the host initially manipulates the
downstream MX bit to communicate the command, but then manipulates the downstream MR bit in response to the
Si3050 responding with the requested data. Similarly, the Si3050 initially manipulates its upstream MR bit to
receive the read command, and then manipulates its upstream MX bit to respond with the requested data. If the
host is transmitting data, the Si3050 always transmits a $FF value on its Monitor data byte. While the Si3050 is
transmitting data, the host should always transmit a $FF value on its Monitor byte. If the Si3050 is transmitting data
and detects a value other than a $FF on the downstream Monitor byte, the Si3050 signals an Abort.
For read and write commands, an initial address must be specified. The Si3050 responds to a read or a write
command at this address, and then subsequently increment this address after every register access.
52
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In this manner, multiple consecutive registers can be read or written in one transmission sequence. By correctly
manipulating the MX and MR bits, a transmission sequence can continue from the beginning specified address
until an invalid memory location is reached. To end a transmission sequence, the host processor must signal an
end-of-message (EOM) by placing the downstream MX and MR bits inactive for two consecutive frames. The
transmission also can be stopped by the Si3050 by signaling an Abort. This is signaled by placing the upstream
MR bit inactive for at least two consecutive cycles in response to the downstream MX bit going active. An abort is
signaled by the Si3050 for the following reasons:
A read or write to an invalid memory address is attempted
An invalid command sequence is received
A data byte was not received for at least two consecutive frames
A collision occurs on the Monitor data bytes while the Si3050 is transmitting data
When the Si3050 aborts because of an invalid command sequence, the state of the Si3050 does not change. If a
read or write to an invalid memory address is attempted, all previous reads or writes in that transmission sequence
are valid up to the read or write to the invalid memory address. If an EOM is detected before a valid command
sequence is communicated, the Si3050 returns to the idle state and remains unchanged.
Rev. 1.5
53
Si3050 + Si3011/18/19
The data presented to the Si3050 in the downstream Monitor bits must be present for two consecutive frames to be
considered valid data. The Si3050 checks to ensure it receives the same data in two consecutive frames. If not, it
does not acknowledge receipt of the data byte and waits until it does receive two consecutive identical data bytes
before acknowledging to the transmitter that it received the data. If the transmitter attempts to signal transmission
of a subsequent data byte by placing the downstream MX bit in an inactive state while the Si3050 is still waiting to
receive a valid data byte transmission of two consecutive identical data bytes, the Si3050 signals an abort and
ends the transmission. Figure 45 shows a state diagram for the Receiver Monitor channel for the Si3050. Figure 46
on page 55 shows a state diagram for the Transmitter Monitor channel for the Si3050.
Idle
MR = 1
MX x LL
Initial
State
MX
1st Byte
MX
Abort
Received
MR = 1
MR = 0
ABT
MX
MX
Any
State
MX
Byte
Valid
Wait
for LL
MX x LL
MR = 0
MR = 0
MX x LL
MX
MX x LL
MX
MX
nth Byte
received
MR = 1
Wait
for LL
MR = 0
MX x LL
New Byte
MR = 1
MX
MR: MR bit calculated and transmitted on DTX line.
MX: MX bit received data downstream (DRX line).
LL: Last look of monitor byte received on DRX line.
ABT: Abort indication to internal source.
Figure 45. Si3050 Monitor Receiver State Diagram
54
Rev. 1.5
Si3050 + Si3011/18/19
MR x MXR
MR x MXR
MXR
MR x MXR
Wait
MX = 1
Abort
MX = 1
Idle
MR = 1
Initial
State
MR x RQT
MR
MR x RQT
MR
1st Byte
EOM
MX = 0
MX = 1
MR x RQT
nth Byte
ack
MR
MX = 1
MR
MR x RQT
MR x RQT
CLS/
ABT
Wait for
ack
MX = 0
Any
State
MR: MR bit received on DRX line.
MX: MX bit calculated and expected on DTX line.
MXR: MX bit sampled on DTX line.
CLS: Collision within the monitor data byte on DTX line.
RQT: Request for transmission from internal source.
ABT: Abort request/indication.
Figure 46. Si3050 Monitor Transmitter State Diagram
Rev. 1.5
55
Si3050 + Si3011/18/19
56
Rev. 1.5
Si3050 + Si3011/18/19
Rev. 1.5
57
Si3050 + Si3011/18/19
5.40. Summary of Monitor Channel Commands
Communication with the Si3050 should be in the following format:
Byte 1: Device Address Byte
Byte 2: Command Byte
Byte 3: Register Address Byte
Bytes 4-n: Data Bytes
Bytes n+1, n+2: EOM
5.41. Device Address Byte
The Device Address byte identifies which device connected to the GCI highway receives the particular message.
This address should be the first byte sent to the Si3050 at the beginning of every transmission sequence. For Read
commands, the address sent to the Si3050 is the first byte transmitted in response to the Read command before
register data is transmitted. This Device Address byte has the following structure:
1
0
0
A
B
0
0
C
The lowest programmable bit, C, has a special function. This bit enables a register read or write, or enables a
special Channel Identification Command (CID).
C = 1: Normal command follows.
C = 0: Channel Identification Command.
The CID is a special command to identify themselves by software. For this special command, the subsequent
command byte transmitted by the host processor must be $00 (binary), and have no address or data bytes. The
Si3050 in turn responds with a fixed 2-byte identification code:
1
1
0
0
0
1
A
1
0
1
0
1
0
1
0
0
Upon sending the 2-byte identification code, the Si3050 sends an EOM (MR = MX = 1) for two consecutive frames.
When A = 0, B must be 0 or the Si3050 signals an abort due to an invalid command. In this mode, bit C is the only
other programmable bit.
A = 0: Response to CID command from the device using channel B1 is placed in Monitor Data.
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A = 1: Response to CID command from the device using channel B2 is placed in Monitor Data.
When C = 1, bits A and B are channel enable bits. When these bits are set to 1, the individual corresponding
channels receives the command in the next command byte. The channels whose corresponding bits are set to 0
ignores the subsequent command byte.
A = 1: Channel B1 receives the command.
A = 0: Channel B1 does not receive the command.
B = 1: Channel B2 receives the command.
B = 0: Channel B2 does not receive the command.
5.42. Command Byte
The Command byte has the following structure:
RW
CMD[6:0]
The RW bit is a register read/write bit.
RW = 0: A write is performed to the Si3050’s register.
RW = 1: A read is performed on the Si3050’s register.
The CMD[6:0] bits specify the actual command to be performed.
CMD[6:0] = 0000001: Read or write a register on the Si3050.
CMD[6:0] = 0000010 – 1111111: Reserved.
5.43. Register Address Byte
The Register Address byte has the following structure:
ADDRESS[7:0]
This byte contains the actual 8-bit address of the register to be read or written.
5.44. SC Channel
The SC channel consists of six C/I bits and two handshaking bits, MR and MX. One of these channels is contained
in every 4-byte sub-frame and is transmitted every frame. The handshaking bits are described in the above Monitor
Channel section. The definition of the six C/I bits depends on the direction the bits are being sent, either
transmitted to the GCI highway bus via the DTX pin or received from the GCI highway bus via the DRX pin.
5.45. Receive SC Channel
:
LSB
MSB
5
3
0
4
7
6
2
1
CIR6
CIR5
CIR4
CIR3
CIR2
CIR1
MR
MX
C/I Bits
These bits are defined as follows:
CIR6: Reserved
CIR5: Reserved
CIR4: ONHM
CIR3: TGDE
CIR2: RG
Rev. 1.5
59
Si3050 + Si3011/18/19
CIR1: OH
Data that is received must be consistent and match for at least two consecutive frames to be considered valid.
When a new command or status is communicated via the C/I bits, the data must be sent for at least two
consecutive frames to be recognized by the Si3050. The following steps describe the protocol of how C/I bits are
stored, detected, and validated. This is illustrated in Figure 49.
1. The current state of the C/I bits are stored in a primary register P. If the received C/I bits are identical to this
current state, no action is taken.
2. Upon receipt of an SC channel with C/I bits that differ from the current state, these new C/I bits are immediately
latched into a secondary register S.
3. The C/I bits in the SC channel received in the frame immediately after the SC channel just stored in S are
compared with the C/I bits in the S register.
a. If the C/I bits in these two channels are identical, then the C/I bits in the S register are loaded into the P
register and are considered a valid change of C/I bits. The Si3050 then responds accordingly to the changed
C/I bits.
b. If a set of C/I bits is latched into the S register and the subsequent set of C/I bits received does not match
either the S or P registers, then the newly received set of C/I bits are latched into the S register. This
continues to occur as long as the subsequent set of C/I bits received differs from the C/I bits in the S and
P registers.
c. If the C/I bits in the SC channel received immediately after the SC channel just stored in S do not match the
C/I bits stored in S, but DO match the C/I bits stored in P, then the single set of C/I bits stored in the S latch
are invalidated, and the current state of the C/I bits in P remains unchanged.
Receive New
CI Code
Yes
= P?
No
P: C/I Primary Register Contents
Store in S
S: C/I Secondary Register Contents
Receive New
C/I Code
Load C/I Register
With New C/I Bits
Yes
= S?
No
Yes
= P?
No
Figure 49. Protocol for Receiving C/I Bits in the Si3050
60
Rev. 1.5
Si3050 + Si3011/18/19
5.46. Transmit SC Channel
The following diagram shows the definition of the transmitted SC channel, which is transmitted MSB first.
LSB
MSB
5
3
0
4
7
6
2
1
CIT6
CIT5
CIT4
CIT3
CIT2
CIT1
MR
MX
C/I Bits
These bits are defined as follows:
CIT6: Reserved
CIT5: CVI
CIT4: DOD
CIT3: INT (represents the state of the INT pin)
CIT2: Battery Reversal (represents the state of bit 7
of the LVS register)
CIT1: TGD
Rev. 1.5
61
Si3050 + Si3011/18/19
6. Control Registers
Note: Registers not listed here are reserved and must not be written.
Table 25. Register Summary
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
2
Control 1
SR
PWMM[1:0]
PWME
IDL
HBE
Control 2
INTE
RDTM
RDTI
INTP
ROVM
ROVI
WDTEN
BTDM
BTDI
RDI
LCSOM
LCSOI
RDT
RXE
2
3
Interrupt Mask
Interrupt Source
DAA Control 1
DAA Control 2
FDTM
FDTI
DODM
DODI
ONHM
PDN
TGDM
TGDI
POLM
2
4
POLI
OH
5
RDTN
RDTP
6
PDL
7
Sample Rate Control
Reserved
HSSM
8
9
Reserved
10
11
DAA Control 3
DDL
LSID[3:0]
REVA[3:0]
System- and Line-Side Device Revision
Line-Side Device Status
Line-Side Device Revision
DAA Control 4
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
FDT
1
LCS[4:0]
REVB[3:0]
RPOL
TX/RX Gain Control 1
International Control 1
International Control 2
International Control 3
International Control 4
Call Progress RX Attenuation
Call Progress TX Attenuation
Ring Validation Control 1
Ring Validation Control 2
Ring Validation Control 3
Resistor Calibration
TXM
RXM
OPE
3
3
3
OHS
IIRE
RZ
RT
3
CALZ
MCAL
CALD
RT2
BTE
OVL
ROV
RFWE
DOD
BTD
OPD
ARM[7:0]
ATM[7:0]
RDLY[1:0]
RMX[5:0]
RAS[5:0]
RDLY[2]
RNGV
RTO[3:0]
RCC[2:0]
RCALS
RCALM
3
RCALD
MINI[1:0]
RCAL[3:0]
ILIM
3
DCV[1:0]
0
DCR
0
DC Termination Control
Reserved
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
2
Loop Current Status
LCS2[7:0]
2
Line Voltage Status
LVS[7:0]
AC Termination Control
DAA Control 5
FULL2
0
ACIM[3:0]
1
2
FULL
FOH[1:0]
PCME
OHS2
0
TGD
0
FILT
LVFD
RG
Ground Start Control
TGDE
PHCF
PCM/SPI Mode Select
PCM Transmit Start Count—Low Byte
PCM Transmit Start Count—High Byte
PCM Receive Start Count—Low Byte
PCM Receive Start Count—High Byte
TX Gain Control 2
PCML
PCMF[1:0]
TRI
TXS[7:0]
TXS[1:0]
RXS[1:0]
RXS[7:0]
TGA2
TXG2[3:0]
RX Gain Control 2
RGA2
TGA3
RGA3
RXG2[3:0]
TXG3[3:0]
RXG3[3:0]
TX Gain Control 3
RX Gain Control 3
GCI Control
GCIF[1:0]
B2D
B1D
2
Line Current/Voltage Threshold Interrupt
CVT[7:0]
2
2
2
2
Line Current/Voltage Threshold Interrupt
Control
CVI
CVS
CVM
CVP
45–52
53–58
59
Programmable Hybrid Register 1–8
Reserved
HYB1–8[7:0]
3
3
Spark Quenching Control
SQ1
SQ0
RG1
GCE
Notes:
1. Bit is available for Si3019 line-side device only.
2. Bit is available for Si3011 and Si3019 line-side devices only.
3. Bit is available for Si3018 and Si3019 line-side devices only.
62
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Register 1. Control 1
Bit
D7
SR
D6
D5
PWMM[1:0]
R/W
D4
D3
PWME
R/W
D2
D1
IDL
R/W
D0
Name
Type
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
SR
Software Reset.
0 = Enables the DAA for normal operation.
1 = Sets all registers to their reset value.
Note: Bit automatically clears after being set.
6
Reserved Read returns zero.
5:4 PWMM[1:0] Pulse Width Modulation Mode.
Used to select the type of signal output on the call progress AOUT pin.
00 = PWM output is clocked at 16.384 MHz as a delta-sigma data stream. A local density of
1s and 0s tracks the combined transmit and receive signals. Use this setting with the optional
call progress circuit shown in Figure 19 on page 20.
01 = Balanced conventional PWM output signal has high and low portions of the modulated
pulse that are centered on the 16 kHz sample clock.
10 = Conventional PWM output signal returns to logic 0 at regular 32 kHz intervals and rises
at a time in the 32 kHz period proportional to its instantaneous amplitude.
11 = Reserved.
3
PWME
Pulse Width Modulation Enable.
0 = Pulse width modulation mode disabled (AOUT).
1 = Enable pulse width modulation mode for the call progress analog output (AOUT). This
mode sums the transmit and receive audio paths and presents this as a CMOS digital-level
output of PWM data. The circuit in Figure 19 on page 20 should be used.
2
1
Reserved Read returns zero.
IDL Isolation Digital Loopback.
0 = Digital loopback across the isolation barrier is disabled.
1 = Enables digital loopback mode across the isolation barrier. The line-side device must be
enabled and off-hook prior to setting this mode. The data path includes the TX and RX filters.
0
Reserved Read returns zero.
Rev. 1.5
63
Si3050 + Si3011/18/19
Register 2. Control 2
Bit
D7
D6
D5
D4
WDTEN
R/W
D3
D2
RDI
R/W
D1
D0
Name
Type
INTE
R/W
INTP
R/W
HBE
R/W
RXE
R/W
Reset settings = 0000_0011
Bit
Name
Function
7
INTE
Interrupt Pin Enable.
0 = The AOUT/INT pin functions as an analog output for call progress monitoring purposes.
1 = The AOUT/INT pin functions as a hardware interrupt pin.
6
INTP
Interrupt Polarity Select.
0 = The AOUT/INT pin, when used in hardware interrupt mode, is active low.
1 = The AOUT/INT pin, when used in hardware interrupt mode, is active high.
5
4
Reserved Read returns zero.
WDTEN Watchdog Timer Enable.
0 = Watchdog timer disabled.
1 = Watchdog timer enabled. When set, this bit can be cleared only by a hardware reset. The
watchdog timer monitors register access. If no register access occurs within a 4 s window, the
DAA is put into an on-hook state. A read or write of a DAA register restarts the watchdog timer
counter. If the watchdog timer times out, the OH bit is cleared, placing the DAA into an
on-hook state. Setting the OH bit places the DAA back into an off-hook state.
3
2
Reserved Read returns zero.
RDI
Ring Detect Interrupt Mode.
This bit operates in conjunction with the RDTM and RDTI bits. This bit selects whether one or
two interrupts are generated for every ring burst.
0 = An interrupt is generated at the beginning of every ring burst.
1 = An interrupt is generated at the beginning and end of every ring burst. The interrupt at the
beginning of the ring burst must be serviced (by writing 0 to the RDTI bit) before the end of the
ring burst in order for both interrupts to occur.
1
0
HBE
RXE
Hybrid Enable.
0 = Disconnects hybrid in transmit path.
1 = Connects hybrid in transmit path.
Receive Enable.
0 = Receive path disabled.
1 = Enables receive path.
64
Rev. 1.5
Si3050 + Si3011/18/19
Register 3. Interrupt Mask
Bit
D7
D6
D5
D4
D3
D2
LCSOM
R/W
D1
D0
Name
Type
RDTM
R/W
ROVM
R/W
FDTM
R/W
BTDM
R/W
DODM
R/W
TGDM
R/W
POLM
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
RDTM
Ring Detect Mask.
0 = A ring signal does not cause an interrupt on the AOUT/INT pin.
1 = A ring signal causes an interrupt on the AOUT/INT pin.
6
5
4
3
ROVM
FDTM
BTDM
DODM
Receive Overload Mask.
0 = A receive overload does not cause an interrupt on the AOUT/INT pin.
1 = A receive overload causes an interrupt on the AOUT/INT pin.
Frame Detect Mask.
0 = The ISOcap losing frame lock does not cause an interrupt on the AOUT/INT pin.
1 = The ISOcap losing frame lock causes an interrupt on the AOUT/INT pin.
Billing Tone Detect Mask.
0 = A detected billing tone does not cause an interrupt on the AOUT/INT pin.
1 = A detected billing tone causes an interrupt on the AOUT/INT pin.
Drop Out Detect Mask.
0 = A line supply dropout does not cause an interrupt on the AOUT/INT pin.
1 = A line supply dropout causes an interrupt on the AOUT/INT pin.
Loop Current Sense Overload Mask.
0 = An interrupt does not occur when the LCS bits are all 1s.
1 = An interrupt occurs when the LCS bits are all 1s.
2
1
LCSOM
TGDM
TIP Ground Detect Mask.
0 = The TGD bit going active does not cause an interrupt on the AOUT/INT pin.
1 = The TGD bit going active causes an interrupt on the AOUT/INT pin.
0
POLM
Polarity Reversal Detect Mask (Si3011 and Si3019 line-side only).
This interrupt is generated from bit 7 of the LVS register. When this bit transitions, it indicates
that the polarity of TIP and RING is switched.
0 = A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin.
1 = A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin.
Rev. 1.5
65
Si3050 + Si3011/18/19
Register 4. Interrupt Source
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RDTI
R/W
ROVI
R/W
FDTI
R/W
BTDI
R/W
DODI
R/W
LCSOI
R/W
TGDI
R/W
POLI
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
RDTI
Ring Detect Interrupt.
0 = A ring signal is not occurring.
1 = A ring signal is detected. If the RDTM bit (Register 3) and INTE bit (Register 2) are set, a
hardware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared.
The RDI bit (Register 2) determines if this bit is set only at the beginning of a ring pulse, or at
the both the beginning and end of a ring pulse. This bit should be cleared after clearing the
PDL bit (Register 6) as powering up the line-side device can cause this interrupt to be trig-
gered.
6
ROVI
Receive Overload Interrupt.
0 = Normal operation.
1 = An excessive input level on the receive pin is detected. If the ROVM bit (Register 3) and
INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must
be written to 0 to clear it. This bit is identical in function to the ROV bit (Register 17) and clear-
ing this bit also clears the ROV bit.
5
4
3
FDTI
BTDI
DODI
Frame Detect Interrupt.
0 = Frame detect is established on the ISOcap link.
1 = This bit is set when the ISOcap link does not have frame lock. If the FDTM bit (Register 3)
and INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. When
set, this bit must be written to 0 to be cleared.
Billing Tone Detect Interrupt.
0 = Normal operation.
1 = The line-side power supply has been disrupted. If the BTDM bit (Register 3) and INTE bit
(Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be writ-
ten to 0 to clear it.
Drop Out Detect Interrupt.
0 = Normal operation.
1 = The line-side power supply has collapsed. (The DOD bit in Register 19 has fired.) If the
DODM bit (Register 3) and INTE bit (Register 2) are set, a hardware interrupt occurs on the
AOUT/INT pin. This bit must be written to 0 to be cleared. This bit should be cleared after
clearing the PDL bit (Register 6) as powering up the line-side device can cause this interrupt
to be triggered.
2
LCSOI
Loop Current Sense Overload Interrupt.
0 = Normal operation.
1 = The LCS bits have reached max value. If the LCSOM bit (Register 3) and the INTE bit are
set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it.
Note: LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent
situation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI
interrupt fires, the OPD bit should be checked to determine if an overcurrent situation exists.
66
Rev. 1.5
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Bit
Name
Function
1
TGDI
TIP Ground Detect Interrupt.
This bit is reverse logic as compared to the TGD bit.
0 = The CO has not grounded TIP causing current to flow.
1 = The CO has grounded TIP, causing current to flow. Once set, this bit must be written to 0
to clear it. If the TDGM bit (Register 3) and INTE bit (Register 3) are set, a hardware interrupt
occurs on the AOUT/INT pin. To clear the interrupt, write this bit to 0.
0
POLI
Polarity Reversal Detect Interrupt (Si3011 and Si3019 line-side only).
0 = Bit 7 of the LVS register has not changed states.
1 = Bit 7 of the LVS register has transitioned from 0 to 1, or from 1 to 0, indicating the polarity
of TIP and RING is switched. If the POLM bit (Register 3) and INTE bit (Register 2) are set, a
hardware interrupt occurs on the AOUT/INT pin. To clear the interrupt, write this bit to 0.
Rev. 1.5
67
Si3050 + Si3011/18/19
Register 5. DAA Control 1
Bit
D7
D6
RDTN
R
D5
RDTP
R
D4
D3
D2
RDT
R
D1
D0
OH
Name
Type
ONHM
R/W
R/W
Reset settings = 0000_0000
Bit
7
Name
Reserved Read returns zero.
Function
6
RDTN
Ring Detect Signal Negative.
0 = No negative ring signal is occurring.
1 = A negative ring signal is occurring.
5
RDTP
Ring Detect Signal Positive.
0 = No positive ring signal is occurring.
1 = A positive ring signal is occurring.
4
3
Reserved Read returns zero.
ONHM
On-Hook Line Monitor.
0 = Normal on-hook mode.
1 = Enables low-power on-hook monitoring mode allowing the host to receive line activity
without going off-hook. This mode is used for caller-ID detection.
2
RDT
Ring Detect.
0 = Reset 5 seconds after last positive ring is detected or when the system executes an
off-hook. Only a positive ring sets this bit when RFWE = 0. When RFWE = 1, either a positive
or negative ring sets this bit.
1 = Indicates a ring is occurring.
1
0
Reserved Read returns zero.
OH
Off-Hook.
0 = Line-side device on-hook.
1 = Causes the line-side device to go off-hook.
68
Rev. 1.5
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Register 6. DAA Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PDL
R/W
PDN
R/W
Reset settings = 0001_0000
Bit
7:5
4
Name
Reserved Read returns zero.
Function
PDL
Powerdown Line-Side Device.
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the line-side device in lower power mode.
3
PDN
Powerdown System-Side Device.
0 = Normal operation.
1 = Powers down the system-side device. A pulse on RESET is required to restore normal
operation.
2:0
Reserved Read returns zero.
Register 7. Sample Rate Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HSSM
R/W
Reset settings = 0000_0000
Bit
7:4
3
Name
Reserved Read returns zero.
Function
HSSM
High-Speed Sampling Mode.
0 = Sample Rate is 8 kHz.
1 = Sample Rate is 16 kHz. The PCM or the GCI highway continues to be at 8 kHz; thus,
twice as many samples are generated per device timeslot. Samples are transmitted in adja-
cent timeslots.
2:0
Reserved Read returns zero.
Rev. 1.5
69
Si3050 + Si3011/18/19
Register 8-9. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit Name
Function
7:0 Reserved Read returns zero.
Register 10. DAA Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
DDL
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:1 Reserved Read returns zero.
Digital Data Loopback.
0 = Normal operation.
0
DDL
1 = Takes data received on DRX and loops it back out to DTX before the TX and RX filters.
Output data is identical to the input data.
70
Rev. 1.5
Si3050 + Si3011/18/19
Register 11. System-Side and Line-Side Device Revision
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
LSID[3:0]
R
REVA[3:0]
R
Reset settings = xxxx_xxxx
Bit
Name
LSID[3:0] Line-Side ID Bits.
Function
7:4
These four bits will always read one of the following values, depending on which line-side
device is used:
Device
Si3011
Si3018
Si3019
LSID[3:0]
0100
0001
0011
3:0 REVA[3:0] System-Side Revision.
Four-bit value indicating the revision of the Si3050 (system-side) device.
Register 12. Line-Side Device Status
Bit
D7
D6
FDT
R
D5
D4
D3
D2
LCS[4:0]
R
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
7
Name
Reserved Read returns zero.
FDT Frame Detect.
Function
6
0 = Indicates ISOcap link has not established frame lock.
1 = Indicates ISOcap link frame lock is established.
5
Reserved Read returns zero.
Off-Hook Loop Current Monitor (3.3 mA/bit).
00000 = Loop current is less than required for normal operation.
4:0
LCS[4:0]
00100 = Minimum loop current for normal operation.
11111 = Loop current is >127 mA, and an overload condition may exist.
Rev. 1.5
71
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Register 13. Line-Side Device Revision
Bit
D7
D6
1
D5
D4
D3
D2
D1
D0
Name
Type
REVB[3:0]
R
R
Reset settings = xxxx_xxxx
Bit
7
Name
Reserved Read returns zero.
Reserved This bit always reads a one.
Function
6
5:2 REVB[3:0] Line-Side Device Revision.
Four-bit value indicating the revision of the line-side device.
1:0 Reserved Read returns zero.
Register 14. DAA Control 4
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RPOL
R/W
Reset settings = 0000_0000
Bit
7:2
1
Name
Reserved Read returns zero.
RPOL Ring Detect Polarity.
Function
0 = The RGDT pin is active low.
1 = The RGDT pin is active high.
0
Reserved Read returns zero.
72
Rev. 1.5
Si3050 + Si3011/18/19
Register 15. TX/RX Gain Control 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TXM
R/W
RXM
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
TXM
Transmit Mute.
0 = Transmit signal is not muted.
1 = Mutes the transmit signal.
6:4
3
Reserved Read returns zero.
RXM
Receive Mute.
0 = Receive signal is not muted.
1 = Mutes the receive signal.
2:0
Reserved Read returns zero.
Rev. 1.5
73
Si3050 + Si3011/18/19
Register 16. International Control 1
Bit
D7
D6
D5
D4
D3
D2
D1
RZ
D0
RT
Name
Type
OHS
R/W
IIRE
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
7
Name
Reserved These bits may be written to a zero or one.
OHS On-Hook Speed. Si3018 and Si3019 line-side only.
Function
6
This bit, in combination with the OHS2 bit (Register 31) and the SQ[1:0] bits (Register 59), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
00
Mean On-Hook Speed
Less than 0.5 ms
3 ms ±10% (meets ETSI standard)
26 ms ±10% (meets Australia spark quenching spec)
0
0
1
0
1
X
00
11
For Si3011 line-side device, this bit may be written to a zero or one.
5
4
Reserved These bits may be written to a zero or one.
IIRE
IIR Filter Enable.
0 = FIR filter enabled for transmit and receive filters. (See Figures 7–10 on page 15.)
1 = IIR filter enabled for transmit and receive filters. (See Figures 11–16 on page 16.)
3:2 Reserved Read returns zero.
1
RZ
Ringer Impedance. Si3018 and Si3019 line-side only.
0 = Maximum (high) ringer impedance.
1 = Synthesized ringer impedance used to satisfy a maximum ringer impedance specification
in countries, such as Poland, South Africa, and Slovenia.
For Si3011 line-side device, this bit may be written to a zero or one.
0
RT
Ringer Threshold Select. Si3018 and Si3019 line-side only.
This bit, in combination with the RT2 bit, is used to satisfy country requirements on ring detec-
tion. Signals below the lower level do not generate a ring detection; signals above the upper
level are guaranteed to generate a ring detection.
RT
0
RT2
0
RT Lower level
13.5 V
RT Upper level
16.5 V
rms
rms
0
1
1
0
Reserved, do not use this setting.
19.35 V 23.65 V
rms
RMS
1
1
40.5 V
49.5 V
rms
RMS
For Si3011 line-side device, this bit may be written to a zero or one.
74
Rev. 1.5
Si3050 + Si3011/18/19
Register 17. International Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
BTD
R
Name
Type
CALZ
R/W
MCAL
R/W
CALD
R/W
RT2
R/W
OPE
R/W
BTE
R/W
ROV
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
CALZ
Clear ADC Calibration.
0 = Normal operation.
1 = Clears the existing ADC calibration data. This bit must be written back to 0 after being set.
6
5
4
MCAL
CALD
RT2
Manual ADC Calibration.
0 = No calibration.
1 = Initiate manual ADC calibration.
Auto-Calibration Disable.
0 = Enable auto-calibration.
1 = Disable auto-calibration.
Ringer Threshold Select 2. Si3018 and Si3019 line-side only.
This bit, in combination with the RT bit, is used to satisfy country requirements on ring detec-
tion. Signals below the lower level do not generate a ring detection; signals above the upper
level are guaranteed to generate a ring detection.
RT
0
RT2
0
RT Lower level
13.5 V
RT Upper level
16.5 V
rms
rms
0
1
1
0
Reserved, do not use this setting.
19.35 V 23.65 V
rms
RMS
1
1
40.5 V
49.5 V
rms
RMS
For Si3011 line-side device, always write this bit to zero.
Overload Protect Enable.
0 = Disabled.
3
2
OPE
BTE
1 = Enabled.
The OPE bit should always be cleared before going off-hook.
Billing Tone Detect Enable.
The DAA can detect events, such as billing tones, that can cause a disruption in the line-side
power supply. When this bit is set, the device will maintain off-hook during such events. If a
billing tone is detected, the BTD bit (Register 17, bit 0) is set to indicate the event. Writing this
bit to zero clears the BTD bit.
0 = Billing tone detection disabled. The BTD bit is not functional.
1 = Billing tone detection enabled. The BTD bit is not functional.
Rev. 1.5
75
Si3050 + Si3011/18/19
Bit
Name
Function
1
ROV
Receive Overload.
This bit is set when the receive input has an excessive input level (i.e., receive pin goes below
ground). Writing a 0 to this location clears this bit and the ROVI bit (Register 4, bit 6).
0 = Normal receive input level.
1 = Excessive receive input level.
0
BTD
Billing Tone Detected.
This bit is set if an event, such as a billing tone, causes a disruption in the line-side power
supply. Writing a zero to BTE clears this bit.
0 = No billing tone detected.
1 = Billing tone detected.
Register 18. International Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RFWE
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:3 Reserved Read returns zero.
2
1
Reserved This bit may be written to a zero or one.
RFWE
Ring Detector Full-Wave Rectifier Enable.
When RNGV (Register 24) is disabled, this bit controls the ring detector mode and the asser-
tion of the RGDT pin. When RNGV is enabled, this bit configures the RGDT pin to either follow
the ringing signal detected by the ring validation circuit, or to follow an unqualified ring detect
one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counter timeout
of approximately 5 seconds.
RNGV
RFWE
RGDT
0
0
1
1
0
1
0
1
Half-Wave
Full-Wave
Validated Ring Envelope
Ring Threshold Crossing One-Shot
0
Reserved Read returns zero.
76
Rev. 1.5
Si3050 + Si3011/18/19
Register 19. International Control 4
Bit
D7
D6
D5
D4
D3
D2
OVL
R
D1
DOD
R
D0
OPD
R
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:3 Reserved Read returns zero.
2
1
OVL
Receive Overload Detect.
This bit has the same function as ROV (Register 17), but clears itself after the overload is
removed. See “5.22.Receive Overload Detection” on page 35. This bit is only masked by the
off-hook counter and is not affected by the BTE bit.
0 = Normal receive input level.
1 = Excessive receive input level.
DOD
Recal/Dropout Detect.
When the line-side device is off-hook, it is powered from the line itself. This bit will read 1
when loop current is not flowing. For example, if this line-derived power supply collapses,
such as when the line is disconnected, this bit is set to 1. Additionally, when on-hook, and the
line-side device is enabled, this bit is set to 1.
0 = Normal operation.
1 = Line supply dropout detected when off-hook.
0
OPD
Overload Protect Detect.
This bit is used to indicate that the DAA has detected a loop current overload. The detector fir-
ing threshold depends on the setting of the ILIM bit (Register 26).
OPD
ILIM
Overcurrent Threshold
Overcurrent Status
0
0
1
1
0
1
0
1
160 mA
60 mA
160 mA
60 mA
No overcurrent condition exists
No overcurrent condition exists
Overcurrent condition has been detected
Overcurrent condition has been detected
Rev. 1.5
77
Si3050 + Si3011/18/19
Register 20. Call Progress RX Attenuation
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
ARM[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
ARM[7:0]
AOUT Receive Path Attenuation.
When decremented from the default setting, these bits linearly attenuate the AOUT
receive path signal used for call progress monitoring. Setting the bits to all 0s mutes the
AOUT receive path.
Attenuation = 20 log(ARM[7:0]/64)
1111_1111 = +12 dB (gain)
0111_1111 = +6 dB (gain)
0100_0000 = 0 dB
0010_0000 = –6 dB (attenuation)
0001_0000 = –12 dB
...
0000_0000 = Mute
Register 21. Call Progress TX Attenuation
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
ATM[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
ATM[7:0]
AOUT Transmit Path Attenuation.
When decremented from the default settings, these bits linearly attenuate the AOUT trans-
mit path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT
transmit path.
Attenuation = 20 log(ATM[7:0]/64)
1111_1111 = +12 dB (gain)
0111_1111 = +6 dB (gain)
0100_0000 = 0 dB
0010_0000 = –6 dB (attenuation)
0001_0000 = –12 dB
...
0000_0000 = Mute
78
Rev. 1.5
Si3050 + Si3011/18/19
Register 22. Ring Validation Control 1
Bit
D7
RDLY[1:0]
R/W
D6
D5
D4
D3
D2
D1
D0
Name
Type
RMX[5:0]
R/W
Reset settings = 1001_0110
Bit
Name
Function
Ring Delay Bits 1 and 0.
7:6
RDLY[1:0]
These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
RDLY[1:0]
Delay
0 ms
256 ms
512 ms
0
0
0
00
01
10
...
1
11
1792 ms
Ring Assertion Maximum Count.
5:0
RMX[5:0]
These bits set the maximum ring frequency for a valid ring signal within a 10% margin of
error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING
event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the
timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then
the frequency of the ring is too high and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/
(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,
f_max], the following equation should be used:
1
--------------------------------------------
RMX5:0 RAS5:0 –
RMX RAS
2 f_max 2 ms
To compensate for error margin and ensure a sufficient ring detection window, it is recom-
mended that the calculated value of RMX[5:0] be incremented by 1.
Rev. 1.5
79
Si3050 + Si3011/18/19
Register 23. Ring Validation Control 2
Bit
D7
RDLY[2]
R/W
D6
D5
D4
D3
D2
D1
RCC[2:0]
R/W
D0
Name
Type
RTO[3:0]
R/W
Reset settings = 0010_1101
Bit
Name
Function
7
RDLY[2]
Ring Delay Bit 2.
This bit, in combination with the RDLY[1:0] bits (Register 22), sets the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
RDLY[1:0]
Delay
0 ms
256 ms
512 ms
0
0
0
00
01
10
...
1
11
1792 ms
6:3
RTO[3:0]
Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring
threshold crossing.
RTO[3:0]
0000
0001
0010
...
Ring Timeout
DO NOT USE THIS SETTING
128 ms
256 ms
1111
1920 ms
2:0
RCC[2:0]
Ring Confirmation Count.
These bits set the amount of time that the ring frequency must be within the tolerances set
by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal.
RCC[2:0]
000
001
010
011
100
101
110
111
Ring Confirmation Count Time
100 ms
150 ms
200 ms
256 ms
384 ms
512 ms
640 ms
1024 ms
80
Rev. 1.5
Si3050 + Si3011/18/19
Register 24. Ring Validation Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RNGV
R/W
RAS[5:0]
R/W
Reset settings = 0001_1001
Bit
Name
Function
7
RNGV
Ring Validation Enable.
0 = Ring validation feature is disabled.
1 = Ring validation feature is enabled in both normal operating mode and low-power
mode.
6
Reserved
RAS[5:0]
This bit must always be written to 0.
5:0
Ring Assertion Time.
These bits set the minimum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-
ular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out
then the frequency of the ring is too low and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every
1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range
[f_min, f_max], the following equation should be used:
1
-------------------------------------------
RAS5:0
2 f_min 2 ms
Register 25. Resistor Calibration
Bit
D7
RCALS
R
D6
RCALM
R/W
D5
RCALD
R/W
D4
D3
D2
RCAL[3:0]
R/W
D1
D0
Name
Type
Reset settings = xx0x_xxxx
Bit
Name
Function
7
RCALS
Resistor Auto Calibration.
0 = Resistor calibration is not in progress.
1 = Resistor calibration is in progress.
6
RCALM Manual Resistor Calibration.
0 = No calibration.
1 = Initiate manual resistor calibration. (After a manual calibration has been initiated, this bit
must be cleared within 1 ms.)
5
4
RCALD
Resistor Calibration Disable.
0 = Internal resistor calibration enabled.
1 = Internal resistor calibration disabled.
Reserved This bit can be written to a 0 or 1.
3:0 RCAL[3:0] Always write back the value read. Result of resistor calibration. Do not modify this value.
Rev. 1.5
81
Si3050 + Si3011/18/19
Register 26. DC Termination Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
DCV[1:0]
R/W
MINI[1:0]
R/W
0
0
ILIM
R/W
DCR
R/W
Reset settings = 0000_0000
Bit
Name
Function
TIP/RING Voltage Adjust. Si3018 and Si3019 line-side only.
7:6
DCV[1:0]
These bits adjust the voltage on the DCT pin of the line-side device, which affects the TIP/
RING voltage on the line. Low-voltage countries should use a lower TIP/RING voltage. Rais-
ing the TIP/RING voltage can improve signal headroom.
DCV[1:0] DCT Pin Voltage
00
01
10
11
3.1 V
3.2 V
3.35 V
3.5 V
For Si3011 line-side device, the only valid setting for DCV[1:0] is 10.
Minimum Operational Loop Current. Si3018 and Si3019 line-side only.
Adjusts the minimum loop current at which the DAA can operate. Increasing the minimum
operational loop current can improve signal headroom at a lower TIP/RING voltage.
MINI[1:0] Min Loop Current
5:4
MINI[1:0]
00
01
10
11
10 mA
12 mA
14 mA
16 mA
For Si3011 line-side device, the only valid setting for MINI[1:0] is 00.
3:2 Reserved These bits must always be written to 0.
Current Limiting Enable.
0 = Current limiting mode disabled.
1 = Current limiting mode enabled. This mode limits loop current to a maximum of 60 mA per
the TBR21 standard.
1
0
ILIM
DC Impedance Selection.
DCR
0 = 50 dc termination is selected. This mode should be used for all standard applications.
1 = 800 dc termination is selected.
82
Rev. 1.5
Si3050 + Si3011/18/19
Register 27. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = xxxx_xxxx
Bit Name
Function
7:0 Reserved Do not write to these register bits.
Register 28. Loop Current Status
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
LCS2[7:0]
R
Reset settings = 0000_0000
Bit
Name
Function
7:0 LCS2[7:0] Loop Current Status.
Eight-bit value returning the loop current. Each bit represents 1.1 mA of loop current.
0000_0000 = Loop current is less than required for normal operation.
Register 29. Line Voltage Status
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
LVS[7:0]
R
Reset settings = 0000_0000
Bit
Name
LVS[7:0] Line Voltage Status.
Function
7:0
Eight-bit value returning the loop voltage. Each bit represents 1 V of loop voltage. This regis-
ter operates in on- and off-hook modes. Bit seven of this register indicates the polarity of the
TIP/RING voltage. When this bit changes state, it indicates that a polarity reversal has
occurred. The value returned is represented in 2s complement format.
0000_0000 = No line is connected.
Rev. 1.5
83
Si3050 + Si3011/18/19
Register 30. AC Termination Control
Bit
D7
D6
D5
D4
D3
D2
ACIM[3:0]
R/W
D1
D0
Name
Type
FULL2
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:6 Reserved Read returns zero.
5
4
Reserved This bit may be written to a zero or one.
Enhanced Full Scale (2x) Transmit and Receive Mode.
0 = Default
FULL2
1 = Transmit/Receive 2x Full Scale
This bit changes the full scale of the ADC and DAC from 0 min to +6 dBm into 600 load (or
1.5 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26)
should be set to all 1s to avoid distortion at low loop currents.
3:0 ACIM[3:0] AC Impedance Selection.
The off-hook ac termination is selected from the following:
0000 = 600
0001 = 900
0010 = 270 + (750 || 150 nF) and 275 + (780 || 150 nF)
0011 = 220 + (820 || 120 nF) and 220 + (820 || 115 nF)
0100 = 370 + (620 || 310 nF)
0101 = 320 + (1050 || 230 nF)
0110 = 370 + (820 || 110 nF)
0111 = 275 + (780 || 115 nF)
1000 = 120 + (820 || 110 nF)
1001 = 350 + (1000 || 210 nF)
1010 = 200 + (680 || 100 nF)
1011 = 600 + 2.16 µF
1100 = 900 + 1 µF
1101 = 900 + 2.16 µF
1110 = 600 + 1 µF
1111 = Global impedance
For si3011 line-side device, always write bits 3:2 and bit 0 to zero.
84
Rev. 1.5
Si3050 + Si3011/18/19
Register 31. DAA Control 5
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
FULL
R/W
FOH[1:0]
RW
0
OHS2
R/W
0
FILT
R/W
LVFD
R/W
Reset settings = 0010_0000
Bit
Name
Function
7
FULL
Full Scale Transmit and Receive Mode. Si3018 and Si3019 line-side only.
0 = Default.
1 = Transmit/receive full scale.
This bit changes the full scale of the ADC and DAC from 0 dBm min to +3.2 dBm into a 600
load (or 1 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits
(Register 26) should be set to all 1s. The MINI[1:0] bits also should be set to all 0s. This ensures
correct operation of the full scale mode.
For Si3011 line-side device, always write this bit to zero.
6:5 FOH[1:0] Fast Off-Hook Selection.
These bits determine the length of the off-hook counter. The default setting is 128 ms.
00 = 512 ms
01 = 128 ms
10 = 64 ms
11 = 8 ms
4
3
Reserved Always write these bits to zero.
OHS2 On-Hook Speed 2.
This bit, in combination with the OHS bit (Register 16) and the SQ[1:0] bits on-hook speeds
specified are measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
00
00
Mean On-Hook Speed
Less than 0.5 ms
3 ms ±10% (meets ETSI standard)
26 ms ±10% (meets Australia spark quenching spec)
0
0
1
0
1
X
11
2
1
Reserved Always write these bits to zero.
FILT
Filter Pole Selection.
0 = The receive path has a low –3 dBFS corner at 5 Hz.
1 = The receive path has a low –3 dBFS corner at 200 Hz.
Line Voltage Force Disable (Si3011 and Si3019 line-side only).
0 = Normal operation.
0
LVFD
1 = The circuitry that forces the LVS register (Register 29) to all 0s at 3 V or less is disabled. The
LVS register may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed
if the line voltage is 0 V.
Rev. 1.5
85
Si3050 + Si3011/18/19
Register 32. Ground Start Control
Bit
D7
D6
D5
D4
D3
D2
TGD
R
D1
TGDE
W
D0
RG
W
Name
Type
Reset settings = 0000_0x11
Bit
Name
Function
7:3 Reserved Read returns zero.
2
1
TGD
TIP Ground Detect.
0 = The CO has grounded TIP, causing current to flow. When current ceases to flow, this bit
returns to a one.
1 = The CO has not grounded TIP causing current to flow.
TGDE
TIP Ground Detect Enable.
0 = The external relay connecting TIP to an isolated supply is closed, enabling current to flow
in TIP if the CO grounds TIP.
1 = The external relay connecting TIP to an isolated supply is open. In this state, the DAA is
unable to determine if the CO has grounded TIP.
0
RG
Ring Ground.
0 = The external relay connecting RING to ground is closed, causing current to flow in RING.
1 = The external relay connecting RING to ground is open, not allowing current to flow in
RING.
86
Rev. 1.5
Si3050 + Si3011/18/19
Register 33. PCM/SPI Mode Select
Bit
D7
D6
D5
D4
PCMF[1:0]
R/W
D3
D2
0
D1
D0
TRI
R/W
Name
Type
PCML
R/W
PCME
R/W
PHCF
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
PCM Analog Loopback.
0 = Normal operation.
7
PCML
1 = Enables analog data to be received from the line, converted to digital data and trans-
mitted across the ISOcap link. The data passes through the RX filter and is looped back
through the TX filter and is transmitted back out to the line.
5
PCME
PCM Enable (Registers 34–37 should be set before PCM transfers are enabled).
0 = Disable PCM transfers.
1 = Enable PCM transfers.
4:3
PCMF[1:0]
PCM Data Format.
00 = A-Law. Signed magnitude data format (refer to Table 23 on page 46).
01 = µ-Law. Signed magnitude data format (refer to Table 22 on page 45).
10 = 8-bit linear. The top 8-bits of the 16-bit linear signal are transferred, and the bottom
8-bits are discarded (2s complement data format).
11 = 16-bit linear (2s complement data format).
2
1
Reserved
PHCF
Always write this bit to zero.
PCM Highway Clock Format.
0 = 1 PCLK per data bit.
1 = 2 PCLKs per data bit.
0
TRI
Tri-state Bit 0.
0 = Tri-state bit 0 on positive edge of PCLK.
1 = Tri-state bit 0 on negative edge of PCLK.
Rev. 1.5
87
Si3050 + Si3011/18/19
Register 34. PCM Transmit Start Count—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TXS[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
TXS[7:0]
PCM Transmit Start Count.
PCM Transmit Start Count equals the number of PCLKs following FSYNC before data
transmission begins.
Register 35. PCM Transmit Start Count—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TXS[1:0]
R/W
Reset settings = 0000_0000
Bit
7:2
1:0
Name
Function
Reserved
TXS[1:0]
Read returns zero.
PCM Transmit Start Count.
PCM Transmit Start Count equals the number of PCLKs following FSYNC before data
transmission begins.
Register 36. PCM Receive Start Count—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RXS[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
RXS[7:0]
PCM Receive Start Count.
PCM Receive Start Count equals the number of PCLKs following FSYNC before data
reception begins.
88
Rev. 1.5
Si3050 + Si3011/18/19
Register 37. PCM Receive Start Count—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RXS[1:0]
R/W
Reset settings = 0000_0000
Bit
7:2
1:0
Name
Function
Reserved
RXS[1:0]
Read returns zero.
PCM Receive Start Count.
PCM Receive Start Count equals the number of PCLKs following FSYNC before data
reception begins.
Register 38. TX Gain Control 2
Bit
D7
D6
D5
D4
D3
D2
TXG2[3:0]
R/W
D1
D0
Name
Type
TGA2
R/W
Reset settings = 0000_0000
Bit
7:5 Reserved Read returns zero.
TGA2 Transmit Gain or Attenuation 2.
Name
Function
4
0 = Incrementing the TXG2[3:0] bits results in gaining up the transmit path.
1 = Incrementing the TXG2[3:0] bits results in attenuating the transmit path.
3:0 TXG2[3:0] Transmit Gain 2.
Each bit increment represents 1 dB of gain or attenuation, up to a maximum of +12 dB and
–15 dB respectively.
For example:
TGA2
TXG2[3:0]
Result
X
0
0
0
1
1
1
0000
0001
:
11xx
0001
:
0 dB gain or attenuation is applied to the transmit path.
1 dB gain is applied to the transmit path.
12 dB gain is applied to the transmit path.
1 dB attenuation is applied to the transmit path.
1111
15 dB attenuation is applied to the transmit path.
Rev. 1.5
89
Si3050 + Si3011/18/19
Register 39. RX Gain Control 2
Bit
D7
D6
D5
D4
D3
D2
RXG2[3:0]
R/W
D1
D0
Name
Type
RGA2
R/W
Reset settings = 0000_0000
Bit
7:5 Reserved Read returns zero.
RGA2 Receive Gain or Attenuation 2.
Name
Function
4
0 = Incrementing the RXG2[3:0] bits results in gaining up the receive path.
1 = Incrementing the RXG2[3:0] bits results in attenuating the receive path.
3:0 RXG2[3:0] Receive Gain 2.
Each bit increment represents 1 dB of gain or attenuation, up to a maximum of +12 dB and
–15 dB respectively.
For example:
RGA2
RXG2[3:0]
Result
X
0
0
0
1
1
1
0000
0001
:
11xx
0001
:
0 dB gain or attenuation is applied to the receive path.
1 dB gain is applied to the receive path.
12 dB gain is applied to the receive path.
1 dB attenuation is applied to the receive path.
1111
15 dB attenuation is applied to the receive path.
90
Rev. 1.5
Si3050 + Si3011/18/19
Register 40. TX Gain Control 3
Bit
D7
D6
D5
D4
D3
D2
TXG3[3:0]
R/W
D1
D0
Name
Type
TGA3
R/W
Reset settings = 0000_0000
Bit
7:5 Reserved Read returns zero.
TGA3 Transmit Gain or Attenuation 3.
Name
Function
4
0 = Incrementing the TGA3[3:0] bits results in gaining up the transmit path.
1 = Incrementing the TGA3[3:0] bits results in attenuating the transmit path.
3:0 TXG3[3:0] Transmit Gain 3.
Each bit increment represents 0.1 dB of gain or attenuation, up to a maximum of 1.5 dB.
For example:
TGA3
TXG3[3:0]
Result
X
0
0
0
1
1
1
0000
0001
:
1111
0001
:
0 dB gain or attenuation is applied to the transmit path.
0.1 dB gain is applied to the transmit path.
1.5 dB gain is applied to the transmit path.
0.1 dB attenuation is applied to the transmit path.
1111
1.5 dB attenuation is applied to the transmit path.
Rev. 1.5
91
Si3050 + Si3011/18/19
Register 41. RX Gain Control 3
Bit
D7
D6
D5
D4
D3
D2
RXG3[3:0]
R/W
D1
D0
Name
Type
RGA3
R/W
Reset settings = 0000_0000
Bit
7:5 Reserved Read returns zero.
RGA3 Receive Gain or Attenuation 2.
Name
Function
4
0 = Incrementing the RXG3[3:0] bits results in gaining up the receive path.
1 = Incrementing the RXG3[3:0] bits results in attenuating the receive path.
3:0 RXG3[3:0] Receive Gain 3.
Each bit increment represents 0.1 dB of gain or attenuation, up to a maximum of 1.5 dB.
For example:
RGA3
RXG3[3:0]
Result
X
0
0
0
1
1
1
0000
0001
:
1111
0001
:
0 dB gain or attenuation is applied to the receive path.
0.1 dB gain is applied to the receive path.
1.5 dB gain is applied to the receive path.
0.1 dB attenuation is applied to the receive path.
1111
1.5 dB attenuation is applied to the receive path.
92
Rev. 1.5
Si3050 + Si3011/18/19
Register 42. GCI Control
Bit
D7
D6
D5
D4
D3
GCIF[1:0]
R/W
D2
D1
D0
Name
Type
B2D
R/W
B1D
R/W
Reset settings = 0000_0000
Bit Name
Function
7:4 Reserved Read returns zero.
3:2 GCIF[1:0] GCI Data Format.
00 = A-Law.
01 = µ-Law.
10 = 8-bit linear. The top 8-bits of the 16-bit linear signal are transferred, and the bottom 8-bits
are discarded.
11 = 16-bit linear. B1 and B2 channels are used for the 16-bits of data. Regardless of whether
the DAA is set to transmit and receive in the B1 or B2 channel, both channels are used to
send and receive the 16-bit linear data.
1
0
B2D
B1D
Channel B2 Enable.
0 = Channel B2 transfers are disabled.
1 = Channel B2 transfers are enabled. If 16-bit linear data format is chosen, disabling the B2
channel results in only the top 8 bits of line data being sent and received in the B1 channel.
Channel B1 Enable.
0 = Channel B1 transfers are disabled.
1 = Channel B1 transfers are enabled. If 16-bit linear data format is chosen, disabling the B1
channel results in only the bottom 8 bits of line data being sent and received in the B2 chan-
nel.
Rev. 1.5
93
Si3050 + Si3011/18/19
Register 43. Line Current/Voltage Threshold Interrupt (Si3011 and Si3019 line-side only)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CVT[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
CVT[7:0] Current/Voltage Threshold.
Function
7:0
These bits determine the threshold at which an interrupt is generated from either the LCS or
LVS register. This interrupt can be generated to occur when the line current or line voltage
rises above or drops below the value in the CVT[7:0] register.
Register 44. Line Current/Voltage Threshold Interrupt Control (Si3011 and Si3019 line-side only)
Bit
D7
D6
D5
D4
D3
CVI
R/W
D2
D1
D0
Name
Type
CVS
R/W
CVM
R/W
CVP
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:4 Reserved Read returns zero.
3
CVI
Current/Voltage Interrupt.
0 = The current/voltage threshold has not been crossed.
1 = The current/voltage threshold is crossed. If the CVM and INTE bits are set, a hardware
interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to 0 to be cleared.
2
1
CVS
CVM
Current/Voltage Select.
0 = The line current shown in the LCS2 register is used to generate an interrupt.
1 = The line voltage shown in the LVS register is used to generate an interrupt.
Current/Voltage Interrupt Mask.
0 = The current/voltage threshold being triggered does not cause a hardware interrupt on the
AOUT/INT pin.
1 = The current/voltage threshold being triggered causes a hardware interrupt on the
AOUT/INT pin.
0
CVP
Current/Voltage Interrupt Polarity.
0 = The current/voltage threshold is triggered by the absolute value of the number in either
the LCS2 or LVS register falling below the value in the CVT[7:0] register.
1 = The current/voltage threshold is triggered by the absolute value of the number in either
the LCS2 or LVS register rising above the value in the CVT[7:0] register.
94
Rev. 1.5
Si3050 + Si3011/18/19
Register 45. Programmable Hybrid Register 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HYB1[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0 HYB1[7:0] Programmable Hybrid Register 1.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the first tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Register 46. Programmable Hybrid Register 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HYB2[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0 HYB2[7:0] Programmable Hybrid Register 2.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the second tap in the eight-tap filter. When
this register is set to all 0s, this filter stage does not have an effect on the hybrid response.
See the section entitled "5.28. Transhybrid Balance" on page 38 for more information on
selecting coefficients for the programmable hybrid.
Rev. 1.5
95
Si3050 + Si3011/18/19
Register 47. Programmable Hybrid Register 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HYB3[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0 HYB3[7:0] Programmable Hybrid Register 3.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the third tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Register 48. Programmable Hybrid Register 4
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HYB4[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0 HYB4[7:0] Programmable Hybrid Register 4.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the fourth tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
96
Rev. 1.5
Si3050 + Si3011/18/19
Register 49. Programmable Hybrid Register 5
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HYB5[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0 HYB5[7:0] Programmable Hybrid Register 5.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the fifth tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Register 50. Programmable Hybrid Register 6
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HYB6[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0 HYB6[7:0] Programmable Hybrid Register 6.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the sixth tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Rev. 1.5
97
Si3050 + Si3011/18/19
Register 51. Programmable Hybrid Register 7
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HYB7[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0 HYB7[7:0] Programmable Hybrid Register 7.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the seventh tap in the eight-tap filter. When
this register is set to all 0s, this filter stage does not have an effect on the hybrid response.
See the section entitled "5.28. Transhybrid Balance" on page 38 for more information on
selecting coefficients for the programmable hybrid.
Register 52. Programmable Hybrid Register 8
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HYB8[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0 HYB8[7:0] Programmable Hybrid Register 8.
These bits can be programmed with a coefficient value to adjust the hybrid response to
reduce near-end echo. This register represents the eighth tap in the eight-tap filter. When this
register is set to all 0s, this filter stage does not have an effect on the hybrid response. See
the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting
coefficients for the programmable hybrid.
Register 53-58. Reserved
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = xxxx_xxxx
Bit
Name
Reserved Do not write to these register bits.
Function
7:0
98
Rev. 1.5
Si3050 + Si3011/18/19
Register 59. Spark Quenching Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
SQ1
R/W
SQ0
R/W
RG1
R/W
GCE
R/W
Reset settings = xxxx_xxxx
Bit
7
Name
Reserved Always write this bit to zero.
Spark Quenching. Si3018 and Si3019 line-side only.
Function
6
SQ1
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
00
00
Mean On-Hook Speed
Less than 0.5 ms
3 ms±10% (meets ETSI standard)
26 ms ±10% (meets Australia spark quenching spec)
0
0
1
0
1
X
11
For Si3011 line-side device, always write this bit to zero.
Reserved Always write this bit to zero.
Spark Quenching. Si3018 and Si3019 line-side only.
5
4
SQ0
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
OHS2
SQ[1:0]
00
00
Mean On-Hook Speed
Less than 0.5 ms
3 ms±10% (meets ETSI standard)
26 ms ±10% (meets Australia spark quenching spec)
0
0
1
0
1
X
11
For Si3011 line-side device, always write this bit to zero.
3
2
Reserved Always write this bit to zero.
Receive Gain 1 (Line-side Revision E or later).
This bit enables receive path gain adjustment.
0 = No gain applied to hybrid, full scale RX on line = 0 dBm.
1 = 1 dB of gain applied to hybrid, full scale RX on line = –1 dBm.
RG1
GCE
Guarded Clear Enable (Line-side Revision E or later).
1
0
This bit (in conjunction with the R2 bit set to 1) enables the Si3050 to meet BT’s Guarded
Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw
approximately 2.5 mA of current from the line while on-hook.
0 = Default, DAA does not draw loop current.
1 = Guarded Clear enabled, DAA draws 2.5 mA while on-hook to meet Guarded Clear
requirement.
Reserved Always write this bit to zero.
Rev. 1.5
99
Si3050 + Si3011/18/19
CS
FSYNC
PCKLK
DTX
1
2
3
4
5
6
18
17
16
15
14
13
GND
VDD
VA
Si3050
Top View
C1A
DRX
C2A
GND
RGDT
RESET
Figure 50. Si3050 QFN
SDITHRU
SCLK
SDO
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
SDI
CS
GND
VDD
FSYNC
PCLK
DTX
VA
C1A
C2A
RESET
DRX
RGDT
12 TGDE
11 TGD
AOUT/INT
RG 10
Figure 51. Si3050 TSSOP
100
Rev. 1.5
Si3050 + Si3011/18/19
Table 26. Si3050 Pin Descriptions
QFN TSSOP
Pin Name
Description
Pin #
Pin #
23
1
SDO
Serial Port Data Output.
Serial port control data output.
24
1
2
3
SDI
CS
Serial Port Data Input.
Serial port control data input.
Chip Select Input.
An active low input control signal that enables the SPI Serial port. When
inactive, SCLK and SDI are ignored and SDO is high impedance.
2
4
FSYNC
Frame Sync Input.
Data framing signal that is used to indicate the start and stop of a
communication/data frame.
3
4
5
6
7
5
6
7
8
9
PCLK
DTX
Master Clock Input.
Master clock input.
Transmit PCM or GCI Highway Data Output.
Outputs data from either the PCM or GCI highway bus.
DRX
Receive PCM or GCI Highway Data Input.
Receives data from either the PCM or GCI highway bus.
RGDT
AOUT/INT
Ring Detect Output.
Produces an active low rectified version of the ring signal.
Analog Speaker Output/Interrupt Output.
Provides an analog output signal for driving a call progress speaker in AOUT
mode. Alternatively, this pin can be set to provide a hardware interrupt signal.
8
10
RG
Ring Ground Output.
Control signal for ring ground relay. Used to support ground start applications.
9
NC
NC
No connect.
No connect.
10
11
11
12
TGD
TIP Ground Detect Input.
Used to detect current flowing in TIP for supporting ground start applications.
12
13
TGDE
TIP Ground Detect Enable Output.
Control signal for the ground detect relay. Used to support ground start appli-
cations.
13
RESET
Reset Input.
An active low input that is used to reset all control registers to a defined,
initialized state. Also used to bring the Si3050 out of sleep mode.
Rev. 1.5
101
Si3050 + Si3011/18/19
Table 26. Si3050 Pin Descriptions (Continued)
QFN TSSOP
Pin Name
Description
Pin #
Pin #
14
14
C2A
Isolation Capacitor 2A.
Connects to one side of the isolation capacitor C2. Used to communicate with
the line-side device.
15
16
15
16
C1A
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor C1. Used to communicate with
the line-side device.
V
Regulator Voltage Reference.
A
This pin connects to an external capacitor and serves as the reference for the
internal voltage regulator.
17
18
19
20
17
18
19
20
V
Digital Supply Voltage.
DD
Provides the 3.3 V digital supply voltage to the Si3050.
GND
SCLK
Ground.
Connects to the system digital ground.
Serial Port Bit Clock Input.
Controls the serial data on SDO and latches the data on SDI.
SDITHRU
SDI Passthrough Output.
Cascaded SDI output signal to daisy-chain the SPI interface with additional
devices.
21
22
NC
NC
No connect.
No connect.
102
Rev. 1.5
Si3050 + Si3011/18/19
7. Pin Descriptions: Si3011/18/19
1
2
20
19
18
17 16
NC
RX
15 DCT3
IB
C1B
C2B
3
4
14
13
QB
IGND
PAD
QE2
5
6
12 SC
11 NC
7
8
9
10
Figure 52. Si3011/18/19 QFN
1
2
3
4
5
6
7
8
16 DCT2
QE
DCT
RX
15
IGND
14
13
12
11
10
9
DCT3
QB
IB
QE2
C1B
C2B
VREG
RNG1
SC
VREG2
RNG2
Figure 53. Si3011/18/19 SOIC/TSSOP
Rev. 1.5
103
Si3050 + Si3011/18/19
Table 27. Si3011/18/19 Pin Descriptions
SOIC/
TSSOP Pin Name
Pin #
QFN
Pin #
Description
1
NC
No connect.
19
1
2
3
4
5
QE
DCT
RX
Transistor Emitter.
Connects to the emitter of Q3.
20
2
DC Termination.
Provides dc termination to the telephone network.
Receive Input.
Serves as the receive side input from the telephone network.
3
IB
Internal Bias.
Provides a bias voltage to the device.
4
C1B
Isolation Capacitor 1B.
Connects to one side of isolation capacitor C1. Used to communicate with the
system-side device.
5
6
C2B
Isolation Capacitor 2B.
Connects to one side of isolation capacitor C2. Used to communicate with the
system-side device.
6
7
7
8
VREG Voltage Regulator.
Connects to an external capacitor to provide bypassing for an internal power sup-
ply.
RNG1
Ring 1.
Connects through a resistor to the TIP lead of the telephone line. Provides the ring
and caller ID signals to the DAA.
8
9
IGND
Isolated Ground. Connects to ground on the line-side interface.
9
RNG2
Ring 2.
Connects through a resistor to the RING lead of the telephone line. Provides the
ring and caller ID signals to the DAA.
10
10
VREG2 Voltage Regulator 2.
Connects to an external capacitor to provide bypassing for an internal power sup-
ply.
11
12
NC
SC
No connect.
11
12
SC Connection.
Enables external transistor network. Should be tied through a 0 resistor to I
.
GND
13
14
15
QE2
QB
Transistor Emitter 2.
Connects to the emitter of Q4.
13
14
Transistor Base.
Connects to the base of transistor Q4.
DCT3
DC Termination 3.
Provides dc termination to the telephone network.
104
Rev. 1.5
Si3050 + Si3011/18/19
Table 27. Si3011/18/19 Pin Descriptions (Continued)
SOIC/
TSSOP Pin Name
Pin #
QFN
Pin #
Description
16
17
NC
No Connect.
15
16
IGND
Isolated Ground.
Connects to ground on the line-side interface.
18
DCT2
DC Termination 2.
Provides dc termination to the telephone network.
Rev. 1.5
105
Si3050 + Si3011/18/19
8. Ordering Guide
AC
Temperature
Range
1
2
Description
Part Number
Package
Terminations
Si3050-E1-FT
Si3050-E1-GT
Si3050-E1-FM
Si3050-E1-GM
Si3011-F-FS
Si3011-F-GS
Si3011-F-FT
Si3011-F-GT
Si3011-F-FM
Si3011-F-GM
Si3018-F-FS
Si3018-F-GS
Si3018-F-FT
Si3018-F-GT
Si3018-F-FM
Si3018-F-GM
Si3019-F-FS
Si3019-F-GS
Si3019-F-FT
Si3019-F-GT
Si3019-F-FM
Si3019-F-GM
Notes:
System-side Voice DAA
System-side Voice DAA
2, 4, 16
TSSOP-20
TSSOP-20
QFN-24
0 to +70 °C
–40 to +85 °C
0 to +70 °C
2, 4, 16
System-side Voice DAA
2, 4, 16
System-side Voice DAA
2, 4, 16
QFN-24
–40 to +85 °C
0 to +70 °C
Line-side Voice DAA-FCC/TBR21 only
Line-side Voice DAA-FCC/TBR21 only
Line-side Voice DAA-FCC/TBR21 only
Line-side Voice DAA-FCC/TBR21 only
Line-side Voice DAA-FCC/TBR21 only
Line-side Voice DAA-FCC/TBR21 only
Line-side Voice DAA-Global
2
2
SOIC-16
SOIC-16
TSSOP-16
TSSOP-16
QFN-20
–40 to +85 °C
0 to +70 °C
2
2
–40 to +85 °C
0 to +70 °C
2
2
QFN-20
–40 to +85 °C
0 to +70 °C
4
SOIC-16
SOIC-16
TSSOP-16
TSSOP-16
QFN-20
Line-side Voice DAA-Global
4
–40 to +85 °C
0 to +70 °C
Line-side Voice DAA-Global
4
Line-side Voice DAA-Global
4
–40 to +85 °C
0 to +70 °C
Line-side Voice DAA-Global
4
Line-side Voice DAA-Global
4
QFN-20
–40 to +85 °C
0 to +70 °C
Line-side Voice DAA-Enhanced Global
Line-side Voice DAA-Enhanced Global
Line-side Voice DAA-Enhanced Global
Line-side Voice DAA-Enhanced Global
Line-side Voice DAA-Enhanced Global
Line-side Voice DAA-Enhanced Global
16
16
16
16
16
16
SOIC-16
SOIC-16
TSSOP-16
TSSOP-16
QFN-20
–40 to +85 °C
0 to +70 °C
–40 to +85 °C
0 to +70 °C
QFN-20
–40 to +85 °C
1. Adding the suffix “R” to the end of the part number (e.g., Si3050-E1-FTR) denotes tape-and-reel packaging.
2. All packages are RoHS-compliant.
106
Rev. 1.5
Si3050 + Si3011/18/19
9. Product Identification
The product identification number is a finished goods part number or is specified by a finished goods part number,
such as a special customer part number.
Example:
Si3050-E1-FSR
Shipping Option
Blank = Tubes
Product Designator
R = Tape and Reel
Product Revision
Package Type
S = SOIC
T = TSSOP
M = QFN
Part Type/Lead Finish
F = Commercial/Lead-Free
G = Industrial Temp/Lead-Free
Rev. 1.5
107
Si3050 + Si3011/18/19
10. Package Outline: 20-Pin TSSOP
Figure 54 illustrates the package details for the Si3050. Table 28 lists the values for the dimensions shown in the
illustration.
Figure 54. 20-Pin Thin Shrink Small Outline Package (TSSOP)
108
Rev. 1.5
Si3050 + Si3011/18/19
‘
Table 28. 20-Pin TSSOP Package Diagram Dimensions
Dimension
Min
—
Nom
—
Max
1.20
0.15
1.05
0.30
0.20
6.60
A
A1
A2
b
0.05
0.80
0.19
0.09
6.40
—
1.00
—
c
—
D
6.50
E
6.40 BSC
4.40
E1
e
4.40
0.45
0°
4.50
0.75
8°
0.65 BSC
0.60
L
L2
θ
0.25 BSC
—
aaa
bbb
ccc
0.10
0.10
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Rev. 1.5
109
Si3050 + Si3011/18/19
10.1. PCB Land Pattern: Si3050 TSSOP
Figure 55. 20-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern
Table 29. 20-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.80
0.65
0.45
1.40
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351
specifications for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition
(MMC) and a card fabrication tolerance of 0.05 mm is
assumed.
110
Rev. 1.5
Si3050 + Si3011/18/19
11. Package Outline: 24-Pin QFN
Figure 56 illustrates the package details for the Si3050. Table 30 lists the values for the dimensions shown in the
illustration.
Figure 56. 24-Pin QFN Package
Rev. 1.5
111
Si3050 + Si3011/18/19
Table 30. 24-Pin QFN Package Dimensions
Dimension
MIN
0.80
0.00
0.18
NOM
—
MAX
—
A
A1
b
—
—
—
—
D
4.00 BSC
2.20
D2
e
2.05
2.35
0.50 BSC
4.00 BSC
2.50
E
E2
L
2.35
0.30
2.65
0.50
0.40
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.08
0.10
0.05
112
Rev. 1.5
Si3050 + Si3011/18/19
12. PCB Land Pattern: Si3050 QFN
Figure 57. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern
Rev. 1.5
113
Si3050 + Si3011/18/19
Table 31. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions
Symbol
P1
MIN
2.10
2.10
0.20
0.75
NOM
2.20
2.20
0.25
0.80
MAX
2.30
2.30
0.30
0.85
P2
X1
Y1
C1
3.90
3.90
0.50
C2
E
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder mask design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 mm minimum, all the
way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter
pins.
4. A 2 x 2 array of 0.90 mm square openings on 1.20 mm pitch should be used
for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
114
Rev. 1.5
Si3050 + Si3011/18/19
13. Package Outline: 16-Pin SOIC
Figure 58 illustrates the package details for the Si3011/18/19. Table 32 lists the values for the dimensions shown in
the illustration.
Figure 58. 16-Pin Small Outline Integrated Circuit (SOIC) Package
Rev. 1.5
115
Si3050 + Si3011/18/19
Table 32. 16-Pin SOIC Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
h
0.25 BSC
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
116
Rev. 1.5
Si3050 + Si3011/18/19
13.1. PCB Land Pattern: Si3011/18/19 SOIC
Figure 59. 16-Pin Small Outline Integrated Circuit (SOIC) PCB Land Pattern
Table 33. 16-Pin Small Outline Integrated Circuit (SOIC) PCB Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern
SOIC127P600X165-16N for Density Level B (Median Land
Protrusion).
2. All feature sizes shown are at Maximum Material Condition
(MMC) and a card fabrication tolerance of 0.05 mm is
assumed.
Rev. 1.5
117
Si3050 + Si3011/18/19
14. Package Outline: 16-Pin TSSOP
Figure 60 illustrates the package details for the Si3011/18/19. Table 34 lists the values for the dimensions shown in
the illustration.
Figure 60. 16-Pin Thin Shrink Small Outline Package (TSSOP)
118
Rev. 1.5
Si3050 + Si3011/18/19
Table 34. 16-Pin TSSOP Package Diagram Dimensions
Dimension
Min
—
Nom
—
Max
1.20
0.15
1.05
0.30
0.20
5.10
A
A1
A2
b
0.05
0.80
0.19
0.09
4.90
—
1.00
—
c
—
D
5.00
E
6.40 BSC
4.40
E1
e
4.40
0.45
0°
4.50
0.75
8°
0.65 BSC
0.60
L
L2
θ
0.25 BSC
—
aaa
bbb
ccc
0.10
0.10
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.5
119
Si3050 + Si3011/18/19
14.1. PCB Land Pattern: Si3011/18/19 TSSOP
Figure 61. 16-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern
Table 35. 16-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Patten Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.80
0.65
0.45
1.40
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351
specifications for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition
(MMC) and a card fabrication tolerance of 0.05 mm is
assumed.
120
Rev. 1.5
Si3050 + Si3011/18/19
15. Package Outline: 20-Pin QFN
Figure 62 illustrates the package details for the Si3011/18/19. Table 36 lists the values for the dimensions shown in
the illustration.
Figure 62. 20-Pin Quad Flat No-Lead (QFN) Package
Rev. 1.5
121
Si3050 + Si3011/18/19
Table 36. 20-Pin QFN Package Diagram Dimensions
Dimension
MIN
0.80
0.00
0.20
0.27
NOM
0.85
MAX
—
A
A1
b
0.02
—
0.25
—
c
0.32
—
D
3.00 BSC
1.70
D2
e
1.65
1.65
1.75
1.75
.50 BSC
3.00 BSC
1.70
E
E2
f
2.53 BSC
0.40
L
0.35
0.00
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
L1
aaa
bbb
ccc
ddd
eee
Notes:
—
—
—
—
—
—
—
—
—
—
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
122
Rev. 1.5
Si3050 + Si3011/18/19
16. PCB Land Pattern: Si3011/18/19 QFN
Figure 63. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern
Rev. 1.5
123
Si3050 + Si3011/18/19
Table 37. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions
Dimension
MIN
MAX
D
D2
e
2.71 REF
1.60
1.80
0.50 BSC
2.71 REF
E
E2
f
1.60
1.80
2.53 BSC
GD
GE
W
X
2.10
2.10
—
—
—
0.34
0.28
—
Y
0.61 REF
ZE
ZD
—
—
3.31
3.31
Notes:
General
1. All dimensions shown are in milllimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
124
Rev. 1.5
Si3050 + Si3011/18/19
SILICON LABS Si3050 SUPPORT DOCUMENTATION
AN30: Ground Start Implementation with Silicon Laboratories’ DAAs
AN67: Layout Guidelines
AN72: Ring Detection/Validation with the Si305x DAAs
AN84: Digital Hybrid with the Si305x DAAs
Si3050PPT-EVB Data Sheet
Note: Refer to www.silabs.com for a current list of support documents for this chipset.
Rev. 1.5
125
Si3050 + Si3011/18/19
Revision 1.2 to Revision 1.3
DOCUMENT CHANGE LIST
Revision 1.01 to Revision 1.1
Updated Deep Sleep Total Supply Current from 1.0
to 1.3 mA typical
Added package thermal information in Table 1,
“Recommended Operating Conditions and Thermal
Information,” on page 5.
Updated package pictures
Removed all SPIM references (SPIM bit is never
present in any Si3050 device).
Added Note 10 to the transhybrid balance parameter
in Table 4 on page 8.
Removed SnPb package options
Minor typo corrections
Updated Table 7, “Switching Characteristics—Serial
Peripheral Interface,” on page 11.
Revision 1.1 to Revision 1.31
Removed R54 and R55 from " " on page 18.
The internal System-Side Revision value (REVA[3:0]
in Register 11) has been incremented by one for
Si3050 revision E.
Changed recommended DCV setting for Japan from
01 to 10 in Table 13 on page 22.
Updated initialization procedure in "5.3. Initialization"
on page 25.
Revision 1.31 to Revision 1.4
Added Si3011 device specifications
Removed incorrect description of FDT bit in "5.8.
Exception Handling" on page 27.
Added Si3050, Si3011, Si3018, and Si3019 QFN
information
Updated Billing Tone and Receive Overload section.
Changed to "5.22. Receive Overload Detection" on
page 35.
Revision 1.4 to Revision 1.5
Updated "3. Bill of Materials" on page 19.
Updated "8. Ordering Guide" on page 106.
Updated text and added description of hybrid
coefficient format in "5.28. Transhybrid Balance" on
page 38.
Updated Si3050 part numbers to reflect the latest
product revision level.
Removed references to line-side revisions C and E.
Updated "8. Ordering Guide" on page 106.
Corrected Si3011 bit settings for Register 26 [7:6
and 5:4].
Updated package information for 20-Pin TSSOP and
16-Pin SOIC on pages 103 and 104.
Added “14.Package Outline: 16-Pin TSSOP”.
Revision 1.1 to Revision 1.2
Updated Table 7, “Switching Characteristics—Serial
Peripheral Interface,” on page 11.
Updated delay time between chip selects.
Updated Table 13, “Country-specific Register
Settings,” on page 22.
Corrected ACIM settings for Brazil.
Updated "5.3. Initialization" on page 25.
Revised Step 6 with standard hexadecimal notation.
Updated Figure 27, “Si3011/18/19 Signal Flow
Diagram,” on page 38.
Corrected HPF pole.
Updated "8. Ordering Guide" on page 106.
126
Rev. 1.5
Si3050 + Si3011/18/19
NOTES:
Rev. 1.5
127
Smart.
Connected.
Energy-Friendly
Products
www.silabs.com/products
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
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thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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