SI3211-E-GM [SILICON]
SLIC, CMOS, ROHS COMPLIANT, QFN-38;
| 型号： | SI3211-E-GM |
| 厂家： | 
SILICON |
| 描述： | SLIC, CMOS, ROHS COMPLIANT, QFN-38 模拟传输接口 电池 电信集成电路 电信电路 光电二极管 控制器 |
| 文件： | 总148页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3210/Si3211
PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC
WITH RINGING/BATTERY VOLTAGE GENERATION
Features
100% programmable global solution
Performs all BORSCHT functions
DC-DC controller provides tracking
battery from a 3.3–35V input (Si3210)
Minimizes power in all modes
Dynamic 0 to –94.5 V output
Choice of inductor (low cost) or
transformer (high efficiency)
Programmable line-feed parameters
2-wire AC impedance and hybrid
Constant current feed (20 to 41 mA)
Loop closure and ring trip thresholds
and filtering
Programmable audio processing
DTMF encoding and decoding
12 kHz/16 kHz pulse metering
Phase-continuous FSK (caller ID)
Dual tone generators
-Law/A-Law and linear PCM audio
Extensive test and diagnostic features
Multiple loopback test modes
DC line V/I measurements
Supports GR-909 MLT
Comprehensive design tools
Reference schematic and PCB
layout
ProSLIC API abstracts SLIC
functions, minimizing software
development
Ordering Information
See page 130.
QFN Pin Assignments
Internal balanced ringing up to 90V
PK
5 REN up to 4 kft; 3 REN up to 8 kft
Programmable frequency, amplitude,
cadence, and wave shape
Si3210/11
RoHS-compliant packages
SPI and PCM bus digital interfaces
QFN
Applications
Fixed Wireless (cellular) Terminals
Terminal Adapters
PBX/IP-PBX/Key telephone systems
Voice-over-IP Systems:
DSL/EMTAs/FTTx
WiMax/LTE
38 37 36 35 34 33 32
DTX
FSYNC
RESET
1
2
3
4
31 SDITHRU
30
DCDRV/DCSW
29 DCFF/DOUT
SDCH/DIO1
SDCL/DIO2
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
28
27
26
25
24
23
22
21
20
TEST
GNDD
VDDD
ITIPN
ITIPP
VDDA2
IRINGP
IRINGN
IGMP
5
6
7
Description
8
9
®
The Si3210/11 ProSLIC chipset provides a complete analog telephone interface ideal
for customer premise equipment (CPE). It integrates a subscriber line interface circuit
(SLIC), voice codec, and battery generation (Si3210) or battery selection (Si3211) into
a single CMOS integrated circuit. The battery supply continuously adapts its output
voltage to minimize power dissipation and enables the entire circuit to be powered
from a single 3.3 or 5 V supply (Si3210). The CMOS ProSLIC interfaces to the line
through either the Si3201 Line-feed IC or a discrete line-feed circuit.
10
11
12
13 14 15 16 17 18 19
Si3210/11 features include software-configurable 5 REN internal ringing up to 90 VPK,
DTMF generation and decoding, Caller ID generation, and a comprehensive set of
telephony signaling capabilities for global operation with a single hardware solution.
The Si3210/11 is packaged in a 38-pin QFN or TSSOP, and the Si3201 is packaged in
a thermally-enhanced 16-pin SOIC.
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Functional Block Diagram
INT
RESET
Si3210/11
Line
Status
CS
SCLK
SDO
Control
Interface
DTMF
Decode
SDI
Gain/
Attenuation/
Filter
A/D
TIP
DTX
Line
Feed
Control
Linefeed
Interface
Prog.
Hybrid
Tone
Generators
PCM
Interface
DRX
RING
Gain/
Attenuation/
Filter
D/A
ZS
FSYNC
PCLK
DC-DC Converter Controller
(Si3210 only)
Discrete
Components
PLL
Rev. 1.61 1/12
Copyright © 2012 by Silicon Laboratories
Si3210
Si3210/Si3211
TABLE OF CONTENTS
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.2. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.3. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.5. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.6. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.7. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.8. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.9. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.10. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.11. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.12. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.13. Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
4.1. DTMF Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
4.2. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5. Pin Descriptions: Si3210/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
8. Package Outlines and PCB Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8.1. 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8.2. 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
8.3. 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.1. Ordering Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.2. Marking Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10. Package Marking (Top Mark) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10.1. QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
10.3. SOIC (Si3201) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
2
Rev. 1.61
Si3210/Si3211
1. Electrical Specifications
1
Table 1. Absolute Maximum Ratings and Thermal Information
Parameter
Symbol
Si3210/11
Value
Unit
DC Supply Voltage
V
, V
, V
DDA2
–0.5 to 6.0
±10
V
mA
V
DDD
DDA1
Input Current, Digital Input Pins
Digital Input Voltage
I
IN
V
–0.3 to (V
+ 0.3)
DDD
IND
2
Operating Temperature Range
T
–40 to 100
C
A
Storage Temperature Range
T
–40 to 150
C
STG
TSSOP-38 Thermal Resistance, Typical
QFN-38 Thermal Resistance, Typical
70
35
C/W
C/W
W
JA
JA
2
Continuous Power Dissipation
P
0.7
D
Si3201
DC Supply Voltage
V
–0.5 to 6.0
–104
V
V
DD
Battery Supply Voltage
V
BAT
Input Voltage: TIP, RING, SRINGE, STIPE pins
Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins
V
(V
– 0.3) to (V + 0.3)
V
INHV
BAT
DD
V
–0.3 to (V + 0.3)
V
IN
DD
2
Operating Temperature Range
T
–40 to 100
–40 to 150
55
C
A
Storage Temperature Range
T
C
STG
3
SOIC-16 Thermal Resistance, Typical
C/W
JA
0.8 at 70 °C
0.6 at 85 °C
2
P
W
Continuous Power Dissipation
D
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. Operation above 125 °C junction temperature may degrade device reliability.
3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
Rev. 1.61
3
Si3210/Si3211
Table 2. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min*
Typ
Max*
Unit
°
Ambient Temperature
Ambient Temperature
T
F-grade
G-grade
0
25
25
70
85
C
A
°
T
–40
C
A
V
,V
,
DDD DDA1
V
Si3210/11 Supply Voltage
3.13
3.3/5.0
5.25
V
DDA2
Si3201 Supply Voltage
Si3201 Battery Voltage
V
3.13
–96
3.3/5.0
—
5.25
–10
V
V
DD
V
V
= V
BATH BAT
BAT
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
Product specifications are only guaranteed for the typical application circuit (including component tolerances).
Table 3. AC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
TX/RX Performance
Overload Level
Single Frequency Distortion
THD = 1.5%
2.5
—
—
—
—
V
PK
2-wire – PCM or
PCM – 2-wire:
200 Hz–3.4 kHz
1
–45
dB
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Active off-hook, and OHT,
any ZAC
2
Signal-to-(Noise + Distortion) Ratio
Audio Tone Generator
Figure 1
45
—
—
—
—
0 dBm0, Active off-hook,
and OHT, any Zac
dB
2
Signal-to-Distortion Ratio
Intermodulation Distortion
—
—
0
–45
0.5
0.5
—
dB
dB
dB
2
Gain Accuracy
2-wire to PCM, 1014 Hz
PCM to 2-wire, 1014 Hz
–0.5
–0.5
0
Gain Accuracy over Frequency
Group Delay over Frequency
Figure 3,4
Figure 5,6
—
—
—
1014 Hz sine wave,
reference level –10 dBm
signal level:
3
Gain Tracking
3 to –37 dB
–37 to –50 dB
–50 to –60 dB
at 1000 Hz
–0.25
–0.5
—
—
0.25
0.5
dB
dB
dB
µs
–1.0
—
1.0
Round-Trip Group Delay
Gain Step Accuracy
—
1100
—
—
–6 to +6 dB
–0.017
–0.25
–0.1
0.017
0.25
0.1
dB
dB
dB
Gain Variation with Temperature
Gain Variation with Supply
All gain settings
—
V
= V
= 3.3/5 V ±5%
DDA
—
DDA
4
Rev. 1.61
Si3210/Si3211
Table 3. AC Characteristics (Continued)
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
2-Wire Return Loss
Test Condition
Min
Typ
Max
Unit
200 Hz to 3.4 kHz
300 Hz to 3.4 kHz
30
30
35
—
—
—
dB
dB
Transhybrid Balance
Noise Performance
C-Message Weighted
Psophometric Weighted
3 kHz flat
—
—
—
40
40
40
—
—
—
—
—
—
15
–75
18
—
dBrnC
dBmP
dBrn
dB
4
Idle Channel Noise
PSRR from VDDA
PSRR from VDDD
PSRR from VBAT
RX and TX, DC to 3.4 kHz
RX and TX, DC to 3.4 kHz
RX and TX, DC to 3.4 kHz
Longitudinal Performance
—
dB
—
dB
200 Hz to 3.4 kHz,
Q1,Q2
56
60
—
dB
150, 1% mismatch
Longitudinal to Metallic
or PCM Balance
5
60 to 240
43
53
53
40
60
60
60
—
—
—
—
—
dB
dB
dB
dB
Q1,Q2
5
300 to 800
Q1,Q2
Using Si3201
Metallic to Longitudinal Balance
Longitudinal Impedance
200 Hz to 3.4 kHz
200 Hz to 3.4 kHz at TIP or
RING
Register selectable
ETBO/ETBA
00
01
10
—
—
—
33
17
17
—
—
—
Active off-hook
200 Hz to 3.4 kHz
Register selectable
Longitudinal Current per Pin
ETBO/ETBA
—
—
—
4
8
12
—
—
—
mA
mA
mA
00
01
10
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be
–10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5. Assumes normal distribution of betas.
Rev. 1.61
5
Si3210/Si3211
Figure 1. Transmit and Receive Path SNDR
9
8
7
6
Fundamental
Output Power
(dBm0)
Acceptable
Region
5
4
3
2.6
2
1
0
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
Figure 2. Overload Compression Performance
6
Rev. 1.61
Si3210/Si3211
Typical Response
Typical Response
Figure 3. Transmit Path Frequency Response
Rev. 1.61
7
Si3210/Si3211
Figure 4. Receive Path Frequency Response
8
Rev. 1.61
Si3210/Si3211
Figure 5. Transmit Group Delay Distortion
Figure 6. Receive Group Delay Distortion
Rev. 1.61
9
Si3210/Si3211
Table 4. Linefeed Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for F-Grade, –40 to 85°C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Loop Resistance Range*
DC Loop Current Accuracy
R
See *Note.
0
—
—
160
10
LOOP
I
= 29 mA, ETBA = 4 mA
–10
%
LIM
DC Open Circuit Voltage
Accuracy
Active Mode; V = 48 V,
OC
–4
—
—
160
—
4
—
V
V
– V
TIP
RING
DC Differential Output
Resistance
R
I
< I
LIM
DO
LOOP
DC Open Circuit Voltage—
Ground Start
I
<I ; V
wrt ground
RING
RING LIM
V
R
–4
4
V
OCTO
ROTO
V
= 48 V
OC
DC Output Resistance—
Ground Start
I
<I ; RING to ground
RING LIM
—
160
—
—
DC Output Resistance—
Ground Start
R
TIP to ground
150
–20
–10
—
—
k
%
%
TOTO
Loop Closure/Ring Ground
Detect Threshold Accuracy
I
= 11.43 mA
= 40.64 mA
—
20
10
—
THR
THR
Ring Trip Threshold
Accuracy
I
—
Ring Trip Response Time
User Programmable Register 70
and Indirect Register 36
—
Ring Amplitude
5 REN load; sine wave;
V
R
44
—
—
V
rms
TR
R
= 160 V
= –75 V
LOOP
BAT
Ring DC Offset
Programmable in Indirect
Register 19
0
—
—
V
OS
Trapezoidal Ring Crest
Factor Accuracy
Crest factor = 1.3
f = 20 Hz
–.05
1.35
—
.05
1.45
Sinusoidal Ring Crest
Factor
R
—
CF
Ringing Frequency Accuracy
Ringing Cadence Accuracy
Calibration Time
–1
–50
—
—
—
—
1
%
Accuracy of ON/OFF Times
CAL to CAL Bit
50
ms
ms
600
Power Alarm Threshold
Accuracy
At Power Threshold = 300 mW
–25
—
25
%
*Note: DC resistance round trip; 160 corresponds to 2 kft, 26 gauge AWG.
10
Rev. 1.61
Si3210/Si3211
Table 5. Monitor ADC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Differential Nonlinearity
(6-bit resolution)
DNLE
–1/2
—
1/2
LSB
Integral Nonlinearity
(6-bit resolution)
INLE
–1
—
1
LSB
Gain Error (Voltage)
Gain Error (Current)
—
—
—
—
10
20
%
%
Table 6. Si321x DC Characteristics, VDDA = VDDD = 5.0 V
(VDDA,VDDD = 4.75 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
—
Max
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
0.7 x V
—
—
IH
DDD
V
—
0.3 x V
V
IL
DDD
DIO1,DIO2,SDITHRU:
IO = –4 mA SDO,
DTX:IO = –8 mA
V
V
– 0.6
– 0.8
—
—
—
—
—
V
V
DDD
DDD
V
OH
DOUT: IO = –40 mA
—
DIO1,DIO2,DOUT,SDITHRU:
IO = 4 mA
SDO,INT,DTX:IO = 8 mA
Low Level Output Voltage
Input Leakage Current
V
—
0.4
10
V
OL
I
–10
µA
L
Table 7. Si321x DC Characteristics, VDDA = VDDD = 3.3 V
(VDDA,VDDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
0.7 x V
—
—
—
—
IH
DDD
V
0.3 x V
—
V
IL
DDD
DIO1,DIO2,SDITHRU: IO =–2 mA
SDO, DTX:IO = –4 mA
V
V
– 0.6
– 0.8
—
—
V
V
DDD
DDD
V
OH
DOUT: IO = –40 mA
—
DIO1,DIO2,DOUT,SDITHRU:
IO = 2 mA
SDO,INT,DTX:IO = 4 mA
Low Level Output Voltage
Input Leakage Current
V
—
—
—
0.4
10
V
OL
I
–10
µA
L
Rev. 1.61
11
Si3210/Si3211
Table 8. Power Supply Characteristics
(Unless otherwise noted, VDDA, VDDD=3.13 to 5.25 V; TA=0 to 70C for F-grade, –40 to 85C for G-grade)
1
2
Parameter
Symbol
Test Condition
Max
Unit
Typ
Typ
Sleep (RESET = 0),
VDDA=VDDD=3.13 to 3.465 V
0.1
—
0.3
mA
Sleep (RESET = 0),
VDDA=VDDD=4.75 to 5.25 V,
TA=0 to 70C/F-grade
—
0.1
0.3
mA
Sleep (RESET = 0),
DDA=VDDD=4.75 to 5.25 V,
TA=–40 to 85C/G-grade
V
—
33
37
0.1
42.8
53
0.35
49
mA
mA
mA
Open
Power Supply Current,
Analog and Digital
IA + ID
Active on-hook
ETBO = 4 mA, codec and Gm amplifier
powered down
68
Active OHT
ETBO = 4 mA
57
72
83
mA
mA
mA
Active off-hook
ETBA = 4 mA, ILIM = 20 mA
73
36
88
47
99
55
Ground Start
Ringing sinewave, REN = 1, VPK = 56 V
45
55
65
—
—
—
mA
µA
µA
µA
Sleep mode, RESET = 0
Open (high impedance)
Active on-hook standby
100
100
110
100
100
110
IVDD
VDD Supply Current (Si3201)
Forward/reverse active off-hook, no ILOOP
,
1
1
1
1
—
—
mA
mA
ETBO = 4 mA, VBAT = –24 V
Forward/reverse OHT, ETBO = 4 mA,
VBAT = –70 V
Sleep (RESET = 0)
Open (DCOF = 1)
0
0
0
0
—
—
mA
mA
Active on-hook
VOC = 48 V, ETBO = 4 mA
3
3
—
—
mA
mA
Active OHT
ETBO = 4 mA
VBAT Supply Current3
IBAT
11
11
Active off-hook
ETBA = 4 mA, ILIM = 20 mA
30
2
30
2
—
—
mA
mA
Ground Start
Ringing: VPK_RING = 56 VPK
,
Sinewave ringing: REN = 1
5.5
—
5.5
—
—
mA
When using Si3201
10
V/µs
VBAT Supply Slew Rate
12
Rev. 1.61
Si3210/Si3211
Table 8. Power Supply Characteristics (Continued)
(Unless otherwise noted, VDDA, VDDD=3.13 to 5.25 V; TA=0 to 70C for F-grade, –40 to 85C for G-grade)
1
2
Parameter
Symbol
Test Condition
Max
Unit
Typ
Typ
Notes:
1. VDDD, VDDA = 3.3 V.
2. VDDD, VDDA = 5.25 V.
3. IBAT = current from VBAT (the large negative supply). For a switched-mode power supply regulator efficiency of 71%,
the user can calculate the regulator current consumption as IBAT x VBAT/(0.71 x VDC).
Table 9. Switching Characteristics (General Inputs)1
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)
Parameter
Symbol
Min
—
Typ
—
Max
20
Unit
ns
Rise Time, RESET
t
r
2
RESET Pulse Width
t
100
—
—
ns
rl
Notes:
1. All timing (except rise and fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and fall times are referenced to the 20% and 80% levels of the waveform.
2. Additional initialization guidelines apply; see section 1.2 ProSLIC Initialization in AN35.
Table 10. Switching Characteristics (SPI)
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF
Parameter
Symbol
Test
Min
Typ
Max
Unit
Conditions
Cycle Time SCLK
t
0.062
—
—
—
—
—
—
—
25
25
20
20
µs
ns
ns
ns
ns
c
Rise Time, SCLK
t
r
Fall Time, SCLK
t
—
f
Delay Time, SCLK Fall to SDO Active
t
—
d1
d2
Delay Time, SCLK Fall to SDO
Transition
t
t
—
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
Hold Time, CS to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
—
25
—
—
—
—
—
—
20
—
—
—
—
—
ns
ns
ns
ns
ns
ns
d3
t
su1
t
20
h1
t
25
su2
t
20
h2
Delay Time between Chip Selects
(Continuous SCLK)
t
440
cs
Delay Time between Chip Selects
(Non-continuous SCLK)
t
220
—
—
ns
cs
Rev. 1.61
13
Si3210/Si3211
Table 10. Switching Characteristics (SPI)
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF
SDI to SDITHRU Propagation Delay
t
—
4
10
ns
d4
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V
tthru
tr
tr
tc
SCLK
CS
tsu1
th1
tcs
tsu2
th2
SDI
td1
td3
td2
SDO
Figure 7. SPI Timing Diagram
Table 11. Switching Characteristics—PCM Highway Serial Interface
VD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF
1
1
1
Parameter
Symbol
Test
Conditions
Units
Min
Typ
Max
—
—
—
—
—
—
—
—
0.256
0.512
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2
0.768
1.024
PCLK Frequency
1/t
c
2
1.536
2.048
4.096
8.192
PCLK Duty Cycle Tolerance
PCLK-to-FSYNC Jitter Tolerance
Rise Time, PCLK
t
40
–120
—
50
—
—
—
—
60
120
25
%
ns
ns
ns
ns
dty
t
jitter
t
r
Fall Time, PCLK
t
—
25
f
Delay Time, PCLK Rise to DTX Active
t
t
t
—
20
d1
d2
d3
Delay Time, PCLK Rise to DTX
Transition
—
—
20
ns
3
Delay Time, PCLK Rise to DTX Tri-state
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
—
25
20
—
—
—
20
—
—
ns
ns
ns
t
su1
t
h1
14
Rev. 1.61
Si3210/Si3211
Table 11. Switching Characteristics—PCM Highway Serial Interface
VD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
Notes:
t
25
20
—
—
—
—
ns
ns
su2
t
h2
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4V, VIL = 0.4 V.
2. Not a valid PCLK frequency for GCI mode.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
tr
tf
tc
PCLK
th1
tsu1
FSYNC
tsu2
th2
DRX
DTX
td2
td1
td3
Figure 8. PCM Highway Interface Timing Diagram
Rev. 1.61
15
Si3210/Si3211
VCC
L2
47 µH
C31
10 µF
C30
10 µF
C16
C15
0.1 µF
C17
0.1 µF 0.1 µF
R1
200k
15
20
38
STIPDC
SCLK
37
C24
0.1 F
SDI
STIPAC
C3
220 nF
SPI Bus
PCM
VCC
R8
470
36
SDO
1
CS
6
C18
4.7 F
C19
4.7 F
FSYNC
3
PCLK
4
15
29
ITIPN
IRINGN
ITIPP
ITIPN
Bus
VCC
DRX
13
16
14
11
10
25
28
26
17
19
5
IRINGN
ITIPP
DTX
1
3
TIP
R322
10k
TIP
C5
22nF
Protection
Circuit
C6
IRINGP
STIPE
IRINGP
STIPE
2
R2
196k
INT
Note 2
7
RESET
22nF
R4
196k
R262
10 k
RING
RING
SRINGE
SRINGE
24
IGMP
R15
243
R7
4.02k
R6
22
IGMN
4.02k
18
SVBAT
11
R5
200k
IREF
12
CAPP
C4
220 nF
R9
C26
0.1 F
R14
40.2k
470
C2
10 F
C1
10 F
14
CAPM
21
16
SRINGAC
SRINGDC
Notes:
13
QGND
R3
1. Values and configurations for these components can
be derived from Table 19 or from “AN45: Design
Guide for the SI3210 DC-DC Converter”.
200k
GND
2. Only one component per system needed.
3. All circuit ground should have a single-point
Q9
2N2222
R21
15
VCC
R291
R281
connection to the ground plane.
4. Si3201 bottom-side exposed pad should be
electrically and thermally connected to bulk ground
plane.
VDC
Note 1
VBAT DC-DC Converter
VDC
Circuit
5. Pin numbers for TSSOP shown.
Figure 9. Si3210/Si3210M Application Circuit Using Si3201
16
Rev. 1.61
Si3210/Si3211
Table 12. Si3210/Si3210M + Si3201 External Component Values
Component(s)
Value
Package
Supplier
10 µF, 6 V Ceramic or 16 V Low Leakage
Electrolytic, ±20%
C1,C2
Radial
Murata, Nichicon URL1C100MD
C3,C4
C5,C6
220 nF, 100 V, X7R, ±20%
22 nF, 100 V, X7R, ±20%
0.1 µF, 6 V, Y5V, ±20%
4.7 µF, ceramic, 6 V, X7R, ±20%
0.1 µF, 100 V, X7R, ±20%
10 µF, 10 V, Electrolytic, ±20%
47 µH, 150 mA
1812
1206
603
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Panasonic
C15,C16,C17,C24
C18,C19
C26
1206
1210
Radial
SMD
805
C30,C31
L2
Coilcraft
1
1
1
R1 ,R3 ,R5
200 k, 1/10 W, ±1%
196 k, 1/10 W, ±1%
4.02 k, 1/10 W, ±1%
470 , 1/10 W, ±1%
1
1
R2 ,R4
805
R6,R7
R8,R9
R14
805
805
40.2 k, 1/10 W, ±1%
243 , 1/10 W, ±1%
805
R15
805
R21
15 , 1/4 W, ±5%
805
2
R26
10 k, 1/10 W, ±1%
805
1/10 W, 1% (See “AN45: Design Guide for
the Si3210 DC-DC Converter” or Table 19
for value selection)
R28,R29
805
805
2
R32
10 k, 1/10 W, ±5%
ON Semi MMBT2222ALT1; Central
Semi CMPT2222A; Zetex
FMMT2222
Q9
60 V, General Purpose Switching NPN
SOT-23
Notes:
1. These resistors must be in an 0805 or larger package.
2. Only one component per system needed.
Rev. 1.61
17
Si3210/Si3211
VDC
F1
SDCH
SDCL
R191
C142
0.1 µF
C252
10 µF
R181
Note 1
R201
C10
0.1 µF
R16
200
Q7
FZT953
DCFF
Q8
2N2222
D1
ES1D
VBAT
C9
10 µF
R17
L1
DCDRV
Note 1
GND
Notes:
1. Values and configurations for these components can be derived from
“AN45: Design Guide for the Si3210 DC-DC Converter” or Table 21.
2. Voltage rating for C14 and C25 must be greater than VDC.
Figure 10. Si3210 BJT/Inductor DC-DC Converter Circuit
18
Rev. 1.61
Si3210/Si3211
Table 13. Si3210 BJT/Inductor DC-DC Converter Component Values
Component(s)
C9
Value
Package
Radial
1210
Supplier
Panasonic
10 µF, 100 V, Electrolytic, ±20%
0.1 µF, 50 V, X7R, ±20%
0.1 µF, X7R, ±20%
C10
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Panasonic
C14*
1210
C25*
10 µF, Electrolytic, ±20%
200 , 1/10 W, ±5%
Radial
805
R16
1/10 W, ±5% (See AN45 or Table 21 for
value selection)
R17
R18
805
1/4 W, ±5% (See AN45 or Table 21 for
value selection)
1206
1/10 W, ±1% (See AN45 or Table 21 for
value selection)
R19,R20
F1
805
Fuse
SMD
Belfuse SSQ Series
DO214-
AA
General Semi ES1D; Central Semi
CMR1U-02
D1
Ultra Fast Recovery 200 V, 1A Rectifier
API Delevan SPD127 series, Sumida
CDRH127 series, Datatronics DR340-
1 series, Coilcraft DS5022, TDK
SLF12565
1 A, Shielded Inductor
(See AN45 or Table 21 for value selection)
L1
SMD
Zetex FZT953, FZT955, ZTX953,
ZTX955; Sanyo 2SA1552
Q7
Q8
120 V, High Current Switching PNP
60 V, General Purpose Switching NPN
SOT-223
SOT-23
ON Semi MMBT2222ALT1,
MPS2222A; Central Semi
CMPT2222A; Zetex FMMT2222
*Note: Voltage rating of this device must be greater than VDC
.
Rev. 1.61
19
Si3210/Si3211
VDC
F1
SDCH
SDCL
R191
C252
C142
Note 1 R181
10 µF
0.1 µF
R201
1
R22
22
2
3
C27
470 pF
D1
VBAT
ES1D
6
DCFF
4
10
M1
C9
10 µF
T11
IRLL014N
Note 1
R17
200 k
DCDRV
NC
GND
Notes:
1. Values and configurations for these components can be derived from AN45
or Table 20.
2. Voltage rating for C14 and C25 must be greater than VDC.
Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit
20
Rev. 1.61
Si3210/Si3211
Table 14. Si3210M MOSFET/Transformer DC-DC Converter Component Values
Component(s)
Value
Package
Radial
1210
Supplier
Panasonic
C9
10 µF, 100 V, Electrolytic, ±20%
0.1 µF, X7R, ±20%
C14*
C25*
C27
R17
Murata, Johanson, Novacap, Venkel
Panasonic
10 µF, Electrolytic, ±20%
470 pF, 100 V, X7R, ±20%
200 k, 1/10 W, ±5%
Radial
1206
Murata, Johanson, Novacap, Venkel
805
1/4 W, ±5% (See “AN45: Design Guide for
the Si3210 DC-DC Converter” or Table 20
for value selection)
R18
1206
805
1/10 W, ±1% (See AN45 or Table 20
for value selection)
R19,R20
R22
F1
22 , 1/10 W, ±5%
805
Fuse
SMD
Belfuse SSQ Series
General Semi ES1D; Central Semi
CMR1U-02
D1
T1
Ultra Fast Recovery 200 V, 1 A Rectifier D214-AA
Coiltronic CTX01-15275;
Datatronics SM76315;
Midcom 31353R-02
Power Transformer
SMD
Intl Rect. IRLL014N; Intersil
HUF76609D3S; ST Micro
STD5NE10L, STN2NE10L
M1
100 V, Logic Level Input MOSFET
SOT-223
*Note: Voltage rating of this device must be greater than VDC
.
Rev. 1.61
21
Si3210/Si3211
VCC
L2
47 µH
C31
10 µF
C30
10 µF
C16
C15
0.1 µF
C17
0.1 µF 0.1 µF
R1
200k
15
20
38
STIPDC
SCLK
37
SDI
STIPAC
C24
0.1 F
SPI Bus
VCC
C3
220 nF
R8
470
36
SDO
1
CS
C18
4.7 F
C19
4.7 F
6
FSYNC
3
15
29
25
ITIPN
PCLK
ITIPN
PCM
Bus
4
DRX
13
IRINGN
IRINGN
5
VCC
DTX
1
3
16
14
28
26
ITIPP
ITIPP
TIP
R321
10k
TIP
C5
22 nF
IRINGP
IRINGP
Protection
2
INT
Circuit
C6
R2
196k
Note 1
7
17
19
RESET
11
10
22 nF
STIPE
STIPE
R4
196k
R261
10k
RING
RING
24
SRINGE
SRINGE
IGMP
R15
243
R7
4.02k
R6
22
IGMN
4.02k
18
SVBAT
11
IREF
R5
200k
12
CAPP
C9
C2
10 F
C1
10 F
R14
40.2k
14
CAPM
R9
470
C4
220 nF
0.1 µF
21
16
GND
SRINGAC
SRINGDC
13
QGND
R3
200k
NC NC
NC
Notes:
GND
1. Only one component per system needed.
2. All circuit grounds should have a single-
point connection to the ground plane.
Q8
5551
D1
4003
3. Si3201 bottom-side exposed pad should
be electrically and thermally connected to
bulk ground plane.
Q7
5401
R16
200k
R18
1.8k
4. Pin numbers for TSSOP shown.
VBATL
VBATH
Figure 12. Si3211 Typical Application Circuit Using Si3201
22
Rev. 1.61
Si3210/Si3211
Table 15. Si3211 + Si3201 External Component Values
Component(s)
Value
Package
Supplier
C1,C2
10 µF, 6 V Ceramic or 16 V, Low-Leakage
Electrolytic, ±20%
Radial
Murata, Nichicon URL1C100MD
C3,C4
220 nF, 100 V, X7R, ±20%
22 nF, 100 V, X7R, ±20%
0.1 µF, 100 V, X7R, ±20%
0.1 µF, 6 V, Y5V, ±20%
4.7 µF Ceramic, 6 V, X7R, ±20%
10 µF, 10 V, Electrolytic, ±20%
47 µH, 150 mA
1812
1206
1210
1206
1206
Radial
SMD
MELF
SOT-89
SOT-223
805
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Panasonic
C5,C6
C9
C15,C16,C17,C24
C18,C19
C30,C31
L2
Coilcraft
D1
200 V, 1 A Rectifier
ON Semi: MRA4003, IN4003
ON Semi: 2N5401
Q7
120 V, PNP, BJT
Q8
120 V, NPN, BJT
ON Semi: 2N5551
1
1
1
1
R1 ,R3 ,R5 ,R16
200 k, 1/10 W, ±1%
196 k, 1/10 W, ±1%
4.02 k, 1/10 W, ±1%
470 , 1/10 W, ±1%
1
1
R2 ,R4
805
R6,R7
R8,R9
R14
805
805
40.2 k, 1/10 W, ±1%
243 , 1/10 W, ±1%
805
R15
805
R18
1.8 k, 1/10 W, ±5%
10 k, 1/10 W, ±1%
805
2
R26
805
2
R32
10 k, 1/10 W, ±5%
805
Notes:
1. These resistors must be in an 0805 or larger package.
2. Only one component per system needed.
Rev. 1.61
23
Si3210/Si3211
VCC
L2
47 µH
C31
10 µF
C30
10 µF
C16
C15
0.1 µF
C17
0.1 µF 0.1 µF
R1
200k
38
SCLK
15
20
37
GND
STIPDC
STIPAC
SDI
SPI Bus
36
SDO
1
R8
470
C3
220nF
CS
6
FSYNC
Q4
5401
Q1
5401
28 ITIPP
29 ITIPN
17 STIPE
3
PCLK
4
R10
10
PCM Bus
DRX
C324
Q6
5551
TIP
5
0.1 µF
VCC
DTX
C8
220nF
R102 (100k)
R13
5.1k
C5
R2
2
22nF
R32
Protection
Circuit
100k
10k
R6
80.6
C6
22nF
26
2
IRINGP
INT
Note 2
7
Q2
5401
Q3
5401
25
RESET
RING
IRINGN
C344
R11
10
R4
100k
R262
10k
0.1 µF
19
24
Q5
5551
R104 (100k)
SRINGE
SVBAT
IGMP
R15
243
C7
220nF
22
R12
5.1k
IGMN
C26
0.1 µF
C334
0.1 µF
R5
100k
18
R105 (100k)
11
IREF
R7
80.6
12
C4
220nF
CAPP
R9
470
C2
10uF
C1
10uF
R14
14
CAPM
21
16
Notes:
40.2k
SRINGAC
SRINGDC
1. Values and configurations for these compo-
nents can be derived from Table 19 or from
“AN45: Design Guide for the Si3210 DC-DC
Converter”.
13
QGND
R3
200k
GND
2. Only one component per system needed.
3. All circuit grounds should have a single-point
connection to the ground plane.
4. Optional components to improve idle channel
noise.
5. The trace resistance between R6 and C26
should equal the trace resistance between R7
and C26.
R21
15
Q9
2N2222
VCC
VDC
1
1
R29
R28
Note 1
DC-DC Converter
Circuit
VBAT
VDC
6. Pin numbers for TSSOP shown.
Figure 13. Si3210/Si3210M Typical Application Circuit Using Discrete Components
24
Rev. 1.61
Si3210/Si3211
Table 16. Si3210/Si3210M External Component Values—Discrete Solution
Component(s)
Value
Package
Supplier/Part Number
10 µF, 6 V Ceramic or 16 V Low-Leakage
Murata, Panasonic, Nichicon
URL1C100MD
C1,C2
Radial
Electrolytic, 20%
C3,C4
C5,C6
220 nF, 100 V, X7R, 20%
22 nF, 100 V, X7R, 20%
220 nF, 50 V, X7R, 20%
0.1 µF, 6 V, Y5V, 20%
0.1 µF, 100 V, X7R, 20%
10 µF, 10 V, Electrolytic, ±20%
0.1 µF, 50 V, ±20%
1812
1206
1812
603
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Panasonic
C7,C8
C15,C16,C17
C26
1210
Radial
805
C30,C31
C32,C33,C34
L2
Venkel
47 µH, 150 mA
SMD
Coilcraft
Central Semi CMPT5401; ON Semi
MMBT5401LT1, 2N5401; Zetex
FMMT5401;
Q1,Q2,Q3,Q4
120 V, PNP, BJT
120 V, NPN, BJT
SOT-23
Fairchild 2N5401; Samsung 2N5401
Central Semi CZT5551, ON Semi
2N5551;
Fairchild 2N5551; Phillips 2N5551
Q5,Q6
Q9
SOT-223
ON Semi MMBT2222ALT1, MPS2222A;
Central Semi CMPT2222A; Zetex
FMMT2222
NPN General Purpose BJT
200 k, 1/10 W, 1%
100 k, 1/10 W, ±1%
SOT-23
805
1
1
R1 , R3
1
1
1
R2 , R4 , R5 ,
1
1
R102 , R104 ,
805
1
R105
R6,R7
R8,R9
R10,R11
R12,R13
R14
80.6 , 1/4 W, 1%
470 , 1/10 W, 1%
10 , 1/10 W, 5%
5.1 k, 1/10 W, 5%
40.2 k, 1/10 W, 1%
243 , 1/10 W, 1%
15 , 1/4 W, 1%
1210
805
805
805
805
805
805
805
R15
R21
2
R26
10 k, 1/10 W, ±1%
1/10 W, 1% (See “AN45: Design Guide
for the Si3210/15/16 DC-DC Converter” or
Table 19 for value selection)
R28,R29
805
805
2
R32
10 k, 1/10 W, 5%
Notes:
1. These resistors must be in 0805 or larger package.
2. Only one component per system needed.
Rev. 1.61
25
Si3210/Si3211
VCC
L2
47 µH
C31
10 µF
C30
10 µF
C16
C15
0.1 µF
C17
0.1 µF 0.1 µF
R1
200k
38
15
20
GND
STIPDC
SCLK
37
SDI
STIPAC
SPI Bus
36
R8
470
SDO
C3
1
220nF
CS
6
Q4
5401
28
29
17
Q1
5401
ITIPP
ITIPN
STIPE
FSYNC
3
R10
10
PCLK
C324
0.1µF
PCM Bus
4
Q6
5551
TIP
DRX
C8
220nF
5
R13
5.1k
R102 (100k)
VCC
C5
DTX
R2
22nF
Protection
Circuit
100k
1
R32
R6
80.6
10k
C6
22nF
26
25
19
IRINGP
IRINGN
2
INT
7
Q2
5401
Q3
5401
Note 1
RING
C344
0.1µF
R11
10
R4
100k
RESET
1
SRINGE
Q5
R26
10k
R104 (100k)
24
5551
IGMP
C7
220nF
R15
243
R12
5.1k
C26
0.1 µF
C334
0.1µF
R5
100k
22
IGMN
18
SVBAT
R105 (100k)
R7
80.6
11
IREF
C4
220nF
R9
470
12
CAPP
21
16
SRINGAC
SRINGDC
C2
10uF
14
C1
10uF
R14
40.2k
CAPM
R3
200k
Notes:
13
QGND
1. Only one component per system needed.
2. All circuit grounds should have a single-point
connection to the ground plane.
3. The trace resistance between R6 and C26
should equal the trace resistance between
R7 and C26.
GND
Q8
5551
D1
4003
NC NC
NC
Q7
5401
R16
200k
R18
1.8k
4. Optional components to improve idle channel
noise.
5. Pin numbers for TSSOP shown.
VBATL
VBATH
Figure 14. Si3211 Typical Application Circuit Using Discrete Solution
26
Rev. 1.61
Si3210/Si3211
Table 17. Si3211 External Component Values—Discrete Solution
Component(s)
Value
Package
Supplier/Part Number
10 µF, 6 V Ceramic or 16 V Low Leakage
Murata, Panasonic, Nichicon
URL1C100MD
C1,C2
Radial
Electrolytic, 20%
C3,C4
C5,C6
220 nF, 100 V, X7R, 20%
22 nF, 100 V, X7R, 20%
220 nF, 50 V, X7R, 20%
0.1 µF, 100 V, X7R, 20%
0.1 µF, 6 V, Y5V, 20%
10 µF, 10 V, X7R, ±20%
0.1 µF, 50 V, X7R, ±20%
47 µH, 150 mA
1812
1206
1812
1210
603
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Murata, Johanson, Novacap, Venkel
Panasonic
C7,C8
C9
C15,C16,C17
C30,C31
C32, C33, C34
L2
Murata, Johanson, Novacap, Venkel
Panasonic
Radial
805
Venkel
SMD
805
Coilcraft
1
1
1
R1 ,R3 ,R16
200 k, 1/10 W, 1%
1
1
1
R2 , R4 , R5 ,
1
1
R102 , R104 ,
100 k, 1/10 W, ±1%
805
1
R105
R6,R7
R8,R9
R10,R11
R12,R13
R14
80.6 , 1/4 W, 1%
470 , 1/10 W, 1%
10 , 1/10 W, 5%
5.1 k, 1/10 W, 5%
40.2 k, 1/10 W, 1%
243 , 1/10 W, 1%
1.8 k, 1/10 W, 5%
10 k, 1/10 W, ±1%
10 k, 1/10 W, 5%
200 V 1A Rectifier
1210
805
805
805
805
R15
805
R18
805
2
R26
805
2
R32
805
D1
MELF
ON Semi MRA4003, 1N4003
Central Semi CMPT5401; ON Semi
MMBT5401LT1, 2N5401; Zetex
FMMT5401
Q1,Q2,Q3,Q4,Q7
120 V, PNP, BJT
SOT-23
Central Semi CZT5551, ON Semi
2N5551
Q5,Q6
120 V, NPN, BJT
120 V, NPN, BJT
SOT-223
SOT-223
Central Semi CMPT5551, ON Semi
2N5551
Q8
Notes:
1. These resistors must be in an 0805 or larger package.
2. Only one component per system needed.
Rev. 1.61
27
Si3210/Si3211
QRDN
5401
QTDN
5401
Q3
Q4
R23
R24
RRBN0
3.0k
RTBN0
3.0k
QRP
QTN
5551
Q5
Q6
C8
5551
C7
CRBN
100 nF
CTBN
100 nF
R7
RRE
80.6
R12
RRBN
5.1k
R6
RTE
80.6
R13
RTBN
5.1k
Figure 15. Si321x Optional Equivalent Q5, Q6 Bias Circuit
Table 18. Si321x Optional Bias Component Values
Component
C7,C8
Value
Package
1210
Supplier/Part Number
100 nF, 100 V, X7R, 20%
3.0 k, 1/10 W, 5%
Murata, Johanson, Venkel
R23,R24
805
The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5 and Q6.
For this optional subcircuit, C7 and C8 differ in voltage and capacitance from the standard circuit. R23 and R24 are
additional components.
Table 19. Component Value Selection for Si3210/Si3210M
Component
Value
Package
Comments
1/10 W, 1% resistor
R28 = (V + V )/148 µA
DD
BE
R28
For V = 3.3 V: 26.1 k
805
DD
where V is the nominal VBE for Q9
BE
For V = 5.0 V: 37.4 k
DD
1/10 W, 1% resistor
R29 = V
/148 µA
CLAMP
For V
For V
For V
= 80 V: 541 k
= 85 V: 574 k
= 100 V: 676 k
CLAMP
CLAMP
R29
805
where V
is the clamping voltage
CLAMP
for V
BAT
CLAMP
28
Rev. 1.61
Si3210/Si3211
1
Table 20. Component Value Selection Examples for Si3210M MOSFET/Transformer DC-DC Converter
VDC
Maximum Ringing Load/
Loop Resistance
Winding
Transformer Ratio
R18
R19, R20
2
Connections
3.3 V
5.0 V
12 V
3 REN/117
5 REN/117
5 REN/117
5 REN/117
1–2
1–2
1–3
1–4
1–2
1–2
1–3
1–4
0.06
0.10
0.6
7.15 k
16.5 k
56.2 k
121 k
24 V
2.1
Notes:
1. There are other system and software conditions that influence component value selection.
Refer to “AN45: Design Guide for the Si3210 DC-DC Converter” for detailed guidance.
2. Applies to transformer specified in Table 14; other transformers may vary.
Table 21. Component Value Selection Examples for Si3210 BJT/Inductor DC-DC Converter
VDC
5 V
Maximum Ringing Load/Loop Resistance
3 REN/117
L1
R17
R18
R19, R20
16.5 k
56.2 k
121 k
67 µH
150 µH
220 µH
150
162
175
0.15
0.56
2.0
12 V
24 V
5 REN/117
5 REN/117
Note: There are other system and software conditions that influence component value selection.
Refer to “AN45: Design Guide for the Si3210 DC-DC Converter” for detailed guidance.
Rev. 1.61
29
Si3210/Si3211
2.1.1. DC Feed Characteristics
2. Functional Description
The ProSLIC has programmable constant voltage and
constant current zones as shown in Figure 16. Open-
®
The ProSLIC is a single, low-voltage CMOS device
that provides all the SLIC, codec, DTMF detection, and
signal generation functions needed for a complete
analog telephone interface. The ProSLIC performs all
battery, overvoltage, ringing, supervision, codec, hybrid,
and test (BORSCHT) functions. Unlike most monolithic
SLICs, the Si3210 does not require externally-supplied
high-voltage battery supplies. Instead, it generates all
necessary battery voltages from a positive dc supply
using its own dc-dc converter controller. Two fully-
programmable tone generators can produce DTMF
tones, phase continuous FSK (caller ID) signaling, and
call progress tones. DTMF decoding and pulse metering
signal generation are also integrated. The Si3201
linefeed interface IC performs all high-voltage functions.
As an option, the Si3201 can also be replaced with low-
cost discrete components as shown in the typical
application circuits in Figures 12, 13, and 14.
circuit TIP-to-RING voltage (V ) defines the constant
voltage zone and is programmable from 0 V to 94.5 V in
OC
1.5 V steps. The loop current limit (I ) defines the
LIM
constant current zone and is programmable from 20 mA
to 41 mA in 3 mA steps. The ProSLIC has an inherent
dc output resistance (R ) of 160 .
O
V(TIP-RING) (V)
Constant
Voltage
Zone
VOC
RO=160
Constant Current
Zone
The ProSLIC is ideal for short loop applications, such as
terminal adapters, cable telephony, PBX/key systems,
wireless local loop (WLL), and voice over IP solutions.
ILIM
ILOOP(mA)
Figure 16. Simplified DC Current/Voltage
Linefeed Characteristic
The linefeed provides programmable on-hook voltage,
programmable off-hook loop current, reverse battery
operation, loop or ground start operation, and on-hook
transmission ringing voltage. Loop current and voltage
are continuously monitored using an integrated A/D
converter. Balanced 5 REN ringing with or without a
programmable dc offset is integrated. The available
offset, frequency, waveshape, and cadence options are
designed to ring the widest variety of terminal devices
and to reduce external controller requirements.
The TIP-to-RING voltage (V ) is offset from ground by
OC
a programmable voltage (V ) to provide voltage
CM
headroom to the positive-most terminal (TIP in forward
polarity states and RING in reverse polarity states) for
carrying audio signals. Table 22 summarizes the
parameters to be initialized before entering an active
state.
Table 22. Programmable Ranges of DC
Linefeed Characteristics
A complete audio transmit and receive path is
integrated, including DTMF decoding, ac impedance,
and hybrid gain. These features are software-
programmable, allowing for a single hardware design to
meet international requirements. Digital voice data
transfer occurs over a standard PCM bus. Control data
is transferred using a standard SPI. The device is
available in a 38-pin QFN or TSSOP package.
Parameter Programmable Default Register
Location*
Range
Value
Bits
ILIM
VOC
VCM
20 to 41 mA
20 mA
ILIM[2:0]
Direct
Register 71
0 to 94.5 V
0 to 94.5 V
48 V
3 V
VOC[5:0]
VCM[5:0]
Direct
Register 72
2.1. Linefeed Interface
The ProSLIC’s linefeed interface offers a rich set of
features and programmable flexibility to meet the
broadest applications requirements. The dc linefeed
characteristics are software-programmable. Key
current, voltage, and power measurements are acquired
in real time and provided in software registers.
Direct
Register 73
*Note: The ProSLIC uses registers that are both directly and
indirectly mapped. A “direct” register is one that is mapped
directly.
30
Rev. 1.61
Si3210/Si3211
2.1.2. Linefeed Architecture
See “2.1.5. Power Monitoring and Line Fault Detection”
for more details.
The ProSLIC is a low-voltage CMOS device that uses
either an Si3201 linefeed interface IC or low-cost In the forward active and reverse active states, linefeed
external components to control the high voltages circuitry is on, and the audio signal paths are powered
required for subscriber line interfaces. Figure 17 is a down.
simplified illustration of the linefeed control loop circuit
for TIP or RING and the external components used.
audio signal paths are powered up to provide data
In the forward and reverse on-hook transmission states,
The ProSLIC uses both voltage and current sensing to transmission during an on-hook loop condition.
control TIP and RING. DC and ac line voltages on TIP
The TIP Open state turns off all control currents to the
external bipolar devices connected to TIP and provides
an active linefeed on RING for ground start operation.
and RING are measured through sense resistors R
DC
and R . The ProSLIC uses linefeed transistors Q and
AC
P
Q to drive TIP and RING. Q isolates the high-voltage
N
DN
The RING Open state provides similar operation with
the RING drivers off and TIP active.
base of Q from the ProSLIC.
N
The ProSLIC measures voltage at various nodes in
The ringing state drives programmable ringing
waveforms onto the line.
order to monitor the linefeed current. R , R , and
DC
SE
R
provide access to these measuring points. The
BAT
2.1.4. Loop Voltage and Current Monitoring
sense circuitry is calibrated on-chip to guarantee
measurement accuracy with standard external The ProSLIC continuously monitors the TIP and RING
component
Calibration" on page 36 for details.
tolerances.
See
"2.1.9.
Linefeed voltages and external BJT currents. These values are
available in registers 78–89. Table 24 on page 33 lists
the values that are measured and their associated
registers. An internal A/D converter samples the
2.1.3. Linefeed Operation States
The ProSLIC linefeed has eight states of operation as
shown in Table 23. The state of operation is controlled
using the Linefeed Control register (direct Register 64).
measured voltages and currents from the analog sense
circuitry and translates them into the digital domain. The
A/D updates the samples at a rate of 800 Hz. Two
derived values are also reported: loop voltage and loop
The open state turns off all currents into the external
bipolar transistors and can be used in the presence of
fault conditions on the line and to generate Open Switch
Intervals (OSIs). TIP and RING are effectively tri-stated
with a dc output impedance of about 150 k.
current. The loop voltage, V – V
, is reported as a
TIP
RING
1-bit sign, 6-bit magnitude format. For ground start
operation, the reported value is the RING voltage. The
loop current, (I – I + I –I )/2, is reported in a 1-
Q1
Q2
Q5 Q6
The ProSLIC can also automatically enter the open bit sign, 6-bit magnitude format. In RING open and TIP
state if it detects excessive power being consumed in open states, the loop current is reported as (I – I ) +
Q1
Q2
the external bipolar transistors.
(I –I ).
Q5 Q6
Rev. 1.61
31
Si3210/Si3211
Audio
Codec
Monitor A/D
A/D
A/D
D/A
DSP
D/A
SLIC DAC
Battery Sense
Emitter Sense
AC
Control
DC
Control
AC Sense
DC Sense
RAC
CAC
Si3201
RBP
AC
Control
Loop
QDN
DC
Control
Loop
QP
RDC
RSE
RBAT
TIP or
RING
QN
RE
VBAT
Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown)
Table 23. ProSLIC Linefeed Operations
LF[2:0]*
000
Linefeed State
Open
Description
TIP and RING tri-stated
001
Forward Active
V
V
> V
> V
TIP
TIP
RING
RING
010
Forward On-Hook Transmission
TIP Open
; audio signal paths powered on
011
TIP tri-stated, RING active; used for ground start
Ringing waveform applied to TIP and RING
100
Ringing
101
Reverse Active
V
V
> V
TIP
RING
RING
110
Reverse On-Hook Transmission
Ring Open
> V ; audio signal paths powered on
TIP
111
RING tri-stated, TIP active
Note: The linefeed register (LF) is located in direct Register 64.
32
Rev. 1.61
Si3210/Si3211
Table 24. Measured Real-Time Linefeed Interface Characteristics
Parameter
Measurement
Range
Resolution
Register
Bits
Location*
Loop Voltage Sense (V
– V
)
RING
–94.5 to +94.5 V
1.5 V
LVSP,
LVS[6:0]
Direct Register 78
Direct Register 79
TIP
Loop Current Sense
–78.75 to +78.5 mA
1.25 mA
LCSP,
LCS[5:0]
TIP Voltage Sense
RING Voltage Sense
0 to –95.88 V
0 to –95.88 V
0 to –95.88 V
0 to –95.88 V
0 to 81.35 mA
0 to 81.35 mA
0 to 9.59 mA
0 to 9.59 mA
0 to 80.58 mA
0 to 80.58 mA
0.376 V
0.376 V
VTIP[7:0]
Direct Register 80
Direct Register 81
VRING[7:0]
Battery Voltage Sense 1 (V
Battery Voltage Sense 2 (V
)
)
0.376 V
VBATS1[7:0] Direct Register 82
VBATS2[7:0] Direct Register 83
BAT
BAT
0.376 V
Transistor 1 Current Sense
Transistor 2 Current Sense
Transistor 3 Current Sense
Transistor 4 Current Sense
Transistor 5 Current Sense
Transistor 6 Current Sense
0.319 mA
0.319 mA
37.6 µA
IQ1[7:0]
IQ2[7:0]
IQ3[7:0]
IQ4[7:0]
IQ5[7:0]
IQ6[7:0]
Direct Register 84
Direct Register 85
Direct Register 86
Direct Register 87
Direct Register 88
Direct Register 89
37.6 µA
0.316 mA
0.316 mA
*Note: The ProSLIC uses registers that are both directly and indirectly mapped.
A “direct” register is one that is mapped directly.
2.1.5. Power Monitoring and Line Fault Detection
In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each
external bipolar transistor. Real-time output power of any one of the six linefeed transistors can be read by setting
the Power Monitor Pointer (direct Register 76) to point to the desired transistor and then reading the Line Power
Output Monitor (direct Register 77).
The real-time power measurements are low-pass filtered and compared to a maximum power threshold. Maximum
power thresholds and filter time constants are software-programmable and should be set for each transistor pair
based on the characteristics of the transistors used. Table 25 describes the registers associated with this function.
If the power in any external transistor exceeds the programmed threshold, a power alarm event is triggered. The
ProSLIC sets the Power Alarm register bit, generates an interrupt (if enabled), and automatically enters the Open
state (if AOPN = 1). This feature protects the external transistors from fault conditions and, combined with the loop
voltage and current monitors, allows diagnosis of the type of fault condition present on the line.
The value of each thermal low-pass filter pole is set according to the equation:
4096
800
3
------------------
Thermal LPF register =
2
where is the thermal time constant of the transistor package, 4096 is the full range of the 12-bit register, and 800
is the sample rate in hertz. Generally = 3 seconds for SOT223 packages and = 0.16 seconds for SOT23, but
check with the manufacturer for the package thermal constant of a specific device. For example, the power alarm
threshold and low-pass filter values for Q5 and Q6 using a SOT223 package transistor are computed as follows:
Thus, indirect Register 34 should be set to 150Dh.
Rev. 1.61
33
Si3210/Si3211
PMAX
7
1.28
0.0304
7
------------------------------
Resolution
-----------------
PPT56 =
2
=
2 = 5389 = 150Dh
Note: The power monitor resolution for Q3 and Q4 is different from that of Q1, Q2, Q5, and Q6.
Table 25. Associated Power Monitoring and Power Fault Registers
Parameter
Description/ Range Resolution
Register
Bits
Location*
Power Monitor Pointer
Line Power Monitor Output
0 to 5 points to Q1 to
Q6, respectively
n/a
PWRMP[2:0]
PWROM[7:0]
Direct Register 76
Direct Register 77
0 to 7.8 W for Q1,
Q2, Q5, Q6
0 to 0.9 W for Q3, Q4
30.4 mW
3.62 mW
30.4 mW
3.62 mW
30.4 mW
Power Alarm Threshold, Q1 & Q2
Power Alarm Threshold, Q3 & Q4
Power Alarm Threshold, Q5 & Q6
Thermal LPF Pole, Q1 & Q2
Thermal LPF Pole, Q3 & Q4
Thermal LPF Pole, Q5 & Q6
Power Alarm Interrupt Pending
0 to 7.8 W
0 to 0.9 W
0 to 7.8 W
PPT12[7:0]
PPT34[7:0]
PPT56[7:0]
NQ12[7:0]
NQ34[7:0]
NQ56[7:0]
Indirect Register 32
Indirect Register 33
Indirect Register 34
Indirect Register 37
Indirect Register 38
Indirect Register 39
Direct Register 19
See equation above.
See equation above.
See equation above.
Bits 2 to 7 correspond
to Q1 to Q6, respec-
tively
n/a
n/a
n/a
QnAP[n+1],
where n = 1
to 6
Power Alarm Interrupt Enable
Bits 2 to 7 correspond
to Q1 to Q6, respec-
tively
QnAE[n+1],
where n = 1
to 6
Direct Register 22
Direct Register 67
Power Alarm
Automatic/Manual Detect
0 = manual mode
1 = enter open state
upon power alarm
AOPN
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
34
Rev. 1.61
Si3210/Si3211
LCS
LVS
Input
Signal
Processor
ISP_OUT
Digital
LPF
+
–
LCIP
LCR
Debounce
Filter
Interrupt
Logic
NCLR
LCDI
LCIE
LFS LCVE
HYSTEN
Loop Closure
Threshold
LCRT LCRTL
Figure 18. Loop Closure Detection
2.1.6. Loop Closure Transition Detection
A loop closure transition event signals that the terminal equipment has gone from on-hook to off-hook or from off-
hook to on-hook; detection occurs while the ProSLIC linefeed is in its on-hook transmission or active states. The
ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter. The functional blocks
required to implement loop closure detection are shown in Figure 18. The primary input to the system is the Loop
Current Sense value provided in the LCS register (direct Register 79). The LCS value is processed in the Input
Signal Processor when the ProSLIC is in the on-hook transmission or active linefeed state, as indicated by the
Linefeed Shadow register, LFS[2:0] (direct Register 64). The data then feeds into a programmable digital low-pass
filter, which removes unwanted ac signal components before threshold detection.
The output of the low-pass filter is compared to a programmable threshold, LCRT (indirect Register 28). The
threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains
in its present state unless the input remains in the opposite state for the entire period of time programmed by the
loop closure debounce interval, LCDI (direct Register 69). If the debounce interval has been satisfied, the LCR bit
will change state to indicate that a valid loop closure transition has occurred. A loop closure transition interrupt is
generated if enabled by the LCIE bit (direct Register 22). Table 26 lists the registers that must be written or
monitored to correctly detect a loop closure condition.
2.1.7. Loop Closure Threshold Hysteresis
Silicon revisions C and higher support the addition of programmable hysteresis to the loop closure threshold, which
can be enabled by setting HYSTEN = 1 (direct Register 108, bit 0). The hysteresis is defined by LCRT (indirect
Register 28) and LCRTL (indirect Register 43), which set the upper and lower bounds, respectively.
2.1.8. Voltage-Based Loop Closure Detection
Silicon revisions C and higher also support an optional voltage-based loop closure detection mode, which is
enabled by setting LCVE = 1 (direct Register 108, bit 2). In this mode, the loop voltage is compared to the loop
closure threshold register (LCRT), which represents a minimum voltage threshold instead of a maximum current
threshold. If hysteresis is also enabled, LCRT represents the upper voltage boundary, and LCRTL represents the
lower voltage boundary for hysteresis. Although voltage-based loop closure detection is an option, the default
current-based loop closure detection is recommended.
Rev. 1.61
35
Si3210/Si3211
2.1.9. Linefeed Calibration
Table 26. Register Set for Loop
An internal calibration algorithm corrects for internal and
external component errors. The calibration is initiated by
setting the CAL bit in direct Register 96. Upon
completion of the calibration cycle, this bit is
automatically reset.
Closure Detection
Parameter
Loop Closure
Interrupt Pending
Register
Location
LCIP
Direct Reg. 19
It is recommended that a calibration be executed
following system powerup. Upon release of the chip
reset, the Si3210 will be in the open state. The
calibration can be initiated after powering up the dc-dc
Loop Closure
Interrupt Enable
LCIE
Direct Reg. 22
Indirect Reg. 28
Indirect Reg. 43
Indirect Reg. 35
Direct Reg. 68
Loop Closure Thresh-
old
LCRT[5:0]
LCRTL[5:0]
NCLR[12:0]
LCR
converter and allowing it to settle for time (t
).
settle
Loop Closure
Threshold—Lower
Additional calibrations may be performed, but only one
calibration should be necessary as long as the system
remains powered up.
Loop Closure Filter
Coefficient
During calibration, V , V , and V voltages are
RING
BAT
TIP
Loop Closure Detect
Status (monitor only)
controlled by the calibration engine to provide the
correct external voltage conditions for the algorithm.
Calibration should be performed in the on-hook state.
RING or TIP must not be connected to ground during
the calibration.
Loop Closure Detect
Debounce Interval
LCDI[6:0]
HYSTEN
LCVE
Direct Reg. 69
Direct Reg. 108
Direct Reg. 108
Hysteresis Enable
Voltage-Based Loop
Closure
When using the Si3201, automatic calibration routines
for RING gain mismatch and TIP gain mismatch should
not be performed. Instead of running these two
calibrations automatically, follow the instructions for
manual calibration in “AN35: Si321x User’s Quick
Reference Guide”.
2.2. Battery Voltage Generation and
Switching
The ProSLIC supports two modes of battery supply
operation. First, the Si3210 integrates a dc-dc converter
controller that dynamically regulates a single output
voltage. This mode eliminates the need to supply large
external battery voltages. Instead, it converts a single
positive input voltage into the real-time battery voltage
needed for any given state according to programmed
linefeed parameters. Second, the Si3211 supports
switching between high and low battery voltage
supplies, as would a traditional monolithic SLIC.
For single to low channel count applications, the Si3210
proves to be an economical choice, as the dc-dc
converter eliminates the need to design and build high-
voltage power supplies. For higher channel count
applications where centralized battery voltage supply is
economical or for modular legacy systems where
battery voltage is already available, the Si3211 is
recommended.
2.2.1. DC-DC Converter General Description
(Si3210/Si3210M Only)
The dc-dc converter dynamically generates the large
negative voltages required to operate the linefeed
interface. The Si3210 acts as the controller for a buck-
36
Rev. 1.61
Si3210/Si3211
boost dc-dc converter that converts a positive dc
voltage into the desired negative battery voltage. In
addition to eliminating external power supplies, this
allows the Si3210 to dynamically control the battery
voltage to the minimum required for any given mode of
operation.
Two different dc-dc circuit options are offered: a BJT/
inductor version and a MOSFET/transformer version.
Due to the differences on the driving circuits, there are
two different versions of the Si3210. The Si3210
supports the BJT/inductor circuit option, and the
Si3210M version supports the MOSFET solution. The
only difference between the two versions is the polarity
of the DCFF pin with respect to the DCDRV pin. For the
Si3210, DCDRV and DCFF are of opposite polarity. For
the Si3210M, DCDRV and DCFF are the same polarity.
Table 27 summarizes these differences.
Table 27. Si3210 and Si3210M Differences
Device
DCFF Signal
Polarity
DCPOL
Si3210
Si3210M
= DCDRV
= DCDRV
0
1
Notes:
1. DCFF signal polarity with respect to DCDRV signal.
2. Direct Register 93, bit 5; This is a read-only bit.
Extensive design guidance on each of these circuits can
be obtained from “AN45: Design Guide for the Si3210
DC-DC Converter” and from an interactive dc-dc
converter design spreadsheet. Both of these documents
are available on the Silicon Laboratories website
(www.silabs.com).
2.2.2. BJT/Inductor Circuit Option Using Si3210
The BJT/Inductor circuit option shown in Figure 10 on
page 18 offers a flexible, low-cost solution. Depending
on selected L1 inductance value and the switching
frequency, the input voltage (V ) can range from 5 V to
DC
30 V. Because of the nature of a dc-dc converter’s
operation, peak and average input currents can become
large with small input voltages. Consider this when
selecting the appropriate input voltage and power rating
for the V power supply.
DC
For this solution, a PNP power BJT (Q7) switches the
current flow through low ESR inductor L1. The Si3210
uses the DCDRV and DCFF pins to switch Q7 on and
off. DCDRV controls Q7 through NPN BJT Q8. DCFF is
ac-coupled to Q7 through capacitor C10 to assist R16 in
turning off Q7. Therefore, DCFF must have opposite
polarity to DCDRV, and the Si3210 (not Si3210M) must
be used.
Rev. 1.61
37
Si3210/Si3211
2.2.3. MOSFET/Transformer Circuit Option Using
the Si3210M
The PWM controller operates at a frequency set by the
dc-dc Converter PWM register (direct Register 92).
During a PWM period, the outputs of the control pins,
DCDRV and DCFF, are asserted for a time given by the
read-only PWM Pulse Width register (direct
Register 94).
The MOSFET/transformer circuit option (shown in
Figure 11 on page 20) offers higher power efficiencies
across a larger input voltage range. Depending on the
transformer’s primary inductor value and the switching
frequency, the input voltage (V ) can range from 3.3 V The dc-dc converter must be off for some time in each
DC
to 35 V. Therefore, it is possible to power the entire cycle to allow the inductor or transformer to transfer its
ProSLIC solution from a single 3.3 V or 5 V power stored energy to the output capacitor, C9. This minimum
supply. By nature of a dc-dc converter’s operation, peak off time can be set through the dc-dc Converter
and average input currents can become large with small Switching Delay register, (direct Register 93). The
input voltages. Consider this when selecting the number of 16.384 MHz clock cycles that the controller is
appropriate input voltage and power rating for the V
power supply (number of REN supported).
off is equal to DCTOF (bits 0 through 4) plus 4. If the dc
Monitor pins detect an overload condition, the dc-dc
converter interrupts its conversion cycles regardless of
the register settings to prevent component damage.
These inputs should be calibrated by writing the DCCAL
bit (bit 7) of the dc-dc Converter Switching Delay
register, direct Register 93, after the dc-dc converter
has been turned on.
DC
For this solution, an N-channel power MOSFET (M1)
switches the current flow through a power transformer,
T1. T1 is specified in “AN45: Design Guide for the
Si3210 DC-DC Converter” and includes several taps on
the primary side to facilitate a wide range of input
voltages. The Si3210M version of the Si3210 must be
used for the application circuit depicted in Figure 11 Because the Si3210 dynamically regulates its own
because the DCFF pin is used to drive M1 directly and, battery supply voltage using the dc-dc converter
therefore, must be the same polarity as DCDRV. controller, the battery voltage, V , is offset from the
BAT
DCDRV is not used in this circuit option; connecting negative-most terminal by a programmable voltage,
DCFF and DCDRV together is not recommended.
V
, to allow voltage headroom for carrying audio
OV
signals.
2.2.4. DC-DC Converter Architecture
(Si3210/Si3210M Only)
As mentioned previously, the Si3210 dynamically
adjusts V
illustrate this, the behavior of V
shown in Figure 19. In the active state, the TIP-to-RING
open circuit voltage is kept at V in the constant
to suit the particular circuit requirement. To
BAT
The control logic for a pulse-width-modulated (PWM)
dc-dc converter is incorporated in the Si3210. Output
pins DCDRV and DCFF are used to switch a bipolar
transistor or MOSFET. The polarity of DCFF is opposite
that of DCDRV.
in the active state is
BAT
OC
voltage region while the regulator output voltage
= V + V + V
V
.
OV
BAT
CM
OC
The dc-dc converter circuit is powered on when the
DCOF bit in the Powerdown Register (direct
Register 14, bit 4) is cleared to 0. The switching
When the loop current attempts to exceed I , the dc
line driver circuit enters constant current mode allowing
the TIP to RING voltage to track R
terminal is kept at a constant voltage, it is the RING
terminal voltage that tracks R and, as a result, the
LIM
. As the TIP
LOOP
regulator circuit within the Si3210 is
a
high-
performance, pulse-width modulation controller. The
control pins are driven by the PWM controller logic in
LOOP
|V
|V
| voltage will also track R
| = I
. In this state,
BAT
LOOP
the Si3210. The regulated output voltage (V
) is
BAT
R
+ V
+V . As R
decreases
LOOP
BAT
LIM x LOOP
CM
OV
sensed by the SVBAT pin and is used to detect whether
the output voltage is above or below an internal
reference for the desired battery voltage. The dc
monitor pins, SDCH and SDCL, monitor input current
and voltage to the dc-dc converter external circuitry. If
an overload condition is detected, the PWM controller
will turn off the switching transistor for the remainder of
a PWM period to prevent damage to external
components. It is important that the proper value of R18
below the VOC/I
can continue to track R
tracking mechanism is stopped when |V
(TRACK = 0). The former case is the more common
application and provides the maximum power
dissipation savings. In principle, the regulator output
voltage can go as low as |V
significant power savings.
mark, the regulator output voltage
LIM
(TRACK = 1), or the R
LOOP
LOOP
| = |V
|
BATL
BAT
| = V + V , offering
BAT
CM OV
be selected to ensure safe operation. Guidance is given When TRACK = 0, |V
| will not decrease below
BAT
in AN45.
V
. The RING terminal voltage, however, continues
BATL
to decrease with decreasing R
.
LOOP
38
Rev. 1.61
Si3210/Si3211
The power dissipation on the NPN bipolar transistor TRACK = 0 mode is desired since the regulator output
driving the RING terminal can become large and may voltage has long settling time constants (on the order of
require a higher power rating device. The non-tracking tens of milliseconds) and cannot change rapidly for
mode of operation is required by specific terminal TRACK = 1 mode. Therefore, the brief on-hook voltage
equipment that, in order to initiate certain data measurement would yield approximately the same
transmission modes, goes briefly on-hook to measure voltage as the off-hook line voltage and cause the
the line voltage to determine whether there is any other terminal equipment to incorrectly sense another off-
off-hook terminal equipment on the same line.
hook terminal.
VOC
ILIM
RLOOP
Constant I Region
Constant V Region
VCM
VTIP
VOC
|VTIP - VRING
|
VBATL
TRACK=0
VOV
VRING
VBAT
VOV
V
Figure 19. VTIP, VRING, and VBAT in the Forward Active State
Table 28. Associated Relevant DC-DC Converter Registers
Parameter
Range
Resolution Register Bit
Location
DC-DC Converter Power-off
Control
N/A
N/A
N/A
DCOF
Direct Register 14
DC-DC Converter Calibration
Enable/Status
N/A
DCCAL
Direct Register 93
Direct Register 92
DC-DC Converter PWM Period
DC-DC Converter Min. Off Time
0 to 15.564 µs
(0 to 1.892 µs) + 4 ns
0 to –94.5 V
61.035 ns
61.035 ns
1.5 V
DCN[7:0]
DCTOF[4:0] Direct Register 93
High Battery Voltage—V
VBATH[5:0]
VBATL[5:0]
Direct Register 74
Direct Register 75
BATH
BATL
Low Battery Voltage—V
0 to –94.5 V
1.5 V
VMIND[3:0]
VOV
Indirect Register 41
Direct Register 66
0 to –9 V or
0 to –13.5 V
V
1.5 V
OV
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Rev. 1.61
39
Si3210/Si3211
2.2.5. DC-DC Converter Enhancements
For example, the ProSLIC will switch from high battery
to low battery when it detects an off-hook event through
either a ring trip or loop closure event. If automatic
battery selection is disabled (ABAT = 0), the battery is
selected by the Battery Feed Select bit, BATSL (direct
Register 66, bit 1).
Silicon revisions
C
and higher support two
enhancements to the dc-dc converter. The first is a
multi-threshold error control algorithm that enables the
dc-dc converter to adjust more quickly to voltage
changes. This option is enabled by setting DCSU = 1
(direct Register 108, bit 5). The second enhancement is Silicon revisions C and higher support the option to add
an audio band filter that removes audio band noise from a 60 ms debounce period to the battery switching circuit
the dc-dc converter control loop. This option is enabled when transitioning from high battery to low battery. This
by setting DCFIL = 1 (direct Register 108, bit 1).
option is enabled by setting SWDB = 1 (direct
Register 108, bit 3). This debounce minimizes battery
transitions in the case of pulse dialing or other quick on-
hook to off-hook transitions.
2.2.6. DC-DC Converter During Ringing
When the ProSLIC enters the ringing state, it requires
voltages well above those used in the active mode. The
voltage to be generated and regulated by the dc-dc
2.3. Tone Generation
converter during a ringing burst is set using the V
BATH
Two digital tone generators are provided in the ProSLIC.
They allow the generation of a wide variety of single- or
dual-tone frequency and amplitude combinations and
spare the user the effort of generating the required
POTS signaling tones on the PCM highway. DTMF, FSK
(caller ID), call progress, and other tones can all be
generated on-chip. The tones can be sent to either the
receive or transmit paths (see Figure 25 on page 50).
register (direct Register 74). V
can be set between
BATH
0 and –94.5 V in 1.5 V steps. To avoid clipping the
ringing signal, V must be set larger than the ringing
BATH
amplitude. At the end of each ringing burst, the dc-dc
converter adjusts back to active state regulation as
described above.
2.2.7. External Battery Switching (Si3211 Only)
The Si3211 supports switching between two battery
voltages. The circuit for external battery switching is
defined in Figure 14. Typically, a high-voltage battery
(e.g., –70 V) is used for on-hook and ringing states, and
a low-voltage battery (e.g., –24 V) is used for the off-
hook condition. The ProSLIC uses an external transistor
to switch between the two supplies.
2.3.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 20. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected to give the user flexibility in creating audio
signals. Control and status register bits are placed in the
figure to indicate their association with the tone
generator architecture. These registers are described in
more detail in Table 29.
When the ProSLIC changes operating states, it
automatically switches battery supplies if the automatic/
manual control bit, ABAT (direct Register 67, bit 3), is
set.
40
Rev. 1.61
Si3210/Si3211
8 kHz
Clock
8 kHz
Clock
OZn
Zero Cross
OnE
OSSn
to TX Path
Enable
Zero
Cross
Logic
Two-Pole
Resonance
Oscillator
16-Bit
Modulo
Counter
OAT
Expire
Signal
Routing
Register
Load
Load
Logic
OIT
Expire
to RX Path
OSCn
OATn
OITn
OnIP REL*
INT
Logic
OATnE
OnSO
OSCnX
OSCnY
OnIE
OITnE
OnAP
INT
Logic
OnAE
*Tone Generator 1 Only
n = "1" or "2" for Tone Generator 1 and 2, respectively
Figure 20. Simplified Tone Generator Diagram
2.3.2. Oscillator Frequency and Amplitude
Each of the two tone generators contains a two-pole
resonate oscillator circuit with programmable
OSC1Y = 0
21336
= 0.49819
--------------------
coeff2 = cos
a
8000
frequency and amplitude, which are programmed via
indirect registers OSC1, OSC1X, OSC1Y, OSC2,
OSC2X, and OSC2Y. The sample rate for the two
oscillators is 8000 Hz. The equations are as follows:
15
OSC2 = 0.49819 (2 ) = 16324 = 3FC4h
1
0.50181
--
OSC2X =
--------------------- 215 – 1 0.5 = 2370 = 942h
4
1.49819
coeff = cos(2f /8000 Hz),
n
n
OSC2Y = 0
where f is the frequency to be generated;
n
The above computed values would be written to the
corresponding registers to initialize the oscillators. Once
the oscillators are initialized, the oscillator control
registers can be accessed to enable the oscillators and
direct their outputs.
15
OSCn = coeff x (2 );
n
Desired Vrms
-------------------------------------
1
4
15
1 – coeff
1 + coeff
--
OSCnX =
----------------------- 2 – 1
1.11 Vrms
2.3.3. Tone Generator Cadence Programming
where desired Vrms is the amplitude to be generated;
OSCnY = 0,
Each of the two tone generators contains two timers,
one for setting the active period and one for setting the
inactive period. The oscillator signal is generated during
the active period and suspended during the inactive
period. Both the active and inactive periods can be
programmed from 0 to 8 seconds in 125 µs steps. The
active period time interval is set using OAT1 (direct
registers 36 and 37) for tone generator 1 and OAT2
(direct registers 40 and 41) for tone generator 2.
n = 1 or 2 for oscillator 1 or oscillator 2, respectively.
For example, in order to generate a DTMF digit of 8, the
two required tones are 852 Hz and 1336 Hz. Assuming
the generation of half-scale values (ignoring twist) is
desired, the following values are calculated:
2852
8000
----------------
coeff1 = cos
= 0.78434
To enable automatic cadence for tone generator 1,
define the OAT1 and OIT1 registers and then set the
O1TAE bit (direct Register 32, bit 4) and O1TIE bit
(direct Register 32, bit 3). This enables each of the
timers to control the state of the Oscillator Enable bit,
O1E (direct Register 32, bit 2). The 16-bit counter will
begin counting until the active timer expires, at which
OSC1 = 0.78434215 = 25701= 6465h
1
4
0.21556
1.78434
--
OSC1X =
--------------------- 215 – 1 0.5 = 1424 = 590h
Rev. 1.61
41
Si3210/Si3211
time the 16-bit counter will reset to zero and begin The operation of tone generator 2 is identical to that of
counting until the inactive timer expires. The cadence tone generator 1 using its respective control registers.
continues until the user clears the O1TAE and O1TIE
control bits. The zero crossing detect feature can be
implemented by setting the OZ1 bit (direct Register 32,
bit 5). This ensures that each oscillator pulse ends
without a dc component. The timing diagram in
Figure 21 is an example of an output cadence using the
zero crossing feature.
Note: Tone Generator 2 should not be enabled simultane-
ously with the ringing oscillator due to resource sharing
within the hardware.
Continuous phase frequency-shift keying (FSK)
waveforms may be created using tone generator 1 (not
available on tone generator 2) by setting the REL bit
(direct Register 32, bit 6), which enables reloading of
One-shot oscillation can be achieved by enabling O1E the OSC1, OSC1X, and OSC1Y registers at the
and O1TAE. Direct control over the cadence can be expiration of the active timer, OAT1.
achieved by controlling the O1E bit (direct Register 32,
bit 2) directly if O1TAE and O1TIE are disabled.
Table 29. Associated Tone Generator Registers
Tone Generator 1
Parameter
Description / Range
Register Bits
OSC1[15:0]
OSC1X[15:0]
OSC1Y[15:0]
OAT1[15:0]
OIT1[15:0]
Location
Oscillator 1 Frequency Coefficient Sets oscillator frequency
Indirect Register 13
Indirect Register 14
Indirect Register 15
Direct Registers 36 & 37
Direct Register 38 & 39
Direct Register 32
Oscillator 1 Amplitude Coefficient
Oscillator 1 initial phase coefficient
Oscillator 1 Active Timer
Sets oscillator amplitude
Sets initial phase
0 to 8 seconds
Oscillator 1 Inactive Timer
Oscillator 1 Control
0 to 8 seconds
Status and control
registers
OSS1, REL, OZ1,
O1TAE, O1TIE,
O1E, O1SO[1:0]
Tone Generator 2
Description/Range
Parameter
Register
OSC2[15:0]
OSC2X[15:0]
OSC2Y[15:0]
OAT2[15:0]
OIT2[15:0]
Location
Oscillator 2 Frequency Coefficient Sets oscillator frequency
Indirect Register 16
Indirect Register 17
Indirect Register 18
Direct Registers 40 & 41
Direct Register 42 & 43
Direct Register 33
Oscillator 2 Amplitude Coefficient
Oscillator 2 initial phase coefficient
Oscillator 2 Active Timer
Sets oscillator amplitude
Sets initial phase
0 to 8 seconds
Oscillator 2 Inactive Timer
Oscillator 2 Control
0 to 8 seconds
Status and control
registers
OSS2, OZ2,
O2TAE, O2TIE,
O2E, O2SO[1:0]
42
Rev. 1.61
Si3210/Si3211
O1E
0,1 ...
..., OAT1 0,1 ...
..., OIT1 0,1 ...
..., OAT1 0,1 ...
...
...
OSS1
Tone
Gen. 1
Signal
Output
Figure 21. Tone Generator Timing Diagram
2.3.4. Enhanced FSK Waveform Generation
2.4. Ringing Generation
Silicon revisions C and higher support enhanced FSK
generation capabilities, which can be enabled by setting
FSKEN = 1 (direct Register 108, bit 6) and REN = 1
(direct Register 32, bit 6). In this mode, the user can
define mark (1) and space (0) attributes once during
initialization by defining indirect registers 99–104. The
user need only indicate 0-to-1 and 1-to-0 transitions in
the information stream. By writing to FSKDAT (direct
Register 52), this mode applies a 24 kHz sample rate to
tone generator 1 to give additional resolution to timers
and frequency generation. “AN32: Si321x Frequency
Shift Keying (FSK) Modulation” gives detailed
instructions on how to implement FSK in this mode.
Additionally, sample source code is available from
Silicon Laboratories upon request.
The ProSLIC provides fully-programmable internal
balanced ringing with or without a dc offset to ring a
wide variety of terminal devices. All parameters
associated with ringing (ringing frequency, waveform,
amplitude, dc offset, and ringing cadence) are software-
programmable. Both sinusoidal and trapezoidal ringing
waveforms are supported, and the trapezoidal crest
factor is programmable. Ringing signals of up to 88 V
peak or more can be generated, enabling the ProSLIC
to drive a 5 REN (1380 + 40 µF) ringer load across
loop lengths of 2000 feet (160 ) or more.
2.4.1. Ringing Architecture
The ringing generator architecture is nearly identical to
that of the tone generator. The sinusoidal ringing
waveform is generated using an internal two-pole
resonance oscillator circuit with programmable
frequency and amplitude. However, since ringing
frequencies are very low compared to the audio band
signaling frequencies, the ringing waveform is
generated at a rate of 1 kHz instead of 8 kHz.
2.3.5. Tone Generator Interrupts
Both the active and inactive timers can generate their
own interrupt to signal “on/off” transitions to the
software. The timer interrupts for tone generator 1 can
be individually enabled by setting the O1AE and O1IE
bits (direct Register 21, bits 0 and 1, respectively).
Timer interrupts for tone generator two are O2AE and
O2IE (direct Register 21, bits 2 and 3, respectively). A
pending interrupt for each of the timers is determined by
reading the O1AP, O1IP, O2AP, and O2IP bits in the
Interrupt Status 1 register (direct Register 18, bits 0
through 3, respectively).
The ringing generator has two timers that function the
same as the tone generator timers. They allow on/off
cadence settings of up to 8 seconds on and 8 seconds
off. In addition to controlling ringing cadence, these
timers control the transition into and out of the ringing
state. Table 30 summarizes the list of registers used for
ringing generation.
Note: Tone generator 2 should not be enabled concurrently
with the ringing generator due to resource sharing
within the hardware.
Rev. 1.61
43
Si3210/Si3211
Table 30. Registers for Ringing Generation
Parameter
Range/ Description
Register
Bits
Location
Ringing Waveform
Ringing Voltage Offset Enable
Sine/Trapezoid
Enabled/
TSWS
RVO
Direct Register 34
Direct Register 34
Disabled
Ringing Active Timer Enable
Ringing Inactive Timer Enable
Ringing Oscillator Enable
Enabled/
Disabled
Enabled/
Disabled
RTAE
RTIE
ROE
Direct Register 34
Direct Register 34
Direct Register 34
Enabled/
Disabled
Ringing Oscillator Active Timer
Ringing Oscillator Inactive Timer
Linefeed Control (Initiates Ringing State)
High Battery Voltage
0 to 8 seconds
0 to 8 seconds
Ringing State = 100b
0 to –94.5 V
0 to 94.5 V
15 to 100 Hz
0 to 94.5 V
Sets initial phase for
sinewave and period
for
RAT[15:0]
RIT[15:0]
LF[2:0]
VBATH[5:0]
ROFF[15:0]
RCO[15:0]
RNGX[15:0]
RNGY[15:0]
Direct Registers 48 and 49
Direct Registers 50 and 51
Direct Register 64
Direct Register 74
Ringing dc voltage offset
Ringing frequency
Ringing amplitude
Ringing initial phase
Indirect Register 19
Indirect Register 20
Indirect Register 21
Indirect Register 22
trapezoid
Common Mode Bias Adjust During Ringing
0 to 22.5 V
VCMR[3:0]
Indirect Register 40
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
When the ringing state is invoked by writing
Desired VPK0 to 94.5 V
-----------------------------------------------------------------------
96 V
1
4
15
1 – coeff
1 + coeff
--
RNGX =
----------------------- 2
LF[2:0] = 100 (direct Register 64), the ProSLIC will go
into the ringing state and start the first ring. At the
expiration of RAT, the ProSLIC will turn off the ringing
waveform and will go to the on-hook transmission state.
At the expiration of RIT, ringing will again be initiated.
This process will continue as long as the two timers are
enabled and the Linefeed Control register is set to the
ringing state.
RNGY = 0
The minimum allowed peak TIP-to-RING ringing voltage
depends on the linefeed state. In the forward active
linefeed state, the selected ringing amplitude (RNGX,
Indirect Register 21) plus the selected ringing dc voltage
offset (ROFF, Indirect Register 19) must be greater than
the selected on-hook line voltage setting (VOC, direct
Register 72). In the reverse active linefeed state, the
selected ringing amplitude (RNGX, Indirect Register 21)
minus the selected ringing dc voltage offset (ROFF,
Indirect Register 19) must be greater than the selected
on-hook line voltage setting (VOC, direct Register 72).
2.4.2. Sinusoidal Ringing
To configure the ProSLIC for sinusoidal ringing, the
frequency and amplitude are initialized by writing to the
following indirect registers: RCO, RNGX, and RNGY.
The equations for RCO, RNGX, RNGY are as follows:
RCO = coeff 215
Using a 70 VPK 20 Hz ringing signal as an example, the
equations are as follows:
where
2f
1000 Hz
2 20
1000 Hz
----------------------
coeff = cos
----------------------
coeff = cos
= 0.99211
and f = desired ringing frequency in Hertz.
44
Rev. 1.61
Si3210/Si3211
For example, to generate a 71 V , 20 Hz ringing
signal, the equations are as follows:
RCO = 0.99211 215 = 32509 = 7EFDh
PK
1
4
15 70
0.00789
1.99211
--
------
= 376 = 0177h
RNGX =
--------------------- 2
1
2
1
96
-- ---------------
8000 = 200 = C8h
RNGY20 Hz =
20 Hz
RNGY = 0
215= 24235 = 5EABh
71
96
------
In addition, the user must select the sinusoidal ringing
waveform by writing TSWS = 0 (direct Register 34,
bit 0).
RNGX71 VPK =
For a crest factor of 1.3 and a period of 0.05 seconds
(20 Hz), the rise time requirement is 0.0153 seconds.
2.4.3. Trapezoidal Ringing
In addition to the sinusoidal ringing waveform, the
ProSLIC supports trapezoidal ringing. Figure 22
illustrates a trapezoidal ringing waveform with offset
RCO20 Hz, 1.3 crest factor
2 24235
-------------------------------------
=
= 396= 018Ch
0.0153 8000
V
.
ROFF
In addition, the user must select the trapezoidal ringing
waveform by writing TSWS = 1 in direct Register 34.
2.4.4. Ringing DC voltage Offset
VTIP-RING
A dc offset can be added to the ac ringing waveform by
defining the offset voltage in ROFF (indirect
Register 19). The offset, V
, is added to the ringing
ROFF
signal when RVO is set to 1 (direct Register 34, bit 1).
The value of ROFF is calculated as follows:
VROFF
T=1/freq
VROFF
15
-----------------
ROFF =
2
96
2.4.5. Linefeed Considerations During Ringing
tRISE
time
Care must be taken to keep the generated ringing signal
within the ringing voltage rails (GNDA and V
) to
BAT
maintain proper biasing of the external bipolar
transistors. If the ringing signal nears the rails, a
distorted ringing signal and excessive power dissipation
in the external transistors results.
Figure 22. Trapezoidal Ringing Waveform
To configure the ProSLIC for trapezoidal ringing, the
user should follow the same basic procedure as in the
Sinusoidal Ringing section, but using the following
equations:
To prevent this invalid operation, set the V
value
BATH
(direct Register 74) to a value higher than the maximum
peak ringing voltage. The discussion below outlines the
considerations and equations that govern the selection
1
--
RNGY = Period 8000
2
of the V
voltage.
setting for a particular desired peak ringing
BATH
Desired VPK
RNGX =
215
-----------------------------------
96 V
First, the required amount of ringing overhead voltage,
, is calculated based on the maximum value of
V
OVR
2 RNGX
tRISE 8000
current through the load, I
gain of Q5 and Q6, and a reasonable voltage required
to keep Q5 and Q6 out of saturation. For ringing signals
up to V = 87 V, V
However, to determine V
equations below.
, the minimum current
--------------------------------
LOAD,PK
RCO =
RCO is a value added or subtracted from the waveform
to ramp the signal up or down in a linear fashion. This
value is a function of rise time, period, and amplitude,
where rise time and period are related through the
following equation for the crest factor of a trapezoidal
waveform.
= 7.5 V is a safe value.
for a specific case, use the
PK
OVR
OVR
VAC,PK
NREN
-----------------
6.9 k
------------------
ILOAD,PK
=
+ IOS = VAC,PK
+ IOS
RLOAD
3
4
1
--
----------
tRISE
=
T 1 –
CF2
where T = ringing period, and CF = desired crest factor.
Rev. 1.61
45
Si3210/Si3211
where:
ringing to a dc linefeed state. This mode is enabled by
setting ILIMEN = 1 (direct Register 108, bit 7).
N
is the ringing REN load (max value = 5),
REN
2.4.6. Ring Trip Detection
I
is the offset current flowing in the line driver circuit
OS
(max value = 2 mA), and
A ring trip event signals that the terminal equipment has
gone off-hook during the ringing state. The ProSLIC
performs ring trip detection digitally using its on-chip A/
V
= amplitude of the ac ringing waveform.
AC,PK
It is good practice to provide a buffer of a few more
milliamperes for I to account for possible line
D
converter. The functional blocks required to
LOAD,PK
implement ring trip detection are shown in Figure 23.
The primary input to the system is the loop current
sense (LCS) value provided by the current monitoring
circuitry and reported in direct Register 79. LCS data is
processed by the input signal processor when the
ProSLIC is in the ringing state as indicated by the
Linefeed Shadow register (direct Register 64). The data
then feeds into a programmable digital low-pass filter
that removes unwanted ac signal components before
threshold detection.
leakages, etc. The total I
smaller than 80 mA.
current should be
LOAD,PK
+ 1
------------
80.6 + 1 V
VOVR = ILOAD,PK
where is the minimum expected current gain of
transistors Q5 and Q6.
The minimum value for V
following:
is therefore given by the
BATH
The output of the low-pass filter is compared to a
programmable threshold, RPTP (indirect Register 29).
The threshold comparator output feeds a programmable
debouncing filter. The output of the debouncing filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the ring trip debounce interval,
RTDI[6:0] (direct Register 70). If the debounce interval
has been satisfied, the RTP bit of direct Register 68 will
be set to indicate that a valid ring trip has occurred. A
ring trip interrupt is generated if enabled by the RTIE bit
(direct Register 22). Table 31 lists the registers that
must be written or monitored to correctly detect a ring
trip condition.
VBATH = VAC,PK + VROFF + VOVR
The ProSLIC is designed to create a fully-balanced
ringing waveform, meaning that the TIP and RING
common mode voltage, (V
+ V
)/2, is fixed. This
TIP
RING
voltage is referred to as VCM_RING and is
automatically set to the following:
VBATH – VCMR
---------------------------------------------
VCM_RING =
2
VCMR is an indirect register, which provides the
headroom by the ringing waveform with respect to the
rail. The value is set as a 4-bit setting in indirect
Register 40 with an LSB voltage of 1.5 V/LSB.
V
BATH
Register 40 should be set with the calculated V
provide voltage headroom during ringing.
to The recommended values for RPTP, NRTP, and RTDI
vary according to the programmed ringing frequency.
Register values for various ringing frequencies are
given in Table 32.
OVR
Silicon revisions C and higher support the option to
briefly increase the maximum differential current limit
between the voltage transition of TIP and RING from
Input
Signal
Processor
LCS
ISP_OUT
Digital
LPF
+
–
DBIRAW
RTIP
RTP
Debounce
Filter
Interrupt
Logic
NRTP
RTDI
RTIE
LFS
Ring Trip
Threshold
RPTP
Figure 23. Ring Trip Detector
46
Rev. 1.61
Si3210/Si3211
Table 31. Associated Registers for Ring Trip Detection
Parameter
Ring Trip Interrupt Pending
Register
Location
RTIP
RTIE
Direct Register 19
Direct Register 22
Direct Register 70
Indirect Register 29
Indirect Register 36
Direct Register 68
Ring Trip Interrupt Enable
Ring Trip Detect Debounce Interval
Ring Trip Threshold
RTDI[6:0]
RPTP[5:0]
NRTP[12:0]
RTP
Ring Trip Filter Coefficient
Ring Trip Detect Status (monitor only)
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Table 32. Recommended Ring Trip Values for Ringing
Ringing
NRTP
RPTP
RTDI
Frequency
Hz
16.667
20
decimal
64
hex
decimal
34 mA
34 mA
34 mA
34 mA
34 mA
34 mA
hex
decimal
15.4 ms
12.3 ms
8.96 ms
7.5 ms
5 ms
hex
0F
0B
09
07
05
05
0200
0320
0380
0400
06A8
0800
3600
3600
3600
3600
3600
3600
100
112
30
40
128
213
256
50
60
4.8 ms
2.5. Pulse Metering Generation
Desired Vrms
-------------------------------------------
Full Scale Vrms
1
4
15
1 – coeff
--
PLSX =
----------------------- 2 – 1
There is an additional tone generator suitable for
generating tones above the audio frequency. This
oscillator is provided for the generation of billing tones
that are typically 12 kHz or 16 kHz. The generator
follows the same algorithm as described in "2.3. Tone
1 + coeff
= 0.85 V
where full scale V
for a matched load.
rms
rms
The initial phase of the pulse metering signal is set to 0
internally; so, there is no register to serve this purpose.
Generation" on page 40 with the exception that the The pulse metering generator timers and associated
sample rate for computation is 64 kHz instead of 8 kHz. pulse metering timer registers are similar to those of the
The equations are as follows:
tone generators. These timers count 8 kHz sample
periods like the other tones even though the sinusoid is
generated at 64 kHz.
2f
coeff = cos
--------------------------
64000 Hz
PLSCO = coeff 215 – 1
Rev. 1.61
47
Si3210/Si3211
Table 33. Associated Pulse Metering Generator Registers
Parameter
Description / Range
Register Bits
Location
Pulse Metering Frequency
Coefficient
Sets oscillator frequency
PLSCO[15:0]
Indirect Register 25
Pulse Metering Amplitude
Coefficient
Sets oscillator amplitude
0 to PLSX (full amplitude)
PLSX[15:0]
PLSD[15:0]
Indirect Register 24
Indirect Register 23
Pulse Metering Attack/Decay
Ramp Rate
Pulse Metering Active Timer
Pulse Metering Inactive Timer
Pulse Metering Control
0 to 8 seconds
0 to 8 seconds
PAT[15:0]
PIT[15:0]
Direct Registers 44 & 45
Direct Register 46 & 47
Direct Register 35
Status and control registers
PSTAT, PMAE,
PMIE, PMOE
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped
directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28
through 31).
The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The
volume value is incremented by the value in the PLSD register (indirect Register 23) at an 8 kHz rate. The
sinusoidal generator output is multiplied by this volume before being sent to the DAC. The volume will ramp from 0
to 7FFF in increments of PLSD; so, the value of PLSD will set the slope of the ramp. When the pulse metering
signal is turned off, the volume will ramp to 0 by decrementing according to the value of PLSD.
Pulse Metering Oscillator
X
To DAC
Volume
8 Khz
PLSD
+/–
Clip to 7FFF or 0
Figure 24. Pulse Metering Volume Envelope
48
Rev. 1.61
Si3210/Si3211
filter is available in the transmit path: THPF. THPF
implements the high-pass attenuation requirements for
signals below 65 Hz. The linear PCM data stream
output from THPF is amplified by the transmit-path
programmable gain amplifier, ADCG, which can be
programmed from – dB to 6 dB. The DTMF decoder
can receive the linear PCM data stream at this point to
perform the digit extraction when enabled by the user.
The final step in transmit path signal processing is the
user-selectable A-law or µ-law compression, which can
reduce the data stream word width to 8 bits. Depending
on the PCM_Mode register selection, every 8-bit
compressed serial data word will occupy one time slot
on the PCM highway, or every 16-bit uncompressed
serial data word will occupy two time slots on the PCM
highway.
2.6. DTMF Detection
The dual-tone multi-frequency (DTMF) tone signaling
standard is also known as touch tone. It is an in-band
signaling system used to replace the pulse-dial
signaling standard. In DTMF, two tones are used to
generate a DTMF digit. One tone is chosen from four
possible row tones, and one tone is chosen from four
possible column tones. The sum of these tones
constitutes one of 16 possible DTMF digits.
2.6.1. DTMF Detection Architecture
DTMF detection is performed using a modified Goertzel
algorithm to compute the dual frequency tone (DFT) for
each of the eight DTMF frequencies as well as their
second harmonics. At the end of the DFT computation,
the squared magnitudes of the DFT results for the eight
DTMF fundamental tones are computed. The row
results are sorted to determine the strongest row
frequency; the column frequencies are sorted as well.
At the completion of this process, a number of checks
are made to determine whether the strongest row and
column tones constitute a DTMF digit.
The detection process is performed twice within the
45 ms minimum tone time. A digit must be detected on
two consecutive tests following a pause to be
recognized as a new digit. If all tests pass, an interrupt
is generated, and the DTMF digit value is loaded into
the DTMF register. If tones occur at the maximum rate
of 100 ms per digit, the interrupt must be serviced within
85 ms so that the current digit is not overwritten by a
new one. There is no buffering of the digit information.
2.7. Audio Path
Unlike traditional SLICs, the codec function is integrated
into the ProSLIC. The 16-bit codec offers programmable
gain/attenuation blocks and several loopback modes.
The signal path block diagram is shown in Figure 25.
2.7.1. Transmit Path
In the transmit path, the analog signal fed by the
external ac coupling capacitors is amplified by the
analog transmit amplifier, ATX, prior to the A/D
converter. The gain of the ATX is user-selectable to one
of mute/–3.5/0/3.5 dB options. The main role of ATX is
to coarsely adjust the signal swing to be as close as
possible to the full-scale input of the A/D converter in
order to maximize the signal-to-noise ratio of the
transmit path. After passing through an anti-aliasing
filter, the analog signal is processed by the A/D
converter, producing an 8 kHz, 16-bit wide, linear PCM
data stream. The standard requirements for transmit
path attenuation for signals above 3.4 kHz are
implemented as part of the combined decimation filter
characteristic of the A/D converter. One more digital
Rev. 1.61
49
Si3210/Si3211
50
Rev. 1.61
Si3210/Si3211
2.7.2. Receive Path
From this point of view, at frequencies greater than
4 kHz, the plot in Figure 4 should be interpreted as the
maximum allowable magnitude of any spurious signals
In the receive path, the optionally-compressed 8-bit
data is first expanded to 16-bit words. The PCMF
register bit can bypass the expansion process, in
which case two 8-bit words are assembled into one 16-
bit word. DACG is the receive path programmable gain
amplifier, which can be programmed from – dB to
that are generated when
a PCM data stream
representing a sine wave signal in the range of 300 Hz
to 3.4 kHz at a level of 0 dBm0 is applied at the digital
input.
6 dB. An 8 kHz, 16-bit signal is then provided to a D/A The group delay distortion in either path is limited to no
converter. The resulting analog signal is amplified by more than the levels indicated in Figure 5 on page 9.
the analog receive amplifier, ARX, which is user- The reference in Figure 5 is the smallest group delay for
selectable to one of several options: mute, –3.5, 0, or a sine wave in the range of 500 Hz to 2500 Hz at
3.5 dB. It is then applied at the input of the 0 dBm0.
transconductance amplifier (Gm), which drives the off-
The block diagram for the voice-band signal processing
chip current buffer (I
).
BUF
paths is shown in Figure 25. Both the receive and
transmit paths employ the optimal combination of
analog and digital signal processing to provide
maximum performance while offering sufficient flexibility
to allow users to optimize for their particular ProSLIC
application. All programmable signal-processing blocks
are indicated symbolically in Figure 25 by a dashed
arrow across them. The two-wire (TIP/RING) voice-
band interface to the ProSLIC is implemented using a
small number of external components. The receive path
2.7.3. Audio Characteristics
The dominant source of distortion and noise in both the
transmit and receive paths is the quantization noise
introduced by the µ-law or the A-law compression
process. Figure 1 on page 6 specifies the minimum
signal-to-noise-and-distortion ratio for either path for a
sine wave input of 200 Hz to 3400 Hz.
Both the µ-law and the A-law speech encoding allow the
audio codec to transfer and process audio signals larger
than 0 dBm0 without clipping. The maximum PCM code
is generated for a µ-law encoded sine wave of
3.17 dBm0 or an A-law encoded sine wave of
3.14 dBm0. The ProSLIC overload clipping limits are
driven by the PCM encoding process. Figure 2 on page
interface consists of a unity-gain current buffer, I
,
BUF
while the transmit path interface is simply an ac
coupling capacitor. Signal paths, although implemented
differentially, are shown as single-ended for simplicity.
2.7.4. Transhybrid Balance
6 shows the acceptable limits for the analog-to-analog The ProSLIC provides programmable transhybrid
fundamental power transfer-function, which bounds the balance with gain block H. (See Figure 25.) In the ideal
behavior of ProSLIC.
case, where the synthesized SLIC impedance exactly
matches the subscriber loop impedance, the
transhybrid balance should be set to subtract a –6 dB
level from the transmit path signal. The transhybrid
balance gain can be adjusted from –2.77 dB to
+4.08 dB around the ideal setting of –6 dB by
programming the HYBA[2:0] bits of the Hybrid Control
register (direct Register 11). Note that adjusting any of
the analog or digital gain blocks will not require any
modification of the transhybrid balance gain block, as
the transhybrid gain is subtracted from the transmit path
signal prior to any gain adjustment stages. If desired,
the transhybrid balance can also be disabled using the
appropriate register setting.
The transmit path gain distortion versus frequency is
shown in Figure 3 on page 7. The same figure also
presents the minimum required attenuation for any out-
of-band analog signal that may be applied on the line.
Note the presence of a high-pass filter transfer function
that ensures at least 30 dB of attenuation for signals
below 65 Hz. The low-pass filter transfer function that
attenuates signals above 3.4 kHz has to exceed the
requirements specified by the equations in Figure 3 on
page 7 and is implemented as part of the A-to-D
converter.
The receive path transfer function requirement, shown
in Figure 4 on page 8, is very similar to the transmit path
transfer function. The most notable difference is the
2.7.5. Loopback Testing
absence of the high-pass filter portion. The only other Four loopback test options are available in the ProSLIC:
differences are the maximum 2 dB of attenuation at
The full analog loopback (ALM2) tests almost all the
200 Hz (as opposed to 3 dB for the transmit path) and
circuitry of both the transmit and receive paths. The
the 28 dB of attenuation for any frequency above
compressed 8-bit word transmit data stream is fed
4.6 kHz. The PCM data rate is 8 kHz and, thus, no
back serially to the input of the receive path
frequencies greater than 4 kHz can be digitally encoded
expander. (See Figure 25.) The signal path starts
with the analog signal at the input of the transmit
in the data stream.
Rev. 1.61
51
Si3210/Si3211
path and ends with an analog signal at the output of transistors Q1 and Q2 (see Figure 13 on page 24). G
m
the receive path.
is referenced to an off-chip resistor (R ).
15
An additional analog loopback (ALM1) takes the
digital stream at the output of the A/D converter and
feeds it back to the D/A converter. (See Figure 25.)
The signal path starts with the analog signal at the
input of the transmit path and ends with an analog
signal at the output of the receive path. This
loopback option allows testing of the analog signal
processing circuitry of the Si3210 to be carried out
completely independently of any activity in the DSP.
The full digital loopback tests almost all the circuitry
of both the transmit and receive paths. The analog
signal at the output of the receive path are fed back
to the input of the transmit path by way of the hybrid
filter path. (See Figure 25.) The signal path starts
with 8-bit PCM data input to the receive path and
ends with 8-bit PCM data at the output of the
transmit path. The user can bypass the companding
process and interface directly to the 16-bit data.
An additional digital loopback (DLM) takes the digital
stream at the input of the D/A converter in the
receive path and feeds it back to the transmit A/D
digital filter. The signal path starts with 8-bit PCM
data input to the receive path and ends with 8-bit
PCM data at the output of the transmit path. This
loopback option allows the testing of the digital
signal processing circuitry of the Si3210 to be carried
out completely independently of any analog signal
processing activity. The user can bypass the
companding process and interface directly to the 16-
bit data.
The ProSLIC also provides a means of compensating
for degraded subscriber loop conditions involving
excessive line capacitance (leakage). The CLC[1:0] bits
of direct Register 10 increase the ac signal magnitude
to compensate for the additional loss at the high end of
the audio frequency range. The default setting of
CLC[2:0] assumes no line capacitance.
Silicon revisions C and higher support the option to
remove the internal reference resistor used to
synthesize ac impedances for 600 + 2.16 µF and
900 + 2.16 µF settings so that an external resistor
reference may be used. This option is enabled by
setting ZSEXT = 1 (direct Register 108, bit 4).
2.9. Clock Generation
The ProSLIC will generate the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or
8.192 MHz. (Note that 768 kHz and 1.536 MHz are not
valid rates for GCI mode.) The ratio of the PCLK rate to
the FSYNC rate is determined via a counter clocked by
PCLK. The three-bit ratio information is automatically
transferred into an internal register, PLL_MULT,
following a reset of the ProSLIC. The PLL_MULT is
used to control the internal PLL, which multiplies PCLK
as needed to generate the 16.384 MHz rate needed to
run the internal filters and other circuitry.
The PLL clock synthesizer settles very quickly following
powerup. However, the settling time depends on the
PCLK frequency, and it can be approximated by the
following equation:
2.8. Two-Wire Impedance Matching
The ProSLIC provides on-chip, programmable, two-wire
impedance settings to meet a wide variety of worldwide
two-wire return loss requirements. The two-wire
impedance is programmed by loading one of the eight
available impedance values into the TISS[2:0] bits of the
Two-Wire Impedance Synthesis Control register (direct
Register 10). If direct Register 10 is not user-defined,
the default setting of 600 will be loaded into the TISS
register.
64
FPCLK
----------------
=
TSETTLE
2.10. Interrupt Logic
The ProSLIC is capable of generating interrupts for the
following events:
Real and complex two-wire impedances are realized by
internal feedback of a programmable amplifier (RAC), a
Loop current/ring ground detected
Ring trip detected
Power alarm
switched
capacitor
network
(XAC),
and
a
transconductance amplifier (G ). (See Figure 25.) RAC
m
DTMF digit detected
creates the real portion, and XAC creates the imaginary
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
portion of G ’s input. G then creates a current that
m
m
models the desired impedance value to the subscriber
loop. The differential ac current is fed to the subscriber
loop via the ITIPP and IRINGP pins through an off-chip
current buffer, I , which is implemented using
BUF
52
Rev. 1.61
Si3210/Si3211
Pulse metering active timer expired
Pulse metering inactive timer expired
Indirect register access complete
The interface to the interrupt logic consists of six registers. Three interrupt status registers contain one bit for each
of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource.
Three interrupt enable registers also contain one bit for each interrupt function. In the case of the interrupt enable
registers, the bits are active high. Refer to the appropriate functional description section for operational details of
the interrupt functions.
When a resource reaches an interrupt condition, it will signal an interrupt to the interrupt control block. The interrupt
control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set.
The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is
asserted, IRQ will assert low. Upon receiving the interrupt, the interrupt handler should read interrupt status
registers to determine which resource is requesting service. To clear a pending interrupt, write the desired bit in the
appropriate interrupt status register to 1. Writing a 0 has no effect. This provides a mechanism for clearing
individual bits when multiple interrupts occur simultaneously. While the interrupt status registers are non-zero, the
INT pin will remain asserted.
2.11. Serial Peripheral Interface
The control interface to the ProSLIC is a 4-wire interface modeled after commonly-available micro-controller and
serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and
serial data output (SDO). Data is transferred a byte at a time with each register access consisting of a pair of byte
transfers. Figures 26 and 27 illustrate read and write operation in the SPI bus.
The first byte of the pair is the command/address byte. The MSB of this byte indicates a register read when 1 and
a register write when 0. The remaining seven bits of the command/address byte indicate the address of the register
to be accessed. The second byte of the pair is the data byte. Because the falling edge of CS provides
resynchronization of the SPI state machine in the event of a framing error, it is recommended (but not required) that
CS be taken high between byte transfers as shown in Figures 26 and 27.
During a read operation, the SDO becomes active and the 8-bit contents of the register are driven out MSB first.
The SDO will be high impedance on either the falling edge of SCLK following the LSB, or the rising of CS as
specified by the SPIM bit (direct Register 0, bit 6). SDI is a “don’t care” during the data portion of read operations.
During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin will remain high
impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the
rising edge. The clock should return to a logic high when no transfer is in progress.
Indirect registers are accessed through direct registers 29 through 30. Instructions on how to access them is
described in “3. Control Registers” beginning on page 60.
There are a number of variations of usage on this four-wire interface:
Continuous Clocking: During continuous clocking, the data transfers are controlled by the assertion of the CS
pin. CS must assert before the falling edge of SCLK on which the first bit of data is expected during a read
cycle, and must remain low for the duration of the 8-‘bit transfer (command/address or data).
SDI/SDO Wired Operation: Independent of the clocking options described, SDI and SDO can be treated as
two separate lines or wired together if the master is capable of tristating its output during the data byte transfer
of a read operation.
Daisy Chain Mode: This mode allows communication with banks of up to eight ProSLIC devices using one
chip select signal. When the SPIDC bit in the SPI Mode Select register is set, data transfer mode changes to a
3-byte operation: a chip select byte, an address/control byte, and a data byte. Using the circuit shown in
Figure 28, a single device may select from the bank of devices by setting the appropriate chip select bit to 1.
Each device uses the LSB of the chip select byte, shifts the data right by one bit, and passes the chip select
byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered.
Rev. 1.61
53
Si3210/Si3211
Don't
Care
SCLK
CS
SDI
a6 a5 a4 a3 a2 a1 a0
d7 d6 d5 d4 d3 d2 d1 d0
0
SDO
High Impedance
Figure 26. Serial Write 8-Bit Mode
Don't
Care
SCLK
CS
SDI
Don't Care
a6 a5 a4 a3 a2 a1 a0
1
SDO
d7 d6 d5 d4 d3 d2 d1 d0
High Impedance
Figure 27. Serial Read 8-Bit Mode
54
Rev. 1.61
Si3210/Si3211
SDI0
SDO
CS
SDI
CS
CPU
SDO
SDI
SDITHRU
SDI1
SDI2
SDI
CS
SDO
SDITHRU
SDI
CS
SDO
SDITHRU
SDI3
SDI
CS
SDO
SDITHRU
Chip Select Byte
Address Byte
Data Byte
SCLK
SDI0
SDI1
SDI2
SDI3
C7 C6 C5 C4 C3 C2 C1 C0
– C7 C6 C5 C4 C3 C2 C1
R/W A6 A5 A4 A3 A2 A1 A0
R/W A6 A5 A4 A3 A2 A1 A0
R/W A6 A5 A4 A3 A2 A1 A0
R/W A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
–
–
–
–
C7 C6 C5 C4 C3 C2
–
C7 C6 C5 C4 C3
Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the
LSB of the chip select byte for its chip select.
Figure 28. SPI Daisy Chain Mode
Rev. 1.61
55
Si3210/Si3211
2.12. PCM Interface
The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM
samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as PCM Mode Select (direct
Register 1), PCM Transmit Start Count (direct registers 2 and 3), and PCM Receive Start Count (direct registers 4
and 5). The interface can be configured to support from 4 to 128 8-bit timeslots in each frame. This corresponds to
PCLK frequencies of 256 kHz to 8.192 MHz in power of 2 increments. (768 kHz and 1.536 MHz are also available,
but these frequencies are not valid for GCI mode.) Timeslots for data transmission and reception are independently
configured using the TXS and RXS registers. By setting the correct starting point of the data, the ProSLIC can be
configured to support long FSYNC and short FSYNC variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel time
slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit.
DTX will return to high impedance either on the negative edge of PCLK during the LSB or on the positive edge of
PCLK following the LSB. This is based on the setting of the TRI bit of the PCM Mode Select register. Tristating on
the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver
contention. In addition to 8-bit data modes, there is a 16-bit mode provided. This mode can be activated via the
PCMT bit of the PCM Mode Select register. GCI timing is also supported in which the duration of a data bit is two
PCLK cycles. This mode is also activated via the PCM Mode Select register. Setting the TXS or RXS register
greater than the number of PCLK cycles in a sample period will stop data transmission because TXS or RXS will
never equal the PCLK count. Figures 29–32 illustrate the usage of the PCM highway interface to adapt to common
PCM standards.
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PCLK_CNT
DRX
MSB
MSB
LSB
LSB
DTX
HI-Z
HI-Z
Figure 29. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
PCLK
FSYNC
PCLK_CNT
DRX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
MSB
MSB
LSB
LSB
DTX
HI-Z
HI-Z
Figure 30. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
56
Rev. 1.61
Si3210/Si3211
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PCLK_CNT
DRX
MSB
MSB
LSB
DTX
HI-Z
HI-Z
LSB
Figure 31. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PCLK_CNT
DRX
MSB
LSB
DTX
HI-Z
HI-Z
Figure 32. GCI Example, Timeslot 1 (TXS/RXS = 0)
2.13. Companding
The ProSLIC supports both µ-255 Law and A-Law companding formats in addition to linear data. These 8-bit
companding schemes follow a segmented curve formatted as sign bit, three chord bits, and four step bits. µ-255
Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is
selected via the PCMF register. Tables 34 and 35 define the µ-Law and A-Law encoding formats.
Rev. 1.61
57
Si3210/Si3211
Table 34. µ-Law Encode-Decode Characteristics1,2
Segment #Intervals X Interval Size Value at Segment Endpoints
Number
Digital Code
Decode Level
8031
8159
10000000b
.
.
.
8
16 X 256
4319
4063
10001111b
10011111b
10101111b
10111111b
11001111b
11011111b
11101111b
4191
2079
1023
495
231
99
.
.
.
7
6
5
4
3
2
16 X 128
16 X 64
16 X 32
16 X 16
16 X 8
2143
2015
.
.
.
1055
991
.
.
.
511
479
.
.
.
239
223
.
.
.
103
95
.
.
.
16 X 4
35
31
33
15 X 2
.
.
.
1
3
1
0
__________________
1 X 1
11111110b
11111111b
2
0
Notes:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
58
Rev. 1.61
Si3210/Si3211
Table 35. A-Law Encode-Decode Characteristics1,2
Segment
Number
#intervals X interval size Value at segment endpoints Digital Code
Decode Level
4096
3968
.
.
2176
2048
10101010b
10100101b
4032
7
16 X 128
2112
1056
528
264
132
66
.
.
.
6
5
4
3
2
16 X 64
16 X 32
16 X 16
16 X 8
1088
1024
10110101b
10000101b
10010101b
11100101b
11110101b
11010101b
.
.
.
544
512
.
.
.
272
256
.
.
.
136
128
.
.
.
16 X 4
68
64
32 X 2
.
.
.
2
0
1
1
Notes:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values.
2. Digital code includes inversion of all even numbered bits.
Rev. 1.61
59
Si3210/Si3211
3. Control Registers
Note: Any register not listed here is reserved and must not be written.
Table 36. Direct Register Summary
Register
Name
Bit 7
Bit 6
Bit 5
Setup
PNI[1:0]
PCME
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
2
SPI Mode Select
PCM Mode Select
SPIDC
PNI2
SPIM
RNI[3:0]
PCMF[1:0]
PCMT
GCI
TRI
PCM Transmit Start
Count—Low Byte
TXS[7:0]
3
4
5
6
PCM Transmit Start
Count—High Byte
TXS[9:8]
PCM Receive Start
Count—Low Byte
RXS[7:0]
PCM Receive Start
Count—High Byte
RXS[9:8]
1
1
1
1
1
Digital Input/Output
Control
DOUT
DIO2
DIO1
PD2
PD1
Audio
8
Audio Path Loopback
Control
ALM2
DLM
ALM1
9
Audio Gain Control
RXHP
TXHP
TXM
RXM
ATX[1:0]
TISE
ARX[1:0]
10
Two-Wire Impedance
Synthesis Control
CLC[1:0]
TISS[2:0]
11
Hybrid Control
HYBP[2:0]
Powerdown
PMON DCOF
ADCM ADCON DACM DACON
Interrupts
PMAP RGIP
HYBA[2:0]
2
14
15
Powerdown Control 1
Powerdown Control 2
MOF
BIASOF SLICOF
GMM
GMON
18
19
20
21
22
23
24
Interrupt Status 1
Interrupt Status 2
Interrupt Status 3
Interrupt Enable 1
Interrupt Enable 2
Interrupt Enable 3
Decode Status
PMIP
Q6AP
RGAP
Q3AP
O2IP
O2AP
Q1AP
CMCP
O2AE
Q1AE
CMCE
O1IP
LCIP
INDP
O1IE
LCIE
INDE
O1AP
RTIP
Q5AP
Q4AP
Q2AP
DTMFP
O1AE
RTIE
PMIE
Q6AE
PMAE
Q5AE
RGIE
Q4AE
RGAE
Q3AE
O2IE
Q2AE
DTMFE
VAL
DIG[3:0]
Indirect Register Access
Notes:
1. Si3211 only.
2. Si3210 only.
60
Rev. 1.61
Si3210/Si3211
Table 36. Direct Register Summary (Continued)
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
28
Indirect Data Access—
Low Byte
IDA[7:0]
29
Indirect Data Access—
High Byte
IDA[15:8]
IAA[7:0]
30
31
Indirect Address
Indirect Address Status
IAS
Oscillators
32
33
34
Oscillator 1 Control
Oscillator 2 Control
OSS1
OSS2
RSS
REL
OZ1
OZ2
O1TAE O1TIE
O2TAE O2TIE
O1E
O2E
ROE
O1SO[1:0]
O2SO[1:0]
RVO TSWS
Ringing Oscillator
Control
RDAC
RTAE
RTIE
35
36
37
38
39
40
41
42
43
44
Pulse Metering
Oscillator Control
PSTAT
PMAE
PMIE
PMOE
Oscillator 1 Active
Timer—Low Byte
OAT1[7:0]
OAT1[15:8]
OIT1[7:0]
OIT1[15:8]
OAT2[7:0]
OAT2[15:8]
OIT2[7:0]
OIT2[15:8]
PAT[7:0]
Oscillator 1 Active
Timer—High Byte
Oscillator 1 Inactive
Timer—Low Byte
Oscillator 1 Inactive
Timer—High Byte
Oscillator 2 Active
Timer—Low Byte
Oscillator 2 Active
Timer—High Byte
Oscillator 2 Inactive
Timer—Low Byte
Oscillator 2 Inactive
Timer—High Byte
Pulse Metering
Oscillator Active Timer—
Low Byte
45
46
Pulse Metering
Oscillator Active Timer—
High Byte
PAT[15:8]
PIT[7:0]
Pulse Metering
Oscillator Inactive
Timer—Low Byte
Notes:
1. Si3211 only.
2. Si3210 only.
Rev. 1.61
61
Si3210/Si3211
Table 36. Direct Register Summary (Continued)
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
47
Pulse Metering
PIT[15:8]
Oscillator Inactive
Timer—High Byte
48
49
50
51
52
Ringing Oscillator
Active Timer—Low Byte
RAT[7:0]
RAT[15:8]
RIT[7:0]
Ringing Oscillator
Active Timer—High Byte
Ringing Oscillator Inac-
tive Timer—Low Byte
Ringing Oscillator Inac-
tive Timer—High Byte
RIT[15:8]
FSK Data
FSKDAT
SLIC
63
Loop Closure Debounce
Interval for Automatic
Ringing
LCD[7:0]
64
65
Linefeed Control
LFS[2:0]
CBY
LF[2:0]
External Bipolar
SQH
ETBE
ETBO[1:0]
ETBA[1:0]
Transistor Control
2
2
1
2
66
67
Battery Feed Control
VOV
MNCM MNDIF SPDS
FVBAT
ABAT
BATSL TRACK
Automatic/Manual
Control
AORD
AOLD
RTP
AOPN
68
69
70
Loop Closure/Ring Trip
Detect Status
DBIRAW
LCR
Loop Closure Debounce
Interval
LCDI[6:0]
RTDI[6:0]
Ring Trip Detect
Debounce Interval
71
72
73
74
75
76
77
Loop Current Limit
ILIM[2:0]
On-Hook Line Voltage
Common Mode Voltage
High Battery Voltage
Low Battery Voltage
Power Monitor Pointer
VSGN
VOC[5:0]
VCM[5:0]
VBATH[5:0]
VBATL[5:0]
PWRMP[2:0]
Line Power Output
Monitor
PWROM[7:0]
78
Loop Voltage Sense
LVSP
LVS[5:0]
Notes:
1. Si3211 only.
2. Si3210 only.
62
Rev. 1.61
Si3210/Si3211
Table 36. Direct Register Summary (Continued)
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
79
80
81
82
83
84
Loop Current Sense
TIP Voltage Sense
LCSP
LCS[5:0]
VTIP[7:0]
RING Voltage Sense
Battery Voltage Sense 1
Battery Voltage Sense 2
VRING[7:0]
VBATS1[7:0]
VBATS2[7:0]
IQ1[7:0]
Transistor 1 Current
Sense
85
86
87
88
89
92
93
94
Transistor 2 Current
Sense
IQ2[7:0]
IQ3[7:0]
IQ4[7:0]
IQ5[7:0]
IQ6[7:0]
Transistor 3 Current
Sense
Transistor 4 Current
Sense
Transistor 5 Current
Sense
Transistor 6 Current
Sense
2
DC-DC Converter PWM
Period
DCN[7:0]
2
2
2
DC-DC Converter
Switching Delay
DCCAL
DCPOL
DCTOF[4:0]
2
DC-DC Converter
PWM Pulse Width
DCPW[7:0]
95
96
Reserved
Calibration Control/
Status Register 1
CAL
CALSP CALR
CALT
CALD
CALC
CALIL
CALM1 CALM2 CALDAC CALADC CALCM
97
98
Calibration Control/
Status Register 2
RING Gain Mismatch
Calibration Result
CALGMR[4:0]
CALGMT[4:0]
CALGD[4:0]
99
TIP Gain Mismatch
Calibration Result
100
Differential Loop
Current Gain
Calibration Result
101
Common Mode Loop
Current Gain
CALGC[4:0]
Calibration Result
Notes:
1. Si3211 only.
2. Si3210 only.
Rev. 1.61
63
Si3210/Si3211
Table 36. Direct Register Summary (Continued)
Register
Name
Current Limit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
102
CALGIL[3:0]
Calibration Result
103
Monitor ADC Offset
Calibration Result
CALMG1[3:0]
CALMG2[3:0]
DACN ADCP
104
105
Analog DAC/ADC Offset
DACP
ADCN
DAC Offset Calibration
Result
DACOF[7:0]
CMBAL[5:0]
CMDCPK[3:0]
106
107
Common Mode Balance
Calibration Result
DC Peak Current
Calibration Result
2
2
108
Enhancement Enable
ILIMEN FSKEN DCSU
ZSEXT SWDB
LCVE
DCFIL HYSTEN
Notes:
1. Si3211 only.
2. Si3210 only.
64
Rev. 1.61
Si3210/Si3211
Register 0. SPI Mode Select
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
SPIDC
R/W
SPIM
R/W
PNI[1:0]
R
RNI[3:0]
R
Reset settings = 00xx_xxxx
Bit
Name
Function
7
SPIDC
SPI Daisy Chain Mode Enable.
0 = Disable SPI daisy chain mode.
1 = Enable SPI daisy chain mode.
6
SPIM
SPI Mode.
0 = Causes SDO to tri-state on rising edge of SCLK of LSB.
1 = Normal operation; SDO tri-states on rising edge of CS.
5:4
PNI[1:0]
Part Number Identification.
00 = Si3210
01 = Si3211
10 = Unused
11 = Si3210M
3:0
RNI[3:0]
Revision Number Identification.
0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc.
Rev. 1.61
65
Si3210/Si3211
Register 1. PCM Mode Select
Bit
D7
D6
D5
D4
PCMF[1:0]
R/W
D3
D2
D1
D0
TRI
R/W
Name
Type
PNI2
PCME
R/W
PCMT
R/W
GCI
R/W
Reset settings = 0000_1000
Bit
Name
Function
7
PNI2
Part Number Identification 2.
0 = Si3210/11 family.
1 = Si3215/16 family.
6
5
Reserved
PCME
Read returns zero.
PCM Enable.
0 = Disable PCM transfers.
1 = Enable PCM transfers.
4:3
PCMF[1:0]
PCM Format.
00 = A-Law
01 = µ-Law
10 = Reserved
11 = Linear
2
1
0
PCMT
GCI
PCM Transfer Size.
0 = 8-bit transfer.
1 = 16-bit transfer.
GCI Clock Format.
0 = 1 PCLK per data bit.
1 = 2 PCLKs per data bit.
TRI
Tri-state Bit 0.
0 = Tri-state bit 0 on positive edge of PCLK.
1 = Tri-state bit 0 on negative edge of PCLK.
66
Rev. 1.61
Si3210/Si3211
Register 2. PCM Transmit Start Count—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TXS[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
TXS[7:0]
PCM Transmit Start Count.
PCM transmit start count equals the number of PCLKs following FSYNC before data trans-
mission begins. See Figure 29 on page 56.
Register 3. PCM Transmit Start Count—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TXS[9:8]
R/W
Reset settings = 0000_0000
Bit
7:2
1:0
Name
Function
Reserved
TXS[9:8]
Read returns zero.
PCM Transmit Start Count.
PCM transmit start count equals the number of PCLKs following FSYNC before data
transmission begins. See Figure 29 on page 56.
Register 4. PCM Receive Start Count—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RXS[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
RXS[7:0]
PCM Receive Start Count.
PCM receive start count equals the number of PCLKs following FSYNC before data
reception begins. See Figure 29 on page 56.
Rev. 1.61
67
Si3210/Si3211
Register 5. PCM Receive Start Count—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RXS[9:8]
R/W
Reset settings = 0000_0000
Bit
7:2
1:0
Name
Function
Reserved
RXS[9:8]
Read returns zero.
PCM Receive Start Count.
PCM receive start count equals the number of PCLKs following FSYNC before data
reception begins. See Figure 29 on page 56.
Register 6. Digital Input/Output Control
Si3210
D4
Bit
D7
D6
D5
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Si3211
D4
Bit
D7
D6
D5
D3
D2
D1
D0
Name
Type
DOUT
R/W
DIO2
R/W
DIO1
R/W
PD2
R/W
PD1
R/W
Reset settings = 0000_0000
68
Rev. 1.61
Si3210/Si3211
Bit
7:5
4
Name
Reserved
DOUT
Function
Read returns zero.
DOUT Pin Output Data (Si3211 only).
0 = DOUT pin driven low.
1 = DOUT pin driven high.
Si3210 = Reserved.
3
2
1
DIO2
DIO1
PD2
DIO2 Pin Input/Output Direction (Si3211 only).
0 = DIO2 pin is an input.
1 = DIO2 pin is an output and driven to value of the PD2 bit.
Si3210 = Reserved.
DIO1 Pin Input/Output Direction (Si3211 only).
0 = DIO1 pin is an input.
1 = DIO1 pin is an output and driven to value of the PD1 bit.
Si3210 = Reserved.
DIO2 Pin Data (Si3211 only).
When DIO2 = 1:
0 = DIO2 pin driven low.
1 = DIO2 pin driven high.
Si3210 = Reserved.
When DIO2 = 0, PD2 value equals the logic input of DIO2 pin.
0
PD1
DIO1 Pin Data (Si3211 only).
When DIO1 = 1:
0 = DIO1 pin driven low.
1 = DIO1 pin driven high.
Si3210 = Reserved.
When DIO1 = 0, PD1 value equals the logic input of DIO1 pin.
Rev. 1.61
69
Si3210/Si3211
Register 8. Audio Path Loopback Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
ALM2
R/W
DLM
R/W
ALM1
R/W
Reset settings = 0000_0010
Bit
7:3
2
Name
Reserved
ALM2
Function
Read returns zero.
Analog Loopback Mode 2. (See Figure 25 on page 50.)
0 = Full analog loopback mode disabled.
1 = Full analog loopback mode enabled.
1
0
DLM
Digital Loopback Mode. (See Figure 25 on page 50.)
0 = Digital loopback disabled.
1 = Digital loopback enabled.
ALM1
Analog Loopback Mode 1. (See Figure 25 on page 50.)
0 = Analog loopback disabled.
1 = Analog loopback enabled.
70
Rev. 1.61
Si3210/Si3211
Register 9. Audio Gain Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RXHP
R/W
TXHP
R/W
TXM
R/W
RXM
R/W
ATX[1:0]
R/W
ARX[1:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
RXHP
Receive Path High Pass Filter Disable.
0 = HPF enabled in receive path, RHPF.
1 = HPF bypassed in receive path, RHPF.
6
5
TXHP
TXM
Transmit Path High Pass Filter Disable.
0 = HPF enabled in transmit path, THPF.
1 = HPF bypassed in transmit path, THPF.
Transmit Path Mute.
Refer to position of digital mute in Figure 25 on page 50.
0 = Transmit signal passed.
1 = Transmit signal muted.
4
RXM
Receive Path Mute.
Refer to position of digital mute in Figure 25 on page 50.
0 = Receive signal passed.
1 = Receive signal muted.
3:2
ATX[1:0]
Analog Transmit Path Gain.
00 = 0 dB
01 = –3.5 dB
10 = 3.5 dB
11 = ATX gain = 0 dB; analog transmit path muted.
1:0
ARX[1:0]
Analog Receive Path Gain.
00 = 0 dB
01 = –3.5 dB
10 = 3.5 dB
11 = Analog receive path muted.
Rev. 1.61
71
Si3210/Si3211
Register 10. Two-Wire Impedance Synthesis Control
Bit
D7
D6
D5
D4
D3
D2
D1
TISS[2:0]
R/W
D0
Name
Type
CLC[1:0]
R/W
TISE
R/W
Reset settings = 0000_1000
Bit
7:6
5:4
Name
Function
Reserved
CLC[1:0]
Read returns zero.
Line Capacitance Compensation.
00 = Off
01 = 4.7 nF
10 = 10 nF
11 = Reserved
3
TISE
Two-Wire Impedance Synthesis Enable.
0 = Two-wire impedance synthesis disabled.
1 = Two-wire impedance synthesis enabled.
2:0
TISS[2:0]
Two-Wire Impedance Synthesis Selection.
000 = 600
001 = 900
010 = 600 + 2.16 µF
011 = 900 + 2.16 µF
100 = CTR21 (270 + 750 || 150 nF)
101 = Australia/New Zealand #1 (220 + 820 || 120 nF)
110 = Slovakia/Slovenia/South Africa (220 + 820 || 115 nF)
111 = New Zealand #2 (370 + 620 || 310 nF)
72
Rev. 1.61
Si3210/Si3211
Register 11. Hybrid Control
Bit
D7
D6
D5
HYBP[2:0]
R/W
D4
D3
D2
D1
HYBA[2:0]
R/W
D0
Name
Type
Reset settings = 0011_0011
Bit
7
Name
Function
Reserved
HYBP[2:0]
Read returns zero.
6:4
Pulse Metering Hybrid Adjustment.
000 = 4.08 dB
001 = 2.5 dB
010 = 1.16 dB
011 = 0 dB
100 = –1.02 dB
101 = –1.94 dB
110 = –2.77 dB
111 = Off
3
Reserved
HYBA[2:0]
Read returns zero.
2:0
Audio Hybrid Adjustment.
000 = 4.08 dB
001 = 2.5 dB
010 = 1.16 dB
011 = 0 dB
100 = –1.02 dB
101 = –1.94 dB
110 = –2.77 dB
111 = Off
Rev. 1.61
73
Si3210/Si3211
Register 14. Powerdown Control 1
Si3210
D4
Bit
D7
D6
D5
D3
D2
D1
BIASOF
R/W
D0
SLICOF
R/W
Name
Type
PMON
R/W
DCOF
R/W
MOF
R/W
Reset settings = 0001_0000
Si3211
D4
Bit
D7
D6
D5
D3
D2
D1
BIASOF
R/W
D0
SLICOF
R/W
Name
Type
PMON
R/W
MOF
R/W
Reset settings = 0001_0000
Bit
7:6
5
Name
Reserved
PMON
Function
Read returns zero.
Pulse Metering DAC Power-On Control.
0 = Automatic power control.
1 = Override automatic control and force pulse metering DAC circuitry on.
4
3
DCOF
MOF
DC-DC Converter Power-Off Control (Si3210 only).
0 = Automatic power control.
1 = Override automatic control and force dc-dc circuitry off.
Si3211 = Read returns 1; it cannot be written.
Monitor ADC Power-Off Control.
0 = Automatic power control.
1 = Override automatic control and force monitor ADC circuitry off.
2
1
Reserved
BIASOF
Read returns zero.
DC Bias Power-Off Control.
0 = Automatic power control.
1 = Override automatic control and force dc bias circuitry off.
0
SLICOF
SLIC Power-Off Control.
0 = Automatic power control.
1 = Override automatic control and force SLIC circuitry off.
74
Rev. 1.61
Si3210/Si3211
Register 15. Powerdown Control 2
Bit
D7
D6
D5
D4
ADCON
R/W
D3
D2
DACON
R/W
D1
D0
GMON
R/W
Name
Type
ADCM
R/W
DACM
R/W
GMM
R/W
Reset settings = 0000_0000
Bit
7:6
5
Name
Reserved
ADCM
Function
Read returns zero.
Analog to Digital Converter Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; ADCON controls on/off state.
4
ADCON
Analog to Digital Converter On/Off Power Control.
When ADCM = 1:
0 = Analog to digital converter powered off.
1 = Analog to digital converter powered on.
ADCON has no effect when ADCM = 0.
3
2
DACM
Digital to Analog Converter Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; DACON controls on/off state.
DACON
Digital to Analog Converter On/Off Power Control.
When DACM = 1:
0 = Digital to analog converter powered off.
1 = Digital to analog converter powered on.
DACON has no effect when DACM = 0.
1
0
GMM
Transconductance Amplifier Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; GMON controls on/off state.
GMON
Transconductance Amplifier On/Off Power Control.
When GMM = 1:
0 = Analog to digital converter powered off.
1 = Analog to digital converter powered on.
GMON has no effect when GMM = 0.
Rev. 1.61
75
Si3210/Si3211
Register 18. Interrupt Status 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PMIP
R/W
PMAP
R/W
RGIP
R/W
RGAP
R/W
O2IP
R/W
O2AP
R/W
O1IP
R/W
O1AP
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
PMIP
Pulse Metering Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
6
5
4
3
2
1
0
PMAP
RGIP
RGAP
O2IP
Pulse Metering Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Ringing Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Ringing Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Oscillator 2 Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
O2AP
O1IP
Oscillator 2 Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Oscillator 1 Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
O1AP
Oscillator 1 Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
76
Rev. 1.61
Si3210/Si3211
Register 19. Interrupt Status 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Q6AP
R/W
Q5AP
R/W
Q4AP
R/W
Q3AP
R/W
Q2AP
R/W
Q1AP
R/W
LCIP
R/W
RTIP
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
Q6AP
Power Alarm Q6 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
6
5
4
3
2
1
0
Q5AP
Q4AP
Q3AP
Q2AP
Q1AP
LCIP
Power Alarm Q5 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q4 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q3 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q2 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Power Alarm Q1 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Loop Closure Transition Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
RTIP
Ring Trip Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Rev. 1.61
77
Si3210/Si3211
Register 20. Interrupt Status 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
DTMFP
R/W
Name
Type
CMCP
R/W
INDP
R/W
Reset settings = 0000_0000
Bit
7:3
2
Name
Reserved
CMCP
Function
Read returns zero.
Common Mode Calibration Error Interrupt.
This bit is set when off-hook/on-hook status changes during the common mode balance
calibration. Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
1
0
INDP
Indirect Register Access Serviced Interrupt.
This bit is set once a pending indirect register service request has been completed. Writ-
ing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
DTMFP
DTMF Tone Detected Interrupt.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
78
Rev. 1.61
Si3210/Si3211
Register 21. Interrupt Enable 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PMIE
R/W
PMAE
R/W
RGIE
R/W
RGAE
R/W
O2IE
R/W
O2AE
R/W
O1IE
R/W
O1AE
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
PMIE
Pulse Metering Inactive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
6
5
4
3
2
1
0
PMAE
RGIE
RGAE
O2IE
Pulse Metering Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Ringing Inactive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Ringing Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Oscillator 2 Inactive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
O2AE
O1IE
Oscillator 2 Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Oscillator 1 Inactive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
O1AE
Oscillator 1 Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Rev. 1.61
79
Si3210/Si3211
Register 22. Interrupt Enable 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Q6AE
R/W
Q5AE
R/W
Q4AE
R/W
Q3AE
R/W
Q2AE
R/W
Q1AE
R/W
LCIE
R/W
RTIE
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
Q6AE
Power Alarm Q6 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
6
5
4
3
2
1
0
Q5AE
Q4AE
Q3AE
Q2AE
Q1AE
LCIE
Power Alarm Q5 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Power Alarm Q4 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Power Alarm Q3 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Power Alarm Q2 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Power Alarm Q1 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Loop Closure Transition Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
RTIE
Ring Trip Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
80
Rev. 1.61
Si3210/Si3211
Register 23. Interrupt Enable 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
DTMFE
R/W
Name
Type
CMCE
R/W
INDE
R/W
Reset settings = 0000_0000
Bit
7:3
2
Name
Reserved
CMCE
Function
Read returns zero.
Common Mode Calibration Error Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
1
0
INDE
Indirect Register Access Serviced Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
DTMFE
DTMF Tone Detected Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Rev. 1.61
81
Si3210/Si3211
Register 24. DTMF Decode Status
Bit
D7
D6
D5
D4
VAL
R
D3
D2
D1
D0
Name
Type
DIG[3:0]
R
Reset settings = 0000_0000
Bit
7:5
4
Name
Reserved
VAL
Function
Read returns zero.
DTMF Valid Digit Decoded.
0 = Not currently detecting digit.
1 = Currently detecting digit.
3:0
DIG[3:0]
DTMF Digit.
0001 = “1”
0010 = “2”
0011 = “3”
0100 = “4”
0101 = “5”
0110 = “6”
0111 = “7”
1000 = “8”
1001 = “9”
1010 = “0”
1011 = “*”
1100 = “#”
1101 = “A”
1110 = “B”
1111 = “C”
0000 = “D”
82
Rev. 1.61
Si3210/Si3211
Register 28. Indirect Data Access—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
IDA[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
IDA[7:0]
Indirect Data Access—Low Byte.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Register 29. Indirect Data Access—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
IDA[15:8]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
IDA[15:8]
Indirect Data Access—High Byte.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Rev. 1.61
83
Si3210/Si3211
Register 30. Indirect Address
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
IAA[7:0]
R/W
Reset settings = xxxx_xxxx
Bit
Name
Function
7:0
IAA[7:0]
Indirect Address Access.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Register 31. Indirect Address Status
Bit
D7
D6
D5
D4
D3
D2
D1
D0
IAS
R
Name
Type
Reset settings = 0000_0000
Bit
7:1
0
Name
Reserved
IAS
Function
Read returns zero.
Indirect Access Status.
0 = No indirect memory access pending.
1 = Indirect memory access pending.
84
Rev. 1.61
Si3210/Si3211
Register 32. Oscillator 1 Control
Bit
D7
OSS1
R
D6
D5
D4
O1TAE
R/W
D3
D2
D1
O1SO[1:0]
R/W
D0
Name
Type
REL
R/W
OZ1
R/W
O1TIE
R/W
O1E
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
OSS1
Oscillator 1 Signal Status.
0 = Output signal inactive.
1 = Output signal active.
6
REL
Oscillator 1 Automatic Register Reload.
This bit should be set for FSK signaling.
0 = Oscillator 1 will stop signaling after inactive timer expires.
1 = Oscillator 1 will continue to read register parameters and output signals.
5
4
OZ1
O1TAE
O1TIE
Oscillator 1 Zero Cross Enable.
0 = Signal terminates after active timer expires.
1 = Signal terminates at zero crossing after active timer expires.
Oscillator 1 Active Timer Enable.
0 = Disable timer.
1 = Enable timer.
3
Oscillator 1 Inactive Timer Enable.
0 = Disable timer.
1 = Enable timer.
2
O1E
Oscillator 1 Enable.
0 = Disable oscillator.
1 = Enable oscillator.
1:0
O1SO[1:0]
Oscillator 1 Signal Output Routing.
00 = Unassigned path (output not connected).
01 = Assign to transmit path.
10 = Assign to receive path.
11 = Assign to both paths.
Rev. 1.61
85
Si3210/Si3211
Register 33. Oscillator 2 Control
Bit
D7
OSS2
R
D6
D5
D4
O2TAE
R/W
D3
D2
D1
O2SO[1:0]
R/W
D0
Name
Type
OZ2
R/W
O2TIE
R/W
O2E
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
OSS2
Oscillator 2 Signal Status.
0 = Output signal inactive.
1 = Output signal active.
6
5
Reserved
OZ2
Read returns zero.
Oscillator 2 Zero Cross Enable.
0 = Signal terminates after active timer expires.
1 = Signal terminates at zero crossing.
4
3
O2TAE
O2TIE
Oscillator 2 Active Timer Enable.
0 = Disable timer.
1 = Enable timer.
Oscillator 2 Inactive Timer Enable.
0 = Disable timer.
1 = Enable timer.
2
O2E
Oscillator 2 Enable.
0 = Disable oscillator.
1 = Enable oscillator.
1:0
O2SO[1:0]
Oscillator 2 Signal Output Routing.
00 = Unassigned path (output not connected)
01 = Assign to transmit path.
10 = Assign to receive path.
11 = Assign to both paths.
86
Rev. 1.61
Si3210/Si3211
Register 34. Ringing Oscillator Control
Bit
D7
RSS
R
D6
D5
RDAC
R
D4
D3
D2
ROE
R
D1
D0
Name
Type
RTAE
R/W
RTIE
R/W
RVO
R/W
TSWS
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
RSS
Ringing Signal Status.
0 = Ringing oscillator output signal inactive.
1 = Ringing oscillator output signal active.
6
5
Reserved
RDAC
Read returns zero.
Ringing Signal DAC/Linefeed Cross Indicator.
For ringing signal start and stop, output to TIP and RING is suspended to ensure conti-
nuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at
TIP and RING.
0 = Ringing signal not present at TIP and RING.
1 = Ringing signal present at TIP and RING.
4
3
2
1
0
RTAE
RTIE
ROE
Ringing Active Timer Enable.
0 = Disable timer.
1 = Enable timer.
Ringing Inactive Timer Enable.
0 = Disable timer.
1 = Enable timer.
Ringing Oscillator Enable.
0 = Ringing oscillator disabled.
1 = Ringing oscillator enabled.
RVO
Ringing Voltage Offset.
0 = No dc offset added to ringing signal.
1 = DC offset added to ringing signal.
TSWS
Trapezoid/Sinusoid Waveshape Select.
0 = Sinusoid
1 = Trapezoid
Rev. 1.61
87
Si3210/Si3211
Register 35. Pulse Metering Oscillator Control
Bit
D7
PSTAT
R
D6
D5
D4
D3
D2
D1
D0
Name
Type
PMAE
R/W
PMIE
R/W
PMOE
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
PSTAT
Pulse Metering Signal Status.
0 = Output signal inactive.
1 = Output signal active.
6:5
4
Reserved
PMAE
Read returns zero.
Pulse Metering Active Timer Enable.
0 = Disable timer.
1 = Enable timer.
3
2
PMIE
PMOE
Pulse Metering Inactive Timer Enable.
0 = Disable timer.
1 = Enable timer.
Pulse Metering Oscillator Enable.
0 = Disable oscillator.
1 = Enable oscillator.
1:0
Reserved
Read returns zero.
Register 36. Oscillator 1 Active Timer—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
OAT1[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
OAT1[7:0]
Oscillator 1 Active Timer.
LSB = 125 µs
88
Rev. 1.61
Si3210/Si3211
Register 37. Oscillator 1 Active Timer—High Byte
Bit
D7
D6
D5
D4
OAT1[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0
OAT1[15:8]
Oscillator 1 Active Timer.
Register 38. Oscillator 1 Inactive Timer—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
OIT1[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
OIT1[7:0]
Oscillator 1 Inactive Timer.
LSB = 125 µs
Register 39. Oscillator 1 Inactive Timer—High Byte
Bit
D7
D6
D5
D4
OIT1[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0
OIT1[15:8]
Oscillator 1 Inactive Timer.
Rev. 1.61
89
Si3210/Si3211
Register 40. Oscillator 2 Active Timer—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
OAT2[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
OAT2[7:0]
Oscillator 2 Active Timer.
LSB = 125 µs
Register 41. Oscillator 2 Active Timer—High Byte
Bit
D7
D6
D5
D4
OAT2[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0
OAT2[15:8]
Oscillator 2 Active Timer.
Register 42. Oscillator 2 Inactive Timer—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
OIT2[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
OIT2[7:0]
Oscillator 2 Inactive Timer.
LSB = 125 µs
90
Rev. 1.61
Si3210/Si3211
Register 43. Oscillator 2 Inactive Timer—High Byte
Bit
D7
D6
D5
D4
OIT2[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0
OIT2[15:8]
Oscillator 2 Inactive Timer.
Register 44. Pulse Metering Oscillator Active Timer—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PAT[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
PAT[7:0]
Pulse Metering Active Timer.
LSB = 125 µs
Register 45. Pulse Metering Oscillator Active Timer—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PAT[15:8]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
PAT[15:8]
Pulse Metering Active Timer.
Rev. 1.61
91
Si3210/Si3211
Register 46. Pulse Metering Oscillator Inactive Timer—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PIT[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
PIT[7:0]
Pulse Metering Inactive Timer.
LSB = 125 µs
Register 47. Pulse Metering Oscillator Inactive Timer—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PIT[15:8]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
PIT[15:8]
Pulse Metering Inactive Timer.
Register 48. Ringing Oscillator Active Timer—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RAT[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
RAT[7:0]
Ringing Active Timer.
LSB = 125 µs
92
Rev. 1.61
Si3210/Si3211
Register 49. Ringing Oscillator Active Timer—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RAT[15:8]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
RAT[15:8]
Ringing Active Timer.
Register 50. Ringing Oscillator Inactive Timer—Low Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RIT[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
RIT[7:0]
Ringing Inactive Timer.
LSB = 125 µs
Register 51. Ringing Oscillator Inactive Timer—High Byte
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RIT[15:8]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
RIT[15:8]
Ringing Inactive Timer.
Rev. 1.61
93
Si3210/Si3211
Register 52. FSK Data
Bit
D7
D6
D5
D4
D3
D2
D1
D0
FSKDAT
R/W
Name
Type
Reset settings = 0000_0000
Bit
7:1
0
Name
Function
Reserved
FSKDAT
Read returns zero.
FSK Data.
When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this
bit serves as the buffered input for FSK generation bit stream data.
Register 63. Loop Closure Debounce Interval
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
LCD[7:0]
Reset settings = 0011_0010 (revision C); 0101_0100 (subsequent revisions)
Bit
Name
Function
Loop Closure Debounce Interval for Automatic Ringing.
7:0
LCD[7:0]
This register sets the loop closure debounce interval for the ringing silent period when
using automatic ringing cadences. The value may be set between 0 ms (0x00) and
159 ms (0x7F) in 1.25 ms steps.
94
Rev. 1.61
Si3210/Si3211
Register 64. Linefeed Control
Bit
D7
D6
D5
LFS[2:0]
R
D4
D3
D2
D1
D0
Name
Type
LF[2:0]
R/W
Reset settings = 0000_0000
Bit
7
Name
Reserved
LFS[2:0]
Function
Read returns zero.
Linefeed Shadow.
6:4
This register reflects the actual real-time linefeed state. Automatic operations may cause
actual linefeed state to deviate from the state defined by linefeed register (e.g., when
linefeed equals ringing state, LFS will equal on-hook transmission state during ringing
silent period and ringing state during ring burst).
000 = Open
001 = Forward active
010 = Forward on-hook transmission
011 = TIP open
100 = Ringing
101 = Reverse active
110 = Reverse on-hook transmission
111 = RING open
3
Reserved
LF[2:0]
Read returns zero.
2:0
Linefeed.
Writing to this register sets the linefeed state.
000 = Open
001 = Forward active
010 = Forward on-hook transmission
011 = TIP open
100 = Ringing
101 = Reverse active
110 = Reverse on-hook transmission
111 = RING open
Rev. 1.61
95
Si3210/Si3211
Register 65. External Bipolar Transistor Control
Bit
D7
D6
D5
D4
D3
ETBO[1:0]
R/W
D2
D1
D0
Name
Type
SQH
R/W
CBY
R/W
ETBE
R/W
ETBA[1:0]
R/W
Reset settings = 0110_0001
Bit
7
Name
Reserved
SQH
Function
Read returns zero.
6
Audio Squelch.
0 = No squelch.
1 = STIPAC and SRINGAC pins squelched.
5
4
CBY
ETBE
Capacitor Bypass.
0 = Capacitors CP (C1) and CM (C2) in circuit.
1 = Capacitors CP (C1) and CM (C2) bypassed.
External Transistor Bias Enable.
0 = Bias disabled.
1 = Bias enabled.
3:2
ETBO[1:0]
External Transistor Bias Levels—On-Hook Transmission State.
DC bias current which flows through external BJTs in the on-hook transmission state.
Increasing this value increases the compliance of the ac longitudinal balance circuit.
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = Reserved
1:0
ETBA[1:0]
External Transistor Bias Levels—Active Off-Hook State.
DC bias current which flows through external BJTs in the active off-hook state. Increasing
this value increases the compliance of the ac longitudinal balance circuit.
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = Reserved
96
Rev. 1.61
Si3210/Si3211
Register 66. Battery Feed Control
Si3210
D4
Bit
D7
D6
D5
D3
D2
D1
D0
TRACK
R/W
Name
Type
VOV
R/W
FVBAT
R/W
Reset settings = 0000_0011
Si3211
D4
Bit
D7
D6
D5
D3
D2
D1
D0
Name
Type
BATSL
R/W
Reset settings = 0000_0110
Bit
7:5
4
Name
Reserved
VOV
Function
Read returns zero.
Overhead Voltage Range Increase. (Si3210 only; See Figure 19 on page 39.)
This bit selects the programmable range for V , which is defined in indirect Register 41.
OV
0 = V = 0 V to 9 V
OV
1 = V = 0 V to 13.5 V
OV
Si3211 = Reserved.
3
FVBAT
V
Manual Setting (Si3210 only).
BAT
0 = Normal operation
1 = V tracks V
register.
BATH
BAT
Si3211 = Read returns 0; it cannot be written.
2
1
Reserved
BATSL
Si3210 = Read returns zero.
Si3211 = Read returns one.
Battery Feed Select (Si3211 only).
This bit selects between high and low battery supplies.
0 = Low battery selected (DCSW pin low).
1 = High battery selected (DCSW pin high).
Si3210 = Read returns zero.
0
TRACK
DC-DC Converter Tracking Mode (Si3210 only).
0 = |V
| will not decrease below VBATL.
BAT
1 = V
tracks V
.
RING
BAT
Si3211 = Reserved.
Rev. 1.61
97
Si3210/Si3211
Register 67. Automatic/Manual Control
Bit
D7
D6
MNCM
R/W
D5
MNDIF
R/W
D4
D3
D2
D1
D0
Name
Type
SPDS
R/W
ABAT
R/W
AORD
R/W
AOLD
R/W
AOPN
R/W
Reset settings = 0001_1111
Bit
7
Name
Reserved
MNCM
Function
Read returns zero.
6
Common Mode Manual/Automatic Select.
0 = Automatic control.
1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow
VCM value.
5
4
3
2
1
0
MNDIF
SPDS
ABAT
Differential Mode Manual/Automatic Select.
0 = Automatic control.
1 = Manual control (forces differential voltage to follow VOC value).
Speed-Up Mode Enable.
0 = Speed-up disabled.
1 = Automatic speed-up.
Battery Feed Automatic/Manual Select (Si3211 only).
0 = Automatic mode disabled.
1 = Automatic mode enabled (automatic switching to low battery in off-hook state).
AORD
AOLD
AOPN
Automatic/Manual Ring Trip Detect.
0 = Manual mode.
1 = Enter off-hook active state automatically upon ring trip detect.
Automatic/Manual Loop Closure Detect.
0 = Manual mode.
1 = Enter off-hook active state automatically upon loop closure detect.
Power Alarm Automatic/Manual Detect.
0 = Manual mode.
1 = Enter open state automatically upon power alarm.
98
Rev. 1.61
Si3210/Si3211
Register 68. Loop Closure/Ring Trip Detect Status
Bit
D7
D6
D5
D4
D3
D2
DBIRAW
R
D1
RTP
R
D0
LCR
R
Name
Type
Reset settings = 0000_0100
Bit
7:3
2
Name
Function
Reserved
DBIRAW
Read returns zero.
Ring Trip/Loop Closure Unfiltered Output.
State of this bit reflects the real-time output of ring trip and loop closure detect circuits
before debouncing.
0 = Ring trip/loop closure threshold exceeded.
1 = Ring trip/loop closure threshold not exceeded.
1
0
RTP
LCR
Ring Trip Detect Indicator (Filtered Output).
0 = Ring trip detect has not occurred.
1 = Ring trip detect occurred.
Loop Closure Detect Indicator (Filtered Output).
0 = Loop closure detect has not occurred.
1 = Loop closure detect has occurred.
Register 69. Loop Closure Debounce Interval
Bit
D7
D6
D5
D4
D3
LCDI[6:0]
R/W
D2
D1
D0
Name
Type
Reset settings = 0000_1010
Bit
7
Name
Function
Reserved
LCDI[6:0]
Read returns zero.
6:0
Loop Closure Debounce Interval.
The value written to this register defines the minimum steady state debounce time. Value
may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default
value = 12.5 ms.
Rev. 1.61
99
Si3210/Si3211
Register 70. Ring Trip Detect Debounce Interval
Bit
D7
D6
D5
D4
D3
RTDI[6:0]
R/W
D2
D1
D0
Name
Type
Reset settings = 0000_1010
Bit
7
Name
Function
Reserved
RTDI[6:0]
Read returns zero.
6:0
Ring Trip Detect Debounce Interval.
The value written to this register defines the minimum steady state debounce time. The
value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default
value = 12.5 ms.
Register 71. Loop Current Limit
Bit
D7
D6
D5
D4
D3
D2
D1
ILIM[2:0]
R/W
D0
Name
Type
Reset settings = 0000_0000
Bit
7:3
2:0
Name
Function
Reserved
ILIM[2:0]
Read returns zero.
Loop Current Limit.
The value written to this register sets the constant loop current. The value may be set
between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps.
100
Rev. 1.61
Si3210/Si3211
Register 72. On-Hook Line Voltage
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
VSGN
R/W
VOC[5:0]
R/W
Reset settings = 0010_0000
Bit
7
Name
Reserved
VSGN
Function
Read returns zero.
6
On-Hook Line Voltage.
The value written to this bit sets the on-hook line voltage polarity (V –V
).
RING
TIP
0 = V –V
is positive
is negative
TIP
RING
RING
1 = V –V
TIP
5:0
VOC[5:0]
On-Hook Line Voltage.
The value written to this register sets the on-hook line voltage (V –V
). Value may
RING
TIP
be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V.
Register 73. Common Mode Voltage
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
VCM[5:0]
R/W
Reset settings = 0000_0010
Bit
7:6
5:0
Name
Function
Reserved
VCM[5:0]
Read returns zero.
Common Mode Voltage.
The value written to this register sets V
for forward active and forward on-hook trans-
TIP
mission states and V
for reverse active and reverse on-hook transmission states.
RING
The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default
value = –3 V.
Rev. 1.61
101
Si3210/Si3211
Register 74. High Battery Voltage
Bit
D7
D6
D5
D4
D3
VBATH[5:0]
R/W
D2
D1
D0
Name
Type
Reset settings = 0011_0010
Bit
7:6
5:0
Name
Function
Reserved
VBATH[5:0]
Read returns zero.
High Battery Voltage.
The value written to this register sets high battery voltage. V
must be greater than or
BATH
equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V
steps. Default value = –75 V. For Si3211, V must be set equal to the voltage supplied
BATL
at the V
node shown in the Si3211 typical application circuit drawings, Figure 12 on
BATL
page 22 and Figure 14 on page 26.
Register 75. Low Battery Voltage
Bit
D7
D6
D5
D4
D3
VBATL[5:0]
R/W
D2
D1
D0
Name
Type
Reset settings = 0001_0000
Bit
7:6
5:0
Name
Function
Reserved
VBATL[5:0]
Read returns zero.
Low Battery Voltage.
The value written to this register sets low battery voltage. V
must be greater than or
BATH
equal to V
. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V
BATL
steps. Default value = –24 V. For Si3211, V
must be set equal to the voltage supplied
BATL
at the V
node shown in the Si3211 typical application circuit drawings, Figure 12 on
BATL
page 22 and Figure 14 on page 26.
102
Rev. 1.61
Si3210/Si3211
Register 76. Power Monitor Pointer
Bit
D7
D6
D5
D4
D3
D2
D1
PWRMP[2:0]
R/W
D0
Name
Type
Reset settings = 0000_0000
Bit
7:3
2:0
Name
Function
Reserved
Read returns zero.
PWRMP[2:0] Power Monitor Pointer.
Selects the external transistor from which to read power output. The power of the
selected transistor is read in the PWROM register.
000 = Q1
001 = Q2
010 = Q3
011 = Q4
100 = Q5
101 = Q6
110 = Undefined
111 = Undefined
Register 77. Line Power Output Monitor
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PWROM[7:0]
R
Reset settings = 0000_0000
Bit
Name
PWROM[7:0] Line Power Output Monitor.
Function
7:0
This register reports the real-time power output of the transistor selected using PWRMP.
The range is 0 W (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6.
The range is 0 W (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4.
Rev. 1.61
103
Si3210/Si3211
Register 78. Loop Voltage Sense
Bit
D7
D6
LVSP
R
D5
D4
D3
D2
D1
D0
Name
Type
LVS[5:0]
R
Reset settings = 0000_0000
Bit
7
Name
Reserved
LVSP
Function
Read returns zero.
6
Loop Voltage Sense Polarity.
This register reports the polarity of the differential loop voltage (V
– V
).
TIP
RING
0 = Positive loop voltage (V
> V
).
RING
TIP
1 = Negative loop voltage (V
< V
).
RING
TIP
5:0
LVS[5:0]
Loop Voltage Sense Magnitude.
This register reports the magnitude of the differential loop voltage (V –V
). The
TIP
RING
range is 0 V to 94.5 V in 1.5 V steps.
Register 79. Loop Current Sense
Bit
D7
D6
LCSP
R
D5
D4
D3
D2
D1
D0
Name
Type
LCS[5:0]
R
Reset settings = 0000_0000
Bit
7
Name
Reserved
LCSP
Function
Read returns zero.
6
Loop Current Sense Polarity.
This register reports the polarity of the loop current.
0 = Positive loop current (forward direction).
1 = Negative loop current (reverse direction).
5:0
LCS[5:0]
Loop Current Sense Magnitude.
This register reports the magnitude of the loop current. The range is 0 mA to 78.75 mA in
1.25 mA steps.
104
Rev. 1.61
Si3210/Si3211
Register 80. TIP Voltage Sense
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
VTIP[7:0]
R
Reset settings = 0000_0000
Bit
Name
Function
7:0
VTIP[7:0]
TIP Voltage Sense.
This register reports the real-time voltage at TIP with respect to ground. The range is 0 V
(0x00) to –95.88 V (0xFF) in .376 V steps.
Register 81. RING Voltage Sense
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
VRING[7:0]
R
Reset settings = 0000_0000
Bit
Name
Function
7:0
VRING[7:0]
RING Voltage Sense.
This register reports the real-time voltage at RING with respect to ground. The range is
0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
Register 82. Battery Voltage Sense 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
VBATS1[7:0]
R
Reset settings = 0000_0000
Bit
Name
VBATS1[7:0] Battery Voltage Sense 1.
Function
7:0
This register is one of two registers that reports the real-time voltage at V
to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
with respect
BAT
Rev. 1.61
105
Si3210/Si3211
Register 83. Battery Voltage Sense 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
VBATS2[7:0]
R
Reset settings = 0000_0000
Bit
Name
VBATS2[7:0] Battery Voltage Sense 2.
Function
7:0
This register is one of two registers that reports the real-time voltage at V
to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
with respect
BAT
Register 84. Transistor 1 Current Sense
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
IQ1[7:0]
R
Reset settings = xxxx_xxxx
Bit
Name
Function
7:0
IQ1[7:0]
Transistor 1 Current Sense.
This register reports the real-time current through Q1. The range is 0 A (0x00) to
81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the
additional ETBO/A current.
Register 85. Transistor 2 Current Sense
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
IQ2[7:0]
R
Reset settings = xxxx_xxxx
Bit
Name
Function
7:0
IQ2[7:0]
Transistor 2 Current Sense.
This register reports the real-time current through Q2. The range is 0 A (0x00) to
81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the
additional ETBO/A current.
106
Rev. 1.61
Si3210/Si3211
Register 86. Transistor 3 Current Sense
Bit
D7
D6
D5
D4
D3
D2
D1
D0
D0
D0
Name
Type
IQ3[7:0]
R
Reset settings = xxxx_xxxx
Bit
Name
Function
7:0
IQ3[7:0]
Transistor 3 Current Sense.
This register reports the real-time current through Q3. The range is 0 A (0x00) to
9.59 mA (0xFF) in 37.6 µA steps.
Register 87. Transistor 4 Current Sense
Bit
D7
D6
D5
D4
D3
D2
D1
Name
Type
IQ4[7:0]
R
Reset settings = xxxx_xxxx
Bit
Name
Function
7:0
IQ4[7:0]
Transistor 4 Current Sense.
This register reports the real-time current through Q4. The range is 0 A (0x00) to
9.59 mA (0xFF) in 37.6 µA steps.
Register 88. Transistor 5 Current Sense
Bit
D7
D6
D5
D4
D3
D2
D1
Name
Type
IQ5[7:0]
R
Reset settings = xxxx_xxxx
Bit
Name
Function
7:0
IQ5[7:0]
Transistor 5 Current Sense.
This register reports the real-time current through Q5. The range is 0 A (0x00) to
80.58 mA (0xFF) in .316 mA steps.
Rev. 1.61
107
Si3210/Si3211
Register 89. Transistor 6 Current Sense
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
IQ6[7:0]
R
Reset settings = xxxx_xxxx
Bit
Name
Function
7:0
IQ6[7:0]
Transistor 6 Current Sense.
This register reports the real-time current through Q6. The range is 0 A (0x00) to
80.58 mA (0xFF) in .316 mA steps.
Register 92. DC-DC Converter PWM Period
Si3210
D4
Bit
D7
DCN[7]
R/W
D6
1
D5
D3
D2
D1
D0
Name
Type
DCN[5:0]
R/W
R
Reset settings = 1111_1111
Si3211
D4
Bit
D7
D6
D5
D3
D2
D1
D0
Name
Type
Reset settings = xxxx_xxxx
Bit
Name
Function
7:0
DCN[7:0]
DC-DC Converter Period.
This bit sets the PWM period for the dc-dc converter. The range is 3.906 µs (0x40) to
15.564 µs (0xFF) in 61.035 ns steps.
Si3211 = Reserved.
Bit 6 is fixed to one and read-only, so there are two ranges of operation:
3.906 µs–7.751 µs, used for MOSFET transistor switching.
11.719 µs–15.564 µs, used for BJT transistor switching.
108
Rev. 1.61
Si3210/Si3211
Register 93. DC-DC Converter Switching Delay
Si3210
D4
Bit
D7
DCCAL
R/W
D6
D5
DCPOL
R
D3
D2
DCTOF[4:0]
R/W
D1
D0
Name
Type
Reset settings = 0001_0100 (Si3210)
Reset settings = 0011_0100 (Si3210M)
Si3211
D4
Bit
D7
D6
D5
D3
D2
D1
D0
Name
Type
Reset settings = xxxx_xxxx
Bit
Name
Function
7
DCCAL
DC-DC Converter Peak Current Monitor Calibration Status (Si3210 only).
Writing a one to this bit starts the dc-dc converter peak current monitor calibration rou-
tine.
0 = Normal operation.
1 = Calibration being performed.
Si3211 = Reserved.
6
5
Reserved
DCPOL
Read returns zero.
DC-DC Converter Feed Forward Pin (DCFF) Polarity (Si3210 only).
This read-only register bit indicates the polarity relationship of the DCFF pin to the
DCDRV pin. Two versions of the Si3210 are offered to support the two relationships.
0 = DCFF pin polarity is opposite of DCDRV pin (Si3210).
1 = DCFF pin polarity is same as DCDRV pin (Si3210M).
Si3211 = Reserved.
4:0
DCTOF[4:0]
DC-DC Converter Minimum Off Time (Si3210 only).
This register sets the minimum off time for the pulse width modulated dc-dc
converter control. T
= (DCTOF + 4) 61.035 ns.
OFF
Si3211 = Reserved.
Rev. 1.61
109
Si3210/Si3211
Register 94. DC-DC Converter PWM Pulse Width
Si3210
D4
Bit
D7
D6
D5
D3
D2
D1
D0
Name
Type
DCPW[7:0]
R
Reset settings = 0000_0000
Si3211
D4
Bit
D7
D6
D5
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0
DCPW[7:0]
DC-DC Converter Pulse Width (Si3210 only).
Pulse width of DCDRV is given by PW = (DCPW – DCTOF – 4)
Si3211 = Reserved.
61.035 ns.
110
Rev. 1.61
Si3210/Si3211
Register 96. Calibration Control/Status Register 1
Bit
D7
D6
D5
CALSP
R/W
D4
D3
D2
D1
D0
Name
Type
CAL
R/W
CALR
R/W
CALT
R/W
CALD
R/W
CALC
R/W
CALIL
R/W
Reset settings = 0001_1111
Bit
7
Name
Reserved
CAL
Function
Read returns zero.
Calibration Control/Status Bit.
6
Setting this bit begins calibration of the entire system.
0 = Normal operation or calibration complete.
1 = Calibration in progress.
5
4
3
CALSP
CALR
CALT
Calibration Speedup.
Setting this bit shortens the time allotted for V
calibration cycle.
0 = 300 ms
1 = 30 ms
settling at the beginning of the
BAT
RING Gain Mismatch Calibration.
For use with discrete solution only. When using the Si3201, consult “AN35: Si321x
User’s Quick Reference Guide” and follow instructions for manual calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
TIP Gain Mismatch Calibration.
For use with discrete solution only. When using the Si3201, consult “AN35: Si321x
User’s Quick Reference Guide” and follow instructions for manual calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
2
1
0
CALD
CALC
CALIL
Differential DAC Gain Calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
Common Mode DAC Gain Calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
I
Calibration.
LIM
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
Rev. 1.61
111
Si3210/Si3211
Register 97. Calibration Control/Status Register 2
Bit
D7
D6
D5
D4
CALM1
R/W
D3
CALM2
R/W
D2
CALDAC
R/W
D1
CALADC
R/W
D0
CALCM
R/W
Name
Type
Reset settings = 0001_1111
Bit
7:5
4
Name
Reserved
CALM1
Function
Read returns zero.
Monitor ADC Calibration 1.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
3
2
CALM2
Monitor ADC Calibration 2.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
CALDAC
DAC Calibration.
Setting this bit begins calibration of the audio DAC offset.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
1
0
CALADC
CALCM
ADC Calibration.
Setting this bit begins calibration of the audio ADC offset.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
Common Mode Balance Calibration.
Setting this bit begins calibration of the ac longitudinal balance.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
Register 98. RING Gain Mismatch Calibration Result
Bit
D7
D6
D5
D4
D3
D2
CALGMR[4:0]
R/W
D1
D0
Name
Type
Reset settings = 0001_0000
Bit
7:5
4:0
Name
Function
Reserved
Read returns zero.
CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current.
112
Rev. 1.61
Si3210/Si3211
Register 99. TIP Gain Mismatch Calibration Result
Bit
D7
D6
D5
D4
D3
D2
CALGMT[4:0]
R/W
D1
D1
D1
D0
D0
D0
Name
Type
Reset settings = 0001_0000
Bit
7:5
4:0
Name
Function
Reserved
Read returns zero.
CALGMT[4:0] Gain Mismatch of IE Tracking Loop for TIP Current.
Register 100. Differential Loop Current Gain Calibration Result
Bit
D7
D6
D5
D4
D3
D2
CALGD[4:0]
R/W
Name
Type
Reset settings = 0001_0001
Bit
7:5
4:0
Name
Function
Reserved
CALGD[4:0]
Read returns zero.
Differential DAC Gain Calibration Result.
Register 101. Common Mode Loop Current Gain Calibration Result
Bit
D7
D6
D5
D4
D3
D2
CALGC[4:0]
R/W
Name
Type
Reset settings = 0001_0001
Bit
7:5
4:0
Name
Function
Reserved
CALGC[4:0]
Read returns zero.
Common Mode DAC Gain Calibration Result.
Rev. 1.61
113
Si3210/Si3211
Register 102. Current Limit Calibration Result
Bit
D7
D6
D5
D4
D3
D2
CALGIL[3:0]
R/W
D1
D0
Name
Type
Reset settings = 0000_1000
Bit
7:5
3:0
Name
Function
Reserved
CALGIL[3:0]
Read returns zero.
Current Limit Calibration Result.
Register 103. Monitor ADC Offset Calibration Result
Bit
D7
D6
CALMG1[3:0]
R/W
D5
D4
D3
D2
D1
D0
Name
Type
CALMG2[3:0]
R/W
Reset settings = 1000_1000
Bit
7:4
3:0
Name
Function
CALMG1[3:0] Monitor ADC Offset Calibration Result 1.
CALMG2[3:0] Monitor ADC Offset Calibration Result 2.
Register 104. Analog DAC/ADC Offset
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
DACP
R/W
DACN
R/W
ADCP
R/W
ADCN
R/W
Reset settings = 0000_0000
Bit
7:4
3
Name
Reserved
DACP
Function
Read returns zero.
Positive Analog DAC Offset.
Negative Analog DAC Offset.
Positive Analog ADC Offset.
Negative Analog ADC Offset.
2
DACN
1
ADCP
0
ADCN
114
Rev. 1.61
Si3210/Si3211
Register 105. DAC Offset Calibration Result
Bit
D7
D6
D5
D4
DACOF[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0
DACOF[7:0]
DAC Offset Calibration Result.
Register 106. Common Mode Balance Calibration Result
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CMBAL[5:0]
Reset settings = 0010_0000
Bit
7:6
5:0
Name
Function
Reserved
CMBAL[5:0]
Read returns zero.
Common Mode Balance Calibration Result.
Register 107. DC Peak Current Monitor Calibration Result
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CMDCPK[3:0]
R/W
Reset settings = 0000_1000
Bit
7:4
3:0
Name
Function
Reserved
Read returns zero.
CMDCPK[3:0] DC Peak Current Monitor Calibration Result.
Rev. 1.61
115
Si3210/Si3211
Register 108. Enhancement Enable
Note: The Enhancement Enable register and associated features are available in silicon revisions C and later.
Si3210
Bit
D7
ILIMEN
R/W
D6
FSKEN
R/W
D5
D4
ZSEXT
R/W
D3
D2
D1
D0
HYSTEN
R/W
Name
Type
DCSU
R/W
LCVE
R/W
DCFIL
R/W
Reset settings = 0000_0000
Si3211
Bit
D7
ILIMEN
R/W
D6
FSKEN
R/W
D5
D4
D3
D2
D1
D0
HYSTEN
R/W
Name
Type
ZSEXT
R/W
SWDB
R/W
LCVE
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
ILIMEN
Current Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
6
FSKEN
FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 99–104). Audio tones are generated using
this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-
olution of 41.67 µs. This provides greater resolution during FSK caller ID signal genera-
tion.
0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 8 kHz.
5
DCSU
DC-DC Converter Control Speedup (Si3210 only).
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
116
Rev. 1.61
Si3210/Si3211
Bit
Name
Function
4
ZSEXT
Impedance Internal Reference Resistor Disable.
When enabled, this bit removes the internal reference resistor used to synthesize ac
impedances for 600 + 2.1 µF and 900 + 2.16 µF so that an external resistor reference
may be used.
0 = Internal resistor used to generate 600 + 2.1 µF and 900 + 2.16 µF impedances.
1 = Internal resistor removed from circuit.
3
SWDB
Battery Switch Debounce (Si3211 only).
When enabled, this bit allows debouncing of the battery switching circuit only when tran-
sitioning from V
to V
external battery supplies (EXTBAT = 1).
BATH
BATL
0 = No debounce used.
1 = 60 ms debounce period used.
Si3210 = Reserved.
2
1
0
LCVE
DCFIL
Voltage-Based Loop Closure.
Enables loop closure to be determined by the TIP-to-RING voltage rather than loop cur-
rent.
0 = Loop closure determined by loop current.
1 = Loop closure determined by TIP-to-RING voltage.
DC-DC Converter Squelch (Si3210 only).
When enabled, this bit squelches noise in the audio band from the dc-dc converter con-
trol loop.
0 = Voice band squelch disabled.
1 = Voice band squelch enabled.
HYSTEN
Loop Closure Hysteresis Enable.
When enabled, this bit allows hysteresis to the loop closure calculation. The upper and
lower hysteresis thresholds are defined by indirect registers 28 and 43, respectively.
0 = Loop closure hysteresis disabled.
1 = Loop closure hysteresis enabled.
Rev. 1.61
117
Si3210/Si3211
4. Indirect Registers
Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A
write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the
contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update.
A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the
value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of
16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition, an
interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.
4.1. DTMF Decoding
All values are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state.
Table 37. DTMF Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
ROW0[15:0]
ROW1[15:0]
ROW2[15:0]
ROW3[15:0]
COL[15:0]
2
3
4
5
FWDTW[15:0]
REVTW[15:0]
ROWREL[15:0]
COLREL[15:0]
ROW2[15:0]
COL2[15:0]
6
7
8
9
10
11
12
PWRMIN[15:0]
HOTL[15:0]
118
Rev. 1.61
Si3210/Si3211
Table 38. DTMF Indirect Registers Description
Description
Addr.
Reference
Page
0
DTMF Row 0 Peak Magnitude Pass Ratio Threshold.
49
This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of
power in row 0 to total power in the row band is greater than ROW0, a row 0 signal is detected.
A value of 0x7FF0 corresponds to a 1.0 ratio.
1
2
3
4
DTMF Row 1 Peak Magnitude Pass Ratio Threshold.
49
49
49
49
This register sets the minimum power ratio threshold for row 1 DTMF detection. If the ratio of
power in row 1 to total power in the row band is greater than ROW1, a row 1 signal is detected.
A value of 0x7FF0 corresponds to a 1.0 ratio.
DTMF Row 2 Peak Magnitude Pass Ratio Threshold.
This register sets the minimum power ratio threshold for row 2 DTMF detection. If the ratio of
power in row 2 to total power in the row band is greater than ROW2, a row 2 signal is detected.
A value of 0x7FF0 corresponds to a 1.0 ratio.
DTMF Row 3 Peak Magnitude Pass Ratio Threshold.
This register sets the minimum power ratio threshold for row 3 DTMF detection. If the ratio of
power in row 3 to total power in the row band is greater than ROW3, a row 3 signal is detected.
A value of 0x7FF0 corresponds to a 1.0 ratio.
DTMF Column Peak Magnitude Pass Threshold.
This register sets the minimum power ratio threshold for column DTMF detection; all columns
use the same threshold. If the ratio of power in a particular column to total power in the column
band is greater than COL, a column detect for that particular column signal is detected. A value
of 0x7FF0 corresponds to a 1.0 ratio.
5
6
7
8
9
DTMF Forward Twist Threshold.
This register sets the threshold for the power ratio of row power to column power. A value of
0x7F0 corresponds to a 1.0 ratio.
49
49
49
49
49
49
49
49
DTMF Reverse Twist Threshold.
This register sets the threshold for the power ratio of column power to row power. A value of
0x7F0 corresponds to a 1.0 ratio.
DTMF Row Ratio Threshold.
This register sets the threshold for the power ratio of highest power row to the other rows. A
value of 0x7F0 corresponds to a 1.0 ratio.
DTMF Column Ratio Threshold.
This register sets the threshold for the power ratio of highest power column to the other col-
umns. A value of 0x7F0 corresponds to a 1.0 ratio.
DTMF Row Second Harmonic Threshold.
This register sets the threshold for the power ratio of peak row tone to its second harmonic. A
value of 0x7F0 corresponds to a 1.0 ratio.
10 DTMF Column Second Harmonic Threshold.
This register sets the threshold for the power ratio of peak column tone to its second harmonic.
A value of 0x7F0 corresponds to a 1.0 ratio.
11 DTMF Power Minimum Threshold.
This register sets the threshold for the minimum total power in the DTMF calculation, under
which the calculation is ignored.
12 DTMF Hot Limit Threshold.
This register sets the two-step AGC in the DTMF path.
Rev. 1.61
119
Si3210/Si3211
4.2. Oscillators
See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing
register values. All values are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but must be written to zeroes.
Table 39. Oscillator Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
13
14
15
16
17
18
OSC1[15:0]
OSC1X[15:0]
OSC1Y[15:0]
OSC2[15:0]
OSC2X[15:0]
OSC2Y[15:0]
19
20
21
22
23
24
25
ROFF[5:0]
RCO[15:0]
RNGX[15:0]
RNGY[15:0]
PLSD[15:0]
PLSX[15:0]
PLSCO[15:0]
120
Rev. 1.61
Si3210/Si3211
Table 40. Oscillator Indirect Registers Description
Addr.
Description
Reference
Page
Oscillator 1 Frequency Coefficient.
13
14
15
16
17
18
41
41
41
41
41
41
Sets tone generator 1 frequency.
Oscillator 1 Amplitude Register.
Sets tone generator 1 signal amplitude.
Oscillator 1 Initial Phase Register.
Sets initial phase of tone generator 1 signal.
Oscillator 2 Frequency Coefficient.
Sets tone generator 2 frequency.
Oscillator 2 Amplitude Register.
Sets tone generator 2 signal amplitude.
Oscillator 2 Initial Phase Register.
Sets initial phase of tone generator 2 signal.
Ringing Oscillator DC Offset.
19 Sets dc offset component (V –V
) to ringing waveform. The range is 0 to 94.5 V in
RING
43
TIP
1.5 V increments.
Ringing Oscillator Frequency Coefficient.
20
21
22
23
24
25
43
43
43
47
47
47
Sets ringing generator frequency.
Ringing Oscillator Amplitude Register.
Sets ringing generator signal amplitude.
Ringing Oscillator Initial Phase Register.
Sets initial phase of ringing generator signal.
Pulse Metering Oscillator Attack/Decay Ramp Rate.
Sets pulse metering attack/decay ramp rate.
Pulse Metering Oscillator Amplitude Register.
Sets pulse metering generator signal amplitude.
Pulse Metering Oscillator Frequency Coefficient.
Sets pulse metering generator frequency.
Rev. 1.61
121
Si3210/Si3211
4.3. Digital Programmable Gain/Attenuation
See functional description sections of digital programmable gain/attenuation for guidelines on computing register
values. All values are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but must be written to zeroes.
Table 41. Digital Programmable Gain/Attenuation Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
26
27
DACG[11:0]
ADCG[11:0]
Table 42. Digital Programmable Gain/Attenuation Indirect Registers Description
Addr.
Description
Reference
Page
26 Receive Path Digital to Analog Converter Gain/Attenuation.
49
This register sets gain/attenuation for the receive path. The digitized signal is effectively mul-
tiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain
of 6 dB.
27 Transmit Path Analog to Digital Converter Gain/Attenuation.
49
This register sets gain/attenuation for the transmit path. The digitized signal is effectively
multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain
of 6 dB.
122
Rev. 1.61
Si3210/Si3211
4.4. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values
are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but must be written to zeroes.
Table 43. SLIC Control Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
28
LCRT[5:0]
RPTP[5:0]
29
30
CML[5:0]
CMH[5:0]
31
32
PPT12[7:0]
33
PPT34[7:0]
PPT56[7:0]
34
35
NCLR[12:0]
36
NRTP[12:0]
NQ12[12:0]
NQ34[12:0]
NQ56[12:0]
37
38
39
40
VCMR[3:0]
VMIND[3:0]*
41
42
43
LCRTL[5:0]
*Note: Si3210 only.
Rev. 1.61
123
Si3210/Si3211
Table 44. SLIC Control Indirect Registers Description
Addr.
Description
Reference
Page
28 Loop Closure Threshold.
35
Loop closure detection threshold. This register defines the upper bounds threshold if hys-
teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.
29 Ring Trip Threshold.
46
Ring trip detection threshold during ringing.
30 Common Mode Minimum Threshold for Speed-Up.
This register defines the negative common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
31 Common Mode Maximum Threshold for Speed-Up.
This register defines the positive common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
32 Power Alarm Threshold for Transistors Q1 and Q2.
33 Power Alarm Threshold for Transistors Q3 and Q4.
34 Power Alarm Threshold for Transistors Q5 and Q6.
35 Loop Closure Filter Coefficient.
33
33
33
35
46
33
33
33
43
36 Ring Trip Filter Coefficient.
37 Thermal Low Pass Filter Pole for Transistors Q1 and Q2.
38 Thermal Low Pass Filter Pole for Transistors Q3 and Q4.
39 Thermal Low Pass Filter Pole for Transistors Q5 and Q6.
40 Common Mode Bias Adjust During Ringing.
Recommended value of 0 decimal.
41 DC-DC Converter V Voltage (Si3210 only).
36
OV
This register sets the overhead voltage, V , to be supplied by the dc-dc converter.
OV
When the VOV bit = 0 (direct Register 66, bit 4), V should be set between 0 and 9 V
OV
(VMIND = 0 to 6h). When the VOV bit = 1, V should be set between 0 and 13.5 V
OV
(VMIND = 0 to 9h).
42 Reserved.
43 Loop Closure Threshold—Lower Bound.
35
This register defines the lower threshold for loop closure hysteresis, which is enabled in
bit 0 of direct Register 108. The range is 0–80 mA in 1.27 mA steps.
124
Rev. 1.61
Si3210/Si3211
4.5. FSK Control
For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These
registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,
bit 6) and REL = 1 (direct Register 32, bit 6).
Table 45. FSK Control Indirect Registers Summary
Addr. D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
99
FSK0X[15:0]
FSK0[15:0]
FSK1X[15:0]
FSK1[15:0]
FSK01[15:0]
FSK10[15:0]
100
101
102
103
104
Table 46. FSK Control Indirect Registers Description
Description
Addr.
Reference Page
99 FSK Amplitude Coefficient for Space.
43 and AN32
When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener-
ating a space or “0”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1X.
100 FSK Frequency Coefficient for Space.
43 and AN32
43 and AN32
43 and AN32
When FSKEN = 1 and REL = 1, this register sets the frequency to be used when gener-
ating a space or “0”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1.
101 FSK Amplitude Coefficient for Mark.
When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener-
ating a mark or “1”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1X.
102 FSK Frequency Coefficient for Mark.
When FSKEN = 1 and REL = 1, this register sets the frequency to be used when gener-
ating a mark or “1”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1.
103 FSK Transition Parameter from 0 to 1.
43 and AN32
43 and AN32
When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is
applied to signal amplitude when transitioning from a space (0) to a mark (1).
104 FSK Transition Parameter from 1 to 0.
When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is
applied to signal amplitude when transitioning from a mark (1) to a space (0).
Rev. 1.61
125
Si3210/Si3211
5. Pin Descriptions: Si3210/11
QFN
TSSOP
38
37
1
2
CS
INT
SCLK
SDI
PCLK
DRX
DTX
FSYNC
36 SDO
38 37 36 35 34 33 32
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
DTX
FSYNC
RESET
31 SDITHRU
35
SDITHRU
30
DCDRV/DCSW
34
DCDRV/DCSW
29 DCFF/DOUT
33 DCFF/DOUT
SDCH/DIO1
SDCL/DIO2
VDDA1
28
27
26
25
24
23
22
21
20
TEST
GNDD
VDDD
ITIPN
ITIPP
RESET
SDCH/DIO1
SDCL/DIO2
VDDA1
32
31
30
TEST
GNDD
VDDD
5
6
7
EPAD
IREF
CAPP
QGND
CAPM
29 ITIPN
8
28
27
IREF
CAPP
QGND
CAPM
ITIPP
VDDA2
9
VDDA2
10
11
12
IRINGP
IRINGN
IGMP
26 IRINGP
STIPDC
SRINGDC
25
24
23
22
21
20
IRINGN
IGMP
GNDA
IGMN
SRINGAC
STIPAC
13 14 15 16 17 18 19
STIPDC 15
SRINGDC 16
STIPE
SVBAT 18
19
17
SRINGE
QFN
Pin #
TSSOP
Pin #
Name
Description
35
1
CS
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high
impedance. When active, the serial port is operational.
36
37
38
1
2
3
4
5
6
INT
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
PCLK
DRX
PCM Bus Clock.
Clock input for PCM bus timing.
Receive PCM Data.
Input data from PCM bus.
DTX
Transmit PCM Data.
Output data to PCM bus.
2
FSYNC
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long
pulse format.
3
4
7
RESET
Reset.
Active low input. Hardware reset used to place all control registers in the
default state.
8
SDCH/DIO1 DC Monitor/General Purpose I/O.
DC-DC converter monitor input used to detect overcurrent situations in the
converter (Si3210 only). General purpose I/O (Si3211 only).
126
Rev. 1.61
Si3210/Si3211
QFN
Pin #
TSSOP
Pin #
Name
Description
5
9
SDCL/DIO2 DC Monitor/General Purpose I/O.
DC-DC converter monitor input used to detect overcurrent situations in the
converter (Si3210 only). General purpose I/O (Si3211 only).
6
7
10
11
VDDA1
IREF
Analog Supply Voltage.
Analog power supply for internal analog circuitry.
Current Reference.
Connects to an external resistor used to provide a high accuracy reference
current.
8
12
CAPP
SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
9
13
14
QGND
CAPM
Component Reference Ground.
10
SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
11
12
13
14
15
16
17
18
STIPDC
SRINGDC
STIPE
TIP Sense.
Analog current input used to sense voltage on the TIP lead.
RING Sense.
Analog current input used to sense voltage on the RING lead.
TIP Emitter Sense.
Analog current input used to sense voltage on the Q6 emitter lead.
SVBAT
V
Sense.
BAT
Analog current input used to sense voltage on dc-dc converter output voltage
lead.
15
16
17
18
19
20
21
22
19
20
21
22
23
24
25
26
SRINGE
STIPAC
SRINGAC
IGMN
RING Emitter Sense.
Analog current input used to sense voltage on the Q5 emitter lead.
TIP Transmit Input.
Analog ac input used to detect voltage on the TIP lead.
RING Transmit Input.
Analog ac input used to detect voltage on the RING lead.
Transconductance Amplifier External Resistor.
Negative connection for transconductance gain setting resistor.
GNDA
Analog Ground.
Ground connection for internal analog circuitry.
IGMP
Transconductance Amplifier External Resistor.
Positive connection for transconductance gain setting resistor.
IRINGN
IRINGP
Negative Ring Current Control.
Analog current output driving Q3.
Positive Ring Current Control.
Analog current output driving Q2.
Rev. 1.61
127
Si3210/Si3211
QFN
Pin #
TSSOP
Pin #
Name
Description
23
24
25
26
27
28
27
28
29
30
31
32
VDDA2
Analog Supply Voltage.
Analog power supply for internal analog circuitry.
ITIPP
ITIPN
VDDD
GNDD
TEST
Positive TIP Current Control.
Analog current output driving Q1.
Negative TIP Current Control.
Analog current output driving Q4.
Digital Supply Voltage.
Digital power supply for internal digital circuitry.
Digital Ground.
Ground connection for internal digital circuitry.
Test.
Enables test modes for Silicon Labs internal testing. This pin should always
be tied to ground for normal operation.
29
30
33
34
DCFF/DOUT DC Feed-Forward/High Current General Purpose Output.
Feed-forward drive of external bipolar transistors to improve dc-dc converter
efficiency (Si3210 only). High current output pin (Si3211 only).
DCDRV/DCSW DC Drive/Battery Switch.
DC-DC converter control signal output which drives external bipolar transistor
(Si3210 only). Battery switch control signal output which drives external
bipolar transistor (Si3211 only).
31
32
33
34
35
36
37
38
SDITHRU
SDO
SDI Passthrough.
Cascaded SDI output signal for daisy-chain mode.
Serial Port Data Out.
Serial port control data output.
SDI
Serial Port Data In.
Serial port control data input.
SCLK
Serial Port Bit Clock Input.
Serial port clock input. Controls the serial data on SDO and latches the data
on SDI.
n/a
n/a
EPAD
Exposed pad.
Must have a low thermal resistance connection to ground.
128
Rev. 1.61
Si3210/Si3211
6. Pin Descriptions: Si3201
TIP
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ITIPP
ITIPN
IRINGP
IRINGN
NC
RING
VBAT
VBATH
NC
STIPE
SRINGE
NC
GND
VDD
Pin #
Name
Input/
Description
Output
1
TIP
NC
I/O
—
I/O
—
—
—
—
TIP Output—Connect to the TIP lead of the subscriber loop.
No Internal Connection—Do not connect to any electrical signal.
RING Output—Connect to the RING lead of the subscriber loop.
Operating Battery Voltage—Connect to the battery supply.
High Battery Voltage—This pin is internally connected to VBAT.
Ground—Connect to a low impedance ground plane.
2, 6, 9, 12
3
4
5
7
8
RING
VBAT
VBATH
GND
VDD
Supply Voltage—Main power supply for all internal circuitry. Connect to a
3.3 V or 5 V supply. Decouple locally with a 0.1 F/6 V capacitor.
10
SRINGE
O
RING Emitter Sense Output—Connect to the SRINGE pin of the Si321x
pin.
11
13
STIPE
O
I
TIP Emitter Sense Output—Connect to the STIPE pin of the Si321x pin.
IRINGN
Negative RING Current Control—Connect to the IRINGN lead of the
Si321x.
14
15
16
IRINGP
ITIPN
I
I
Positive RING Current Drive—Connect to the IRINGP lead of the Si321x.
Negative TIP Current Control—Connect to the ITIPN lead of the Si321x.
Positive TIP Current Control—Connect to the ITIPP lead of the Si321x.
Exposed Thermal Pad—Connect to the bulk ground plane.
ITIPP
I
Bottom-Side
Exposed Pad
—
Rev. 1.61
129
Si3210/Si3211
7. Ordering Guide
Chip
Description DC-DC
DTMF
DCFFPin Package
Output
Lead-Free
and
Temperature
Converter Decoder
RoHS-
Compliant
Si3210-E-FM
Si3210-E-GM
Si3210M-E-FM
Si3210M-E-GM
Si3210-FT
ProSLIC
ProSLIC
ProSLIC
ProSLIC
ProSLIC
ProSLIC
ProSLIC
ProSLIC
ProSLIC
ProSLIC
ProSLIC
ProSLIC
DCDRV
DCDRV
DCDRV
DCDRV
QFN-38
QFN-38
QFN-38
QFN-38
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0 to 70 °C
–40 to 85 °C
0 to 70 °C
–40 to 85 °C
0 to 70 °C
DCDRV TSSOP-38
DCDRV TSSOP-38
DCDRV TSSOP-38
DCDRV TSSOP-38
Si3210-GT
–40 to 85 °C
0 to 70 °C
Si3210M-FT
Si3210M-GT
Si3211-E-FT
Si3211-E-GT
Si3211-E-FM
Si3211-E-GM
Si3201-FS
–40 to 85 °C
0 to 70 °C
n/a
n/a
n/a
n/a
n/a
TSSOP-38
TSSOP-38
QFN-38
–40 to 85 °C
0 to 70 °C
QFN-38
–40 to 85 °C
0 to 70 °C
Linefeed
Interface
SOIC-16
Si3201-GS
Linefeed
Interface
n/a
SOIC-16
Yes
–40 to 85 °C
Note: Add an “R” at the end of the device to denote tape and reel; 2500 quantity per reel.
130
Rev. 1.61
Si3210/Si3211
Table 47. Evaluation Kit Ordering Guide
Item
Supported
ProSLIC
Description
Linefeed
Interface
Si3210PPQX-EVB
Si3210PPQ1-EVB
Si3210PPTX-EVB
Si3210PPT1-EVB
Si3210MPPTX-EVB
Si3210MPPT1-EVB
Si3211PPTX-EVB
Si3210-QFN
Si3210-QFN
Eval Board, Daughter Card
Eval Board, Daughter Card
Eval Board, Daughter Card
Eval Board, Daughter Card
Eval Board, Daughter Card
Eval Board, Daughter Card
Eval Board, Daughter Card
Discrete
Si3201
Si3210-TSSOP
Si3210-TSSOP
Si3210M-TSSOP
Si3210M-TSSOP
Si3211-TSSOP
Discrete
Si3201
Discrete
Si3201
Discrete
Rev. 1.61
131
Si3210/Si3211
8. Package Outlines and PCB Land Patterns
8.1. 38-Pin QFN
8.1.1. Package Outline: 38-Pin QFN
Figure 33 illustrates the package details for the Si321x. Table 48 lists the values for the dimensions shown in the
illustration.
2X
bbb
C B
ccc
C
A
D2
D
A
DETAIL "B"
D/2
A1
D2/2
2X
aaa
C A
38
32
32
38
1
31
31
1
E/2
E2/2
E2
E
12
20
20
12
e
13
19
19
13
38X L
B
38X b
ddd
C A B
C
SEATING PLANE
DETAIL "A"
Detail A
Detail B
Pin-1 Identifier
38
38
L1
1
1
(L)
(b)
Option 1
Option 2
Chamfered Corner
Corner Square
Figure 33. 38-Pin Quad Flat No-Lead Package (QFN)
132
Rev. 1.61
Si3210/Si3211
Table 48. Package Diagram Dimensions1,2,3
Millimeters
Symbol
Min
0.75
0.00
0.18
Nom
0.85
Max
0.95
0.05
0.30
A
A1
b
0.01
0.23
D
5.00 BSC.
3.20
D2
e
3.10
3.30
0.50 BSC.
7.00 BSC.
5.20
E
E2
L
5.10
0.35
0.03
—
5.30
0.55
0.08
0.10
0.10
0.08
0.10
0.45
L1
0.05
aaa
bbb
ccc
ddd
Notes:
—
—
—
—
—
—
—
1. All dimensions shown are in millimeters (mm) unless
otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.
3. Recommended card reflow profile is per the JEDEC/IPC
J-STD-020C specification for Small Body Components.
Rev. 1.61
133
Si3210/Si3211
8.1.2. PCB Land Pattern: 38-Pin QFN
Figure 34 shows the recommended land pattern for the Si3210/11 QFN-38 package. Table 49 lists the values for
the dimensions shown in the illustration.
Figure 34. QFN-38 Land Pattern Drawing
134
Rev. 1.61
Si3210/Si3211
Table 49. QFN-38 PCB Land Pattern Dimensions
Dimension
Feature
Min.
4.70
6.70
Max.
4.80
6.80
C1
C2
E
Pad column spacing
Pad row spacing
Pad pitch
0.50 BSC
X1
X2
Y1
Y2
Pin pad width
0.20
3.20
0.80
5.20
0.30
3.30
0.90
5.30
Thermal pad width
Pin pad width
Thermal pad length
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads
4. A 3x5 array of 0.90mm square openings on 1.10mm pitch should be used for the center
ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPEC J-STD-020C specification for
Small Body Components.
Rev. 1.61
135
Si3210/Si3211
8.2. 38-Pin TSSOP
8.2.1. Package Outline: 38-Pin TSSOP
Figure 35 illustrates the package details for the Si321x. Table 50 lists the values for the dimensions shown in the
illustration.
Figure 35. 38-Pin Thin Shrink Small Outline Package (TSSOP)
Table 50. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Nom
—
Max
1.20
0.15
1.05
0.27
0.20
9.80
A
A1
A2
b
0.05
0.80
0.17
0.09
9.60
—
1.00
—
c
—
D
9.70
E
E1
e
6.40 BSC
4.40
4.30
0.45
0°
4.50
0.75
8°
0.50 BSC
0.60
L
L2
0.25 BSC
—
aaa
bbb
ccc
0.10
0.08
0.20
136
Rev. 1.61
Si3210/Si3211
8.2.2. PCB Land Pattern: 38-Pin TSSOP
Figure 36 illustrates the recommended land pattern for the Si3210/11 TSSOP-38 package. Table 51 lists the values
for the dimensions shown in the illustration.
Figure 36. TSSOP-38 PCB Land Pattern Drawing
Table 51. PCB Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.80
0.50
0.30
1.45
C1
E
X1
Y1
Pad Length
Notes:
1. All dimensions shown are in millimeters (mm) unless
otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition
(MMC). Least Material Condition (LMC) is calculated based
on a Fabirication Allowance of 0.05mm.
5. The recommended card reflow profile is per the JEDEC/IPC
J-STD-020 specification for Small Body Components.
Rev. 1.61
137
Si3210/Si3211
8.3. 16-Pin ESOIC
8.3.1. Package Outline: 16-Pin ESOIC
Figure 37 illustrates the package details for the Si3201. Table 52 lists the values for the dimensions shown in the
illustration.
Figure 37. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package
Table 52. Package Diagram Dimensions
Millimeters
Symbol
A
Min
—
Max
1.75
0.15
—
A1
A2
b
0.00
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
D1
E
3.45
3.65
6.00 BSC
3.90 BSC
E1
E2
e
2.20
0.40
2.40
1.27
1.27 BSC
0.25 BSC
L
L2
h
0.25
0°
0.50
8°
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
138
Rev. 1.61
Si3210/Si3211
8.3.2. PCB Land Pattern: 16-Pin ESOIC
Figure 38 illustrates the recommended land pattern for the Si3201 SOIC-16 package. Table 53 lists the values for
the dimensions shown in the illustration.
Figure 38. SOIC-16 PCB Land Pattern Drawing
Table 53. SOIC-16 PCB Land Pattern Dimensions
Dimension
Feature
Pin pad column spacing
Pin pad row pitch
Pin pad width
Min
Max
C1
E
5.30
5.40
1.27 BSC
X1
Y1
X2
0.50
1.45
2.20
3.50
0.60
1.55
2.30
3.60
Pin pad length
Thermal pad width
Thermal pad length
Y2
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X175-17N.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
Rev. 1.61
139
Si3210/Si3211
9. Product Identification
9.1. Ordering Part Number
The ordering part number indicates the device number, device variant (optional), device revision level, package
type, temperature range, and packing format, e.g., tape-and-reel, and identifies Silicon Laboratories as the
manufacturer. It will be of the following form:
S i 3 2 1 0 M - E - F M R
Packing format, e.g., tape-and-reel
Package and temperature range
Revision level (if applicable
Part variant (if applicable)
Part number
Silicon Laboratories
See the ordering guide above for a list of valid ordering part numbers.
9.2. Marking Part Number
See the Package Marking section for an example and explanation of the markings on the device. Note that the part
number marked on the device is different from the Ordering Part Number and that the product revision level is
st
indicated by the first (1 ) character of the Manufacturing Code.
140
Rev. 1.61
Si3210/Si3211
10. Package Marking (Top Mark)
10.1. QFN Package
Figure 39. QFN Top Mark Diagram
Table 54. Explanation of QFN Top Mark
Line 1 Marking:
Silicon Labs prefix
Device number
“Si”
e.g., “3210”
e.g., “M”
“–”
Device variant (optional)
Separator
Package/temperature range e.g., “FM’, “GM”, etc
Line 2 Marking:
Line 3 Marking:
YY=Year
WW=Work Week
Date of manufacture
TTTTTT=Mfg Code
Internal manufacturing code; 1st
character=product revision level
Circle=0.5 mm Diameter
Lower Left-Justified
Pin 1 Identifier
Circle=1.3 mm Diameter
Center-Justified
“e3” Pb-Free Symbol
e.g., KR, TW, etc
Country of Origin
ISO Code Abbreviation
Rev. 1.61
141
Si3210/Si3211
10.2. TSSOP Package
Figure 40. TSSOP Top Mark Diagram
Table 55. Explanation of TSSOP Top Mark
Line 1 Marking:
Silicon Labs prefix
Device number
“Si”
e.g., “3210”
e.g., “M”
“–”
Device variant (optional)
Separator
Package/temperature range e.g., “FM’, “GM”, etc
Line 2 Marking:
Line 3 Marking:
YY=Year
WW=Work Week
Date of manufacture
RFAIXX=Mfg Code
Internal manufacturing code; 1st
character=product revision level
Circle=0.5 mm Diameter
Lower Left-Justified
Pin 1 Identifier
Circle=1.3 mm Diameter
Center-Justified
“e3” Pb-Free Symbol
e.g., KR, TW, etc
Country of Origin
ISO Code Abbreviation
142
Rev. 1.61
Si3210/Si3211
10.3. SOIC (Si3201) Package
Figure 41. SOIC Top Mark Diagram
Table 56. Explanation of SOIC Top Mark
Silicon Labs prefix
Device number
Separator
“Si”
e.g., “3201”
“–”
Line 1 Marking:
Package/temperature
range
e.g., “GS”
Circle=0.5 mm Diameter
Center-Justified
Pin 1 Identifier
Circle=1.3 mm Diameter
Lower Left-Justified
“e3” Pb-Free Symbol
Date of manufacture
Line 2 Marking:
YY=Year
WW=Work Week
TTTTTT
Internal manufacturing code; 1st
character=product revision level
Rev. 1.61
143
Si3210/Si3211
Moved the schematic for the supply filtering network for
DOCUMENT CHANGE LIST
Revision 1.41 to Revision 1.42
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Moved the symbol for C9 closer to the VBATH pin on the
Si3201 symbol.
Changed R26 to 10 k.
Added Note 4.
16-pin ESOIC dimension A1 corrected in Table 50
on page 136.
Delay time between chip selects, tcs, changed from
220 ns to 440 ns in Table 10 on page 13.
C10 changed from 22 nF to 0.1 µF in Figure 10 on
page 18.
C18, C19 changed from 1.0 µF to 4.7 µF in
Figure 12 on page 22.
Recommended value for Indirect Register 40
changed from 6 to 0 in Table 44 on page 124.
Added QFN package option.
Updated Figure 13.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Added Note 5 and moved the symbol for C26 to better
illustrate its optimal position in a board layout.
Changed R26 to 10 k.
Added Note 6.
Revision 1.42 to Revision 1.43
Updated Figure 14.
Moved the schematic for the supply filtering network for
Table 16, “Si3210/Si3210M External Component
Values—Discrete Solution,” on page 25.
Added TO-92 transistor suppliers to BOM.
"7. Ordering Guide" on page 130
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Added Note 3 and moved the symbol for C26 to better
illustrate its optimal position in a board layout.
Added Note 4.
Updated to include product revision designator.
“Lead-Free” changed to “Lead-Free and RoHS-
Compliant”
Changed R26 to 10 k.
Figure , “,” on page 17.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Figure 12, “Si3211 Typical Application Circuit Using
Si3201,” on page 22.
Corrected connection between D1 and the linefeed
components.
Added Note 5
Updated Table 3.
Corrected longitudinal current per pin for EBTO/
EBTA = 10 to 12 mA.
Updated Table 8.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Figure 13, “Si3210/Si3210M Typical Application
Circuit Using Discrete Components,” on page 24.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Added optional components to STIPE, SRINGE, and
SVBAT pins to improve idle channel noise.
Figure 14, “Si3211 Typical Application Circuit Using
Discrete Solution,” on page 26.
Filled-in typical values for IVDD and IBAT for VDDD
,
VDDA = 3.3 V.
Updated Table 11.
Renamed "PCLK Period Jitter Tolerance" to
"PCLK-to-FSYNC Jitter Tolerance".
Added Note 2.
Updated Table 12.
Changed current rating of L2 to 150 mA.
Added new row for R26 and changed the value to
10 k.
Added title for AN45 to description of R28 and R29.
Added column for component package type.
Added Note 1.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Added optional components to STIPE, SRINGE, and
SVBAT pins to improve idle channel noise.
Table 52, “Package Diagram Dimensions,” on
page 138
Updated Table 13.
Added column for component package type.
Updated Table 14.
Added column for component package type.
Changed A1 max dimension from 0.10 to 0.15.
Revision 1.43 to Revision 1.44
Updated Figure 9.
Moved the schematic for the supply filtering network for
Updated Table 15.
VDDA1, VDDA2, and VDDD from the bottom of the
Changed current rating of L2 to 150 mA.
Added new row for R26 and changed the value to
10 k.
Rearranged the rows for R8 through R32 to be in
numerical order.
diagram to the top.
Moved the symbol for C26 closer to the VBATH pin on
the Si3201 symbol.
Changed R26 to 10 k.
Added Note 5.
Updated Figure 12.
Added column for component package type.
Added Note 1.
144
Rev. 1.61
Si3210/Si3211
Updated Table 16.
Changed current rating of L2 to 150 mA.
Corrected missing reference to R5.
Added new row for R26 and changed the value to 10 k.
Added title for AN45 to description of R28 and R29.
Added column for component package type.
Added Note 1.
Updated Table 17.
Added new row for R26 and changed the value to 10 k.
Added column for component package type.
Added Note 1.
Updated Table 18.
Added column for component package type.
Updated Table 19.
Added column for component package type.
Updated Table 36.
Added mnemonic for bit 7 of direct register 1 (PNI2).
Changed name of Register 94 to match the name in the description of Register 94.
Updated Table 47.
Removed unsupported evaluation kit part numbers.
Updated Register 1.
Added mnemonic and description of bit 7 (PNI2).
Updated Register 75.
Clarified the description of VBATL for Si3211.
Updated "2.1.6. Loop Closure Transition Detection" on page 35.
Modified first and second paragraphs to indicate that a loop closure event signals a transition from on-hook to off-hook or
from off-hook to on-hook.
Updated "2.4.2. Sinusoidal Ringing" on page 44.
Modified second paragraph to indicate the minimum allowed peak TIP-to-RING ringing voltage depends on the linefeed
state; i.e. forward-active or reverse-active.
Updated "2.9. Clock Generation" on page 52.
Modified first paragraph to indicate that 768 kHz and 1.536 MHz are not valid rates for GCI mode.
Updated "2.12. PCM Interface" on page 56.
Modified first paragraph to indicate that 768 kHz and 1.536 MHz are not valid rates for GCI mode.
Updated "8.1.2. PCB Land Pattern: 38-Pin QFN" on page 134 with more detailed package drawing.
Updated "8.3.1. Package Outline: 16-Pin ESOIC" on page 138 with more detailed package drawing.
Revision 1.44 to Revision 1.45
Added Si3211-E-FT and Si3211-E-GT to Ordering Guide
Clarified Ordering Guide
Replaced "X" with revision letter "E" in all ordering codes requiring a revision letter
Removed Note 1 from Ordering Guide
Revision 1.45 to Revision 1.5
Front page:
Changed images to QFN-38
Minor clean-up edits
Removed erroneous reference to polarity reversal feature on front page
Updated references to “K” and “B” temperature grades to “F” and “G”, respectively, in Electrical Characteristics
tables
Clarified Gain Error specifications in “Table 5. Monitor ADC Characteristics”
Corrected description of “Register 9. Audio Gain Control”, Bit 7 (“RHDF”--> “RHPF”)
Corrected reset setting of “Register 68. Loop Closure/Ring Trip Detect Status”(0000_0000b-->0000_0100b)
Removed obsolete non-RoHS-compliant device variants from the Ordering Guide
Updated QFN package drawing and dimensions
Added “8. Package Outlines and PCB Land Patterns”
Rev. 1.61
145
Si3210/Si3211
Added “9. Product Identification”
Added “10. Package Marking (Top Mark)”
Removed erroneous entry in the previous Document Change List, Revision 1.44 to 1.45, “Added QFN-38 image
to front page.”
Added a note to Table 9 cross-referencing it with section 1.2 ProSLIC Initialization in AN35.
Updated contact information.
Revision 1.5 to Revision 1.6
Updated “Power Supply Current, Analog and Digital” specification in Table 8. (Not released.)
Revision 1.6 to Revision 1.61
Updated “Power Supply Current, Analog and Digital” specification in Table 8.
146
Rev. 1.61
Si3210/Si3211
NOTES:
Rev. 1.61
147
Si3210/Si3211
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
148
Rev. 1.61
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