SI3216-FTR_技术文档

Si3216

PROSLIC^®PROGRAMMABLE WIDEBAND SLIC/CODEC

WITH RINGING/BATTERY VOLTAGE GENERATION

Features



Dual-mode wideband (50 Hz to 7 kHz)/

narrowband (200 Hz to 3.4 kHz) codec with

16-bit 16 kHz sampling for enhanced audio

quality



Software-programmable features and

parameters:

Ringing frequency, amplitude, cadence,

and waveshape



Performs all BORSCHT functions

Ideal for customer premise equipment

applications

Software-programmable internal ringing up

to 90 V_PK

2-wire ac impedance and hybrid

Constant current feed (20 to 41 mA)

Loop closure and ring trip thresholds

Software programmable signal

generation and audio processing:

µ-law/A-law companding

FSK (caller ID) generation

Dual audio tone generators

Smooth and abrupt polarity reversal

100% software-configurable global

solution



Ordering Information

Integrated battery supply with dynamic

voltage output

On-chip dc-dc converter continuously

minimizes power in all operating modes

Entire solution can be powered from a

single 3.3 V or 5 V supply

See page 114.

Pin Assignments



3.3 V to 35 V dc input range

Si3216

QFN

Audio loopback, dc, and GR-909

subscriber line diagnostic capabilities

Lead-free and RoHS-compliant packages

available

Dynamic 0 V to –94.5 V output

Low-cost inductor and high-efficiency

transformer versions supported

Applications

38 37 36 35 34 33 32

1

DTX

FSYNC

RESET

SDCH

SDCL

V_DDA1

IREF

CAPP

QGND

CAPM

STIPDC

SRINGDC

31 SDITHRU

2

3

4

30



Voice-over-broadband systems:

DSL, cable, wireless



PBX/IP-PBX/key telephone systems

Terminal adapters: ISDN, Ethernet, USB

DCDRV

29 DCFF

28

27

26

25

24

23

22

21

20

TEST

GNDD

VDDD

ITIPN

ITIPP

V_DDA2

IRINGP

IRINGN

IGMP

Description

5

6

7

The Si3216 ProSLIC^®is a low-voltage CMOS device that provides a complete analog

telephone interface supporting both wideband (50 Hz to 7.0 kHz) and narrowband

(200 Hz to 3.4 kHz) audio codec modes for enhanced voice quality in Voice-over-IP

(VoIP) applications. The ProSLIC integrates subscriber line interface circuit (SLIC),

wideband voice codec, and battery generation functionality into a single fully-

programmable device for global operation using only one hardware solution. The

Si3216’s wideband codec provides expanded audio band (50 Hz to 7 kHz), 16 kHz

sampling rate, and increased dynamic range for improved audio quality over traditional

telephony codecs. The integrated battery supply continuously adapts its output voltage

to minimize power and enables the entire solution to be powered from a single 3.3 V

(Si3216M only) or 5 V supply. Si3216 features include software-configurable 5 REN

internal ringing up to 90 V_PK, DTMF and caller ID generation, and a comprehensive set

of telephony signaling capabilities including expanded support of Japan and China

country requirements. The ProSLIC is packaged in a 38-pin QFN and TSSOP, and the

Si3201 high-voltage line interface device is packaged in a thermally-enhanced 16-pin

SOIC.

8

9

10

11

12

13 14 15 16 17 18 19

U.S. Patent #6,567,521

U.S. Patent #6,812,744

Other patents pending

Functional Block Diagram

INT RESET

Si3216

Line

Status

CS

Control

Interface

SCLK

SDO

SDI

TIP

DTX

Dual-Mode

Wideband/

Narrowband

Codec

Linefeed

Control

Linefeed

Interface

Tone

Generation

Prog.

Hybrid

PCM

Interface

DRX

RING

Z_S

FSYNC

PCLK

Discrete

Components

DC-DC Converter Controller

PLL

Rev. 1.0 12/08

Si3216

2

Rev. 1.0

Si3216

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.2. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.3. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

2.5. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

2.6. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

2.7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

2.8. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

2.9. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

2.10. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

4.1. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

4.2. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

4.3. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

4.4. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

5. Pin Descriptions: Si3216 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

7. Ordering Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

10. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

11. Silicon Labs Si3216 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Rev. 1.0

3

Si3216

1. Electrical Specifications

Table 1. Absolute Maximum Ratings and Thermal Information

1

Parameter

Symbol

Si3216

Value

Unit

DC Supply Voltage

V

, V

DDA2

–0.5 to 6.0

±10

V

mA

V

DDD

DDA1

Input Current, Digital Input Pins

Digital Input Voltage

I

IN

V

–0.3 to (V

+ 0.3)

DDD

IND

2

Operating Temperature Range

T

–40 to 100

C

A

Storage Temperature Range

T

–40 to 150

C

STG

TSSOP-38 Thermal Resistance, Typical

QFN-38 Thermal Resistance, Typical



70

35

C/W

W

JA



2

Continuous Power Dissipation

P

0.7

D

Si3201

DC Supply Voltage

V

–0.5 to 6.0

–104

V

DD

Battery Supply Voltage

V

BAT

Input Voltage: TIP, RING, SRINGE, STIPE pins

Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins

V

(V

– 0.3) to (V + 0.3)

V

INHV

BAT

DD

V

–0.3 to (V + 0.3)

V

IN

DD

2

Operating Temperature Range

T

–40 to 100

–40 to 150

55

C

A

Storage Temperature Range

T

C

STG

3

SOIC-16 Thermal Resistance, Typical



C/W

W

JA

2

Continuous Power Dissipation

P

0.8 at 70 ºC

0.6 at 85 ºC

D

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

2. Operation above 125 ^ºC junction temperature may degrade device reliability.

3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.

4

Rev. 1.0

Si3216

Table 2. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min*

Typ

Max*

Unit

o

Ambient Temperature

Si3216 Supply Voltage

T

K-grade

B-grade

0

25

70

85

C

A

o

T

–40

3.13

C

A

V

,V

,

3.3/5.0

5.25

V

DDD DDA1

V

DDA2

Si3201 Supply Voltage

Si3201 Battery Voltage

V

3.13

–96

3.3/5.0

—

5.25

–10

V

DD

V

= V

BATH BAT

BAT

*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 ^ºC unless otherwise stated.

Product specifications are only guaranteed when the typical application circuit (including component tolerances) is

used.

Rev. 1.0

5

Si3216

Table 3. AC Characteristics—Wideband Audio Mode: Si3216

(V_DDA, V_DDD= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

Parameter

Test Condition

Min

Typ

Max

Unit

TX/RX Performance—Wideband Audio Mode

Overload Level

THD = 1.5%

2.5

—

V

PK

1

Single Frequency Distortion

2-wire – PCM or

PCM – 2-wire:

50 Hz–7.0 kHz

–45

dB

2

Signal-to-(Noise + Distortion) Ratio

50 Hz–7.0 kHz

D/A or A/D 16-bit

Active off-hook and OHT,

Zac = 600 

TBD

45

—

Audio Tone Generator

0 dBm0, Active off-hook and

—

dB

2

Signal-to-Distortion Ratio

OHT, Zac = 600 

Intermodulation Distortion

—

0

–41

0.5

dB

2

Gain Accuracy

2-wire to PCM, 1014 Hz

–0.5

Zac = 600 

PCM to 2-wire, 1014 Hz

–0.5

0

0.5

dB

Zac = 600 

Gain Accuracy Over Frequency

Group Delay Over Frequency

Gain Tracking

Zac = 600 

Figure 1,2

—

1014 Hz sine wave, refer-

ence level –10 dBm

signal level:

3 dB to –37 dB

–37 dB to –50 dB

–50 dB to –60 dB

at 1000 Hz

–0.25

–0.5

–1.0

—

0.25

0.5

dB

s

—

1.0

Round-Trip Group Delay

Gain Step Accuracy

1100

—

–6 dB to 6 dB

–0.017

–0.25

–0.1

20

0.017

0.25

0.1

dB

Gain Variation with Temperature

Gain Variation with Supply

2-Wire Return Loss

All gain settings

—

V

= V

= 3.3/5 V ±5%

DDA

—

DDA

50 Hz–7.0 kHz

25

—

Zac = 600 

Transhybrid Balance

50 Hz–7.0 kHz

20

—

dB

Zac = 600 

Notes:

1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be

–10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.

2. Analog signal measured as V

– V

. Assumes ideal line impedance matching.

TIP

RING

3. The level of any unwanted tones within the bandwidth of 0 to 8 kHz does not exceed –55 dBm.

4. Assumes normal distribution of betas.

6

Rev. 1.0

Si3216

Table 3. AC Characteristics—Wideband Audio Mode: Si3216 (Continued)

(V_DDA, V_DDD= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

Parameter

Test Condition

Min

Typ

Max

Unit

Noise Performance—Wideband Audio Mode

3

Idle Channel Noise

7 kHz flat

—

40

—

23

—

dBrn

dB

PSRR from V

RX and TX, DC to 7 kHz

DDA

DDD

BAT

dB

Longitudinal Performance—Wideband Audio Mode

Longitudinal to Metallic or PCM

Balance

50 Hz–7.0 kHz, 



—

60

—

dB

Q1,Q2

150, 1% mismatch

4



 60 to 240

—

40

60

—

dB

Q1,Q2

4



 300 to 800

Q1,Q2

Metallic to Longitudinal Balance

Longitudinal Impedance

50 Hz–7.0 kHz

—

dB

50 Hz–7.0 kHz at TIP or

RING

Register selectable

ETBO/ETBA

00

01

10

—

33

17

—



Longitudinal Current per Pin

Active off-hook

50 Hz–7.0 kHz

Register selectable

ETBO/ETBA

—

4

8

—

mA

00

01

10

Notes:

1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be

–10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.

2. Analog signal measured as V

– V

. Assumes ideal line impedance matching.

TIP

RING

3. The level of any unwanted tones within the bandwidth of 0 to 8 kHz does not exceed –55 dBm.

4. Assumes normal distribution of betas.

Rev. 1.0

7

Si3216

(dB)

+1

(Hz)

50

100

6.4k 7k

8k

9k

–1

–4.5

–25

–45

Figure 1. Transmit and Receive Path Attenuation Distortion—Wideband Mode

(ms)

4

2

1

0.25

(Hz)

50

100

300

4k

6.4k

7k

Figure 2. Transmit and Receive Path Group Delay Distortion—Wideband Mode

8

Rev. 1.0

Si3216

Table 4. AC Characteristics—Narrowband Audio Mode

(V_DDA, V_DDD= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

Parameter

Test Condition

Min

Typ

Max

Unit

TX/RX Performance—Narrowband Audio Mode

Overload Level

THD = 1.5%

2.5

—

V

PK

1

Single Frequency Distortion

2-wire – PCM or

PCM – 2-wire:

200 Hz–3.4 kHz

–45

dB

2

Signal-to-(Noise + Distortion) Ratio

200 Hz–3.4 kHz

D/A or A/D 16-bit

Active off-hook and OHT,

any Zac

Figure 3

45

—

Audio Tone Generator

0 dBm0, Active off-hook and

OHT, any Zac

—

dB

2

Signal-to-Distortion Ratio

Intermodulation Distortion

—

0

–41

0.5

—

dB

2

Gain Accuracy

2-wire to PCM, 1014 Hz

PCM to 2-wire, 1014 Hz

–0.5

0

Gain Accuracy Over Frequency

Group Delay Over Frequency

Figure 5,6

Figure 7,8

—

3

Gain Tracking

1014 Hz sine wave, refer-

ence level –10 dBm

signal level:

3 dB to –37 dB

–37 dB to –50 dB

–50 dB to –60 dB

at 1000 Hz

–0.25

–0.5

–1.0

—

0.25

0.5

dB

µs

—

1.0

Round-Trip Group Delay

Gain Step Accuracy

Gain Variation with Temperature

Gain Variation with Supply

2-Wire Return Loss

Transhybrid Balance

Notes:

1100

—

–6 dB to 6 dB

–0.017

–0.25

–0.1

30

0.017

0.25

0.1

dB

All gain settings

—

V

= V

= 3.3/5 V ±5%

DDA

—

DDA

200 Hz–3.4 kHz

35

—

30

—

1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be

–10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.

2. Analog signal measured as V

– V

. Assumes ideal line impedance matching.

TIP

RING

3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking performance

in the signal range of 3 dB to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate.

4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.

5. Assumes normal distribution of betas.

Rev. 1.0

9

Si3216

Table 4. AC Characteristics—Narrowband Audio Mode (Continued)

(V_DDA, V_DDD= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

Parameter

Test Condition

Min

Typ

Max

Unit

Noise Performance—Narrowband Audio Mode

4

Idle Channel Noise

C-Message Weighted

Psophometric Weighted

3 kHz flat

—

40

—

15

–75

18

—

dBrnC

dBmP

dBrn

dB

PSRR from VDDA

RX and TX, DC to 3.4 kHz

PSRR from V

—

dB

DDD

BAT

—

dB

Longitudinal Performance—Narrowband Audio Mode

Longitudinal to Metallic or PCM

Balance

200 Hz–3.4 kHz, 



—

60

—

dB

Q1,Q2

150, 1% mismatch

5



 60 to 240

—

40

60

—

dB

Q1,Q2

5



 300 to 800

Q1,Q2

Using Si3201

Metallic to Longitudinal Balance

Longitudinal Impedance

200 Hz–3.4 kHz

at TIP or RING

Register selectable

ETBO/ETBA

00

01

10

—

33

17

—



Longitudinal Current per Pin

Active off-hook

200 Hz–3.4 kHz

Register selectable

ETBO/ETBA

—

4

8

—

mA

00

01

10

Notes:

1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be

–10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.

2. Analog signal measured as V

– V

. Assumes ideal line impedance matching.

TIP

RING

3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking performance

in the signal range of 3 dB to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate.

4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.

5. Assumes normal distribution of betas.

10

Rev. 1.0

Si3216

Figure 3. Transmit and Receive Path SNDR—Narrowband Mode

9

8

7

6

Fundamental

Acceptable

5

Output Power

Region

(dBm0)

4

3

2.6

2

1

0

1

2

3

4

5

6

7

8

9

Fundamental Input Power (dBm0)

Figure 4. Overload Compression Performance

Rev. 1.0

11

Si3216

Typical Response

Figure 5. Transmit Path Frequency Response—Narrowband Mode

12

Rev. 1.0

Si3216

Figure 6. Receive Path Frequency Response—Narrowband Mode

Rev. 1.0

13

Si3216

Figure 7. Transmit Group Delay Distortion—Narrowband Mode

Figure 8. Receive Group Delay Distortion—Narrowband Mode

14

Rev. 1.0

Si3216

Table 5. Linefeed Characteristics

(V_DDA, V_DDD= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Loop Resistance Range

R

See Note

0

—

160

10

4



%

V

LOOP

DC Loop Current Accuracy

I

= 29 mA, ETBA = 4 mA

–10

–4

LIM

DC Open Circuit Voltage

Accuracy

Active Mode; V = 48 V,

OC

V

– V

TIP

RING

DC Differential Output

Resistance

R

I

< I

LIM

—

–4

160

—

4



V

DO

LOOP

DC Open Circuit Voltage—

Ground Start

V

R

I

<I ; V

wrt ground

RING

= 48 V

OCTO

ROTO

RING LIM

V

OC

DC Output Resistance—

Ground Start

I

<I ; RING to ground

—

160

—



RING LIM

DC Output Resistance—

Ground Start

R

TIP to ground

150

–20

—

k

%

TOTO

Loop Closure/Ring Ground

Detect Threshold Accuracy

I

= 11.43 mA

—

20

—

THR

Ring Trip Threshold

Accuracy

R

= 1100 

—

THR

Ring Trip Response Time

User Programmable Register 70

and Indirect Register 23

—

Ring Amplitude

V

R

5 REN load; sine wave;

44

—

V

rms

TR

R

= 160 V

= –75 V

LOOP

BAT

Ring DC Offset

Programmable in Indirect

Register 6

0

—

V

OS

Trapezoidal Ring Crest

Factor Accuracy

Crest factor = 1.3

–.05

1.35

—

.05

1.45

Sinusoidal Ring Crest

Factor

R

—

CF

Ringing Frequency Accuracy

Ringing Cadence Accuracy

Calibration Time

f = 20 Hz

–1

–50

—

1

%

ms

%

Accuracy of ON/OFF Times

CAL to CAL Bit

50

600

25

Power Alarm Threshold

Accuracy

At Power Threshold = 300 mW

–25

Note: DC resistance round trip; 160 corresponds to 2 kft 26 gauge AWG.

Rev. 1.0

15

Si3216

Table 6. Monitor ADC Characteristics

(V_DDA, V_DDD= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Differential Nonlinearity

(6-bit resolution)

DNLE

–1/2

—

1/2

LSB

Integral Nonlinearity

(6-bit resolution)

INLE

–1

—

1

LSB

Gain Error (voltage)

Gain Error (current)

—

10

20

%

Table 7. Si321x DC Characteristics, V_DDA= V_DDD= 5.0 V

(V_DDA, V_DDD= 4.75 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

V

0.7 x V

—

0.3 x V

—

V

IH

DDD

V

IL

DDD

DIO1,DIO2,SDITHRU:I_O= –4 mA

SDO, DTX:I_O= –8 mA

V

– 0.6

OH

DDD

DOUT: I_O= –40 mA

V

– 0.8

—

V

DDD

DIO1,DIO2,DOUT,SDITHRU:

I_O= 4 mA

Low Level Output Voltage

Input Leakage Current

V

—

0.4

OL

SDO,INT,DTX:I_O= 8 mA

I

–10

—

10

µA

L

Table 8. Si321x DC Characteristics, V_DDA= V_DDD= 3.3 V

(V_DDA, V_DDD= 3.13 to 3.47 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

Parameter

Symbol

Test Condition

Min

Typ

—

Max

Unit

V

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

V

0.7 x V

—

IH

DDD

V

—

0.3 x V

—

V

IL

DDD

DIO1,DIO2,SDITHRU:I_O= –2 mA

SDO, DTX:I_O= –4 mA

V

– 0.6

—

V

OH

DDD

DOUT: I_O= –40 mA

V

– 0.8

—

V

DDD

DIO1,DIO2,DOUT,SDITHRU:

I_O= 2 mA

Low Level Output Voltage

Input Leakage Current

V

—

0.4

OL

SDO,INT,DTX:I_O= 4 mA

I

–10

—

10

A

L

16

Rev. 1.0

Si3216

Table 9. Power Supply Characteristics

(V_DDA,V_DDD= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)

1

2

Parameter

Symbol

I + I

Test Condition

Max

Unit

Typ

Power Supply Current,

Analog and Digital

Sleep (RESET = 0)

Open

0.1

33

37

0.13

42.8

53

0.3

49

68

mA

A

D

Active on-hook

ETBO = 4 mA, codec and Gm

amplifier powered down

Active OHT

ETBO = 4 mA

Active off-hook

ETBA = 4 mA, I

57

72

83

mA

= 20 mA

73

36

88

47

99

55

LIM

Ground-start

mA

Ringing

mA

µA

mA

Sinewave, REN = 1, V = 56 V

45

—

55

65

—

PK

V

Supply Current (Si3201)

I

Sleep mode, RESET = 0

Open (high impedance)

100

DD

VDD

—

100

110

1

—

Active on-hook standby

Forward/reverse active off-hook, no

I

, ETBO = 4 mA, V

= –24 V

LOOP

BAT

Forward/reverse OHT, ETBO = 4 mA,

= –70 V

—

1

—

mA

V

BAT

3

V

Supply Current

I

Sleep (RESET = 0)

Open (DCOF = 1)

Active on-hook

—

0

—

mA

BAT

mA

V

= 48 V, ETBO = 4 mA

—

3

—

OC

Active OHT

ETBO = 4 mA

11

Active off-hook

ETBA = 4 mA, I

mA

= 20 mA

—

30

2

—

LIM

Ground-start

Ringing

V

mA

= 56 V

,

PK

—

5.5

—

PK_RING

sinewave ringing, REN = 1

V

Supply Slew Rate

When using Si3201

10

V/µs

BAT

Notes:

1. V_DDD, V_DDA= 3.3 V.

2. V_DDD, V_DDA= 5.25 V.

3. I_BAT= current from V_BAT(the large negative supply). For a switched-mode power supply regulator efficiency of 71%,

the user can calculate the regulator current consumption as I_BATx V_BAT/(0.71 x V_DC).

Rev. 1.0

17

Si3216

Table 10. Switching Characteristics—General Inputs

V_DDA= V_DDA= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C_L= 20 pF)

Parameter

Symbol

Min

—

Typ

—

Max

20

Unit

ns

Rise Time, RESET

RESET Pulse Width

t

r

t

100

—

ns

rl

Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are

_IH= V_D– 0.4 V, V_IL= 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.

V

Table 11. Switching Characteristics—SPI

V_DDA= V_DDA= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C_L= 20 pF

Parameter

Test

Conditions

Symbol

Min

Typ

Max

Unit

Cycle Time SCLK

t

0.062

—

25

20

s

ns

c

Rise Time, SCLK

t

r

Fall Time, SCLK

t

—

f

Delay Time, SCLK Fall to SDO Active

t

—

d1

d2

Delay Time, SCLK Fall to SDO

Transition

—

Delay Time, CS Rise to SDO Tri-state

Setup Time, CS to SCLK Fall

Hold Time, CS to SCLK Rise

Setup Time, SDI to SCLK Rise

Hold Time, SDI to SCLK Rise

t

—

25

—

20

—

ns

d3

t

su1

t

20

h1

t

25

su2

t

20

h2

Delay Time between Chip Selects

(Continuous SCLK)

t

440

cs

d4

Delay Time between Chip Selects

(Non-continuous SCLK)

t

220

—

ns

SDI to SDITHRU Propagation Delay

t

—

4

10

Note: All timing is referenced to the 50% level of the waveform. Input test levels are V_IH= V_DDD–0.4 V, V_IL= 0.4 V

18

Rev. 1.0

Si3216

t_thru

t_c

t_r

SCLK

CS

t_su1

t_h1

t_cs

t_su2

t_h2

SDI

t_d1

t_d3

t_d2

SDO

Figure 9. SPI Timing Diagram

Table 12. Switching Characteristics—PCM Highway Serial Interface

V_D= 3.13 to 5.25 V, T_A= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C_L= 20 pF

Parameter

Test

Conditions

1

Symbol

Units

Min

Typ

Max

PCLK Frequency

1/t

—

0.256

0.512

0.768

1.024

1.536

2.048

4.096

8.192

—

MHz

c

PCLK Duty Cycle Tolerance

PCLK Period Jitter Tolerance

Rise Time, PCLK

t

40

50

—

60

120

25

%

ns

dty

t

–120

—

jitter

t

r

Fall Time, PCLK

t

—

25

f

Delay Time, PCLK Rise to DTX Active

t

—

20

d1

d2

Delay Time, PCLK Rise to DTX

Transition

—

20

2

Delay Time, PCLK Rise to DTX Tri-state

Setup Time, FSYNC to PCLK Fall

Hold Time, FSYNC to PCLK Fall

Setup Time, DRX to PCLK Fall

Hold Time, DRX to PCLK Fall

Notes:

t

—

25

20

25

20

—

20

—

ns

d3

t

su1

t

h1

t

su2

t

h2

1. All timing is referenced to the 50% level of the waveform. Input test levels are V_{IH –}V_{I/O –}0.4 V, V_IL= 0.4 V.

2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).

Rev. 1.0

19

Si3216

t_r

t_f

t_c

PCLK

t_h1

t_su1

FSYNC

t_su2

t_h2

DRX

DTX

t_d2

t_d1

t_d3

Figure 10. PCM Highway Interface Timing Diagram

VCC

R1

200k

15

20

38

37

STIPDC

STIPAC

SCLK

SDI

C24

0.1  F

C3

220 nF

SPI Bus

PCM

VCC

R8

4.7K

36

1

SDO

CS

6

3

4

C18

4.7 F

C19

4.7  F

FSYNC

PCLK

DRX

15

29

ITIPN

IRINGN

ITIPP

ITIPN

Bus

VCC

13

16

14

11

10

25

28

26

17

19

5

IRINGN

ITIPP

DTX

1

3

TIP

R32²

10k

TIP

C5

22nF

IRINGP

STIPE

IRINGP

STIPE

SRINGE

Protection

Circuit

2

7

R2

196k

INT

Note 2

C6

22nF

RESET

R4

196k

R26²

40.2k

RING

SRINGE

24

22

IGMP

IGMN

R15

243

R7

4.02k

R6

4.02k

18

SVBAT

11

12

14

R5

200k

IREF

CAPP

CAPM

C4

220 nF

R9

4.7K

R14

40.2k

C2

10  F

C1

10  F

21

16

SRINGAC

SRINGDC

13

QGND

R3

Notes:

200k

L2

1. Values and configurations for these

components can be derived from Table 18

or from App Note 45.

2. Only one component per system needed.

3. All circuit ground should have a single-point

connection to the ground plane.

4. Si3201 bottom-side exposed pad should be

electrically and thermally connected to bulk

ground plane.

C26

0.1  F

VDDA1 VDDA2

47 H

VDDD

GND

C31

10 F

10 V

Q9

R21

15

C15

C16

C17

C30

10  F

2N2222

0.1 F

0.1  F 0.1  F

VCC

R29¹

R28¹

VDC

Note 1

VBAT

DC-DC Converter

Circuit

VDC

Figure 11. Si3216(M) Application Circuit Using Si3201

20

Rev. 1.0

Si3216

Table 13. Si3216(M) + Si3201 External Component Values

Value

Component (s)

Supplier

C1,C2

10 µF, 6 V Ceramic or 16 V Low Leakage Electrolytic,

±20%

Murata, Nichicon URL1C100MD

C3,C4

C5,C6

220 nF, 100 V, X7R, ±20%

22 nF, 100 V, X7R, ±20%

0.1 µF, 6 V, Y5V, ±20%

4.7 µF Ceramic, 6 V, X7R, ±20%

0.1 µF, 100 V, X7R, ±20%

10 µF, 6 V, Electrolytic, ±20%

47 µH, 150 A

Murata, Johanson, Novacap, Venkel

Panasonic

C15,C16,C17,C24

C18,C19

C26

C30, C31

L2

Coilcraft

R1,R3,R5

R2,R4

200 k, 1/10 W, ±1%

196 k, 1/10 W, ±1%

4.02 k, 1/10 W, ±1%

4.7 k, 1/10 W, ±1%

R6,R7

R8,R9

R14,R26*

R15

40.2 k, 1/10 W, ±1%

243 , 1/10 W, ±1%

R21

15 , 1/4 W, ±5%

R28,R29

1/10 W, 1% (See “AN45: Design Guide for The Si3210

DC-DC Converter” or Table 18 for value selection)

R32*

Q9

10 k, 1/10 W, ±5%

60 V, General Purpose Switching NPN

ON Semi MMBT2222ALT1; Central

Semi CMPT2222A; Zetex

FMMT2222

*Note: Only one component is necessary on each signal in the system.

Rev. 1.0

21

Si3216

VCC

GND

R1

200k

38

37

SCLK

SDI

15

20

GND

STIPDC

STIPAC

SPI Bus

36

1

SDO

CS

R8

4.7k

C3

220nF

6

3

4

FSYNC

PCLK

DRX

Q4

5401

28

29

17

Q1

5401

ITIPP

ITIPN

STIPE

R10

10

PCM Bus

C32⁴

0.1 µF

Q6

5551

TIP

5

VCC

DTX

C8

220nF

R102 (100k)

R13

5.1k

C5

22nF

R2

100k

2

R32

Protection

Circuit

10k

R6

80.6

26

25

19

C6

22nF

2

7

IRINGP

IRINGN

SRINGE

INT

Note 2

Q2

5401

Q3

5401

RESET

RING

C34⁴

0.1 µF

R4

100k

R11

10

R26²

40.2k

24

22

Q5

5551

R104 (100k)

IGMP

IGMN

R15

243

C7

220nF

R12

5.1k

R5

100k

C33⁴

0.1 µF

18

R104 (100k)

SVBAT

11

12

14

IREF

CAPP

CAPM

R7

80.6

C4

220nF

R9

4.7k

C2

10uF

C1

10uF

R14

40.2k

21

16

SRINGAC

SRINGDC

Notes:

13

1. Values and configurations for these

components can be derived from Table 18

or from “AN45: Design Guide for the

Si3210/15/16 DC-DC Converter”.

2. Only one component per system needed.

3. All circuit grounds should have a single-

point connection to the ground plane.

4. Optional components to improve idle

channel noise.

QGND

R3

200k

C26

0.1uF

GND

L2

47 H

R21

15

VDDA1 VDDA2

VDDD

Q9

2N2222

C31

10 F

10 V

VCC

C15

0.1 F

C16

C17

C30

10  F

VDC

1

R29

R28

0.1  F 0.1  F

Note 1

DC-DC Converter

Circuit

VBAT

VDC

Figure 12. Si3216(M) Typical Application Circuit Using Discrete Line Interface Circuit

Table 14. Si3216(M) External Component Values

Component

Value

Supplier/Part Number

C1,C2

10 µF, 6 V Ceramic/Tantalum or 16 V Low Leakage

Murata, Panasonic, Nichicon

URL1C100MD

Electrolytic, 20%

C3,C4

C5,C6

220 nF, 100 V, X7R, 20%

22 nF, 100 V, X7R, 20%

220 nF, 50 V, X7R, 20%

0.1 µF, 6 V, Y5V, 20%

0.1 µF, 100 V, X7R, 20%

10 µF, 16 V, Electrolytic, 20%

47 µH, 150 A

Murata, Johanson, Novacap, Venkel

Panasonic

C7,C8

C15,C16,C17

C26

C30, C31

L2

Coilcraft

Q1,Q2,Q3,Q4

120 V, PNP, BJT

Central Semi CMPT5401; ON Semi

MMBT5401LT1, 2N5401; Zetex

FMMT5401;

Fairchild 2N5401; Samsung 2N5401

Q5,Q6

Q9

120 V, NPN, BJT

Central Semi CZT5551, ON Semi

2N5551;

Fairchild 2N5551; Phillips 2N5551

NPN General Purpose BJT

ON Semi MMBT2222ALT1; Central Semi

CMPT2222A; Zetex FMMT2222

22

Rev. 1.0

Si3216

Table 14. Si3216(M) External Component Values (Continued)

R1,R3

200 k, 1/10 W, 1%

100 k, 1/10 W, 1%

R2,R4,R5,

R102,R104,R105

R6,R7

R8,R9

80.6 , 1/4 W, 1%

4.7 k, 1/10 W, 1%

10 , 1/10 W, 5%

5.1 k, 1/10 W, 5%

40.2 k, 1/10 W, 1%

243 , 1/10 W, 1%

15 , 1/4 W, 1%

R10,R11

R12,R13

R14,R26*

R15

R21

R28,R29

1/10 W, 1% (See “AN45: Design Guide for The

Si3210 DC-DC Converter” or Table 18 for value

selection)

R32*

10 k, 1/10 W, 5%

*Note: Only one component is necessary on each signal in the system.

VDC

F1

SDCH

SDCL

R19¹

C25²

10 µF

C14²

0.1 µF

R18¹

Note 1

R20¹

C10

0.1 µF

R16

200

Q7

FZT953

DCFF

Q8

2N2222

D1

ES1D

VBAT

C9

10 µF

R17

L1

DCDRV

Note 1

GND

Notes:

1. Values and configurations for these components can be derived

from Table 20 or from “AN45: Design Guide for the Si3210/15/16

DC-DC Converter”.

2. Voltage rating for C14 and C25 must be greater than VDC.

Figure 13. Si321x BJT/Inductor DC-DC Converter Circuit

Rev. 1.0

23

Si3216

Table 15. Si321x BJT/Inductor DC-DC Converter Component Values

Component(s)

Value

Supplier

C9

10 µF, 100 V, Electrolytic, ±20%

0.1 µF, X7R, ±20%

Panasonic

C10*

C14*

C25*

R16

R17

Murata, Johanson, Novacap, Venkel

Panasonic

0.1 µF, X7R, ±20%

10 F, Electrolytic, ±20%

200 , 1/10 W, ±5%

1/10 W, ±5% (See “AN45: Design Guide for The Si3210 DC-

DC Converter” or Table 20 for value selection)

R18

R19,R20

F1

1/4 W, ±5% (See AN45 or Table 20 for value selection)

1/10 W, ±1% (See AN45 or Table 20 for value selection)

Fuse

Belfuse SSQ Series

D1

Ultra Fast Recovery 200 V, 1 A Rectifier

General Semi ES1D; Central Semi

CMR1U-02

L1

1A, Shielded Inductor (See AN45 or

Table 20 for value selection)

API Delevan SPD127 series, Sumida

CDRH127 series, Datatronics DR340-1

series, Coilcraft DS5022

Q7

Q8

120 V, High Current Switching PNP

60 V, General Purpose Switching NPN

Zetex FZT953, FZT955, ZTX953,

ZTX955; Sanyo 2SA1552

ON Semi MMBT2222ALT1; Central

Semi CMPT2222A; Zetex FMMT2222

*Note: Voltage rating of this device must be greater than V_DC

.

VDC

F1

SDCH

R19¹

C25²

10 µF

C14²

0.1 µF

R18¹

Note 1

R20¹

SDCL

1

2

3

4

R22

22

C27

470 pF

D1

ES1D

VBAT

6

DCFF

M1

IRLL014N

C9

10 µF

10

1

T1

Note 1

R17

200 k

DCDRV

NC

GND

Notes:

1. Values and configurations for these components can be derived

from Table 19 or from “AN45: Design Guide for the Si3210/15/16

DC-DC Converter”.

2. Voltage rating for C14 and C25 must be greater than VDC.

Figure 14. Si321xM MOSFET/Transformer DC-DC Converter Circuit

24

Rev. 1.0

Si3216

Table 16. Si321xM MOSFET/Transformer DC-DC Converter Component Values

Component (s)

Value

Supplier

C9

10 µF, 100 V, Electrolytic, ±20%

0.1 µF, X7R, ±20%

Panasonic

C14*

C25*

C27

R17

R18

Murata, Johanson, Novacap, Venkel

Panasonic

10 µF, Electrolytic, ±20%

470 pF, 100 V, X7R, ±20%

200 k, 1/10 W, ±5%

Murata, Johanson, Novacap, Venkel

1/4 W, ±5% (See “AN45: Design Guide for the Si3210 DC-

DC Converter” or Table 19 for value selection)

R19,R20

1/10 W, ±1% (See AN45 or Table 19

for value selection)

R22

F1

22 , 1/10 W, ±5%

Fuse

Belfuse SSQ Series

D1

Ultra Fast Recovery 200 V, 1A Rectifier

General Semi ES1D; Central Semi

CMR1U-02

T1

Power Transformer

Coiltronic CTX01-15275;

Datatronics SM76315;

Midcom 31353R-02

M1

100 V, Logic Level Input MOSFET

Intl Rect. IRLL014N; Intersil

HUF76609D3S; ST Micro

STD5NE10L, STN2NE10L

*Note: Voltage rating of this device must be greater than V_DC

.

QRDN

QTDN

Q3

Q4

5401

R23

RRBN0

3.0k

R24

RTBN0

3.0k

QRP

Q5

QTN

5551

Q6

C8

CTBN

100 nF

5551

C7

CRBN

100 nF

R7

RRE

80.6

R12

RRBN

5.1k

R6

RTE

80.6

R13

RTBN

5.1k

Figure 15. Si321x Optional Equivalent Q5, Q6 Bias Circuit

Rev. 1.0

25

Si3216

Table 17. Si321x Optional Bias Component Values

Component

C7,C8

Value

Supplier/Part Number

Murata, Johanson, Venkel

100 nF, 100 V, X7R, 20%

3.0 k, 1/10 W, 5%

R23,R24

The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5, Q6. For

this optional subcircuit, C7 and C8 are different in voltage and capacitance to the standard circuit. R23 and R24 are

additional components.

Table 18. Component Value Selection for Si321x/Si321xM

Component

Value

Comments

R28 = (V + V )/148 µA

R28

1/10 W, 1% resistor

DD

BE

For V = 3.3 V: 26.1 k

where V is the nominal VBE for Q9

BE

DD

For V = 5.0 V: 37.4 k

DD

R29

1/10 W, 1% resistor

R29 = V

/148 µA

CLAMP

For V

= 80 V: 541 k

= 85 V: 574 k

= 100 V: 676 k

where V

is the clamping voltage for V

CLAMP BAT

CLAMP

Table 19. Component Value Selection Examples for Si321xM MOSFET/Transformer DC-DC Converter

VDC

3.3 V

5.0 V

12 V

24 V

Ringing Load/Loop Resistance

3 REN/117 

Transformer Ratio

R18

R19, R20

7.15 k

16.5 k

56.2 k

121 k

1:2

1:3

1:4

0.06 

0.10 

0.68 

2.20 

5 REN/117 

Note: There are other system and software conditions that influence component value selection; so, please refer to “AN45:

Design Guide for the Si3210 DC-DC Converter” for detailed guidance.

Table 20. Component Value Selection Examples for Si321x BJT/Inductor DC-DC Converter

VDC

5 V

Ringing Load/Loop Length

3 REN/117 

L1

R17

R18

R19, R20

16.5 k

56.2k

33 µH

150 µH

560 µH

100 

162 

274 

0.12 

0.56 

2.2 

12 V

24 V

5 REN/117 

121 k

Note: There are other system and software conditions that influence component value selection, so please refer to “AN45:

Design Guide for the Si3210 DC-DC Converter” for detailed guidance.

26

Rev. 1.0

Si3216

2.1.1. DC Feed Characteristics

2. Functional Description

The ProSLIC has programmable constant voltage and

constant current zones as depicted in Figure 16. Open

The ProSLIC is a single, low-voltage CMOS device that

provides all SLIC, codec, DTMF detection, and signal

generation functions needed for a complete analog

telephone interface. The ProSLIC performs all battery,

overvoltage, ringing, supervision, codec, hybrid, and

test (BORSCHT) functions. The Si3216 supports

wideband (50 Hz–7 kHz) and narrowband (200 Hz–

3.4 kHz) audio codec modes to provide an expanded

audio band at a 16 kHz sample rate for enhanced audio

quality as well as standard telephony audio

compatibility. The Si3216 is ideal for Customer Premise

Equipment (CPE) where enhanced audio quality is

required.

circuit TIP-to-RING voltage (V ) defines the constant

OC

voltage zone and is programmable from 0 V to 94.5 V in

1.5 V steps. The loop current limit (I ) defines the

constant current zone and is programmable from 20 mA

to 41 mA in 3 mA steps. The ProSLIC has an inherent

LIM

dc output resistance (R ) of 160 .

O

V_(TIP-RING)(V)

Constant

Voltage

Zone

V_OC

Unlike most monolithic SLICs, the ProSLIC does not

require externally-supplied, high-voltage battery

supplies. Instead, it generates all necessary battery

voltages from a positive dc supply using its own dc-dc

converter controller. Two fully-programmable tone

generators can produce DTMF tones, phase continuous

FSK (caller ID) signaling, and call progress tones. Pulse

metering signal generation is also integrated. The

Si3201 linefeed interface IC performs all high-voltage

functions. As an option, the Si3201 can be replaced with

low-cost discrete components.

R_O=160 

Constant Current

Zone

I_LIM

I_LOOP(mA)

Figure 16. Simplified DC Current/Voltage

Linefeed Characteristic

The TIP-to-RING voltage (V ) is offset from ground by

OC

a programmable voltage (V ) to provide voltage

CM

The linefeed provides programmable on-hook voltage,

programmable off-hook loop current, reverse battery

operation, loop or ground start operation, and on-hook

transmission ringing voltage. Loop current and voltage

are continuously monitored using an integrated A/D

converter. Balanced 5 REN ringing with or without a

programmable dc offset is integrated. The available

offset, frequency, waveshape, and cadence options are

designed to ring the widest variety of terminal devices

and to reduce external controller requirements.

headroom to the positive-most terminal (TIP in forward

polarity states and RING in reverse polarity states) for

carrying audio signals. Table 21 summarizes the

parameters to be initialized before entering an Active

state.

Table 21. Programmable Ranges of DC

Linefeed Characteristics

Parameter Programmable Default

Register

Bits

Location*

Range

Value

A complete audio transmit and receive path is

integrated, including ac impedance and hybrid gain.

These features are software-programmable, allowing

I_LIM

V_OC

V_CM

20 to 41 mA

20 mA

ILIM[2:0]

VOC[5:0]

VCM[5:0]

Direct

Register 71

for

a

single hardware design to meet global

0 to 94.5 V

48 V

3 V

Direct

Register 72

requirements. Digital voice data transfer occurs over a

standard PCM bus. Control data is transferred using a

standard SPI. The device is available in a 38-pin QFN or

TSSOP.

Direct

Register 73

*Note: The ProSLIC uses registers that are both directly

and indirectly mapped. A “direct” register is one that

is mapped directly.

2.1. Linefeed Interface

The ProSLIC’s linefeed interface offers a rich set of

features and programmable flexibility to meet the

broadest application requirements. The dc linefeed

characteristics are software programmable; key current,

voltage, and power measurements are acquired in real

time and provided in software registers.

Rev. 1.0

27

Si3216

2.1.2. Linefeed Architecture

registers. An internal A/D converter samples the

measured voltages and currents from the analog sense

circuitry and translates them into the digital domain. The

A/D updates the samples at an 800 Hz rate. Two

derived values are also reported—loop voltage and loop

The ProSLIC is a low-voltage CMOS device that uses

either an Si3201 linefeed interface IC or low-cost

external components to control the high voltages

required for subscriber line interfaces. Figure 17 is a

simplified illustration of the linefeed control loop circuit

for TIP or RING and the external components used.

current. The loop voltage, V – V

, is reported as a

TIP

RING

1-bit sign, 6-bit magnitude format. For ground start

operation, the reported value is the RING voltage. The

The ProSLIC uses both voltage and current sensing to

control TIP and RING. DC and ac line voltages on TIP

and RING are measured through sense resistors R

loop current, (I – I + I –I )/2, is reported in a 1-

Q1

Q2

Q5 Q6

bit sign, 6-bit magnitude format. In RING open and TIP

Open states, the loop current is reported as (I – I ) +

DC

Q1

Q2

and R , respectively. The ProSLIC uses linefeed

AC

(I –I ).

Q5 Q6

transistors Q and Q to drive TIP and RING. Q

P

N

DN

isolates the high-voltage base of Q from the ProSLIC.

N

The ProSLIC measures voltage at various nodes in

order to monitor the linefeed current. R , R , and

DC

SE

R

provide access to these measuring points. The

BAT

sense circuitry is calibrated on-chip to guarantee

measurement accuracy with standard external

component tolerances. See 2.1.9."Linefeed Calibration"

on page 33 for details.

2.1.3. Linefeed Operation States

The ProSLIC linefeed has eight states of operation as

shown in Table 22. The state of operation is controlled

using the Linefeed Control register (direct Register 64).

The Open state turns off all currents into the external

bipolar transistors and can be used in the presence of

fault conditions on the line and to generate Open Switch

Intervals (OSIs). TIP and RING are tri-stated with a dc

output impedance of about 150 k. The ProSLIC can

also automatically enter the Open state if it detects

excessive power being consumed in the external bipolar

transistors. See 2.1.5."Power Monitoring and Line Fault

Detection" on page 30 for more details.

In the Forward Active and Reverse Active states,

linefeed circuitry is on, and the audio signal paths are

disabled. In the forward and reverse on-hook

transmission states, audio signal paths are enabled to

provide data transmission during an on-hook loop

condition.

The TIP Open state turns off all control currents to the

external bipolar devices connected to TIP and provides

an active linefeed on RING for ground start operation.

The RING Open state provides similar operation with

the RING drivers off and TIP active.

The Ringing state drives programmable ringing

waveforms onto the line.

2.1.4. Loop Voltage and Current Monitoring

The ProSLIC continuously monitors the TIP and RING

voltages and external BJT currents. These values are

available in registers 78–89. Table 23 on page 30 lists

the values that are measured and their associated

28

Rev. 1.0

Si3216

Audio

Codec

Monitor A/D

A/D

D/A

DSP

D/A

SLIC DAC

Battery Sense

Emitter Sense

AC

Control

DC

Control



AC Sense

DC Sense

R_AC

AC

Control

Loop

Q_DN

DC

Control

Loop

Q_P

C_AC

R_BP

R_DC

R_SE

R_BAT

TIP or

RING

Q_N

R_E

V_BAT

Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown)

Table 22. ProSLIC Linefeed Operations

LF[2:0]*

000

Linefeed State

Open

Description

TIP and RING tri-stated

001

Forward Active

V

> V

TIP

RING

010

Forward On-Hook Transmission

TIP Open

; audio signal paths enabled

011

TIP tri-stated, RING active; used for ground start

Ringing waveform applied to TIP and RING

100

Ringing

101

Reverse Active

V

> V

TIP

RING

110

Reverse On-Hook Transmission

Ring Open

> V ; audio signal paths enabled

TIP

111

RING tri-stated, TIP active

*Note: The Linefeed register (LF) is located in direct Register 64.

Rev. 1.0

29

Si3216

Table 23. Measured Real Time Linefeed Interface Characteristics

Parameter

Measurement

Range

Resolution

Register

Bits

Location*

Loop Voltage Sense (V

– V

)

RING

–94.5 to +94.5 V

1.5 V

LVSP,

Direct Register 78

TIP

LVS[6:0]

Loop Current Sense

–80 to +80 mA

1.27 mA

LCSP,

Direct Register 79

LCS[5:0]

TIP Voltage Sense

RING Voltage Sense

0 to –95.88 V

0 to 81.35 mA

0 to 9.59 mA

0 to 80.58 mA

0.376 V

VTIP[7:0]

Direct Register 80

Direct Register 81

VRING[7:0]

Battery Voltage Sense 1 (V

Battery Voltage Sense 2 (V

)

0.376 V

VBATS1[7:0] Direct Register 82

VBATS2[7:0] Direct Register 83

BAT

0.376 V

Transistor 1 Current Sense

Transistor 2 Current Sense

Transistor 3 Current Sense

Transistor 4 Current Sense

Transistor 5 Current Sense

Transistor 6 Current Sense

0.319 mA

37.6 µA

IQ1[7:0]

IQ2[7:0]

IQ3[7:0]

IQ4[7:0]

IQ5[7:0]

IQ6[7:0]

Direct Register 84

Direct Register 85

Direct Register 86

Direct Register 87

Direct Register 88

Direct Register 89

37.6 µA

0.316 mA

*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped

directly.

2.1.5. Power Monitoring and Line Fault Detection

the type of fault condition present on the line.

In addition to reporting voltages and currents, the The value of each thermal low-pass filter pole is set

ProSLIC continuously monitors the power dissipated in according to the following equation:

each external bipolar transistor. Real time output power

4096

800  

3

of any one of the six linefeed transistors can be read by

setting the Power Monitor Pointer (direct Register 76) to

point to the desired transistor and then reading the Line

Power Output Monitor (direct Register 77).

------------------

thermal LPF register =

 2

where  is the thermal time constant of the transistor

package; 4096 is the full range of the 12-bit register, and

800 is the sample rate in Hertz. Generally  = 3 seconds

for SOT223 packages and 0.16 seconds for SOT23, but

check with the manufacturer for the thermal time

constant of a specific device. For example, the power

alarm threshold and low-pass filter values for Q5 and

Q6 using an SOT223 package transistor are computed

as follows:

The real time power measurements are low-pass

filtered and compared to a maximum power threshold.

Maximum power thresholds and filter time constants are

software-programmable and should be set for each

transistor pair based on the characteristics of the

transistors used. Table 24 describes the registers

associated with this function. If the power in any

external transistor exceeds the programmed threshold,

a power alarm event is triggered. The ProSLIC sets the

Power Alarm register bit, generates an interrupt (if

enabled), and automatically enters the Open state (if

AOPN = 1). This feature protects the external

transistors from fault conditions and, combined with the

loop voltage and current monitors, allows diagnosis of

P_MAX

7

1.28

7

------------------------------

-----------------

PPT56 =

 2

=

 2 = 5389 = 150Dh

Resolution

0.0304

Thus, indirect Register 34 should be set to 150Dh.

Note: The power monitor resolution for Q3 and Q4 is different

from that of Q1, Q2, Q5, and Q6.

30

Rev. 1.0

Si3216

Table 24. Associated Power Monitoring and Power Fault Registers

Parameter

Description/

Range

Resolution

Register

Bits

Location*

0 to 5 points to Q1

to Q6, respectively

N/A

Power Monitor Pointer

PWRMP[2:0]

PWROM[7:0]

Direct Register 76

0 to 7.8 W for Q1,

Q2, Q5, Q6

0 to 0.9 W for Q3,

Q4

30.4 mW

3.62 mW

Line Power Monitor Output

Direct Register 77

Power Alarm Threshold, Q1 & Q2

Power Alarm Threshold, Q3 & Q4

Power Alarm Threshold, Q5 & Q6

0 to 7.8 W

0 to 0.9 W

0 to 7.8 W

30.4 mW

3.62 mW

30.4 mW

PPT12[7:0]

PPT34[7:0]

PPT56[7:0]

Indirect Register 19

Indirect Register 20

Indirect Register 21

See equation in “2.1.5. Power

Monitoring and Line Fault Detec-

tion”

Thermal LPF Pole, Q1 & Q2

Thermal LPF Pole, Q3 & Q4

Thermal LPF Pole, Q5 & Q6

Power Alarm Interrupt Pending

NQ12[7:0]

NQ34[7:0]

NQ56[7:0]

Indirect Register 24

Indirect Register 25

Indirect Register 26

Direct Register 19

See equation in “2.1.5. Power

Monitoring and Line Fault Detec-

tion”

See equation in “2.1.5. Power

Monitoring and Line Fault Detec-

tion”

Bits 2 to 7 corre-

QnAP[n+1],

where n = 1 to 6

spond to Q1 to Q6,

respectively

N/A

Bits 2 to 7 corre-

spond to Q1 to Q6,

respectively

QnAE[n+1],

where n = 1 to 6

Power Alarm Interrupt Enable

Direct Register 22

Direct Register 67

0 = manual mode

1 = enter Open

state upon power

alarm

Power Alarm

Automatic/Manual Detect

N/A

AOPN

*Note: The ProSLIC device uses registers that are both directly and indirectly mapped. A “direct” register is one that is

mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28

through 31).

Rev. 1.0

31

Si3216

LCS

LVS

Input

Signal

Processor

ISP_OUT

Digital

LPF

+

–

LCIP

LCR

Debounce

Filter

Interrupt

Logic

NCLR

LCDI

LCIE

LFS LCVE

HYSTEN

Loop Closure

Threshold

LCRT LCRTL

Figure 18. Loop Closure Detection

2.1.6. Loop Closure Detection

2.1.8. Voltage-Based Loop Closure Detection

A loop closure event signals that the terminal equipment An optional voltage-based loop closure detection mode

has gone off-hook during On-Hook Transmission or On- is enabled by setting LCVE = 1 (direct Register 108,

Hook Active states. The ProSLIC performs loop closure bit 2). In this mode, the loop voltage is compared to the

detection digitally using its on-chip monitor A/D loop closure threshold register (LCRT), which

converter. The functional blocks required to implement represents a minimum voltage threshold instead of a

loop closure detection are shown in Figure 18. The maximum current threshold. If hysteresis is also

primary input to the system is the Loop Current Sense enabled, then LCRT represents the upper voltage

value provided in the LCS register (direct Register 79). boundary and LCRTL represents the lower voltage

The LCS value is processed in the Input Signal boundary for hysteresis. Although voltage-based loop

Processor when the ProSLIC is in the On-Hook closure detection is an option, the default current-based

Transmission or On-Hook Active Linefeed state, as loop closure detection is recommended.

indicated by the Linefeed Shadow register, LFS[2:0]

Table 25. Register Set for Loop

Closure Detection

(direct Register 64). The data then feeds into a

programmable digital low-pass filter, which removes

unwanted ac signal components before threshold

detection.

Parameter

Register

Location

The output of the low-pass filter is compared to a

programmable threshold, LCRT (indirect Register 15).

The threshold comparator output feeds a programmable

debouncing filter. The output of the debouncing filter

remains in its present state unless the input remains in

the opposite state for the entire period of time

programmed by the loop closure debounce interval,

LCDI (direct Register 69). If the debounce interval has

been satisfied, the LCR bit will be set to indicate that a

valid loop closure has occurred. A loop closure interrupt

is generated if enabled by the LCIE bit (direct

Register 22). Table 25 lists the registers that must be

written or monitored to correctly detect a loop closure

condition.

Loop Closure

Interrupt Pending

LCIP

Direct Reg.19

Loop Closure

Interrupt Enable

LCIE

Direct Reg. 22

Loop Closure Threshold LCRT[5:0] Indirect Reg.15

Loop Closure

Threshold—Lower

LCRTL[5:0] Indirect Reg. 66

Loop Closure Filter

Coefficient

NCLR[12:0] Indirect Reg. 22

Loop Closure Detect

Status (monitor only)

LCR

Direct Reg. 68

Direct Reg. 69

Loop Closure Detect

Debounce Interval

LCDI[6:0]

2.1.7. Loop Closure Threshold Hysteresis

Programmable hysteresis to the loop closure threshold

can be enabled by setting HYSTEN = 1 (direct

Register 108, bit 0). The hysteresis is defined by LCRT

(indirect Register 15) and LCRTL (indirect Register 66),

which set the upper and lower bounds, respectively.

Hysteresis Enable

HYSTEN

LCVE

Direct Reg. 108

Voltage-Based Loop

Closure

32

Rev. 1.0

Si3216

2.1.9. Linefeed Calibration

only difference between the two versions is the polarity

of the DCFF pin with respect to the DCDRV pin. For the

Si321x, DCDRV and DCFF are opposite polarity. For

the Si321xM, DCDRV and DCFF are the same polarity.

Table 26 summarizes these differences.

An internal calibration algorithm corrects for internal and

external component errors. The calibration is initiated by

setting the CAL bit in direct Register 96. Upon

completion of the calibration cycle, this bit is

automatically reset.

Table 26. Si321x and Si321xM Differences

It is recommended that a calibration be executed

following system powerup. Upon release of the chip

reset, the ProSLIC is in the Open state. After powering

up the dc-dc converter and allowing it to settle for time

Device

DCFF Signal

Polarity

DCPOL

Si321x

0

1

= DCDRV

(T

) the calibration can be initiated. Additional

SETTLE

Si321xM

calibrations may be performed, but only one calibration

should be necessary as long as the system remains

powered up.

Notes:

1. DCFF signal polarity with respect to DCDRV signal.

2. Direct Register 93, bit 5; This is a read-only bit.

During calibration, V , V , and V voltages are

RING

BAT

TIP

Extensive design guidance on each of these circuits can

be obtained from “AN45: Design Guide for the Si3210

DC-DC Converter” and from an interactive dc-dc

converter design spreadsheet. Both of these documents

are available on the Silicon Laboratories website

(www.silabs.com).

controlled by the calibration engine to provide the

correct external voltage conditions for the algorithm.

Calibration should be performed in the On-Hook state.

RING or TIP must not be connected to ground during

the calibration.

When using the Si3201, automatic calibration routines

for RING gain mismatch and TIP gain mismatch should

2.2.2. BJT/Inductor Circuit Option Using Si321x

not be performed. Instead of running these two The BJT/Inductor circuit option, as defined in Figure 13

calibrations automatically, consult “AN35: Si321x User’s on page 23, offers a flexible, low-cost solution.

Quick Reference Guide”, and follow the instructions for Depending on selected L1 inductance value and the

manual calibration.

switching frequency, the input voltage (V ) can range

DC

from 5 V to 30 V. By nature of a dc-dc converter’s

operation, peak and average input currents can become

large with small input voltages. Consider this when

selecting the appropriate input voltage and power rating

2.2. Battery Voltage Generation and

Switching

The ProSLIC integrates a dc-dc converter controller that

dynamically regulates a single output voltage. This

mode eliminates the need to supply large external

battery voltages. Instead, it converts a single positive

input voltage into the real-time battery voltage needed

for any given state according to programmed linefeed

parameters.

for the V power supply.

DC

For this solution, a PNP power BJT (Q7) switches the

current flow through low ESR inductor L1. The Si3216

uses the DCDRV and DCFF pins to switch Q7 on and

off. DCDRV controls Q7 through NPN BJT Q8. DCFF is

ac-coupled to Q7 through capacitor C10 to assist R16 in

turning off Q7. Therefore, DCFF must have opposite

polarity to DCDRV, and the Si321x (not Si321xM) must

be used.

2.2.1. DC-DC Converter General Description

The dc-dc converter dynamically generates the large

negative voltages required to operate the linefeed

interface. The ProSLIC acts as the controller for a buck-

boost dc-dc converter that converts a positive dc

voltage into the desired negative battery voltage. In

addition to eliminating external power supplies, this

allows the ProSLIC to dynamically control the battery

voltage to the minimum required for any given mode of

operation.

2.2.3. MOSFET/Transformer Circuit Option Using

Si321xM

The MOSFET/transformer circuit option, as defined in

Figure 14 on page 24, offers higher power efficiencies

across a larger input voltage range. Depending on the

transformer’s primary inductor value and the switching

frequency, the input voltage (V ) can range from 3.3 V

DC

to 35 V. Therefore, it is possible to power the entire

ProSLIC solution from a single 3.3 V or 5 V power

supply. By nature of a dc-dc converter’s operation, peak

and average input currents can become large with small

input voltages. Consider this when selecting the

Two different dc-dc circuit options are offered: a BJT/

inductor version and a MOSFET/transformer version.

Due to the differences on the driving circuits, there are

two different versions of the ProSLIC. The Si321x

supports the BJT/inductor circuit option, and the

Si321xM version supports the MOSFET solution. The

appropriate input voltage and power rating for the V

DC

Rev. 1.0

33

Si3216

power supply (number of REN supported).

the register settings to prevent component damage.

These inputs should be calibrated by writing the DCCAL

bit (bit 7) of the dc-dc Converter Switching Delay

register, direct Register 93, after the dc-dc converter

has been turned on.

For this solution, an n-channel power MOSFET (M1)

switches the current flow through a power transformer

T1. T1 is specified in “AN45: Design Guide for the

Si3210/15/16 DC-DC Converter” and includes several

taps on the primary side to facilitate a wide range of Because the ProSLIC dynamically regulates its own

input voltages. The “M” version of the ProSLIC must be battery supply voltage using the dc-dc converter

used for the application circuit depicted in Figure 14 on controller, the battery voltage (V

) is offset from the

BAT

page 24 because the DCFF pin is used to drive M1 negative-most terminal by a programmable voltage

directly and, therefore, must be the same polarity as (V ) to allow voltage headroom for carrying audio

OV

DCDRV. DCDRV is not used in this circuit option; signals.

connecting DCFF and DCDRV together is not

recommended.

As mentioned previously, the ProSLIC dynamically

adjusts V

to suit the particular circuit requirement. To

BAT

2.2.4. DC-DC Converter Architecture

illustrate this, the behavior of V

in the Active state is

BAT

shown in Figure 19. In the Active state, the TIP-to-RING

open circuit voltage is kept at V in the constant

The control logic for a pulse-width modulated (PWM)

dc-dc converter is incorporated in the ProSLIC. Output

pins DCDRV and DCFF are used to switch a bipolar

transistor or MOSFET. The polarity of DCFF is opposite

that of DCDRV.

OC

voltage region while the regulator output voltage,

= V + V + V

V

.

OV

BAT

CM

OC

When the loop current attempts to exceed I , the dc

LIM

line driver circuit enters constant current mode allowing

The dc-dc converter circuit is powered on when the

DCOF bit in the powerdown register (direct Register 14,

bit 4) is cleared to 0. The switching regulator circuit

within the ProSLIC is a high-performance, pulse-width

modulation controller. The control pins are driven by the

PWM controller logic in the ProSLIC. The regulated

the TIP to RING voltage to track R

. As the TIP

LOOP

terminal is kept at a constant voltage, it is the RING

terminal voltage that tracks R and, as a result, the

LOOP

|V

| voltage will also track R

. In this state,

+ V . As R

BAT

LOOP

| = I

x R

+ V

BAT

LIM

LOOP

CM OV LOOP

decreases below the VOC/I

mark, the regulator

LIM

output voltage (V ) is sensed by the SVBAT pin and

BAT

output voltage can continue to track

R

LOOP

used to detect whether the output voltage is above or

below an internal reference for the desired battery

voltage. The dc monitor pins SDCH and SDCL monitor

input current and voltage to the dc-dc converter external

circuitry. If an overload condition is detected, the PWM

controller will turn off the switching transistor for the

remainder of a PWM period to prevent damage to

(TRACK = 1), or the R tracking mechanism is

LOOP

stopped when |V

| = |V

|

(TRACK = 0). The

BAT

BATL

former case is the more common application and

provides the maximum power dissipation savings. In

principle, the regulator output voltage can go as low as

|V

| = V + V , offering significant power savings.

BAT

CM OV

external components. It is important that the proper When TRACK = 0, |V

| does not decrease below

BAT

value of R18 be selected to ensure safe operation.

V

. The RING terminal voltage, however, continues

BATL

Guidance is given in “AN45: Design Guide for the to decrease with decreasing R

. The power

LOOP

Si3210/15/16 DC-DC Converter”.

dissipation on the NPN bipolar transistor driving the

RING terminal can become large and may require a

higher power rating device. The non-tracking mode of

operation is required by specific terminal equipment

which, in order to initiate certain data transmission

modes, goes briefly on-hook to measure the line voltage

to determine whether there is any other off-hook

terminal equipment on the same line. TRACK = 0 mode

is desired since the regulator output voltage has long

settling time constants (tens of milliseconds) and cannot

change rapidly for TRACK = 1 mode. Therefore, the

brief on-hook voltage measurement would yield

approximately the same voltage as the off-hook line

voltage and would cause the terminal equipment to

incorrectly sense another off-hook terminal.

The PWM controller operates at a frequency set by the

dc-dc Converter PWM register (direct Register 92).

During a PWM period the outputs of the control pins

DCDRV and DCFF are asserted for a time given by the

read-only PWM Pulse Width register (direct

Register 94).

The dc-dc converter must be off for some time in each

cycle to allow the inductor or transformer to transfer its

stored energy to the output capacitor, C9. This minimum

off time can be set through the dc-dc Converter

Switching Delay register, (direct Register 93). The

number of 16.384 MHz clock cycles that the controller is

off is equal to DCTOF (bits 0 through 4) plus 4. If the dc

monitor pins detect an overload condition, the dc-dc

converter interrupts its conversion cycles regardless of

34

Rev. 1.0

Si3216

V_OC

I_LIM

R_LOOP

Constant I Region

Constant V Region

V_CM

V_TIP

V_OC

|V_TIP- V_RING

|

V_BATL

TRACK=0

V_OV

V_RING

V_BAT

V_OV

V

Figure 19. V_TIP, V_RING, and V_BATin the Forward Active State

Table 27. Associated Relevant DC-DC Converter Registers

Parameter

Range

Resolution Register Bit

Location

DC-DC Converter Power-Off

Control

N/A

DCOF

Direct Register 14

DC-DC Converter Calibration

Enable/Status

N/A

DCCAL

Direct Register 93

DC-DC Converter PWM Period

DC-DC Converter Min. Off Time

0 to 15.564 µs

61.035 ns

DCN[7:0]

Direct Register 92

Direct Register 93

(0 to 1.892 µs) +

4 ns

DCTOF[4:0]

High Battery Voltage—V

Low Battery Voltage—V

0 to –94.5 V

1.5 V

VBATH[5:0]

VBATL[5:0]

Direct Register 74

Direct Register 75

BATH

BATL

V

0 to –9 V or

0 to –13.5 V

VMIND[3:0]

VOV

Indirect Register 64

Direct Register 66

OV

Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped

directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31).

Rev. 1.0

35

Si3216

2.2.5. DC-DC Converter Enhancements

described above.

The ProSLIC supports two selectable enhancements to

the dc-dc converter. The first is a multi-threshold error

control algorithm that enables the dc-dc converter to

adjust more quickly to voltage changes. This option is

enabled by setting DCSU = 1 (direct Register 108,

bit 5). The second enhancement is an audio band filter

that removes audio band noise from the dc-dc converter

control loop. This option is enabled by setting DCFIL = 1

(direct Register 108, bit 1).

2.3. Tone Generation

Two digital tone generators are provided in the ProSLIC.

They allow the generation of a wide variety of single or

dual tone frequency and amplitude combinations and

spare the user the effort of generating the required

POTS signaling tones on the PCM highway. DTMF, FSK

(caller ID), call progress, and other tones can all be

generated on-chip. The tones can be sent to either the

receive or transmit paths. (See Figure 24 on page 44.)

2.2.6. DC-DC Converter During Ringing

2.3.1. Tone Generator Architecture

When the ProSLIC enters the Ringing state, it requires

voltages well above those used in the active mode. The

voltage to be generated and regulated by the dc-dc

A simplified diagram of the tone generator architecture

is shown in Figure 20. The oscillator, active/inactive

timers, interrupt block, and signal routing block are

connected to give the user flexibility in creating audio

signals. Control and status register bits are placed in the

figure to indicate their association with the tone

generator architecture. These registers are described in

more detail in Table 28 on page 38.

converter during a ringing burst is set using the V

BATH

register (direct Register 74). V

can be set between

BATH

0 and –94.5 V in 1.5 V steps. To avoid clipping the

ringing signal, V must be set larger than the ringing

BATH

amplitude. At the end of each ringing burst the dc-dc

converter adjusts back to active state regulation as

16 kHz

Clock

8 kHz

Clock

OZn

Zero Cross

OnE

OSSn

to TX Path

Enable

Zero

Cross

Logic

Two-Pole

Resonance

Oscillator

16-Bit

Modulo

Counter

OAT

Expire

Signal

Routing

Register

Load

Logic

OIT

Expire

to RX Path

OSCn

OATn

OITn

OnIP REL*

INT

Logic

OATnE

OnSO

OSCnX

OSCnY

OnIE

OITnE

OnAP

INT

Logic

OnAE

*Tone Generator 1 Only

n = "1" or "2" for Tone Generator 1 and 2, respectively

Figure 20. Simplified Tone Generator Diagram

36

Rev. 1.0

Si3216

2.3.2. Oscillator Frequency and Amplitude

Each of the two-tone generators contains a two-pole Each of the two-tone generators contains two timers,

resonant oscillator circuit with programmable one for setting the active period and one for setting the

2.3.3. Tone Generator Cadence Programming

a

frequency and amplitude. These two-tone generators inactive period. The oscillator signal is generated during

are programmed via indirect registers OSC1, OSC1X, the active period and suspended during the inactive

OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate period. Both the active and inactive periods can be

for the two oscillators is 16 kHz. The equations are as programmed from 0 to 8 seconds in 125 µs steps. The

follows:

active period time interval is set using OAT1 (direct

registers 36 and 37) for tone generator 1 and OAT2

(direct registers 40 and 41) for tone generator 2.

coeff = cos(2f /16 kHz),

n

where f is the frequency to be generated;

n

To enable automatic cadence for tone generator 1,

define the OAT1 and OIT1 registers and then set the

O1TAE bit (direct Register 32, bit 4) and O1TIE bit

(direct Register 32, bit 3). This enables each of the

timers to control the state of the Oscillator Enable bit,

O1E (direct Register 32, bit 2). The 16-bit counter

begins counting until the active timer expires, at which

time the 16-bit counter resets to zero and begins

counting until the inactive timer expires. The cadence

continues until the user clears the O1TAE and O1TIE

control bits. The zero crossing detect feature can be

implemented by setting the OZ1 bit (direct Register 32,

bit 5). This ensures that each oscillator pulse ends

without a dc component. The timing diagram in

Figure 21 is an example of an output cadence using the

zero crossing feature.

15

OSCn = coeff x (2 );

n

Desired V_rms

-------------------------------------

1

4

15

1 – coeff

1 + coeff

--

OSCnX =

 -----------------------  2 – 1 

1.11 V_rms

where desired V

is the amplitude to be generated;

OSCnY = 0,

rms

n = 1 or 2 for oscillator 1 or oscillator 2, respectively.

For example, to generate a DTMF digit of 8, the two

required tones are 852 Hz and 1336 Hz. Assuming the

generation of half-scale values (ignoring twist) is

desired, the following values are calculated:

2852

16000









----------------

coeff₁= cos

= 0.94455

One-shot oscillation can be achieved by enabling O1E

and O1TAE. Direct control over the cadence can be

achieved by controlling the O1E bit (direct Register 32,

bit 2) directly if O1TAE and O1TIE are disabled.

OSC1 = 0.944552¹⁵ = 30951 = 78E6h

---------------------  2¹⁵– 1  0.5 = 692 = 2B3h

.05545

1

--

OSC1X =



4

1.94455

The operation of tone generator 2 is identical to that of

tone generator 1 using its respective control registers.

OSC1Y = 0

Note: Tone Generator 2 should not be enabled simultane-

ously with the ringing oscillator due to resource sharing

within the hardware.

21336

16000









--------------------

coeff₂= cos

= 0.86550

15

OSC2 = 0.86550 (2 ) = 28361 = 6EC8h

Continuous phase frequency-shift keying (FSK)

waveforms may be created using tone generator 1 (not

available on tone generator 2) by setting the REL bit

(direct Register 32, bit 6), which enables reloading of

the OSC1, OSC1X, and OSC1Y registers at the

expiration of the active timer (OAT1).

1

0.13450

--

OSC2X =



---------------------  2¹⁵– 1  0.5 = 1098 = 44Bh

4

1.86550

OSC2Y = 0

The above computed values are written to the

corresponding registers to initialize the oscillators. Once

the oscillators are initialized, the oscillator control

registers can be accessed to enable the oscillators and

direct their outputs.

Rev. 1.0

37

Si3216

Table 28. Associated Tone Generator Registers

Tone Generator 1

Parameter

Description/Range

Sets oscillator frequency

Sets oscillator amplitude

Sets initial phase

0 to 8 s

Register Bits

OSC1[15:0]

OSC1X[15:0]

OSC1Y[15:0]

OAT1[15:0]

OIT1[15:0]

Location

Oscillator 1 Frequency Coefficient

Oscillator 1 Amplitude Coefficient

Oscillator 1 initial phase coefficient

Oscillator 1 Active Timer

Indirect Register 0

Indirect Register 1

Indirect Register 2

Direct Registers 36 & 37

Direct Registers 38 & 39

Direct Register 32

Oscillator 1 Inactive Timer

Oscillator 1 Control

0 to 8 s

Status and control

registers

OSS1, REL, OZ1,

O1TAE, O1TIE,

O1E, O1SO[1:0]

Tone Generator 2

Description/Range

Sets oscillator frequency

Sets oscillator amplitude

Sets initial phase

0 to 8 s

Parameter

Register

OSC2[15:0]

OSC2X[15:0]

OSC2Y[15:0]

OAT2[15:0]

OIT2[15:0]

Location

Oscillator 2 Frequency Coefficient

Oscillator 2 Amplitude Coefficient

Oscillator 2 initial phase coefficient

Oscillator 2 Active Timer

Indirect Register 3

Indirect Register 4

Indirect Register 5

Direct Registers 40 & 41

Direct Registers 42 & 43

Direct Register 33

Oscillator 2 Inactive Timer

Oscillator 2 Control

0 to 8 s

Status and control

registers

OSS2, OZ2,

O2TAE, O2TIE,

O2E, O2SO[1:0]

O1E

0,1 ...

..., OAT1 0,1 ...

..., OIT1 0,1 ...

..., OAT1 0,1 ...

...

OSS1

Tone

Gen. 1

Signal

Output

Figure 21. Tone Generator Timing Diagram

38

Rev. 1.0

Si3216

2.3.4. Enhanced FSK Waveform Generation

2.4.1. Ringing Architecture

Enhanced FSK generation capabilities can be enabled The ringing generator architecture is nearly identical to

by setting FSKEN = 1 (direct Register 108, bit 6) and that of the tone generator. The sinusoid ringing

REN = 1 (direct Register 32, bit 6). In this mode, the waveform is generated using an internal two-pole

user can define mark (1) and space (0) attributes once resonance oscillator circuit with programmable

during initialization by defining indirect Registers 69–74. frequency and amplitude. However, since ringing

The user need only indicate 0-to-1 and 1-to-0 transitions frequencies are very low compared to the audio band

in the information stream. By writing to FSKDAT (direct signaling frequencies, the ringing waveform is

Register 52), this mode applies a 24 kHz sample rate to generated at a 1 kHz rate instead of 8 kHz.

tone generator 1 to give additional resolution to timers

The ringing generator has two timers that function the

and frequency generation. “AN32: Si321x Frequency

same as for the tone generator timers. They allow on/off

Shift Keying (FSK) Modulation” gives detailed

cadence settings up to 8 seconds on/ 8 seconds off. In

instructions on how to implement FSK in this mode.

addition to controlling ringing cadence, these timers

Additionally, sample source code is available from

control the transition into and out of the Ringing state.

Silicon Laboratories upon request.

Table 29 summarizes the list of registers used for

2.3.5. Tone Generator Interrupts

ringing generation.

Note: Tone generator 2 should not be enabled concurrently

with the ringing generator due to resource sharing

within the hardware.

Both the active and inactive timers can generate their

own interrupt to signal “on/off” transitions to the

software. The timer interrupts for tone generator 1 can

be individually enabled by setting the O1AE and O1IE When the Ringing state is invoked by writing

bits (direct Register 21, bits 0 and 1, respectively). LF[2:0] = 100 (direct Register 64), the ProSLIC goes

Timer interrupts for tone generator 2 are O2AE and into the Ringing state and starts the first ring. At the

O2IE (direct Register 21, bits 2 and 3, respectively). A expiration of RAT, the ProSLIC turns off the ringing

pending interrupt for each of the timers is determined by waveform and goes to the on-hook transmission state.

reading the O1AP, O1IP, O2AP, and O2IP bits in the Upon expiration of RIT, ringing again initiates. This

Interrupt Status 1 register (direct Register 18, bits 0 process continues as long as the two timers are

through 3, respectively).

enabled and the Linefeed Control register is set to the

Ringing state.

2.4. Ringing Generation

The ProSLIC provides fully-programmable internal

balanced ringing with or without a dc offset to ring a

wide variety of terminal devices. All parameters

associated with ringing are software-programmable:

ringing frequency, waveform, amplitude, dc offset, and

ringing cadence. Both sinusoidal and trapezoidal ringing

waveforms are supported, and the trapezoidal crest

factor is programmable. Ringing signals of up to 90 V

peak or more can be generated, enabling the ProSLIC

to drive a 5 REN (1380  + 40 µF) ringer load across

loop lengths of 2000 feet (160 ) or more.

Rev. 1.0

39

Si3216

Table 29. Registers for Ringing Generation

Parameter

Range/ Description

Register

Bits

Location

Ringing Waveform

Ringing Voltage Offset Enable

Sine/Trapezoid

Enabled/

Disabled

Enabled/

Disabled

Enabled/

Disabled

Enabled/

Disabled

0 to 8 s

TSWS

RVO

Direct Register 34

Ringing Active Timer Enable

Ringing Inactive Timer Enable

Ringing Oscillator Enable

RTAE

RTIE

Direct Register 34

ROE

Ringing Oscillator Active Timer

Ringing Oscillator Inactive Timer

Linefeed Control (Initiates Ringing State)

RAT[15:0]

RIT[15:0]

LF[2:0]

Direct Registers 48 and

49

Direct Registers 50 and

51

0 to 8 s

Direct Register 64

Ringing State = 100_b

High Battery Voltage

Ringing dc voltage offset

Ringing frequency

Ringing amplitude

Ringing initial phase

0 to –94.5 V

0 to 94.5 V

15 to 100 Hz

VBATH[5:0]

ROFF[15:0]

RCO[15:0]

RNGX[15:0]

RNGY[15:0]

Direct Register 74

Indirect Register 6

Indirect Register 7

Indirect Register 8

Indirect Register 9

0 to 94.5 V

Sets initial phase for

sinewave and period

for trapezoid

Common Mode Bias Adjust During Ringing

0 to 22.5 V

VCMR[3:0]

Indirect Register 27

Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped

directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through

31).

2.4.2. Sinusoidal Ringing

equations are as follows:

To configure the ProSLIC for sinusoidal ringing, the

frequency and amplitude are initialized by writing to the

following indirect registers: RCO, RNGX, and RNGY.

The equations for RCO, RNGX, RNGY are as follows:

2  20

1000 Hz



coeff = cos





= 0.99211

----------------------



RCO = 0.99211  2¹⁵ = 32509 = 7EFDh

RCO = coeff  2¹⁵

1

4

15 70

0.00789

1.99211

--

------

= 376 = 0177h

RNGX =



---------------------  2



96

where

RNGY = 0

2f

1000 Hz









----------------------

coeff = cos

In addition, the user must select the sinusoidal ringing

waveform by writing TSWS = 0 (direct Register 34,

bit 0).

and f = desired ringing frequency in hertz.

Desired V_PK0 to 94.5 V

-----------------------------------------------------------------------

96 V

1

4

15

1 – coeff

1 + coeff

2.4.3. Trapezoidal Ringing

--

RNGX =



-----------------------  2



In addition to the sinusoidal ringing waveform, the

ProSLIC supports trapezoidal ringing. Figure 22

illustrates a trapezoidal ringing waveform with offset

RNGY = 0

In selecting a ringing amplitude, the peak TIP-to-RING

ringing voltage must be greater than the selected on-

hook line voltage setting (VOC, direct Register 72). For

V

.

ROFF

example, to generate a 70 V 20 Hz ringing signal, the

PK

40

Rev. 1.0

Si3216

In addition, the user must select the trapezoidal ringing

waveform by writing TSWS = 1 in direct Register 34.

V_TIP-RING

2.4.4. Ringing DC Voltage Offset

A dc offset can be added to the ac ringing waveform by

defining the offset voltage in ROFF (indirect Register 6).

The offset, V

, is added to the ringing signal when

ROFF

RVO is set to 1 (direct Register 34, bit 1). The value of

ROFF is calculated as follows:

V_ROFF

T=1/freq

V_ROFF

15

-----------------

ROFF =

 2

96

t_RISE

time

2.4.5. Linefeed Considerations During Ringing

Care must be taken to keep the generated ringing signal

within the ringing voltage rails (GNDA and V

maintains proper biasing of the external bipolar

) to

BAT

Figure 22. Trapezoidal Ringing Waveform

To configure the ProSLIC for trapezoidal ringing, the transistors. If the ringing signal nears the rails, a

user should follow the same basic procedure as in the distorted ringing signal and excessive power dissipation

Sinusoidal Ringing section, but using the following in the external transistors will result.

equations:

To prevent this invalid operation, set the V

value

BATH

(direct Register 74) to a value higher than the maximum

peak ringing voltage. The discussion below outlines the

considerations and equations that govern the selection

1

2

--

RNGY =  Period  8000

of the V

voltage.

setting for a particular desired peak ringing

Desired V_PK

BATH

 2¹⁵

-----------------------------------

RNGX =

96 V

First, the required amount of ringing overhead voltage,

, is calculated based on the maximum value of

V

OVR

2  RNGX

RCO = --------------------------------

t_RISE 8000

current through the load, I

, the minimum current

LOAD,PK

gain of Q5 and Q6, and a reasonable voltage required

to keep Q5 and Q6 out of saturation. For ringing signals

RCO is a value which is added or subtracted from the

waveform to ramp the signal up or down in a linear

fashion. This value is a function of rise time, period, and

amplitude, where rise time and period are related

through the following equation for the crest factor of a

trapezoidal waveform.

up to V = 87 V, V

= 7.5 V is a safe value.

PK

OVR

However, to determine V

equations below.

for a specific case, use the

OVR

V_AC,PK

N_REN





I_LOAD,PK= ------------------ + I_OS= V_AC,PK ----------------- + I_OS





R_LOAD

6.9 k

3

4

1





--

t_RISE

=

T 1 – ----------

₂

where:

is the ringing REN load (max value = 5),



CF

N

REN

where T = ringing period, and CF = desired crest factor.

I

is the offset current flowing in the line driver circuit

OS

For example, to generate a 71 V , 20 Hz ringing

PK

(max value = 2 mA), and

signal, the equations are as follows:

V

= amplitude of the ac ringing waveform.

AC,PK

1

2

1

It is good practice to provide a buffer of a few more

milliamperes for I to account for possible line

-- ---------------

 8000 = 200 = C8h

RNGY20 Hz =



20 Hz

LOAD,PK

leakages, etc. The total I

smaller than 80 mA.

current should be

LOAD,PK

71

96

 2¹⁵= 24235 = 5EABh

------

RNGX71 V_PK =

For a crest factor of 1.3 and a period of 0.05 s (20 Hz),

the rise time requirement is 0.0153 s.

 + 1

------------

 80.6  + 1 V

V_OVR= I_LOAD,PK





where  is the minimum expected current gain of

transistors Q5 and Q6.

RCO20 Hz, 1.3 crest factor

2  24235

The minimum value for V

following equation:

is, therefore, given by the

BATH

-------------------------------------

=

= 396= 018Ch

0.0153  8000

Rev. 1.0

41

Si3216

The primary input to the system is the Loop Current

Sense (LCS) value provided by the current monitoring

circuitry and reported in direct Register 79. LCS data is

processed by the input signal processor when the

ProSLIC is in the Ringing state as indicated by the

Linefeed Shadow register (direct Register 64). The data

then feeds into a programmable digital low pass filter,

which removes unwanted ac signal components before

threshold detection.

V_BATH= V_AC,PK+ V_ROFF+ V_OVR

The ProSLIC is designed to create a fully-balanced

ringing waveform, meaning that the TIP and RING

common mode voltage, (V

+ V

)/2, is fixed. This

TIP

RING

voltage is referred to as V

set to the following:

and is automatically

CM_RING

V

_BATH– V_CMR

V_{CM_RING}= --------------------------------------

The output of the low-pass filter is compared to a

programmable threshold, RPTP (indirect Register 16).

The threshold comparator output feeds a programmable

debouncing filter. The output of the debouncing filter

remains in its present state unless the input remains in

the opposite state for the entire period of time

programmed by the ring trip debounce interval,

RTDI[6:0] (direct Register 70). If the debounce interval

has been satisfied, the RTP bit of direct Register 68 will

be set to indicate that a valid ring trip has occurred. A

ring trip interrupt is generated if enabled by the RTIE bit

(direct Register 22). Table 30 lists the registers that

must be written or monitored to correctly detect a ring

trip condition.

2

V

is an indirect register, which provides the

headroom by the ringing waveform with respect to the

rail. The value is set as a 4-bit setting in indirect

Register 27 with an LSB voltage of 1.5 V/LSB.

Register 27 should be set with the calculated V

provide voltage headroom during ringing.

CMR

V

BATH

to

OVR

The ProSLIC has a mode to briefly increase the

maximum differential current limit between the voltage

transition of TIP and RING from ringing to a dc linefeed

state. This mode is enabled by setting I

Register 108, bit 7).

= 1 (direct

LIMEN

2.4.6. Ring Trip Detection

The recommended values for RPTP, NRTP, and RTDI

vary according to the programmed ringing frequency.

Register values for various ringing frequencies are

given in Table 31.

A ring trip event signals that the terminal equipment has

gone off-hook during the Ringing state. The ProSLIC

performs ring trip detection digitally using its on-chip A/

D

converter. The functional blocks required to

implement ring trip detection are shown in Figure 23.

Input

Signal

Processor

LCS

ISP_OUT

Digital

LPF

+

–

DBIRAW

RTIP

RTP

Debounce

Filter

Interrupt

Logic

NRTP

RTDI

RTIE

LFS

Ring Trip

Threshold

RPTP

Figure 23. Ring Trip Detector

42

Rev. 1.0

Si3216

Table 30. Associated Registers for Ring Trip Detection

Register

Parameter

Location

Ring Trip Interrupt Pending

Ring Trip Interrupt Enable

RTIP

RTIE

Direct Register 19

Direct Register 22

Direct Register 70

Indirect Register 16

Indirect Register 23

Direct Register 68

Ring Trip Detect Debounce Interval

Ring Trip Threshold

RTDI[6:0]

RPTP[5:0]

NRTP[12:0]

RTP

Ring Trip Filter Coefficient

Ring Trip Detect Status (monitor only)

Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped

directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through

31).

Table 31. Recommended Ring Trip Values for Ringing

Ringing

NRTP

RPTP

RTDI

Frequency

Hz

16.667

20

decimal

64

hex

decimal

34 mA

hex

decimal

15.4 ms

12.3 ms

8.96 ms

7.5 ms

5 ms

hex

0F

0B

09

07

05

0200

0320

0380

0400

06A8

0800

3600

100

112

30

40

128

213

256

50

60

4.8 ms

noise ratio of the transmit path. After passing through an

anti-aliasing filter, the analog signal is processed by the

A/D converter, producing a 16-bit wide, linear PCM data

stream. The standard requirements for transmit path

attenuation for signal frequencies above the audio band

are implemented as part of the combined decimation

filter characteristic of the A/D converter. An additional

filter, THPF, implements the high-pass attenuation

requirements for signals below 50 Hz. The linear PCM

data stream output from THPF is amplified by the

2.5. Audio Path

Unlike traditional SLICs, the codec function is integrated

into the ProSLIC. The 16-bit codec offers software-

selectable 200 Hz to 3.4 kHz narrowband and 50 Hz to

7 kHz (Si3216 only) wideband audio modes,

programmable gain/attenuation blocks, and several

loop-back modes. The signal path block diagram is

shown in Figure 24.

2.5.1. Transmit Path

In the transmit path, the analog signal fed by the external transmit-path programmable gain amplifier, ADCG,

ac coupling capacitors is amplified by the analog which can be programmed from – dB to 6 dB. The final



transmit amplifier, ATX, prior to the A/D converter. ATX step in the transmit path signal processing is the user-

has the following gain options: mute, –3.5, 0, and selectable A-law or µ-law compression block. In

3.5 dB. The main role of ATX is to coarsely adjust the narrowband mode, µ-law or A-law compression can be

signal swing to be as close as possible to the full-scale selected to reduce the data stream word width to 8 bits.

input of the A/D converter to maximize the signal-to-

Rev. 1.0

43

Si3216

44

Rev. 1.0

Si3216

2.5.2. Receive Path

2.5.5. Loopback Testing

In the receive path, digital voice is expanded from µ/A- Four loopback test options are available in the ProSLIC:

law if enabled. DACG is the receive path programmable



The full analog loopback (ALM2) tests almost all the

circuitry of both the transmit and receive paths. The

transmit data stream is fed back serially to the input

of the receive path expander. (See Figure 24.) The

signal path starts with the analog signal at the input

of the transmit path and ends with an analog signal

at the output of the receive path.

gain amplifier which can be programmed from – dB to

6 dB. A 16-bit signal is then provided to a D/A converter.

The resulting analog signal is amplified by the analog

receive amplifier, ARX, which has the following gain

options: mute, –3.5, 0, and 3.5 dB. It is then applied at

the input of the transconductance amplifier (Gm), which

drives the off-chip current buffer (I

).

BUF



An additional analog loopback (ALM1) takes the

digital stream at the output of the A/D converter and

feeds it back to the D/A converter. (See Figure 24.)

The signal path starts with the analog signal at the

input of the transmit path and ends with an analog

signal at the output of the receive path. This

loopback option allows testing of the analog signal

processing circuitry of the ProSLIC completely

independently of any activity in the DSP.

2.5.3. Companding

The ProSLIC supports both µ-255 law and A-law

companding formats when narrowband mode is

selected. µ-255 law is more commonly used in North

America and Japan, while A-law is used primarily in

Europe. Data format is selected using the PCMF

register. Tables 32 and 33 define µ-law and A-law

formats, respectively.



The full digital loopback tests almost all the circuitry

of both the transmit and receive paths. The analog

signal at the output of the receive path is fed back to

the input of the transmit path by way of the hybrid

filter path. (See Figure 24.) The signal path starts

with PCM data input to the receive path and ends

with PCM data at the output of the transmit path.

The dominant source of distortion and noise in both the

transmit and receive paths is the quantization noise

introduced by the µ-law or the A-law compression

process. Figure 3 on page 11 specifies the minimum

signal-to-noise and distortion ratio for either path for a

sine wave input of 200 Hz to 3400 Hz.

Both µ-law and A-law speech encoding allow the audio

codec to transfer and process audio signals larger than

0 dBm0 without clipping. The maximum PCM code is

generated for a µ-law encoded sine wave of 3.17 dBm0

or an A-law encoded sine wave of 3.14 dBm0. The

ProSLIC overload clipping limits are driven by the PCM

encoding process. Figure 4 on page 11 shows the

acceptable limits for the analog-to-analog fundamental

power transfer function, which bounds the behavior of

ProSLIC.



An additional digital loopback (DLM) takes the digital

stream at the input of the D/A converter in the

receive path and feeds it back to the transmit A/D

digital filter. The signal path starts with PCM data

input to the receive path and ends with PCM data at

the output of the transmit path. This loopback option

allows testing of the ProSLIC digital signal

processing circuitry completely independently of any

analog signal processing activity.

2.5.4. Transhybrid Balance

2.6. Two-Wire Impedance Matching

The ProSLIC provides programmable transhybrid

balance with gain block H. (See Figure 24.) In the ideal

case where the synthesized SLIC impedance exactly

matches the subscriber loop impedance, the

transhybrid balance should be set to subtract a –6 dB

level from the transmit path signal. The transhybrid

balance gain can be adjusted from –2.77 dB to

+4.08 dB around the ideal setting of –6 dB by

programming the HYBA[2:0] bits of the Hybrid Control

register (direct Register 11). Adjusting any of the analog

or digital gain blocks does not require any modification

of the transhybrid balance gain block, as the transhybrid

gain is subtracted from the transmit path signal prior to

any gain adjustment stages. The transhybrid balance

can also be disabled, if desired, using the appropriate

register setting.

The ProSLIC provides on-chip programmable two-wire

impedance settings to meet a wide variety of worldwide

two-wire return loss requirements. The two-wire

impedance is programmed by loading one of the eight

available impedance values into the TISS[2:0] bits of the

Two-Wire Impedance Synthesis Control register (direct

Register 10). If direct Register 10 is not user-defined,

the default setting of 600  will be loaded into the TISS

register.

Real and complex two-wire impedances are realized by

internal feedback of a programmable amplifier (RAC), a

switched

capacitor

network

(XAC),

and

a

transconductance amplifier (G ) (See Figure 24.) RAC

m

creates the real portion, and XAC creates the imaginary

portion of the ac impedance. G then creates a current

m

that models the desired impedance value to the

subscriber loop. The differential ac current is fed to the

Rev. 1.0

45

Si3216

subscriber loop via the ITIPP and IRINGP pins through

2.8. Interrupt Logic

an off-chip current buffer (I

), which is implemented

BUF

The ProSLIC is capable of generating interrupts for the

following events:

using transistors Q1 and Q2 (see Figure on page 22).

is referenced to an off-chip resistor (R ).

G

m

15



Loop current/ring ground detected

Ring trip detected

The ProSLIC also provides a means of compensating

for degraded subscriber loop conditions involving

excessive line capacitance (leakage). The CLC[1:0] bits

of direct Register 10 increase the ac signal magnitude

to compensate for the additional loss at the high end of

the audio frequency range. The default setting of

CLC[2:0] assumes no line capacitance.

Power alarm

Active timer 1 expired

Inactive timer 1 expired

Active timer 2 expired

Inactive timer 2 expired

Ringing active timer expired

Ringing inactive timer expired

Indirect register access complete

When 600 + 1 µF or 900 + 2.16 µF impedances are

selected, an internal reference resistor is removed from

the impedance synthesis circuit to accommodate an

external resistor, R

, inserted into the application

ZREF

The interface to the interrupt logic consists of six

registers. Three interrupt status registers contain 1 bit

for each of the above interrupt functions. These bits are

set when an interrupt is pending for the associated

resource. Three interrupt enable registers also contain 1

bit for each interrupt function. In the case of the interrupt

enable registers, the bits are active high. Refer to the

circuit as shown in Figure 25.

C3

R8

to TIP

STIPAC

Si3216

R_ZREF

appropriate

operational details of the interrupt functions.

functional

description

section

for

SRINGAC

R9

to RING

C4

When a resource reaches an interrupt condition, it

signals an interrupt to the interrupt control block. The

interrupt control block then sets the associated bit in the

interrupt status register if the enable bit for that interrupt

is set. The INT pin is an open-drain output and a NOR

of the bits of the interrupt status registers. Therefore, if a

bit in the interrupt status registers is asserted, IRQ

asserts low. Upon receiving the interrupt, the interrupt

handler should read interrupt status registers to

determine which resource is requesting service. To

clear a pending interrupt, write the desired bit in the

appropriate interrupt status register to 1. Writing a 0 has

no effect. This provides a mechanism for clearing

individual bits when multiple interrupts occur

simultaneously. While the interrupt status registers are

non-zero, the INT pin will remain asserted.

For 600 + 1 F, R_ZREF= 12 k and C3, C4 = 100 nF

For 900 + 2.16 F, R_ZREF= 18 k and C3, C4 = 220 nF

Figure 25. R_ZREFExternal Resistor Placement

2.7. Clock Generation

The ProSLIC generates the necessary internal clock

frequencies from the PCLK input. PCLK must be

synchronous to the 8 kHz FSYNC clock and run at one

of the following rates: 256 kHz, 512 kHz, 768 kHz,

1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz, or

8.192 MHz. The ratio of the PCLK rate to the FSYNC

rate is determined via a counter clocked by PCLK. The

three-bit ratio information is automatically transferred

into an internal register, PLL_MULT, following a reset of

the ProSLIC. The internal PLL_MULT register is used to

control the internal PLL, which multiplies PCLK as

needed to generate the 16.384 MHz rate needed to run

the internal filters and other circuitry.

2.9. Serial Peripheral Interface

The control interface to the ProSLIC is a 4-wire interface

modeled after commonly-available microcontroller and

serial peripheral devices. The interface consists of a

clock (SCLK), chip select (CS), serial data input (SDI),

and serial data output (SDO). Data is transferred a byte

at a time with each register access consisting of a pair

of byte transfers. Figures 26 and 27 illustrate read and

write operation in the SPI bus.

The PLL clock synthesizer settles very quickly following

powerup. However, the settling time depends on the

PCLK frequency and it can be approximately predicted

by the following equation:

The first byte of the pair is the command/address byte.

The MSB of this byte indicates a register read when 1

and a register write when 0. The remaining seven bits of

64

F_PCLK

T_SETTLE= ----------------

46

Rev. 1.0

Si3216

the command/address byte indicate the address of the

register to be accessed. The second byte of the pair is

the data byte. During a read operation, the SDO

becomes active, and the 8-bit contents of the register

are driven out MSB first. The SDO will be high

impedence on either the falling edge of SCLK following

the LSB or the rising edge of CS, whichever comes first.

SDI is a “don’t care” during the data portion of read

operations. During write operations, data is driven into

the ProSLIC via the SDI pin MSB first. The SDO pin

remains high-impedance during write operations. Data

always transitions with the falling edge of the clock and

is latched on the rising edge. The clock should return to

a logic high when no transfer is in progress.

the 8 bit transfer (command/address or data).

 SDI/SDO wired operation. Independent of the

clocking options described, SDI and SDO can be

treated as two separate lines or wired together if the

master is capable of tristating its output during the

data byte transfer of a read operation.

 Daisy chain mode. This mode allows

communication with banks of up to eight ProSLIC

devices using one chip select signal. When the

SPIDC bit in the SPI Mode Select register is set,

data transfer mode changes to a 3-byte operation: a

chip select byte, an address/control byte, and a data

byte. Using the circuit shown in Figure 28, a single

device may select from the bank of devices by

setting the appropriate chip select bit to “1”. Each

device uses the LSB of the chip select byte, shifts

the data right by one bit, and passes the chip select

byte using the SDITHRU pin to the next device in the

chain. Address/control and data bytes are unaltered.

There are a number of variations of usage on this four-

wire interface:

 Continuous clocking. During continuous clocking,

the data transfers are controlled by the assertion of

the CS pin. CS must assert before the falling edge of

SCLK on which the first bit of data is expected during

a read cycle and must remain low for the duration of

Don't Care

SCLK

CS

SDI

a6 a5 a4 a3 a2 a1 a0

d7 d6 d5 d4 d3 d2 d1 d0

0

SDO

High Impedance

Figure 26. Serial Write 8-Bit Mode

Don't Care

SCLK

CS

SDI

Don't Care

a6 a5 a4 a3 a2 a1 a0

1

SDO

d7 d6 d5 d4 d3 d2 d1 d0

High Impedance

Figure 27. Serial Read 8-Bit Mode

Rev. 1.0

47

Si3216

SDI0

SDO

CS

SDI

CS

CPU

SDO

SDI

SDITHRU

SDI1

SDI2

SDI3

SDI

CS

SDO

SDITHRU

SDI

CS

SDO

SDITHRU

SDI

CS

SDO

SDITHRU

Chip Select Byte

Address Byte

Data Byte

SCLK

C7 C6 C5 C4 C3 C2 C1 C0

– C7 C6 C5 C4 C3 C2 C1

R/W A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

SDI0

SDI1

SDI2

SDI3

–

C7 C6 C5 C4 C3 C2

–

C7 C6 C5 C4 C3

Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the

LSB of the chip select byte for its chip select.

Figure 28. SPI Daisy Chain Mode

48

Rev. 1.0

Si3216

2.10. PCM Interface

The ProSLIC contains a flexible programmable interface Figure 29 illustrates the use of the PCM in wideband

for the transmission and reception of digital PCM mode. DTX data is high-impedance except for the

samples. PCM data transfer is controlled via the PCLK duration of the 16-bit PCM transmit. DTX returns to

and FSYNC inputs as well as the PCM Mode Select high-impedance either on the negative edge of PCLK

(direct Register 1), PCM Transmit Start Count (direct during the LSB or on the positive edge of PCLK

registers 2 and 3), and PCM Receive Start Count (direct following the LSB. This is based on the setting of the

registers 4 and 5) registers. The interface can be TRI bit of the PCM Mode Select register. Tristating on

configured to support from 2 to 64 16-bit timeslots in the negative edge allows the transmission of data by

each frame. This corresponds to PCLK frequencies of multiple sources in adjacent timeslots without the risk of

256 kHz to 8.192 MHz in power-of-2 increments. driver contention. GCI timing is also supported in which

(768 kHz and 1.536 MHz are also available.) Timeslots the duration of a data bit is two PCLK cycles. This mode

for data transmission and reception are independently is also activated via the PCM Mode Select register.

configured using the TXS and RXS registers. For the Setting the TXS or RXS register greater than the

Si3216 in wideband mode (WBE = 1, PCMF = 11, and number of PCLK cycles in a sample period stops data

PCMT = 1), TXS and RXS set the correct starting point transmission because TXS or RXS never equals the

of the data for the first timeslot within the 8 kHz frame, PCLK count.

and the second timeslot is set to follow 62.5 µs later.

PCLK

FSYNC

63

0

1

0

1

2

3

16 17 18

33 34 35

48

49

PCLK_CNT

DRX

Bit Bit

15 14

Bit Bit

15 14

Bit Bit

1

0

MSB

LSB

Bit Bit

15 14

Bit Bit

15 14

Bit Bit

DTX

1

0

1

0

HI-Z

MSB

LSB

MSB

LSB

Figure 29. Wideband PCM Operation Example, Short FSYNC, PCLK = 512 kHz (TXS/RXS = 1)

Rev. 1.0

49

Si3216

Table 32. µ-Law Encode-Decode Characteristics^1,2

Segment #Intervals X Interval Size

Number

Value at Segment Endpoints Digital Code

Decode Level

8159

10000000

8031

b

.

8

16 X 256

4319

4063

10001111

4191

2079

1023

495

231

99

b

.

7

6

5

4

3

2

16 X 128

16 X 64

16 X 32

16 X 16

16 X 8

2143

2015

10011111

b

.

1055

991

10101111

b

.

511

479

10111111

b

.

239

223

11001111

b

.

103

95

11011111

11101111

11111110

.

16 X 4

15 X 2

35

31

33

.

3

1

0

1

2

0

__________________

1 X 1

b

11111111

Notes:

1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.

2. Digital code includes inversion of all magnitude bits.

50

Rev. 1.0

Si3216

Table 33. A-Law Encode-Decode Characteristics^1,2

Segment

Number

#intervals X interval size Value at segment endpoints Digital Code

Decode Level

4096

3968

.

2176

2048

10101010_b

10100101_b

4032

2112

7

16 X 128

.

6

5

4

3

2

16 X 64

16 X 32

16 X 16

16 X 8

16 X 4

32 X 2

.

1088

1024

10110101_b

10000101_b

10010101_b

11100101_b

11110101_b

11010101_b

1056

528

264

132

66

.

544

512

.

272

256

.

136

128

.

68

64

.

2

0

1

Notes:

1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values.

2. Digital code includes inversion of all even numbered bits.

Rev. 1.0

51

Si3216

3. Control Registers

Note: Any register not listed here is reserved and must not be written.

Table 34. Direct Register Summary

Register Name

Bit 7

Bit 6

Bit 5

Setup

PNI[1:0]

PCME

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

2

SPI Mode Select

SPIDC

PNI2

SPIM

WBE

RNI[3:0]

PCM Mode Select

PCMF[1:0]

PCMT

GCI

TRI

PCM Transmit Start

Count—Low Byte

TXS[7:0]

3

4

5

6

PCM Transmit Start

Count—High Byte

TXS[9:8]

PCM Receive Start

Count—Low Byte

RXS[7:0]

PCM Receive Start

Count—High Byte

RXS[9:8]

Part Number

Identification

PNI[2:0]

TXHP

Audio

8

Audio Path Loopback

Control

ALM2

DLM

ALM1

9

Audio Gain Control

RXHP

TXM

RXM

ATX[1:0]

TISE

ARX[1:0]

TISS[2:0]

10

Two-Wire Impedance

Synthesis Control

CLC[1:0]

11

Hybrid Control

HYBP[2:0]

Powerdown

HYBA[2:0]

14

15

Powerdown Control 1

Powerdown Control 2

DCOF

ADCM ADCON DACM DACON

Interrupts

RGIP

PFR

BIASOF SLICOF

GMM

GMON

18

19

20

21

22

23

Interrupt Status 1

Interrupt Status 2

Interrupt Status 3

Interrupt Enable 1

Interrupt Enable 2

Interrupt Enable 3

RGAP

Q3AP

O2IP

O2AP

Q1AP

O1IP

LCIP

INDP

O1IE

LCIE

INDE

O1AP

RTIP

Q6AP

Q6AE

Q5AP

Q4AP

Q2AP

RGIE

Q4AE

RGAE

Q3AE

O2IE

O2AE

Q1AE

O1AE

RTIE

Q5AE

Q2AE

Indirect Register Access

28

29

30

Indirect Data Access—

Low Byte

IDA[7:0]

Indirect Data Access—

High Byte

IDA[15:8]

IAA[7:0]

Indirect Address

52

Rev. 1.0

Si3216

Table 34. Direct Register Summary (Continued)

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

31

Indirect Address Status

IAS

Oscillators

32

33

34

Oscillator 1 Control

Oscillator 2 Control

OSS1

OSS2

RSS

REL

OZ1

OZ2

O1TAE O1TIE

O2TAE O2TIE

O1E

O2E

ROE

O1SO[1:0]

O2SO[1:0]

Ringing Oscillator

Control

RDAC

RTAE

RTIE

RVO

TSWS

36

37

38

39

40

41

42

43

48

49

50

51

52

Oscillator 1 Active

Timer—Low Byte

OAT1[7:0]

OAT1[15:8]

OIT1[7:0]

OIT1[15:8]

OAT2[7:0]

OAT2[15:8]

OIT2[7:0]

OIT2[15:8]

RAT[7:0]

Oscillator 1 Active

Timer—High Byte

Oscillator 1 Inactive

Timer—Low Byte

Oscillator 1 Inactive

Timer—High Byte

Oscillator 2 Active

Timer—Low Byte

Oscillator 2 Active

Timer—High Byte

Oscillator 2 Inactive

Timer—Low Byte

Oscillator 2 Inactive

Timer—High Byte

Ringing Oscillator

Active Timer—Low Byte

Ringing Oscillator

Active Timer—High Byte

RAT[15:8]

RIT[7:0]

Ringing Oscillator Inac-

tive Timer—Low Byte

Ringing Oscillator Inac-

tive Timer—High Byte

RIT[15:8]

FSK Data

FSKDAT

SLIC

63

Loop Closure Debounce

Interval

LCD[7:0]

64

65

Linefeed Control

LFS[2:0]

CBY

LF[2:0]

AOLD

External Bipolar

Transistor Control

SQH

ETBE

VOV

ETBO[1:0]

FVBAT

ETBA[1:0]

66

67

Battery Feed Control

TRACK

AOPN

Automatic/Manual

Control

MNCM MNDIF SPDS

AORD

Rev. 1.0

53

Si3216

Table 34. Direct Register Summary (Continued)

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

68

69

70

Loop Closure/Ring Trip

Detect Status

DBIRAW

RTP

LCR

Loop Closure Debounce

Interval

LCDI[6:0]

RTDI[6:0]

Ring Trip Detect

Debounce Interval

71

72

73

74

75

76

77

Loop Current Limit

ILIM[2:0]

On-Hook Line Voltage

Common Mode Voltage

High Battery Voltage

Low Battery Voltage

Power Monitor Pointer

VSGN

VOC[5:0]

VCM[5:0]

VBATH[5:0]

VBATL[5:0]

PWRMP[2:0]

Line Power Output

Monitor

PWROM[7:0]

78

79

80

81

82

83

84

Loop Voltage Sense

Loop Current Sense

TIP Voltage Sense

LVSP

LCSP

LVS[5:0]

LCS[5:0]

VTIP[7:0]

VRING[7:0]

RING Voltage Sense

Battery Voltage Sense 1

Battery Voltage Sense 2

VBATS1[7:0]

VBATS2[7:0]

IQ1[7:0]

Transistor 1 Current

Sense

85

86

87

88

89

92

93

94

95

Transistor 2 Current

Sense

IQ2[7:0]

IQ3[7:0]

IQ4[7:0]

IQ5[7:0]

IQ6[7:0]

DCN[7:0]

Transistor 3 Current

Sense

Transistor 4 Current

Sense

Transistor 5 Current

Sense

Transistor 6 Current

Sense

DC-DC Converter PWM

Period

DC-DC Converter

Switching Delay

DCCAL

DCPOL

DCTOF[4:0]

DC-DC Converter PWM

Pulse Width

DCPW[7:0]

Reserved

54

Rev. 1.0

Si3216

Table 34. Direct Register Summary (Continued)

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

96

Calibration Control/

CAL

CALSP CALR

CALT

CALD

CALC

CALIL

Status Register 1

CALM1 CALM2 CALDAC CALADC

CALGMR[4:0]

97

Calibration Control/

Status Register 2

98

RING Gain Mismatch

Calibration Result

99

TIP Gain Mismatch

Calibration Result

CALGMT[4:0]

100

Differential Loop

Current Gain

CALGD[4:0]

Calibration Result

101

Common Mode Loop

Current Gain

CALGC[4:0]

Calibration Result

102

103

Current Limit

Calibration Result

CALGIL[3:0]

Monitor ADC Offset

Calibration Result

CALMG1[3:0]

CALMG2[3:0]

104

105

Analog DAC/ADC Offset

DACP

DACN

ADCP

ADCN

DAC Offset Calibration

Result

DACOF[7:0]

107

108

DC Peak Current Moni-

tor Calibration Result

CMDCPK[3:0]

Enhancement Enable

ILIMEN FSKEN DCSU

LCVE

DCFIL HYSTEN

Rev. 1.0

55

Si3216

Register 0. SPI Mode Select

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

SPIDC

R/W

SPIM

R/W

PNI[1:0]

R

RNI[3:0]

R

Reset settings = 00xx_xxxx

Bit

Name

Function

7

SPIDC

SPI Daisy Chain Mode Enable.

0 = Disable SPI daisy chain mode.

1 = Enable SPI daisy chain mode.

6

SPIM

SPI Mode.

0 = Causes SDO to tri-state on rising edge of SCLK of LSB.

1 = Normal operation; SDO tri-states on rising edge of CS.

5:4

PNI[1:0]

Part Number Identification.

Note: PNI[2:0] can be read in direct register 6.

00 = Si3216

01 = Reserved

10 = Reserved

11 = Si3216M

3:0

RNI[3:0]

Revision Number Identification.

0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc.

56

Rev. 1.0

Si3216

Register 1. PCM Mode Select

Bit

D7

PNI2

R

D6

D5

D4

PCMF[1:0]

R/W

D3

D2

D1

D0

TRI

R/W

Name

Type

WBE

R/W

PCME

R/W

PCMT

R/W

GCI

R/W

Reset settings = 1000_1000

Bit

Name

Function

7

PNI2

Part Number Identification 2.

Note: PNI[2:0] can be read in direct Register 6.

0 = Si3210, Si3211 family.

1 = Si3216 family.

6

WBE

Wideband Enable.

0 = Narrowband (200 Hz–3.4 kHz) audio filtering at 8 kHz sample rate.

1 = Wideband (50 Hz–7 kHz) audio filtering at 16 kHz sample rate when PCMF = 11 and

PCMT = 1.

5

PCME

PCM Enable.

0 = Disable PCM transfers.

1 = Enable PCM transfers.

4:3

PCMF[1:0]

PCM Format.

00 = A-Law

01 = µ-Law

10 = Reserved

11 = Linear

2

1

0

PCMT

GCI

PCM Transfer Size.

0 = 8-bit transfer.

1 = 16-bit transfer.

GCI Clock Format.

0 = 1 PCLK per data bit.

1 = 2 PCLKs per data bit.

TRI

Tri-state Bit 0.

0 = Tri-state bit 0 on positive edge of PCLK.

1 = Tri-state bit 0 on negative edge of PCLK.

Rev. 1.0

57

Si3216

Register 2. PCM Transmit Start Count—Low Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

TXS[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

TXS[7:0]

PCM Transmit Start Count.

PCM transmit start count equals the number of PCLKs following FSYNC before data trans-

mission begins. See Figure 29 on page 49.

Register 3. PCM Transmit Start Count—High Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

TXS[9:8]

R/W

Reset settings = 0000_0000

Bit

7:2

1:0

Name

Function

Reserved

TXS[9:8]

Read returns zero.

PCM Transmit Start Count.

PCM transmit start count equals the number of PCLKs following FSYNC before data

transmission begins. See Figure 29 on page 49.

Register 4. PCM Receive Start Count—Low Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RXS[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

RXS[7:0]

PCM Receive Start Count.

PCM receive start count equals the number of PCLKs following FSYNC before data

reception begins. See Figure 29 on page 49.

58

Rev. 1.0

Si3216

Register 5. PCM Receive Start Count—High Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RXS[9:8]

R/W

Reset settings = 0000_0000

Bit

7:2

1:0

Name

Function

Reserved

RXS[9:8]

Read returns zero.

PCM Receive Start Count.

PCM receive start count equals the number of PCLKs following FSYNC before data

reception begins. See Figure 29 on page 49.

Register 6. Part Number Identification

Bit

D7

D6

PNI[2:0]

R

D5

D4

D3

D2

D1

D0

Name

Type

Reset settings = 0xx0_0000

Bit

Name

Function

7:5

PNI[2:0]

Part Number Identification.

Note: PNI[2] can be read in direct Register 1. PNI[1:0] can be read in direct Register 0.

000 = Reserved

001 = Reserved

010 = Reserved

011 = Reserved

100 = Si3216

101 = Reserved

110 = Reserved

111 = Si3216M

4:0

Reserved

Read returns zero.

Rev. 1.0

59

Si3216

Register 8. Audio Path Loopback Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

ALM2

R/W

DLM

R/W

ALM1

R/W

Reset settings = 0000_0010

Bit

7:3

2

Name

Reserved

ALM2

Function

Read returns zero.

Analog Loopback Mode 2. (See Figure 24 on page 44.)

0 = Full analog loopback mode disabled.

1 = Full analog loopback mode enabled.

1

0

DLM

Digital Loopback Mode. (See Figure 24 on page 44.)

0 = Digital loopback disabled.

1 = Digital loopback enabled.

ALM1

Analog Loopback Mode 1. (See Figure 24 on page 44.)

0 = Analog loopback disabled.

1 = Analog loopback enabled.

60

Rev. 1.0

Si3216

Register 9. Audio Gain Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RXHP

R/W

TXHP

R/W

TXM

R/W

RXM

R/W

ATX[1:0]

R/W

ARX[1:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

RXHP

Receive Path High Pass Filter Disable.

0 = HPF enabled in receive path, RHDF.

1 = HPF bypassed in receive path, RHDF.

6

5

TXHP

TXM

Transmit Path High Pass Filter Disable.

0 = HPF enabled in transmit path, THPF.

1 = HPF bypassed in transmit path, THPF.

Transmit Path Mute.

Refer to position of digital mute in Figure 24 on page 44.

0 = Transmit signal passed.

1 = Transmit signal muted.

4

RXM

Receive Path Mute.

Refer to position of digital mute in Figure 24 on page 44.

0 = Receive signal passed.

1 = Receive signal muted.

3:2

ATX[1:0]

Analog Transmit Path Gain.

00 = 0 dB

01 = –3.5 dB

10 = 3.5 dB

11 = ATX gain = 0 dB; analog transmit path muted.

1:0

ARX[1:0]

Analog Receive Path Gain.

00 = 0 dB

01 = –3.5 dB

10 = 3.5 dB

11 = Analog receive path muted.

Rev. 1.0

61

Si3216

Register 10. Two-Wire Impedance Synthesis Control

Bit

D7

D6

D5

D4

D3

D2

D1

TISS[2:0]

R/W

D0

Name

Type

CLC[1:0]

R/W

TISE

R/W

Reset settings = 0000_1000

Bit

7:6

5:4

Name

Reserved Read returns zero.

Function

CLC[1:0]

Line Capacitance Compensation.

00 = Off

01 = 4.7 nF

10 = 10 nF

11 = Reserved

3

TISE

Two-Wire Impedance Synthesis Enable.

0 = Two-wire impedance synthesis disabled.

1 = Two-wire impedance synthesis enabled.

2:0

TISS[2:0]

Two-Wire Impedance Synthesis Selection.

000 = 600 

001 = 900 

010 = Japan (600  + 1 µF); requires external resistor R

= 12 k and C3, C4 = 100 nF.

ZREF

011 = 900  + 2.16 µF; requires external resistor R

= 18 k and C3, C4 = 220 nF.

ZREF

100 = CTR21 (270  + 750  || 150 nF).

101 = Australia/New Zealand #1 (220  + 820  || 120 nF).

110 = Slovakia/Slovenia/South Africa (220  + 820  || 115 nF).

111 = China (200  + 680  || 100 nF).

62

Rev. 1.0

Si3216

Register 11. Hybrid Control

Bit

D7

D6

D5

HYBP[2:0]

R/W

D4

D3

D2

D1

HYBA[2:0]

R/W

D0

Name

Type

Reset settings = 0011_0011

Bit

7

Name

Function

Reserved

HYBP[2:0]

Read returns zero.

6:4

Pulse Metering Hybrid Adjustment.

000 = 4.08 dB

001 = 2.5 dB

010 = 1.16 dB

011 = 0 dB

100 = –1.02 dB

101 = –1.94 dB

110 = –2.77 dB

111 = Off

3

Reserved

HYBA[2:0]

Read returns zero.

2:0

Audio Hybrid Adjustment.

000 = 4.08 dB

001 = 2.5 dB

010 = 1.16 dB

011 = 0 dB

100 = –1.02 dB

101 = –1.94 dB

110 = –2.77 dB

111 = Off

Rev. 1.0

63

Si3216

Register 14. Powerdown Control 1

Bit

D7

D6

D5

D4

D3

D2

D1

BIASOF

R/W

D0

SLICOF

R/W

Name

Type

DCOF

R/W

PFR

R/W

Reset settings = 0001_0000

Bit

7:5

4

Name

Reserved

DCOF

Function

Read returns zero.

DC-DC Converter Power-Off Control.

0 = Automatic power control.

1 = Override automatic control and force dc-dc circuitry off.

3

PFR

PLL Free-Run Control.

0 = Automatic free-run control.

1 = Override automatic control and force PLL into free-run state.

2

1

Reserved

BIASOF

Read returns zero.

DC Bias Power-Off Control.

0 = Automatic power control.

1 = Override automatic control and force dc bias circuitry off.

0

SLICOF

SLIC Power-Off Control.

0 = Automatic power control.

1 = Override automatic control and force SLIC circuitry off.

64

Rev. 1.0

Si3216

Register 15. Powerdown Control 2

Bit

D7

D6

D5

D4

ADCON

R/W

D3

D2

DACON

R/W

D1

D0

Name

Type

ADCM

R/W

DACM

R/W

GMM

R/W

GMON

R/W

Reset settings = 0000_0000

Bit

7:6

5

Name

Reserved

ADCM

Function

Read returns zero.

Analog to Digital Converter Manual/Automatic Power Control.

0 = Automatic power control.

1 = Manual power control; ADCON controls on/off state.

4

ADCON

Analog to Digital Converter On/Off Power Control.

When ADCM = 1:

0 = Analog to digital converter powered off.

1 = Analog to digital converter powered on.

ADCON has no effect when ADCM = 0.

3

2

DACM

Digital to Analog Converter Manual/Automatic Power Control.

0 = Automatic power control.

1 = Manual power control; DACON controls on/off state.

DACON

Digital to Analog Converter On/Off Power Control.

When DACM = 1:

0 = Digital to analog converter powered off.

1 = Digital to analog converter powered on.

DACON has no effect when DACM = 0.

1

0

GMM

Transconductance Amplifier Manual/Automatic Power Control.

0 = Automatic power control.

1 = Manual power control; GMON controls on/off state.

GMON

Transconductance Amplifier On/Off Power Control.

When GMM = 1:

0 = Analog to digital converter powered off.

1 = Analog to digital converter powered on.

GMON has no effect when GMM = 0.

Rev. 1.0

65

Si3216

Register 18. Interrupt Status 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RGIP

R/W

RGAP

R/W

O2IP

R/W

O2AP

R/W

O1IP

R/W

O1AP

R/W

Reset settings = 0000_0000

Bit

7:6

5

Name

Reserved

RGIP

Function

Read returns zero.

Ringing Inactive Timer Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

4

3

2

1

0

RGAP

O2IP

Ringing Active Timer Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

Oscillator 2 Inactive Timer Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

O2AP

O1IP

Oscillator 2 Active Timer Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

Oscillator 1 Inactive Timer Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

O1AP

Oscillator 1 Active Timer Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

66

Rev. 1.0

Si3216

Register 19. Interrupt Status 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Q6AP

R/W

Q5AP

R/W

Q4AP

R/W

Q3AP

R/W

Q2AP

R/W

Q1AP

R/W

LCIP

R/W

RTIP

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

Q6AP

Power Alarm Q6 Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

6

5

4

3

2

1

0

Q5AP

Q4AP

Q3AP

Q2AP

Q1AP

LCIP

Power Alarm Q5 Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

Power Alarm Q4 Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

Power Alarm Q3 Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

Power Alarm Q2 Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

Power Alarm Q1 Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

Loop Closure Transition Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

RTIP

Ring Trip Interrupt Pending.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

Rev. 1.0

67

Si3216

Register 20. Interrupt Status 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

INDP

R/W

Reset settings = 0000_0000

Bit

7:2

1

Name

Reserved

INDP

Function

Read returns zero.

Indirect Register Access Serviced Interrupt.

This bit is set once a pending indirect register service request has been completed.

Writing 1 to this bit clears a pending interrupt.

0 = No interrupt pending.

1 = Interrupt pending.

0

Reserved

Read returns zero.

68

Rev. 1.0

Si3216

Register 21. Interrupt Enable 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RGIE

R/W

RGAE

R/W

O2IE

R/W

O2AE

R/W

O1IE

R/W

O1AE

R/W

Reset settings = 0000_0000

Bit

7:6

5

Name

Reserved

RGIE

Function

Read/write bit with no function.

Ringing Inactive Timer Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

4

3

2

1

0

RGAE

O2IE

Ringing Active Timer Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

Oscillator 2 Inactive Timer Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

O2AE

O1IE

Oscillator 2 Active Timer Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

Oscillator 1 Inactive Timer Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

O1AE

Oscillator 1 Active Timer Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

Rev. 1.0

69

Si3216

Register 22. Interrupt Enable 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Q6AE

R/W

Q5AE

R/W

Q4AE

R/W

Q3AE

R/W

Q2AE

R/W

Q1AE

R/W

LCIE

R/W

RTIE

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

Q6AE

Power Alarm Q6 Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

6

5

4

3

2

1

0

Q5AE

Q4AE

Q3AE

Q2AE

Q1AE

LCIE

Power Alarm Q5 Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

Power Alarm Q4 Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

Power Alarm Q3 Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

Power Alarm Q2 Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

Power Alarm Q1 Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

Loop Closure Transition Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

RTIE

Ring Trip Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

70

Rev. 1.0

Si3216

Register 23. Interrupt Enable 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

INDE

R/W

Reset settings = 0000_0000

Bit

7:2

1

Name

Reserved

INDE

Function

Read returns zero.

Indirect Register Access Serviced Interrupt Enable.

0 = Interrupt masked.

1 = Interrupt enabled.

0

Reserved

Read/write bit with no function.

Rev. 1.0

71

Si3216

Register 28. Indirect Data Access—Low Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IDA[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

IDA[7:0]

Indirect Data Access—Low Byte.

A write to IDA followed by a write to IAA will place the contents of IDA into an indirect

register at the location referenced by IAA at the next indirect register update (16 kHz

update rate—a write operation). Writing IAA only will load IDA with the value stored at

IAA at the next indirect memory update (a read operation).

Register 29. Indirect Data Access—High Byte

Bit

D7

D6

D5

D4

IDA[15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

IDA[15:8]

Indirect Data Access—High Byte.

A write to IDA followed by a write to IAA will place the contents of IDA into an indirect

register at the location referenced by IAA at the next indirect register update (16 kHz

update rate—a write operation). Writing IAA only will load IDA with the value stored at

IAA at the next indirect memory update (a read operation).

72

Rev. 1.0

Si3216

Register 30. Indirect Address

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IAA[7:0]

R/W

Reset settings = xxxx_xxxx

Bit

Name

Function

7:0

IAA[7:0]

Indirect Address Access.

A write to IDA followed by a write to IAA will place the contents of IDA into an indirect

register at the location referenced by IAA at the next indirect register update (16 kHz

update rate—a write operation). Writing IAA only will load IDA with the value stored at

IAA at the next indirect memory update (a read operation).

Register 31. Indirect Address Status

Bit

D7

D6

D5

D4

D3

D2

D1

D0

IAS

R

Name

Type

Reset settings = 0000_0000

Bit

7:1

0

Name

Reserved

IAS

Function

Read returns zero.

Indirect Access Status.

0 = No indirect memory access pending.

1 = Indirect memory access pending.

Rev. 1.0

73

Si3216

Register 32. Oscillator 1 Control

Bit

D7

OSS1

R

D6

D5

D4

D3

D2

D1

O1SO[1:0]

R/W

D0

Name

Type

REL

R/W

OZ1

R/W

O1TAE

R/W

O1TIE

R/W

O1E

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

OSS1

Oscillator 1 Signal Status.

0 = Output signal inactive.

1 = Output signal active.

6

REL

Oscillator 1 Automatic Register Reload.

This bit should be set for FSK signaling.

0 = Oscillator 1 will stop signaling after inactive timer expires.

1 = Oscillator 1 will continue to read register parameters and output signals.

5

4

OZ1

O1TAE

O1TIE

Oscillator 1 Zero Cross Enable.

0 = Signal terminates after active timer expires.

1 = Signal terminates at zero crossing after active timer expires.

Oscillator 1 Active Timer Enable.

0 = Disable timer.

1 = Enable timer.

3

Oscillator 1 Inactive Timer Enable.

0 = Disable timer.

1 = Enable timer.

2

O1E

Oscillator 1 Enable.

0 = Disable oscillator.

1 = Enable oscillator.

1:0

O1SO[1:0]

Oscillator 1 Signal Output Routing.

00 = Unassigned path (output not connected).

01 = Assign to transmit path.

10 = Assign to receive path.

11 = Assign to both paths.

74

Rev. 1.0

Si3216

Register 33. Oscillator 2 Control

Bit

D7

OSS2

R

D6

D5

D4

O2TAE

R/W

D3

D2

D1

O2SO[1:0]

R/W

D0

Name

Type

OZ2

R/W

O2TIE

R/W

O2E

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

OSS2

Oscillator 2 Signal Status.

0 = Output signal inactive.

1 = Output signal active.

6

5

Reserved

OZ2

Read returns zero.

Oscillator 2 Zero Cross Enable.

0 = Signal terminates after active timer expires.

1 = Signal terminates at zero crossing.

4

3

O2TAE

O2TIE

Oscillator 2 Active Timer Enable.

0 = Disable timer.

1 = Enable timer.

Oscillator 2 Inactive Timer Enable.

0 = Disable timer.

1 = Enable timer.

2

O2E

Oscillator 2 Enable.

0 = Disable oscillator.

1 = Enable oscillator.

1:0

O2SO[1:0]

Oscillator 2 Signal Output Routing.

00 = Unassigned path (output not connected).

01 = Assign to transmit path.

10 = Assign to receive path.

11 = Assign to both paths.

Rev. 1.0

75

Si3216

Register 34. Ringing Oscillator Control

Bit

D7

RSS

R

D6

D5

RDAC

R

D4

D3

D2

ROE

R

D1

D0

Name

Type

RTAE

R/W

RTIE

R/W

RVO

R/W

TSWS

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

RSS

Ringing Signal Status.

0 = Ringing oscillator output signal inactive.

1 = Ringing oscillator output signal active.

6

5

Reserved

RDAC

Read returns zero.

Ringing Signal DAC/Linefeed Cross Indicator.

For ringing signal start and stop, output to TIP and RING is suspended to ensure conti-

nuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at

TIP and RING.

0 = Ringing signal not present at TIP and RING.

1 = Ringing signal present at TIP and RING.

4

3

2

1

0

RTAE

RTIE

ROE

Ringing Active Timer Enable.

0 = Disable timer.

1 = Enable timer.

Ringing Inactive Timer Enable.

0 = Disable timer.

1 = Enable timer.

Ringing Oscillator Enable.

0 = Ringing oscillator disabled.

1 = Ringing oscillator enabled.

RVO

Ringing Voltage Offset.

0 = No dc offset added to ringing signal.

1 = DC offset added to ringing signal.

TSWS

Trapezoid/Sinusoid Waveshape Select.

0 = Sinusoid.

1 = Trapezoid.

76

Rev. 1.0

Si3216

Register 36. Oscillator 1 Active Timer—Low Byte

Bit

D7

D6

D5

D4

OAT1[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

OAT1[7:0]

Oscillator 1 Active Timer.

LSB = 125 µs

Register 37. Oscillator 1 Active Timer—High Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

OAT1[15:8]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

OAT1[15:8]

Oscillator 1 Active Timer.

Register 38. Oscillator 1 Inactive Timer—Low Byte

Bit

D7

D6

D5

D4

OIT1[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

OIT1[7:0]

Oscillator 1 Inactive Timer.

LSB = 125 µs

Rev. 1.0

77

Si3216

Register 39. Oscillator 1 Inactive Timer—High Byte

Bit

D7

D6

D5

D4

OIT1[15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

OIT1[15:8]

Oscillator 1 Inactive Timer.

Register 40. Oscillator 2 Active Timer—Low Byte

Bit

D7

D6

D5

D4

OAT2[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

OAT2[7:0]

Oscillator 2 Active Timer.

LSB = 125 µs

Register 41. Oscillator 2 Active Timer—High Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

OAT2[15:8]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

OAT2[15:8]

Oscillator 2 Active Timer.

78

Rev. 1.0

Si3216

Register 42. Oscillator 2 Inactive Timer—Low Byte

Bit

D7

D6

D5

D4

OIT2[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

OIT2[7:0]

Oscillator 2 Inactive Timer.

LSB = 125 µs

Register 43. Oscillator 2 Inactive Timer—High Byte

Bit

D7

D6

D5

D4

OIT2[15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

OIT2[15:8]

Oscillator 2 Inactive Timer.

Register 48. Ringing Oscillator Active Timer—Low Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RAT[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

RAT[7:0]

Ringing Active Timer.

LSB = 125 µs

Rev. 1.0

79

Si3216

Register 49. Ringing Oscillator Active Timer—High Byte

Bit

D7

D6

D5

D4

RAT[15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

RAT[15:8]

Ringing Active Timer.

Register 50. Ringing Oscillator Inactive Timer—Low Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RIT[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

RIT[7:0]

Ringing Inactive Timer.

LSB = 125 µs

Register 51. Ringing Oscillator Inactive Timer—High Byte

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RIT[15:8]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

RIT[15:8]

Ringing Inactive Timer.

80

Rev. 1.0

Si3216

Register 52. FSK Data

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

FSKDAT

R/W

Reset settings = 0000_0000

Bit

7:1

0

Name

Function

Reserved

FSKDAT

Read returns zero.

FSK Data.

When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this

bit serves as the buffered input for FSK generation bit stream data.

Register 63. Loop Closure Debounce Interval

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

LCD[7:0]

Reset settings = 0101_0100

Bit

Name

Function

7:0

LCD[7:0]

Loop Closure Debounce Interval for Automatic Ringing.

This register sets the loop closure debounce interval for the ringing silent period when

using automatic ringing cadences. The value may be set between 0 ms (0x00) and

159 ms (0x7F) in 1.25 ms steps.

Rev. 1.0

81

Si3216

Register 64. Linefeed Control

Bit

D7

D6

D5

LFS[2:0]

R

D4

D3

D2

D1

D0

Name

Type

LF[2:0]

R/W

Reset settings = 0000_0000

Bit

7

Name

Reserved

LFS[2:0]

Function

Read returns zero.

6:4

Linefeed Shadow.

This register reflects the actual real time linefeed state. Automatic operations may cause

actual linefeed state to deviate from the state defined by linefeed register (e.g., when

linefeed equals Ringing state, LFS will equal on-hook transmission state during ringing

silent period and Ringing state during ring burst).

000 = Open

001 = Forward active

010 = Forward on-hook transmission

011 = TIP open

100 = Ringing

101 = Reverse active

110 = Reverse on-hook transmission

111 = RING open

3

Reserved

LF[2:0]

Read returns zero.

2:0

Linefeed.

Writing to this register sets the linefeed state.

000 = Open

001 = Forward active

010 = Forward on-hook transmission

011 = TIP open

100 = Ringing

101 = Reverse active

110 = Reverse on-hook transmission

111 = RING open

82

Rev. 1.0

Si3216

Register 65. External Bipolar Transistor Control

Bit

D7

D6

D5

D4

D3

D2

D1

ETBA[1:0]

R/W

D0

Name

Type

SQH

R/W

CBY

R/W

ETBE

R/W

ETBO[1:0]

R/W

Reset settings = 0110_0001

Bit

7

Name

Reserved

SQH

Function

Read returns zero.

6

Audio Squelch.

0 = No squelch.

1 = STIPAC and SRINGAC pins squelched.

5

4

CBY

ETBE

Capacitor Bypass.

0 = Capacitors CP (C1) and CM (C2) in circuit.

1 = Capacitors CP (C1) and CM (C2) bypassed.

External Transistor Bias Enable.

0 = Bias disabled.

1 = Bias enabled.

3:2

ETBO[1:0]

External Transistor Bias Levels—On-Hook Transmission State.

DC bias current which flows through external BJTs in the on-hook transmission state.

Increasing this value increases the compliance of the ac longitudinal balance circuit.

00 = 4 mA

01 = 8 mA

10 = 12 mA

11 = Reserved

1:0

ETBA[1:0]

External Transistor Bias Levels—Active Off-Hook State.

DC bias current which flows through external BJTs in the active off-hook state. Increasing

this value increases the compliance of the ac longitudinal balance circuit.

00 = 4 mA

01 = 8 mA

10 = 12 mA

11 = Reserved

Rev. 1.0

83

Si3216

Register 66. Battery Feed Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

TRACK

R/W

Name

Type

VOV

R/W

FVBAT

R/W

Reset settings = 0000_0011

Bit

7:5

4

Name

Reserved

VOV

Function

Read returns zero.

Overhead Voltage Range Increase. (See Figure 19 on page 35.)

This bit selects the programmable range for V , which is defined in indirect Register 41.

OV

0 = V = 0 V to 9 V

OV

1 = V = 0 V to 13.5 V

OV

3

FVBAT

V

Manual Setting.

BAT

0 = Normal operation.

1 = V tracks VBATH register.

BAT

2:1

0

Reserved

TRACK

Read returns zero.

DC-DC Converter Tracking Mode.

0 = |V

1 = V

| will not decrease below VBATL.

BAT

tracks V

.

RING

84

Rev. 1.0

Si3216

Register 67. Automatic/Manual Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

MNCM

R/W

MNDIF

R/W

SPDS

R/W

AORD

R/W

AOLD

R/W

AOPN

R/W

Reset settings = 0001_1111

Bit

7

Name

Reserved

MNCM

Function

Read returns zero.

6

Common Mode Manual/Automatic Select.

0 = Automatic control.

1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow

VCM value.

5

4

MNDIF

SPDS

Differential Mode Manual/Automatic Select.

0 = Automatic control.

1 = Manual control (forces differential voltage to follow VOC value).

Speed-Up Mode Enable.

0 = Speed-up disabled.

1 = Automatic speed-up.

3

2

Reserved

AORD

Read returns zero.

Automatic/Manual Ring Trip Detect.

0 = Manual mode.

1 = Enter off-hook Active state automatically upon ring trip detect.

1

0

AOLD

AOPN

Automatic/Manual Loop Closure Detect.

0 = Manual mode.

1 = Enter off-hook Active state automatically upon loop closure detect.

Power Alarm Automatic/Manual Detect.

0 = Manual mode.

1 = Enter Open state automatically upon power alarm.

Rev. 1.0

85

Si3216

Register 68. Loop Closure/Ring Trip Detect Status

Bit

D7

D6

D5

D4

D3

D2

DBIRAW

R

D1

RTP

R

D0

LCR

R

Name

Type

Reset settings = 0000_0000

Bit

7:3

2

Name

Function

Reserved

DBIRAW

Read returns zero.

Ring Trip/Loop Closure Unfiltered Output.

The state of this bit reflects the real time output of ring trip and loop closure detect circuits

before debouncing.

0 = Ring trip/loop closure threshold exceeded.

1 = Ring trip/loop closure threshold not exceeded.

1

0

RTP

LCR

Ring Trip Detect Indicator (Filtered Output).

0 = Ring trip detect has not occurred.

1 = Ring trip detect occurred.

Loop Closure Detect Indicator (Filtered Output).

0 = Loop closure detect has not occurred.

1 = Loop closure detect has occurred.

Register 69. Loop Closure Debounce Interval

Bit

D7

D6

D5

D4

D3

LCDI[6:0]

R/W

D2

D1

D0

Name

Type

Reset settings = 0000_1010

Bit

7

Name

Function

Reserved

LCDI[6:0]

Read returns zero.

6:0

Loop Closure Debounce Interval.

The value written to this register defines the minimum steady state debounce time. Value

may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default

value = 12.5 ms.

86

Rev. 1.0

Si3216

Register 70. Ring Trip Detect Debounce Interval

Bit

D7

D6

D5

D4

D3

RTDI[6:0]

R/W

D2

D1

D0

Name

Type

Reset settings = 0000_1010

Bit

7

Name

Function

Reserved

RTDI[6:0]

Read returns zero.

6:0

Ring Trip Detect Debounce Interval.

The value written to this register defines the minimum steady state debounce time. The

value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default

value = 12.5 ms.

Register 71. Loop Current Limit

Bit

D7

D6

D5

D4

D3

D2

D1

ILIM[2:0]

R/W

D0

Name

Type

Reset settings = 0000_0000

Bit

7:3

2:0

Name

Function

Reserved

ILIM[2:0]

Read returns zero.

Loop Current Limit.

The value written to this register sets the constant loop current. The value may be set

between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps.

Rev. 1.0

87

Si3216

Register 72. On-Hook Line Voltage

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VSGN

R/W

VOC[5:0]

R/W

Reset settings = 0010_0000

Bit

7

Name

Reserved

VSGN

Function

Read returns zero.

6

On-Hook Line Voltage.

The value written to this bit sets the on-hook line voltage polarity (V –V

).

RING

TIP

0 = V –V

is positive.

is negative.

TIP

RING

1 = V –V

TIP

5:0

VOC[5:0]

On-Hook Line Voltage.

The value written to this register sets the on-hook line voltage (V –V

). Value may

RING

TIP

be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V.

Register 73. Common Mode Voltage

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VCM[5:0]

R/W

Reset settings = 0000_0010

Bit

7:6

5:0

Name

Function

Reserved

VCM[5:0]

Read returns zero.

Common Mode Voltage.

The value written to this register sets V

for forward active and forward on-hook trans-

TIP

mission states and V

for reverse active and reverse on-hook transmission states.

RING

The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default

value = –3 V.

88

Rev. 1.0

Si3216

Register 74. High Battery Voltage

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VBATH[5:0]

R/W

Reset settings = 0011_0010

Bit

7:6

5:0

Name

Function

Reserved

VBATH[5:0]

Read returns zero.

High Battery Voltage.

The value written to this register sets high battery voltage. V

must be greater than or

BATH

equal to V

. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V

BATL

steps. Default value = –75 V.

Register 75. Low Battery Voltage

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VBATL[5:0]

R/W

Reset settings = 0001_0000

Bit

7:6

5:0

Name

Function

Reserved

VBATL[5:0]

Read returns zero.

Low Battery Voltage.

The value written to this register sets low battery voltage. V

must be greater than or

BATH

equal to V

. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V

BATL

steps. Default value = –24 V.

Rev. 1.0

89

Si3216

Register 76. Power Monitor Pointer

Bit

D7

D6

D5

D4

D3

D2

D1

PWRMP[2:0]

R/W

D0

Name

Type

Reset settings = 0000_0000

Bit

7:3

2:0

Name

Function

Reserved

Read returns zero.

PWRMP[2:0] Power Monitor Pointer.

Selects the external transistor from which to read power output. The power of the

selected transistor is read in the PWROM register.

000 = Q1

001 = Q2

010 = Q3

011 = Q4

100 = Q5

101 = Q6

110 = Undefined

111 = Undefined

Register 77. Line Power Output Monitor

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

PWROM[7:0]

R

Reset settings = 0000_0000

Bit

Name

PWROM[7:0] Line Power Output Monitor.

Function

7:0

This register reports the real time power output of the transistor selected using PWRMP.

The range is 0 W (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6.

The range is 0 W (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4.

90

Rev. 1.0

Si3216

Register 78. Loop Voltage Sense

Bit

D7

D6

LVSP

R

D5

D4

D3

D2

D1

D0

Name

Type

LVS[5:0]

R

Reset settings = 0000_0000

Bit

7

Name

Reserved

LVSP

Function

Read returns zero.

6

Loop Voltage Sense Polarity.

This register reports the polarity of the differential loop voltage (V

– V

).

TIP

RING

0 = Positive loop voltage (V

> V

).

RING

TIP

1 = Negative loop voltage (V

< V

).

RING

TIP

5:0

LVS[5:0]

Loop Voltage Sense Magnitude.

This register reports the magnitude of the differential loop voltage (V – V

). The

TIP

RING

range is 0 V to 94.5 V in 1.5 V steps.

Register 79. Loop Current Sense

Bit

D7

D6

LCSP

R

D5

D4

D3

D2

D1

D0

Name

Type

LCS[5:0]

R

Reset settings = 0000_0000

Bit

7

Name

Reserved

LCSP

Function

Read returns zero.

6

Loop Current Sense Polarity.

This register reports the polarity of the loop current.

0 = Positive loop current (forward direction).

1 = Negative loop current (reverse direction).

5:0

LCS[5:0]

Loop Current Sense Magnitude.

This register reports the magnitude of the loop current. The range is 0 mA to 78.75 mA in

1.25 mA steps.

Rev. 1.0

91

Si3216

Register 80. TIP Voltage Sense

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VTIP[7:0]

R

Reset settings = 0000_0000

Bit

Name

Function

7:0

VTIP[7:0]

TIP Voltage Sense.

This register reports the real time voltage at TIP with respect to ground. The range is 0 V

(0x00) to –95.88 V (0xFF) in. 376 V steps.

Register 81. RING Voltage Sense

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VRING[7:0]

R

Reset settings = 0000_0000

Bit

Name

Function

7:0

VRING[7:0]

RING Voltage Sense.

This register reports the real time voltage at RING with respect to ground. The range is

0 V (0x00) to –95.88 V (0xFF) in .376 V steps.

Register 82. Battery Voltage Sense 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VBATS1[7:0]

R

Reset settings = 0000_0000

Bit

Name

VBATS1[7:0] Battery Voltage Sense 1.

Function

7:0

This register is one of two registers that reports the real time voltage at V

to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps.

with respect

BAT

92

Rev. 1.0

Si3216

Register 83. Battery Voltage Sense 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VBATS2[7:0]

R

Reset settings = 0000_0000

Bit

Name

VBATS2[7:0] Battery Voltage Sense 2.

Function

7:0

This register is one of two registers that reports the real time voltage at V

to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps.

with respect

BAT

Register 84. Transistor 1 Current Sense

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IQ1[7:0]

R

Reset settings = xxxx_xxxx

Bit

Name

Function

7:0

IQ1[7:0]

Transistor 1 Current Sense.

This register reports the real time current through Q1. The range is 0 A (0x00) to

81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the

additional ETBO/A current.

Register 85. Transistor 2 Current Sense

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IQ2[7:0]

R

Reset settings = xxxx_xxxx

Bit

Name

Function

7:0

IQ2[7:0]

Transistor 2 Current Sense.

This register reports the real time current through Q2. The range is 0 A (0x00) to

81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the

additional ETBO/A current.

Rev. 1.0

93

Si3216

Register 86. Transistor 3 Current Sense

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IQ3[7:0]

R

Reset settings = xxxx_xxxx

Bit

Name

Function

7:0

IQ3[7:0]

Transistor 3 Current Sense.

This register reports the real time current through Q3. The range is 0 A (0x00) to

9.59 mA (0xFF) in 37.6 µA steps.

Register 87. Transistor 4 Current Sense

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IQ4[7:0]

R

Reset settings = xxxx_xxxx

Bit

Name

Function

7:0

IQ4[7:0]

Transistor 4 Current Sense.

This register reports the real time current through Q4. The range is 0 A (0x00) to

9.59 mA (0xFF) in 37.6 µA steps.

Register 88. Transistor 5 Current Sense

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IQ5[7:0]

R

Reset settings = xxxx_xxxx

Bit

Name

Function

7:0

IQ5[7:0]

Transistor 5 Current Sense.

This register reports the real time current through Q5. The range is 0 A (0x00) to

80.58 mA (0xFF) in .316 mA steps.

94

Rev. 1.0

Si3216

Register 89. Transistor 6 Current Sense

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IQ6[7:0]

R

Reset settings = xxxx_xxxx

Bit

Name

Function

7:0

IQ6[7:0]

Transistor 6 Current Sense.

This register reports the real time current through Q6. The range is 0 A (0x00) to

80.58 mA (0xFF) in .316 mA steps.

Register 92. DC-DC Converter PWM Period

Bit

Name DCN[7]

Type R/W

D7

D6

1

D5

D4

D3

D2

D1

D0

DCN[5:0]

R

R/W

Reset settings = 1111_1111

Bit

Name

Function

7:0

DCN[7:0]

DC-DC Converter Period.

This register sets the PWM period for the dc-dc converter. The range is 3.906 µs (0x40)

to 15.564 µs (0xFF) in 61.035 ns steps.

Bit 6 is fixed to one and read-only, so there are two ranges of operation:

3.906–7.751 µs, used for MOSFET transistor switching (Si3216M).

11.719–15.564 µs, used for BJT transistor switching (Si3216).

Rev. 1.0

95

Si3216

Register 93. DC-DC Converter Switching Delay

Bit

Name DCCAL

Type R/W

D7

D6

D5

DCPOL

R

D4

D3

D2

DCTOF[4:0]

R/W

D1

D0

Reset settings = 0001_0100 (Si3216)

Reset settings = 0011_0100 (Si3216M)

Bit

Name

Function

7

DCCAL

DC-DC Converter Peak Current Monitor Calibration Status.

Writing a one to this bit starts the dc-dc converter peak current monitor calibration rou-

tine.

0 = Normal operation.

1 = Calibration being performed.

6

5

Reserved

DCPOL

Read returns zero.

DC-DC Converter Feed Forward Pin (DCFF) Polarity.

This read-only register bit indicates the polarity relationship of the DCFF pin to the

DCDRV pin. Two versions of the Si3216 are offered to support the two relationships.

0 = DCFF pin polarity is opposite of DCDRV pin (Si3216).

1 = DCFF pin polarity is same as DCDRV pin (Si3216M).

4:0

DCTOF[4:0]

DC-DC Converter Minimum Off Time.

This register sets the minimum off time for the pulse width modulated dc-dc

converter control. T

= (DCTOF + 4)x61.035 ns.

OFF

Register 94. DC-DC Converter PWM Pulse Width

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DCPW[7:0]

R

Reset settings = 0000_0000

Bit

Name

Function

7:0

DCPW[7:0]

DC-DC Converter Pulse Width.

Pulse width of DCDRV is given by PW = (DCPW – DCTOF – 4) x 61.035 ns.

96

Rev. 1.0

Si3216

Register 96. Calibration Control/Status Register 1

Bit

D7

D6

D5

CALSP

R/W

D4

D3

D2

D1

D0

Name

Type

CAL

R/W

CALR

R/W

CALT

R/W

CALD

R/W

CALC

R/W

CALIL

R/W

Reset settings = 0001_1111

Bit

7

Name

Reserved

CAL

Function

Read returns zero.

6

Calibration Control/Status Bit.

Setting this bit begins calibration of the entire system.

0 = Normal operation or calibration complete.

1 = Calibration in progress.

5

4

3

CALSP

CALR

CALT

Calibration Speedup.

Setting this bit shortens the time allotted for V

calibration cycle.

0 = 300 ms

1 = 30 ms

settling at the beginning of the

BAT

RING Gain Mismatch Calibration.

For use with discrete solution only. When using the Si3201, consult “AN35: Si321x

User’s Quick Reference Guide” and follow the instructions for manual calibration.

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

TIP Gain Mismatch Calibration.

For use with discrete solution only. When using the Si3201, consult “AN35: Si321x

User’s Quick Reference Guide” and follow the instructions for manual calibration.

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

2

1

0

CALD

CALC

CALIL

Differential DAC Gain Calibration.

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

Common Mode DAC Gain Calibration.

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

I

Calibration.

LIM

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

Rev. 1.0

97

Si3216

Register 97. Calibration Control/Status Register 2

Bit

D7

D6

D5

D4

CALM1

R/W

D3

D2

D1

D0

Name

Type

CALM2 CALDAC CALADC

R/W

Reset settings = 0001_1110

Bit

7:5

4

Name

Reserved

CALM1

Function

Read returns zero.

Monitor ADC Calibration 1.

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

3

2

CALM2

Monitor ADC Calibration 2.

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

CALDAC

DAC Calibration.

Setting this bit begins calibration of the audio DAC offset.

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

1

0

CALADC

Reserved

ADC Calibration.

Setting this bit begins calibration of the audio ADC offset.

0 = Normal operation or calibration complete.

1 = Calibration enabled or in progress.

Read returns zero.

98

Rev. 1.0

Si3216

Register 98. RING Gain Mismatch Calibration Result

Bit

D7

D6

D5

D4

D3

D2

CALGMR[4:0]

R/W

D1

D0

Name

Type

Reset settings = 0001_0000

Bit

7:5

4:0

Name

Function

Reserved

Read returns zero.

CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current.

Register 99. TIP Gain Mismatch Calibration Result

Bit

D7

D6

D5

D4

D3

D2

CALGMT[4:0]

R/W

Name

Type

Reset settings = 0001_0000

Bit

7:5

4:0

Name

Function

Reserved

Read returns zero.

CALGMT[4:0] Gain Mismatch of IE Tracking Loop for TIP Current.

Register 100. Differential Loop Current Gain Calibration Result

Bit

D7

D6

D5

D4

D3

D2

CALGD[4:0]

R/W

Name

Type

Reset settings = 0001_0001

Bit

7:5

4:0

Name

Function

Reserved

CALGD[4:0]

Read returns zero.

Differential DAC Gain Calibration Result.

Rev. 1.0

99

Si3216

Register 101. Common Mode Loop Current Gain Calibration Result

Bit

D7

D6

D5

D4

D3

D2

CALGC[4:0]

R/W

D1

D0

Name

Type

Reset settings = 0001_0001

Bit

7:5

4:0

Name

Function

Reserved

CALGC[4:0]

Read returns zero.

Common Mode DAC Gain Calibration Result.

Register 102. Current Limit Calibration Result

Bit

D7

D6

D5

D4

D3

D2

CALGIL[3:0]

R/W

D1

Name

Type

Reset settings = 0000_1000

Bit

7:4

3:0

Name

Function

Reserved

CALGIL[3:0]

Read returns zero.

Current Limit Calibration Result.

Register 103. Monitor ADC Offset Calibration Result

Bit

D7

D6

D5

D4

D3

D2

D1

Name

Type

CALMG1[3:0]

R/W

CALMG2[3:0]

R/W

Reset settings = 1000_1000

Bit

7:4

3:0

Name

Function

CALMG1[3:0] Monitor ADC Offset Calibration Result 1.

CALMG2[3:0] Monitor ADC Offset Calibration Result 2.

100

Rev. 1.0

Si3216

Register 104. Analog DAC/ADC Offset

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DACP

R/W

DACN

R/W

ADCP

R/W

ADCN

R/W

Reset settings = 0000_0000

Bit

7:4

3

Name

Reserved

DACP

Function

Read returns zero.

Positive Analog DAC Offset.

Negative Analog DAC Offset.

Positive Analog ADC Offset.

Negative Analog ADC Offset.

2

DACN

1

ADCP

0

ADCN

Register 105. DAC Offset Calibration Result

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DACOF[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

DACOF[7:0]

DAC Offset Calibration Result.

Register 107. DC Peak Current Monitor Calibration Result

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CMDCPK[3:0]

R/W

Reset settings = 0000_1000

Bit

7:4

3:0

Name

Function

Reserved

Read returns zero.

CMDCPK[3:0] DC Peak Current Monitor Calibration Result.

Rev. 1.0

101

Si3216

Register 108. Enhancement Enable

Bit

Name ILIMEN

Type R/W

D7

D6

FSKEN

R/W

D5

D4

D3

D2

D1

D0

HYSTEN

R/W

DCSU

R/W

LCVE

R/W

DCFIL

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

ILIMEN

Current Limit Increase.

When enabled, this bit temporarily increases the maximum differential current limit at the

end of a ring burst to enable a faster settling time to a dc linefeed state.

0 = The value programmed in ILIM (direct Register 71) is used.

1 = The maximum differential loop current limit is temporarily increased to 41 mA.

6

FSKEN

FSK Generation Enhancement.

When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only

when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are

used for FSK generation (indirect registers 99–104). Audio tones are generated using

this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-

olution of 41.67 µs. This provides greater resolution during FSK caller ID signal genera-

tion.

0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always

used.

1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only

when REL = 1; otherwise clocked at 8 kHz.

5

DCSU

DC-DC Converter Control Speedup.

When enabled, this bit invokes a multi-threshold error control algorithm which allows the

dc-dc converter to adjust more quickly to voltage changes.

0 = Normal control algorithm used.

1 = Multi-threshold error control algorithm used.

4

3

2

Reserved

LCVE

Write has no effect.

Read returns zero.

Voltage-Based Loop Closure.

Enables loop closure to be determined by the TIP-to-RING voltage rather than loop cur-

rent.

0 = Loop closure determined by loop current.

1 = Loop closure determined by TIP-to-RING voltage.

102

Rev. 1.0

Si3216

Bit

Name

Function

1

DCFIL

DC-DC Converter Squelch.

When enabled, this bit squelches noise in the audio band from the dc-dc converter con-

trol loop.

0 = Voice band squelch disabled.

1 = Voice band squelch enabled.

0

HYSTEN

Loop Closure Hysteresis Enable.

When enabled, this bit allows hysteresis to the loop closure calculation. The upper and

lower hysteresis thresholds are defined by Indirect Registers 28 and 43, respectively.

0 = Loop closure hysteresis disabled.

1 = Loop closure hysteresis enabled.

Rev. 1.0

103

Si3216

4. Indirect Registers

Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A

write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the

contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update.

A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the

value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of

16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition, an

interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.

The indirect memory map is different from what is described in the data sheet. The indirect memory map is as

follows:

Table 35. Si3210 to Si3216 Indirect Register Cross Reference

Si3210

Indirect

Register

Si3216

Indirect

Register

Indirect

Register

Si3210

Indirect

Register

Si3216

Indirect

Register

Indirect

Register

Name

Si3210

Indirect

Register

Si3216

Indirect

Register

Indirect

Register

Name

OSC1

OSC1X

OSC1Y

OSC2

OSC2X

OSC2Y

ROFF

RCO

13

14

15

16

17

18

19

20

21

22

26

0

1

27

28

29

30

31

32

33

34

35

36

37

14

15

16

17

18

19

20

21

22

23

24

ADCG

LCRT

RPTP

CML

38

39

25

26

27

64

66

69

70

71

72

73

74

NQ34

NQ56

2

40

VCMR

VMIND

LCRTL

FSK0X

FSK0

3

41

4

CMH

43

5

PPT12

PPT34

PPT56

NCLR

NRTP

NQ12

99

6

100

101

102

103

104

7

FSK1X

FSK1

8

RNGX

RNGY

DACG

9

FSK01

FSK10

13

4.1. Oscillators

See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing

register values. All values are represented in 2s-complement format.

Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read

and written but should be written to zeroes.

Table 36. Oscillator Indirect Registers Summary

Addr. D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

1

2

3

4

5

OSC1[15:0]

OSC1X[15:0]

OSC1Y[15:0]

OSC2[15:0]

OSC2X[15:0]

OSC2Y[15:0]

6

ROFF[5:0]

104

Rev. 1.0

Si3216

Table 36. Oscillator Indirect Registers Summary (Continued)

Addr. D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

7

8

9

RCO[15:0]

RNGX[15:0]

RNGY[15:0]

Table 37. Oscillator Indirect Registers Description

Description

Addr.

Reference

Page

0

Oscillator 1 Frequency Coefficient.

37

39

Sets tone generator 1 frequency.

1

2

3

4

5

6

Oscillator 1 Amplitude Register.

Sets tone generator 1 signal amplitude.

Oscillator 1 Initial Phase Register.

Sets initial phase of tone generator 1 signal.

Oscillator 2 Frequency Coefficient.

Sets tone generator 2 frequency.

Oscillator 2 Amplitude Register.

Sets tone generator 2 signal amplitude.

Oscillator 2 Initial Phase Register.

Sets initial phase of tone generator 2 signal.

Ringing Oscillator DC Offset.

Sets dc offset component (V –V

) to ringing waveform. The range is 0 to 94.5 V in

RING

TIP

1.5 V increments.

7

8

9

Ringing Oscillator Frequency Coefficient.

39

Sets ringing generator frequency.

Ringing Oscillator Amplitude Register.

Sets ringing generator signal amplitude.

Ringing Oscillator Initial Phase Register.

Sets initial phase of ringing generator signal.

4.2. Digital Programmable Gain/Attenuation

See functional description sections of digital programmable gain/attenuation for guidelines on computing register

values. All values are represented in 2s-complement format.

Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read

and written but should be written to zeros.

Table 38. Digital Programmable Gain/Attenuation Indirect Registers Summary

Addr. D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

13

14

DACG[11:0]

ADCG[11:0]

Rev. 1.0

105

Si3216

Table 39. Digital Programmable Gain/Attenuation Indirect Registers Description

Addr.

Description

Reference

Page

13 Receive Path Digital to Analog Converter Gain/Attenuation.

43

This register sets gain/attenuation for the receive path. The digitized signal is effectively mul-

tiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain

(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain

of 6 dB.

14 Transmit Path Analog to Digital Converter Gain/Attenuation.

43

This register sets gain/attenuation for the transmit path. The digitized signal is effectively

multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain

(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain

of 6 dB.

106

Rev. 1.0

Si3216

4.3. SLIC Control

See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values

are represented in 2s-complement format.

Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read

and written but should be written to zeroes.

Table 40. SLIC Control Indirect Registers Summary

Addr. D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

15

16

17

18

19

20

21

22

23

24

25

26

27

LCRT[5:0]

RPTP[5:0]

CML[5:0]

CMH[5:0]

PPT12[7:0]

PPT34[7:0]

PPT56[7:0]

NCLR[12:0]

NRTP[12:0]

NQ12[12:0]

NQ34[12:0]

NQ56[12:0]

VCMR[3:0]

64

66

VMIND[3:0]

LCRTL[5:0]

Table 41. SLIC Control Indirect Registers Description

Description

Addr.

Reference Page

15 Loop Closure Threshold.

32

Loop closure detection threshold. This register defines the upper bounds threshold if hys-

teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.

16 Ring Trip Threshold.

42

Ring trip detection threshold during ringing.

17 Common Mode Minimum Threshold for Speed-Up.

This register defines the negative common mode voltage threshold. Exceeding this

threshold enables a wider bandwidth of dc linefeed control for faster settling times. The

range is 0–23.625 V in 0.375 V steps.

18 Common Mode Maximum Threshold for Speed-Up.

This register defines the positive common mode voltage threshold. Exceeding this

threshold enables a wider bandwidth of dc linefeed control for faster settling times. The

range is 0–23.625 V in 0.375 V steps.

Rev. 1.0

107

Si3216

Table 41. SLIC Control Indirect Registers Description (Continued)

Description

Addr.

Reference Page

19 Power Alarm Threshold for Transistors Q1 and Q2.

20 Power Alarm Threshold for Transistors Q3 and Q4.

21 Power Alarm Threshold for Transistors Q5 and Q6.

22 Loop Closure Filter Coefficient.

30

32

42

30

23 Ring Trip Filter Coefficient.

24 Thermal Low Pass Filter Pole for Transistors Q1 and Q2.

25 Thermal Low Pass Filter Pole for Transistors Q3 and Q4.

26 Thermal Low Pass Filter Pole for Transistors Q5 and Q6.

27 Common Mode Bias Adjust During Ringing.

39

Recommended value of 0 decimal.

DC-DC Converter V Voltage.

33

OV

This register sets the overhead voltage, V , to be supplied by the dc-dc converter.

OV

64

66

When the VOV bit = 0 (direct Register 66, bit 4), V should be set between 0 and 9 V

OV

(VMIND = 0 to 6h). When the VOV bit = 1, V should be set between 0 and 13.5 V

OV

(VMIND = 0 to 9h).

Loop Closure Threshold—Lower Bound.

This register defines the lower threshold for loop closure hysteresis, which is enabled in

bit 0 of direct Register 108. The range is 0–80 mA in 1.27 mA steps.

32

108

Rev. 1.0

Si3216

4.4. FSK Control

For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These

registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,

bit 6) and REL = 1 (direct Register 32, bit 6).

Table 42. FSK Control Indirect Registers Summary

Addr. D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

69

70

71

72

73

74

FSK0X[15:0]

FSK0[15:0]

FSK1X[15:0]

FSK1[15:0]

FSK01[15:0]

FSK10[15:0]

Table 43. FSK Control Indirect Registers Description

Description

Addr.

Reference Page

FSK Amplitude Coefficient for Space.

69

39 and AN32

When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener-

ating a space or 0. When the active timer (OAT1) expires, the value of this register is

loaded into oscillator 1 instead of OSC1X.

FSK Frequency Coefficient for Space.

70

71

72

39 and AN32

When FSKEN = 1 and REL = 1, this register sets the frequency to be used when gener-

ating a space or 0. When the active timer (OAT1) expires, the value of this register is

loaded into oscillator 1 instead of OSC1.

FSK Amplitude Coefficient for Mark.

When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener-

ating a mark or 1. When the active timer (OAT1) expires, the value of this register is

loaded into oscillator 1 instead of OSC1X.

FSK Frequency Coefficient for Mark.

When FSKEN = 1 and REL = 1, this register sets the frequency to be used when gener-

ating a mark or 1. When the active timer (OAT1) expires, the value of this register is

loaded into oscillator 1 instead of OSC1.

FSK Transition Parameter from 0 to 1.

73

74

39 and AN32

When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is

applied to signal amplitude when transitioning from a space (0) to a mark (1).

FSK Transition Parameter from 1 to 0.

When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is

applied to signal amplitude when transitioning from a mark (1) to a space (0).

Rev. 1.0

109

Si3216

5. Pin Descriptions: Si3216

QFN

TSSOP

38

37

1

2

CS

INT

SCLK

SDI

PCLK

DRX

DTX

FSYNC

RESET

SDCH

SDCL

V_DDA1

IREF

CAPP

QGND

CAPM

36 SDO

3

4

5

6

7

8

9

10

11

12

13

14

38 37 36 35 34 33 32

1

2

3

4

DTX

FSYNC

RESET

SDCH

SDCL

V_DDA1

IREF

CAPP

QGND

CAPM

STIPDC

31 SDITHRU

35

34

33

32

31

30

SDITHRU

DCDRV

DCFF

TEST

GNDD

VDDD

30

DCDRV

29

DCFF

28

27

26

25

24

23

22

21

20

TEST

GNDD

VDDD

ITIPN

ITIPP

V_DDA2

IRINGP

IRINGN

IGMP

5

6

7

29 ITIPN

8

28

27

ITIPP

V_DDA2

9

10

11

26 IRINGP

25

24

23

22

21

20

IRINGN

IGMP

GNDA

IGMN

SRINGAC

STIPAC

SRINGDC ¹²

13 14 15 16 17 18 19

STIPDC 15

SRINGDC 16

STIPE

SVBAT 18

SRINGE

17

19

Pin #

QFN TSSOP

Pin #

Name

Description

35

1

CS

Chip Select.

Active low. When inactive, SCLK and SDI are ignored and SDO is high-impedance.

When active, the serial port is operational.

36

37

38

1

2

3

4

5

6

INT

PCLK

DRX

DTX

Interrupt.

Maskable interrupt output. Open drain output for wire-ORed operation.

PCM Bus Clock.

Clock input for PCM bus timing.

Receive PCM Data.

Input data from PCM bus.

Transmit PCM Data.

Output data to PCM bus.

2

FSYNC Frame Synch.

8 kHz frame synchronization signal for the PCM bus. May be short or long pulse for-

mat.

3

4

7

8

RESET Reset.

Active low input. Hardware reset used to place all control registers in the default

state.

SDCH

DC Monitor.

DC-DC converter monitor input used to detect overcurrent situations in the con-

verter.

110

Rev. 1.0

Si3216

Pin #

QFN TSSOP

Pin #

Name

Description

5

9

SDCL

DC Monitor.

DC-DC converter monitor input used to detect overcurrent situations in the con-

verter.

6

7

8

10

11

12

VDDA1 Analog Supply Voltage.

Analog power supply for internal analog circuitry.

Current Reference.

IREF

Connects to an external resistor used to provide a high accuracy reference current.

CAPP

SLIC Stabilization Capacitor.

Capacitor used in low pass filter to stabilize SLIC feedback loops.

9

13

14

QGND Component Reference Ground.

10

CAPM SLIC Stabilization Capacitor.

Capacitor used in low pass filter to stabilize SLIC feedback loops.

11

12

13

14

15

16

17

18

19

20

21

22

23

15

16

17

18

19

20

21

22

23

24

25

26

27

STIPDC TIP Sense.

Analog current input used to sense voltage on the TIP lead.

SRINGDC RING Sense.

Analog current input used to sense voltage on the RING lead.

STIPE TIP Emitter Sense.

Analog current input used to sense voltage on the Q6 emitter lead.

SVBAT VBAT Sense.

Analog current input used to sense voltage on dc-dc converter output voltage lead.

SRINGE RING Emitter Sense.

Analog current input used to sense voltage on the Q5 emitter lead.

STIPAC TIP Transmit Input.

Analog ac input used to detect voltage on the TIP lead.

SRINGAC RING Transmit Input.

Analog ac input used to detect voltage on the RING lead.

IGMN

Transconductance Amplifier External Resistor.

Negative connection for transconductance gain setting resistor.

GNDA Analog Ground.

Ground connection for internal analog circuitry.

IGMP

Transconductance Amplifier External Resistor.

Positive connection for transconductance gain setting resistor.

IRINGN Negative Ring Current Control.

Analog current output driving Q3.

IRINGP Positive Ring Current Control.

Analog current output driving Q2.

VDDA2 Analog Supply Voltage.

Analog power supply for internal analog circuitry.

Rev. 1.0

111

Si3216

Pin #

QFN TSSOP

Pin #

Name

Description

24

25

26

27

28

29

30

31

32

ITIPP

Positive TIP Current Control.

Analog current output driving Q1.

ITIPN

Negative TIP Current Control.

Analog current output driving Q4.

VDDD

Digital Supply Voltage.

Digital power supply for internal digital circuitry.

GNDD Digital Ground.

Ground connection for internal digital circuitry.

Test.

TEST

Enables test modes for Silicon Labs internal testing. This pin should always be tied

to ground for normal operation.

29

33

DCFF

DC Feed-Forward/High Current General Purpose Output.

Feed-forward drive of external bipolar transistors to improve dc-dc converter

efficiency.

30

31

32

33

34

35

36

37

38

DCDRV DC Drive/Battery Switch.

DC-DC converter control signal output which drives external bipolar transistor.

SDITHRU SDI Passthrough.

Cascaded SDI output signal for daisy-chain mode.

Serial Port Data Out.

SDO

SDI

Serial port control data output.

Serial Port Data In.

Serial port control data input.

SCLK

Serial Port Bit Clock Input.

Serial port clock input. Controls the serial data on SDO and latches the data on SDI.

112

Rev. 1.0

Si3216

6. Pin Descriptions: Si3201

TIP

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ITIPP

ITIPN

IRINGP

IRINGN

NC

RING

VBAT

VBATH

NC

STIPE

SRINGE

NC

GND

VDD

Pin #

Name

Input/

Description

Output

1

TIP

NC

I/O

TIP Output—Connect to the TIP lead of the subscriber loop.

2, 6, 9, 12

No Internal Connection—Do not connect to any electrical signal.

RING Output—Connect to the RING lead of the subscriber loop.

Operating Battery Voltage—Connect to the battery supply.

High Battery Voltage—This pin is internally connected to VBAT.

Ground—Connect to a low impedance ground plane.

3

4

5

7

8

RING

VBAT

VBATH

GND

VDD

Supply Voltage—Main power supply for all internal circuitry. Connect to a

3.3 V or 5 V supply. Decouple locally with a 0.1 F/6 V capacitor.

10

SRINGE

O

RING Emitter Sense Output—Connect to the SRINGE pin of the Si321x

pin.

11

13

STIPE

O

I

TIP Emitter Sense Output—Connect to the STIPE pin of the Si321x pin.

IRINGN

Negative RING Current Control—Connect to the IRINGN lead of the

Si321x.

14

15

16

IRINGP

ITIPN

I

Positive RING Current Drive—Connect to the IRINGP lead of the Si321x.

Negative TIP Current Control—Connect to the ITIPN lead of the Si321x.

Positive TIP Current Control—Connect to the ITIPP lead of the Si321x.

Exposed Thermal Pad—Connect to the bulk ground plane.

ITIPP

Bottom-Side

Exposed Pad

Rev. 1.0

113

Si3216

7. Ordering Guides

Table 44. Device Ordering Guide

Package

Device

Description Wideband DCFF Pin

Lead-Free and

Temperature

Codec

Output

DCDRV

N/A

RoHS-Compliant

Si3216-C-FM

Si3216-C-GM

Si3216M-C-FM

Si3216M-C-GM

Si3216-KT

ProSLIC



QFN-38

Yes

No

0 to 70 °C

–40 to 85 °C

0 to 70 °C

QFN-38

–40 to 85 °C

0 to 70 °C

TSSOP-38

SOIC-16

Si3216-BT

No

–40 to 85 °C

0 to 70 °C

Si3216-FT

Yes

No

Si3216-GT

–40 to 85 °C

0 to 70 °C

Si3216M-KT

Si3216M-BT

Si3216M-FT

Si3216M-GT

Si3201-KS

No

–40 to 85 °C

0 to 70 °C

Yes

No

–40 to 85 °C

0 to 70 °C

Linefeed

Interface

Si3201-BS

Si3201-FS

Si3201-GS

Linefeed

Interface

N/A

SOIC-16

No

Yes

–40 to 85 °C

0 to 70 °C

Linefeed

Interface

Linefeed

Interface

–40 to 85 °C

Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.

114

Rev. 1.0

Si3216

Table 45. Evaluation Kit Ordering Guide

Item

Supported

ProSLIC

Description

Linefeed

Interface

Discrete

Si3201

Si3216PPQX-EVB

Si3216PPQ1-EVB

Si3216DCQX-EVB

Si3216DCQ1-EVB

Si3216MPPQX-EVB

Si3216MPPQ1-EVB

Si3216MDCQ1-EVB

Si3216MDCQX-EVB

Si3216PPTX-EVB

Si3216PPT1-EVB

Si3216DCX-EVB

Si3216-QFN

Eval Board, Daughter Card

Daughter Card Only

Si3216-QFN

Discrete

Si3201

Si3216-QFN

Daughter Card Only

Si3216M-QFN

Si3216-TSSOP

Eval Board, Daughter Card

Daughter Card Only

Discrete

Si3201

Daughter Card Only

Discrete

Si3201

Eval Board, Daughter Card

Daughter Card Only

Discrete

Si3201

Si3216DC1-EVB

Daughter Card Only

Rev. 1.0

115

Si3216

8. Package Outline: 38-Pin QFN

Figure 30 illustrates the package details for the Si321x. Table 46 lists the values for the dimensions shown in the

illustration.

Figure 30. 38-Pin Quad Flat No-Lead Package (QFN)

Table 46. Package Diagram Dimensions^1,2,3

Millimeters

Symbol

Min

0.75

0.00

0.18

Nom

0.85

Max

0.95

0.05

0.30

A

A1

b

0.01

0.23

D

5.00 BSC.

3.20

D2

e

3.10

3.30

0.50 BSC.

7.00 BSC.

5.20

E

E2

L

5.10

0.35

0.03

—

5.30

0.55

0.08

0.10

0.08

0.10

0.45

L1

0.05

aaa

bbb

ccc

ddd

Notes:

—

1. All dimensions shown are in millimeters (mm) unless

otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.

3. Recommended card reflow profile is per the JEDEC/IPC

J-STD-020C specification for Small Body Components.

116

Rev. 1.0

Si3216

9. Package Outline: 38-Pin TSSOP

Figure 31 illustrates the package details for the Si321x. Table 47 lists the values for the dimensions shown in the

illustration.

B

E/2

2x

E1

E



L

C

2x

B A

ddd

e

ccc

A

D

C

aaa

C

A

Seating Plane

b

A1

C

38x

M

bbb

C B A

Approximate device weight is 115.7 mg

Figure 31. 38-Pin Thin Shrink Small Outline Package (TSSOP)

Table 47. Package Diagram Dimensions

Millimeters

Symbol

Min

—

Nom

—

Max

1.20

0.15

0.27

0.20

9.80

A

A1

b

0.05

0.17

0.09

9.60

—

c

—

D

9.70

e

E

0.50 BSC

6.40 BSC

4.40

E1

L

4.30

0.45

0°

4.50

0.75

8°

0.60



—

aaa

bbb

ccc

ddd

0.10

0.08

0.05

0.20

Rev. 1.0

117

Si3216

10. Package Outline: 16-Pin ESOIC

Figure 32 illustrates the package details for the Si3201. Table 48 lists the values for the dimensions shown in the

illustration.

16

9

8

x45°

h

E

H

.25 M B M

–B–



1

L

B

Bottom Side

Exposed Pad

2.3 x 3.6 mm

.25 M C A M B S

Detail F

–A–

D

C

A

–C–

See Detail F

A1

e



Seating Plane

Weight: Approximate device weight is 0.15 grams.

Figure 32. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package

Table 48. Package Diagram Dimensions

Millimeters

Symbol

Min

1.35

0

Max

1.75

0.15

.51

A

A1

B

C

D

E

e

.33

.19

.25

9.80

3.80

10.00

4.00

1.27 BSC

H

h

5.80

.25

.40

—

6.20

.50

L

1.27

0.10

8º





0º

118

Rev. 1.0

Si3216

11. Silicon Labs Si3216 Support Documentation



AN32: Si321x Frequency Shift Keying (FSK) Modulation

AN33: Si321x Neon Flashing

AN34: Si321x Hardware Reference Guide

AN35: Si321x User’s Quick Reference Guide

AN39: Connecting the ProSLIC to the W & G PCM-4

AN45: Design Guide for the Si321x DC-DC Converter

AN46: Demonstration Software Guide for the Si3210 DC-DC Converter

AN47: Si321x Linefeed Power Monitoring and Protection

Si321xPPT-EVB: Evaluation board data sheet

Note: Refer to www.silabs.com for a current list of support documents for this chipset.

Rev. 1.0

119

Si3216

DOCUMENT CHANGE LIST

Revision 0.61 to Revision 0.9



Separated the Si3216/15 document into two data

sheets.



Added Quad Flat No-Lead (QFN) package.

Removed references to Si3215.

Updated Figure 11 on page 20.

Changed C18, C19 from 1.0 µF to 4.7 µF.

Updated Figure 13 on page 23.

Changed C10 from 22 nF to 0.1 µF.

Updated Table 11 on page 18.

Changed delay time between chip selects, t_cs, from 220 ns to

440 ns



Updated Table 41 on page 107.

Changed recommended values for Indirect Register 27 from 6 to

0.

Updated 7."Ordering Guides" on page 114.

Revision 0.9 to Revision 0.91



Figure 12 on page 22.

Added optional components to application schematic to improve

idle channel noise.



Table 14 on page 22.

Added TO-92 transistor suppliers to BOM.

Table 45, “Evaluation Kit Ordering Guide,” on

page 115.

Updated to include Si3216M-QFN daughter card.

Table 48, “Package Diagram Dimensions,” on

page 118.



Changed A1 from 0.10 to 0.15.

7."Ordering Guides" on page 114.

Updated table to include product revision designator.

Rev. C Si3216 Silicon:



Register 14. Powerdown Control 1 on page 64.

Changed Bit 3 from “Monitor ADC Power-Off Control” to “PLL

Free-Run Control”

Revision 0.91 to Revision 1.0



Added chamfered Pin 1 identifier option to Package

Outline: 38-Pin QFN.



Clarified Ordering Guide

Replaced "X" with revision letter "C" in all ordering codes

requiring a revision letter.

Removed Note 2 from Ordering Guide

120

Rev. 1.0

Si3216

NOTES:

Rev. 1.0

121

Si3216

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: ProSLICinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, and ProSLIC are registered trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

122

Rev. 1.0


型号：	SI3216-FTR
厂家：	SILICON
描述：	Programmable Codec, A/MU-Law, 1-Func, CMOS, PDSO38, ROHS COMPLIANT, TSSOP-38 电池电信光电二极管电信集成电路
文件：	总122页 (文件大小：731K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI3216-FTR [SILICON]

相关型号：

SI3216-GTR

SI3216-KTR

SI3216M-FTR

SI3216M-GT

SI3216M-GTR

SI3216MPPQ1-EVB

SI3216MPPQX-EVB

SI3216PPQ1-EVB

SI3216PPQX-EVB

SI32170-B-FM1

SI32170-B-FM1R

SI32170-B-GMR