SI3220DC0-EVB [SILICON]
DUAL PROSLIC㈢ PROGRAMMABLE CMOS SLIC/CODEC; 双PROSLIC㈢可编程CMOS SLIC / CODEC
| 型号： | SI3220DC0-EVB |
| 厂家： | 
SILICON |
| 描述： | DUAL PROSLIC㈢ PROGRAMMABLE CMOS SLIC/CODEC |
| 文件： | 总112页 (文件大小：1511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3220/25
DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC
Features
ꢀ
ꢀ
ꢀ
Performs all BORSCHT functions
Ideal for applications up to 18 kft
Internal balanced ringing to 65 Vrms
ꢀ
Loop or ground start operation with
smooth/abrupt polarity reversal
Modem/fax tone detection
DTMF generation/decoding
Dual tone generators
A-Law/µ-Law, linear PCM
companding
PCM and SPI bus digital interfaces
with programmable interrupts
GCI mode support
ꢀ
ꢀ
ꢀ
ꢀ
(Si3220)
ꢀ
ꢀ
External bulk ringer support (Si3225)
Software-programmable parameters:
ꢁ Ringing frequency, amplitude, cadence,
and waveshape (Si3220)
ꢁ Two-wire ac impedance
ꢁ Transhybrid balance
ꢁ DC current loop feed (18–45 mA)
ꢁ Loop closure and ring trip thresholds
ꢁ Ground key detect threshold
Automatic switching of up to three battery
supplies
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
3.3 or 5 V operation
Part Number
Ringing
Method
GR-909 loop diagnostics
Audio diagnostics with loopback
12 kHz/16 kHz pulse metering
(Si3220)
FSK caller ID generation
Lead-free/RoHS-compliant
ꢀ
ꢀ
Si3220
Si3225
Internal
ꢀ
ꢀ
External
Ringer
On-hook transmission
Applications
Ordering Information
ꢀ
ꢀ
ꢀ
ꢀ
Digital loop carriers
ꢀ
ꢀ
ꢀ
ꢀ
Private Branch Exchange (PBX) systems
Cable telephony
Voice over IP/voice over DSL
ISDN terminal adapters
See “Dual ProSLIC Selection
Guide” on page 109.
Central Office telephony
Pair gain remote terminals
Wireless local loop
Description
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
The Dual ProSLIC® is a series of low-voltage CMOS devices that integrate both
SLIC and codec functionality into a single IC to provide a complete dual-channel
analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI
specifications. The Si3220 includes internal ringing generation to eliminate
centralized ringers and ringing relays, and the Si3225 supports centralized ringing
for long loop and legacy applications. On-chip subscriber loop and audio testing
allows remote diagnostics and fault detection with no external test equipment or
relays. The Si3220 and Si3225 operate from a single 3.3 or 5 V supply and
interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200 linefeed
interface IC performs all high-voltage functions and operates from a 3.3 V or 5 V
supply as well as single or dual battery supplies up to 100 V. The Si3220 and
Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is
available in a thermally-enhanced 16-pin small outline (SOIC) package.
Functional Block Diagram
INT RESET
Si3220/25
Codec A
SLIC A
CS
SCLK
SDO
SDI
2-Wire AC
Impedance
Pulse Metering
SPI
Control
Interface
Linefeed
Control
DAC
TIP
Subscriber Line
Diagnostics
Hybrid Balance
DTMF Decode
Linefeed
Interface
Channel A
RING
Linefeed
Monitor
ADC
Ringing
Generator
& Ring Trip
FSK
CallerID
DSP
Sense
DTX
DRX
PCM /
GCI
Interface
Codec B
SLIC B
Dual Tone
Generators
Gain Adjust
Linefeed
Control
TIP
DAC
FSYNC
Loop Closure,
& Ground Key
Detection
Linefeed
Interface
Modem Tone
Detection
Channel B
Linefeed
Monitor
ADC
RING
Programmable
Audio Filters
PLL
PCLK
Relay Drivers
Rev. 1.2 2/06
Copyright © 2006 by Silicon Laboratories
Si3220/25
Si3220/25
2
Rev. 1.2
Si3220/25
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.1. Dual ProSLIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.3. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.4. Adaptive Linefeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5. Ground Start Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6. Linefeed Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.7. Loop Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.8. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.9. Automatic Dual Battery Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.10. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.11. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.12. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.13. Internal Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.14. Ringing Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.15. Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.16. Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.17. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.18. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.19. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.20. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.21. Caller ID Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.22. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.23. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
3.24. Modem Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.25. Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
3.26. System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
3.27. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.28. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.29. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
3.30. PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
3.31. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
3.32. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
4. Pin Descriptions: Si3220/25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
5. Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
6. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8. Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9. Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Rev. 1.2
3
Si3220/25
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter
Symbol
Test
Value
Unit
Condition
VDD, VDD1–VDD4
VBATH
Supply Voltage, Si3200 and Si3220/Si3225
–0.5 to 6.0
0.4 to –104
0.4 to –109
VBATH
V
V
2
High Battery Supply Voltage, Si3200
Continuous
10 ms
VBAT,VBATL
VTIP,VRING
Low Battery Supply Voltage, Si3200
TIP or RING Voltage, Si3205
Continuous
Continuous
Pulse < 10 µs
Pulse < 4 µs
V
–104
V
V
–15
–35
BATH
BATH
ITIP, IRING
TIP, RING Current, Si3200
±100
mA
mA
STIPAC, STIPDC, SRINGAC, SRINGDC Current,
Si3220/Si3225
±20
Input Current, Digital Input Pins
I
Continuous
±10
±50
mA
mV
IN
Si3220/25 Analog Ground Differential Voltage
(GND1 to ePad, GND2 to ePad, or GND1 to GND2)
∆V
GNDA
3
Si3220/25 Digital Ground Differential Voltage (GND3
to GND4)
∆V
±50
mV
mV
GNDD
3
Si3220/25 Analog to Digital Ground Differential Volt-
∆V
±200
GND,A–D
3
age (GND1/GND2/ePad to GND3/GND4)
Digital Input Voltage
V
–0.3 to (VDDD + 0.3)
–40 to 100
–40 to 150
25
V
°C
IND
Operating Temperature Range
Storage Temperature Range
Si3220/Si3225 Thermal Resistance,
T
A
T
°C
STG
θ
°C/W
JA
3
Typical (TQFP-64 ePad)
4
Si3200 Thermal Resistance, Typical
(SOIC-16 ePad)
θ
55
1
°C/W
W
JA
5
Continuous Power Dissipation, Si3200
P
P
T = 85 °C,
SOIC-16
D
D
A
Continuous Power Dissipation, Si3220/25
T = 85 °C,
1.6
W
A
TQFP-64
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The dv/dt of the voltage applied to the VBAT, VBATH, and VBATL pins must be limited to 10 V/µs.
3. The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to the
GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are not
exceeded under any operating condition in addition to providing thermal dissipation.
4. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC® User Guide” or to the Si3220/3225
evaluation board data sheet for specific layout examples.
5. On-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 °C. For optimal
reliability, junction temperatures above 140 °C should be avoided.
4
Rev. 1.2
Si3220/25
Table 2. Recommended Operating Conditions
Parameter
Symbol
Test
Min*
Typ
Max*
Unit
Condition
o
Ambient Temperature
T
K/F-Grade
B/G-Grade
0
25
25
70
85
C
A
o
Ambient Temperature
T
–40
3.13
3.13
–15
–15
C
A
Supply Voltage, Si3220/Si3225
V
–V
3.3/5.0
3.3/5.0
—
5.25
5.25
–99
V
V
V
V
DD1
DD4
Supply Voltage, Si3200
V
DD
High Battery Supply Voltage, Si3200
VBATH
VBATL
Low Battery Supply Voltage, Si3200
—
V
BATH
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
Table 3. 3.3 V Power Supply Characteristics1
(VDD, VDD1 – VDD4 = 3.3 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
–V
Current (Si3220/
Si3225)
Symbol
I –I
VDD1 VDD4
Test Condition
Sleep mode, RESET = 0
Open (high-impedance)
Active on-hook standby
Forward/reverse active off-hook
Min
—
Typ
200
17
Max
—
Unit
µA
V
Supply
DD1
DD4
—
—
mA
mA
—
16
—
—
45 + I
—
mA
LIM
+ ABIAS
Forward/reverse active OHT
OBIAS = 4 mA, V
= –70 V
—
—
47
26
—
—
mA
mA
BAT
Ringing, V
= 45 V , V
= –70 V,
RING
rms BAT
2
Sine Wave, 1 REN load
Notes:
1. All specifications are for a single channel based on measurements with both channels in the same operating state.
2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating
conditions.
3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must
include an additional (VDD + |VBAT|) x ILOOP term.
Rev. 1.2
5
Si3220/25
Table 3. 3.3 V Power Supply Characteristics1 (Continued)
(VDD, VDD1 – VDD4 = 3.3 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Supply Current
Symbol
Test Condition
Sleep mode, RESET = 0
Open (high-impedance)
Active on-hook standby
Forward/reverse active off-hook,
Min
—
Typ
110
110
110
Max
—
Unit
µA
V
I
VDD
DD
(Si3200)
—
—
µA
—
—
µA
ABIAS = 4 mA, V
= –24 V
—
110
—
µA
BAT
Forward/reverse OHT, OBIAS = 4 mA,
= –70 V
V
—
—
110
110
—
—
µA
µA
BAT
Ringing, V
= 45 V
,
RING
rms
V
= –70 V,
BAT
Sine Wave, 1 REN load
V
Supply Current
I
Sleep mode, RESET=0,
—
—
—
—
100
189
—
—
—
—
µA
µA
µA
mA
BAT
VBAT
(Si3200)
V
= –70 V
BAT
Open (high-impedance),
= –70 V
V
BAT
Active on-hook standby,
= –70 V
517
V
BAT
Forward/reverse active off-hook,
ABIAS = 4 mA, V = –24 V
4.5 +
I
BAT
LIM
Forward/reverse OHT, OBIAS = 4 mA,
= –70 V
V
—
—
8.6
6.5
—
—
mA
mA
BAT
Ringing, V
= 45 V
,
RING
rms
V
= –70 V,
BAT
2
Sine Wave, 1 REN load
Notes:
1. All specifications are for a single channel based on measurements with both channels in the same operating state.
2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating
conditions.
3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must
include an additional (VDD + |VBAT|) x ILOOP term.
6
Rev. 1.2
Si3220/25
Table 3. 3.3 V Power Supply Characteristics1 (Continued)
(VDD, VDD1 – VDD4 = 3.3 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Chipset Power
Consumption
P
Sleep mode, RESET = 0,
—
8
—
mW
SLEEP
V
= –70 V
BAT
P
Open (high-impedance), V
= –70 V
= –70 V
—
—
69
89
—
—
mW
mW
OPEN
BAT
P
Active on-hook standby, V
STBY
BAT
3
P
Forward/reverse active off-hook,
ABIAS = 4 mA, V = –24 V
ACTIVE
—
267
—
mW
BAT
P
Forward/reverse OHT, OBIAS = 4 mA,
= –70 V
OHT
V
—
—
757
541
—
—
mW
mW
BAT
P
Ringing, V
= 45 v
,
RING
RING
rms
2
V
= –70 V, 1 REN load
BAT
Notes:
1. All specifications are for a single channel based on measurements with both channels in the same operating state.
2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating
conditions.
3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must
include an additional (VDD + |VBAT|) x ILOOP term.
Rev. 1.2
7
Si3220/25
Table 4. 5 V Power Supply Characteristics1
(VDD, VDD1 – VDD4 = 5 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
– V
Symbol
I –I
VDD1 VDD4
Test Condition
Sleep mode, RESET = 0
Open (high-impedance)
Active on-hook standby
Forward/reverse active off-hook
Min
—
Typ
1
Max
—
Unit
mA
mA
mA
V
Supply
DD1
DD4
Current (Si3220/Si3225)
—
22
21
—
—
—
—
62 +
—
mA
I
+
LIM
ABIAS
Forward/reverse active OHT
OBIAS = 4 mA
—
—
65
31
—
—
mA
mA
Ringing, V
= 45 V
,
RING
rms
2
V
= –70 V, 1 REN load
BAT
V
Supply Current
I
Sleep mode, RESET = 0
Open (high-impedance)
Active on-hook standby
—
—
—
110
110
110
—
—
—
µA
µA
µA
DD
VDD
(Si3200)
Forward/reverse active off-hook,
ABIAS = 4 mA, V = –24 V
—
110
—
µA
BAT
Forward/reverse OHT, OBIAS = 4 mA,
= –70 V
V
—
—
110
110
—
—
µA
µA
BAT
Ringing, V
= 45 V
,
RING
rms
V
= –70 V,
BAT
1 REN load
Notes:
1. All specifications are for a single channel based on measurements with both channels in the same operating state.
2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating
conditions.
3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must
include an additional (VDD + |VBAT|) x ILOOP term.
8
Rev. 1.2
Si3220/25
Table 4. 5 V Power Supply Characteristics1 (Continued)
(VDD, VDD1 – VDD4 = 5 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
V
I
Sleep mode, RESET = 0,
—
125
—
µA
BAT
VBAT
(Si3200)
V
= –70 V
BAT
Open (high-impedance), V
= –70 V
= –70 V
—
—
190
700
—
—
µA
µA
BAT
Active on-hook standby, V
BAT
Forward/reverse active off-hook,
ABIAS = 4 mA, V = –24 V
—
4.7 +
—
mA
BAT
I
LIM
Forward/reverse OHT, OBIAS = 4 mA,
= –70 V
V
—
—
8.8
6.5
—
—
mA
mA
BAT
Ringing, V
= 45 V
,
RING
rms
V
= –70 V,
BAT
2
1 REN load
Chipset Power
Consumption
P
Sleep mode, RESET = 0,
—
13.8
—
mW
SLEEP
V
= –70 V
BAT
P
Open (high-impedance), V
= –70 V
= –70 V
—
—
123
154
—
—
mW
mW
OPEN
BAT
P
Active on-hook standby, V
STBY
BAT
3
P
Forward/reverse active off-hook,
ABIAS = 4 mA, V = –24 V
ACTIVE
—
436
—
mW
BAT
P
Forward/reverse OHT, OBIAS = 4 mA,
= –70 V
OHT
V
—
—
941
610
—
—
mW
mW
BAT
P
Ringing, V
= 45 V
,
RING
RING
rms
2
V
= –70 V, 1 REN load
BAT
Notes:
1. All specifications are for a single channel based on measurements with both channels in the same operating state.
2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating
conditions.
3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must
include an additional (VDD + |VBAT|) x ILOOP term.
Rev. 1.2
9
Si3220/25
Table 5. AC Characteristics
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
TX/RX Performance
Overload Level
2.5
Figure 6
—
—
—
—
—
V
PK
Overload Compression
2-Wire – PCM
2-Wire – PCM or PCM – 2-Wire:
200 Hz to 3.4 kHz
1
–85
–65
dB
dB
Single Frequency Distortion
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
—
–87
—
–65
—
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Figure 5
Signal-to-(Noise + Distortion)
2
Ratio
Active off-hook, and OHT, any Z
T
Audio Tone Generator Signal-to-
Distortion Ratio
0 dBm0, Active off-hook, and
46
—
—
dB
2
OHT, any Z
T
Intermodulation Distortion
—
—
—
–41
dB
dB
2
2-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
0 dBm 0
–0.25
+0.25
Gain Accuracy
Attenuation Distortion vs. Freq.
Group Delay vs. Frequency
Figure 7,8
Figure 9
—
—
—
—
—
—
—
—
—
—
3
1014 Hz sine wave,
reference level –10 dBm
Signal level:
Gain Tracking
3 dB to –37 dB
–37 dB to –50 dB
—
—
—
—
—
—
± 0.25
± 0.5
± 1.0
700
dB
dB
dB
µs
–50 dB to –60 dB
—
Round-Trip Group Delay
1014 Hz, Within same time-slot
600
Crosstalk between Channels
TX or RX to TX
TX or RX to RX
0 dBm0,
300 Hz to 3.4 kHz
300 Hz to 3.4 kHz
—
—
—
–108
–108
–75
–75
—
dB
dB
dB
4
Step size around 0 dB
200 Hz to 3.4 kHz
±0.0005
Gain Step Increment
5
26
30
—
dB
2-Wire Return Loss
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the
complete range. See "3.25. Audio Path Processing" on page 69.
5. VDD1 – VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register
coefficients.
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
10
Rev. 1.2
Si3220/25
Table 5. AC Characteristics (Continued)
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
5
300 Hz to 3.4 kHz
34
40
—
dB
Transhybrid Balance
Noise Performance
6
C-Message weighted
—
12
15
dBrnC
Idle Channel Noise
Psophometric weighted
3 kHz flat
—
—
40
60
–78
—
–75
18
—
dBmP
dBrn
dB
PSRR from V
PSRR from V
– V
RX and TX, dc to 3.4 kHz
RX and TX, dc to 3.4 kHz
Longitudinal Performance
200 Hz to 1 kHz
—
DD1
BAT
DD4
—
—
dB
Longitudinal to Metallic/PCM
Balance (forward or reverse)
58
53
40
70
58
—
—
—
—
dB
dB
dB
1 kHz to 3.4 kHz
Metallic/PCM to Longitudinal
Balance
200 Hz to 3.4 kHz
7
Longitudinal Impedance
200 Hz to 3.4 kHz at TIP or RING
Register-dependent
OBIAS/ABIAS
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
—
—
—
—
50
25
25
20
—
—
—
—
Ω
Ω
Ω
Ω
7
Longitudinal Current per Pin
Active off-hook
200 Hz to 3.4 kHz
Register-dependent
OBIAS/ABIAS
00 = 4 mA
—
—
—
—
4
8
8
—
—
—
—
mA
mA
mA
mA
01 = 8 mA
10 = 12 mA
11 = 16 mA
10
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the
complete range. See "3.25. Audio Path Processing" on page 69.
5. VDD1 – VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register
coefficients.
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
Rev. 1.2
11
Si3220/25
Table 6. Linefeed Characteristics
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min Typ Max Unit
2
Maximum Loop Resistance (adaptive
linefeed disabled )
R
R
= 430 Ω,
1870
—
—
Ω
LOOP
DC,MAX
1
I
= 18 mA, V
= –52 V,
LOOP
BAT
ABIAS = 8 mA
VOCDELTA = 0
2
Maximum Loop Resistance (adaptive
linefeed enabled )
R
R
= 430 Ω,
2030
—
—
Ω
LOOP
DC,MAX
1
I
= 18 mA, V
= –52 V,
LOOP
BAT
ABIAS = 8 mA
VOCDELTA ≠ 0
DC Loop Current Accuracy
I
= 18 mA
—
—
—
—
±10
±4
%
V
LIM
DC Open Circuit Voltage Accuracy
Active Mode; V = 48 V,
OC
V
– V
TIP
RING
DC Differential Output Resistance
R
I
< I
—
—
320
—
—
Ω
DO
LOOP
LIM
DC On-Hook Voltage Accuracy—Ground
Start
V
I
<I ; V wrt ground,
±4
V
OHTO
RING LIM RING
V
= –51 V
RING
DC Output Resistance—Ground Start
DC Output Resistance—Ground Start
Loop Closure Detect Threshold Accuracy
Ground Key Detect Threshold Accuracy
Ring Trip Threshold Accuracy
R
I
<I ; RING to ground
—
300
—
320
—
—
—
Ω
kΩ
%
ROTO
RING LIM
R
TIP to ground
TOTO
I
I
= 13 mA
= 13 mA
±10 ±15
±10 ±15
THR
THR
—
%
Si3220, ac detection,
VRING = 70 Vpk, no offset,
= 80 mA
—
±4
±5
mA
I
TH
Si3220, dc detection,
—
—
±1.5 ±2
mA
20 V dc offset, I = 13 mA
TH
Si3225, dc detection,
—
±4.5 mA
48 V dc offset, R
= 1500 Ω
= 100 V
= 0 Ω,
loop
3
Ringing Amplitude, Si3220
V
Open circuit, V
93
82
—
—
—
—
V
V
RING
BATH
PK
PK
5 REN load, R
LOOP
V
= 100 V
BATH
Sinusoidal Ringing Total
Harmonic Distortion
R
—
2
—
%
THD
Ringing Frequency Accuracy
Ringing Cadence Accuracy
Calibration Time
f = 16 Hz to 100 Hz
Accuracy of ON/OFF times
↑CAL to ↓CAL bit
—
—
—
—
—
—
±1
%
±50 ms
600 ms
Notes:
1. Adaptive linefeed is enabled when the VOCDELTA RAM address is set to a non-zero value and is disabled when
VOCDELTA is set to 0.
2. RDC,MAX is the maximum dc resistance of the CPE; hence the specified total loop resistance is RLOOP + RDC,MAX
.
3. Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series
protection resistance.
12
Rev. 1.2
Si3220/25
Table 6. Linefeed Characteristics (Continued)
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ Max Unit
Loop Voltage Sense Accuracy
Accuracy of boundaries for
each output code;
—
±2
±7
—
±4
%
%
%
V
– V
= 48 V
TIP
RING
Loop Current Sense Accuracy
Accuracy of boundaries for
each output code;
—
—
±10
±25
I
= 18 mA
LOOP
Power Alarm Threshold Accuracy
Power Threshold = 300 mW
Notes:
1. Adaptive linefeed is enabled when the VOCDELTA RAM address is set to a non-zero value and is disabled when
VOCDELTA is set to 0.
2. RDC,MAX is the maximum dc resistance of the CPE; hence the specified total loop resistance is RLOOP + RDC,MAX
.
3. Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series
protection resistance.
Table 7. Monitor ADC Characteristics
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
—
Typ
8
Max
—
Unit
Resolution
Bits
Differential Nonlinearity
DNL
INL
–1.0
±0.75
+1.5
LSB
LSB
Integral Nonlinearity
Gain Error
—
—
±0.6
±0.1
±1.5
LSB
LSB
±0.25
Rev. 1.2
13
Si3220/25
Table 8. Si3200 Characteristics
(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
– V (Forward)
Min
Typ Max
Unit
TIP/RING Pulldown Transistor Satura-
tion Voltage
V
V
V
OV
RING
BAT
– V
(Reverse)
BAT
TIP
1
I
= 22 mA, I
= 4 mA
ABIAS
⎯
⎯
3
⎯
V
V
LIM
I
= 45 mA,
= 16 mA
4
—
LIM
1
I
ABIAS
TIP/RING Pullup Transistor
Saturation Voltage
V
R
GND – V
(Forward)
CM
TIP
GND – V
(Reverse)
RING
1
I
= 22 mA
= 45 mA
⎯
⎯
3
4
⎯
—
V
V
LIM
1
I
LIM
Battery Switch Saturation
Impedance
(V
– V
)/I
(Note 2)
⎯
15
⎯
Ω
SAT
BAT
BATH OUT
OPEN State TIP/RING Leakage Current
Internal Blocking Diode Forward Voltage
I
R = 0 Ω
⎯
⎯
⎯
100
µA
V
LKG
L
V
V
– V (Note 2)
BATL
0.8
⎯
F
BAT
Notes:
1. VAC = 2.5 VPK, RLOAD = 600 Ω.
2. IOUT = 60 mA.
Table 9. DC Characteristics (VDD, VDD1–VDD4 = 5 V)
(VDD, VDD1 – VDD4 = 4.75 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
5.25
Unit
High Level Input
Voltage
V
0.7 x VDD
—
V
IH
Low Level Input
Voltage
V
—
VDD – 0.6
—
—
—
—
—
0.3 x VDD
—
V
V
V
V
IL
High Level Output
Voltage
V
I = 8 mA
OH
O
Low Level Output
Voltage
V
DTX, SDO, INT, SDITHRU:
0.4
OL
I = –8 mA
O
BATSELa/b, RRDa/b,
—
0.72
GPOa/b, TRD1a/b,TRD2a/b:
I = –40 mA
O
SDITHRU Internal
Pullup Resistance
20
—
—
—
30
63
11
—
—
—
kΩ
Ω
Relay Driver Source
Impedance
R
V
V
–V
= 4.75 V
DD4
OUT
DD1
I < 28 mA
O
Relay Driver Sink
Impedance
R
–V = 4.75 V
DD4
—
Ω
IN
L
DD1
I < 85 mA
O
Input Leakage Current
I
±10
µA
14
Rev. 1.2
Si3220/25
Table 10. DC Characteristics (VDD, VDD1–VDD4 = 3.3 V)
(VDD, VDD1 – VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
0.7 x V
—
Typ
—
Max
5.25
Unit
V
High Level Input Voltage
Low Level Input Voltage
V
IH
DD
V
—
0.3 x V
—
V
IL
DD
High Level Output
Voltage
V
I = 4 mA
V – 0.6
DD
—
V
OH
O
Low Level Output
Voltage
V
DTX, SDO, INT,
SDITHRU:
—
—
—
0.4
V
OL
I = –4 mA
O
BATSELa/b, RRDa/b,
—
0.72
GPOa/b, TRD1a/b, TRD2a/b:
I = –40 mA
O
SDITHRU internal pullup
resistance
35
—
—
—
50
63
11
—
—
—
kΩ
Ω
Relay Driver Source Imped-
ance
R
V
V
–V
= 3.13 V
DD4
OUT
DD1
IO < 28 mA
Relay Driver Sink Impedance
R
–V = 3.13 V
IO < 85 mA
—
Ω
IN
L
DD1
DD4
Input Leakage Current
I
±10
µA
Table 11. Switching Characteristics—General Inputs1
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF)
Parameter
Symbol
Min
—
Typ
—
Max
5
Unit
Rise Time, RESET
RESET Pulse Width, GCI Mode
t
ns
ns
µs
r
2
t
500
6
—
—
rl
rl
RESET Pulse Width, SPI Daisy Chain Mode
t
—
—
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VDD
–
0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 kΩ per device.
Rev. 1.2
15
Si3220/25
Table 12. Switching Characteristics—SPI
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF
Parameter
Symbol
Test Conditions
Min
62
—
Typ
—
Max
—
Unit
ns
Cycle Time SCLK
t
c
Rise Time, SCLK
t
—
25
ns
r
Fall Time, SCLK
t
—
—
25
ns
f
Delay Time, SCLK Fall to SDO Active
t
—
—
20
ns
d1
d2
Delay Time, SCLK Fall to SDO
Transition
t
t
—
—
20
ns
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
—
25
20
25
20
220
—
—
—
—
—
—
—
4
20
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
d3
t
su1
Hold Time, CS to SCLK Rise
t
h1
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time between Chip Selects
SDI to SDITHRU Propagation Delay
t
su2
t
h2
t
cs
t
d4
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V
tc
tr
tf
SCLK
CS
tsu1
th1
tcs
tsu2
th2
SDI
td1
td3
td2
SDO
td4
SDITHRU
Figure 1. SPI Timing Diagram
16
Rev. 1.2
Si3220/25
Table 13. Switching Characteristics—PCM Highway Interface
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF)
1
1
1
Parameter
Symbol
Test
Conditions
Units
Min
Typ
Max
PCLK Period
t
122
—
3906
ns
p
Valid PCLK Inputs
—
—
—
—
—
—
—
—
—
256
512
768
1.024
1.536
1.544
2.048
4.096
8.192
—
—
—
—
—
—
—
—
—
kHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
2
FSYNC Period
t
—
40
—
—
—
—
—
125
50
—
—
60
µs
%
fs
PCLK Duty Cycle Tolerance
PCLK Period Jitter Tolerance
Rise Time, PCLK
t
dty
t
±120
25
ns
ns
ns
ns
ns
jitter
t
—
r
Fall Time, PCLK
t
—
25
f
Delay Time, PCLK Rise to DTX Active
t
t
—
20
d1
d2
Delay Time, PCLK Rise to DTX
Transition
—
20
Delay Time, PCLK Rise to DTX
Tristate
t
—
—
20
ns
d3
3
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
FSYNC Pulse Width
t
25
20
25
20
—
—
—
—
—
—
—
ns
ns
ns
ns
su1
t
h1
t
—
su2
t
—
h2
t
t /2
125 µs–t
p
wfs
p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4 V, VIL = 0.4 V.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
Rev. 1.2
17
Si3220/25
tr
tf
tp
PCLK
th1
twfs
tsu1
tfs
FSYNC
tsu2
th2
DRX
DTX
td2
td1
td3
Figure 2. PCM Highway Interface Timing Diagram
18
Rev. 1.2
Si3220/25
Table 14. Switching Characteristics—GCI Highway Serial Interface
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
1
Test
Conditions
Parameter
Symbol
Min
Typ
Max
Units
PCLK Period (2.048 MHz PCLK Mode)
PCLK Period (4.096 MHz PCLK Mode)
t
t
—
—
—
40
488
244
125
50
—
—
—
60
ns
ns
µs
%
p
p
2
FSYNC Period
t
fs
PCLK Duty Cycle Tolerance
FSYNC Jitter Tolerance
t
dty
t
—
—
±120
ns
jitter
Rise Time, PCLK
t
—
—
—
—
—
25
20
25
20
—
—
—
—
—
—
—
—
—
—
25
25
20
20
20
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
r
Fall Time, PCLK
t
f
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
t
t
t
d1
d2
d3
3
Delay Time, PCLK Rise to DTX Tristate
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
FSYNC Pulse Width
t
su1
t
h1
t
su2
t
h2
t
t /2
p
wfs
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and
fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
tr
tf
tp
PCLK
th1
tsu1
tfs
FSYNC
tsu2
th2
Frame 0,
Bit 0
DRX
DTX
td1
td2
td3
Frame 0,
Bit 0
Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)
Rev. 1.2
19
Si3220/25
tr
tf
tc
PCLK
th1
tfs
tsu1
FSYNC
tsu2
th2
Frame 0,
Bit 0
DRX
DTX
td1
td3
td2
Frame 0,
Bit 0
Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode)
Acceptable Region
Figure 5. Transmit and Receive Path SNDR
20
Rev. 1.2
Si3220/25
9
8
7
6
5
4
Fundamental
Output Power
(dBm0)
Acceptable
Region
3
2.6
2
1
0
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
Figure 6. Overload Compression Performance
TX Attenuation Distortion
5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
TX Pass−Band Detail
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−1.2
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
Figure 7. Transmit Path Frequency Response
Rev. 1.2
21
Si3220/25
RX Attenuation Distortion
5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
RX Pass−Band Detail
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−1.2
0
250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000
Frequency (Hz)
Figure 8. Receive Path Frequency Response
22
Rev. 1.2
Si3220/25
TX Group Delay Distortion
1100
1000
900
800
700
600
500
400
300
200
100
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400
Frequency (Hz)
Figure 9. Transmit Group Delay Distortion
RX Group Delay Distortion
1100
1000
900
800
700
600
500
400
300
200
100
0
Typical Response
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400
Frequency (Hz)
Figure 10. Receive Group Delay Distortion
Rev. 1.2
23
Si3220/25
24
Rev. 1.2
Si3220/25
% $ 7 6 ( / D
7 5 ' ꢁ D
7 5 ' ꢂ D
% $ 7 6 ( / E
ꢊ ꢁ
ꢉ ꢋ
ꢆ ꢄ
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ꢆ ꢆ
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ꢆ ꢇ
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ꢃ ꢄ
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ꢃ ꢊ
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* 3 2 E
ꢊ ꢂ
7 5 ' ꢁ E
ꢊ ꢄ
1 &
1 &
7 5 ' ꢂ E
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1 &
ꢁ ꢅ
7 + ( 5 0 D
, 5 , 1 * 3 D
ꢂ ' * 1
9 ' ' ꢂ
, 7 , 3 3 D
, 5 , 1 * 1 D
, 7 , 3 1 D
7 + ( 5 0 E
ꢁ ꢇ
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ꢁ ꢃ
ꢁ ' * 1
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9 ' ' ꢁ
ꢁ ꢉ
, 7 , 3 3 E
ꢁ ꢊ
ꢁ ꢁ
, 5 , 1 * 1 E
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ꢁ ꢂ
6 5 , 1 *
6 5 , 1 * ' & E
ꢁ ꢄ
6 5 , 1 *
6 7 , 3 $ & D
6 5 , 1 * $ & E
ꢂ ꢋ
6 7 , 3 $ & E
ꢂ ꢅ
6 7 , 3 ' & D
6 7 , 3 ' & E
ꢂ ꢇ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
Rev. 1.2
25
Si3220/25
% $ 7 6 ( / D
% $ 7 6 ( / E
ꢊ ꢁ
ꢉ ꢋ
ꢆ ꢄ
ꢆ ꢂ
ꢆ ꢁ
ꢆ ꢊ
ꢆ ꢉ
ꢆ ꢆ
ꢆ ꢃ
ꢆ ꢇ
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ꢆ ꢋ
ꢃ ꢄ
ꢃ ꢂ
ꢃ ꢁ
ꢃ ꢊ
ꢃ ꢉ
7 5 ' ꢁ D
5 5 ' E
ꢊ ꢂ
7 5 ' ꢂ D
5 7 5 3 D
7 5 ' ꢁ E
ꢊ ꢄ
7 5 ' ꢂ E
ꢁ ꢋ
% / . 5 1 *
5 7 5 3 E
ꢁ ꢅ
7 + ( 5 0 D
, 5 , 1 * 3 D
7 + ( 5 0 E
ꢁ ꢇ
, 5 , 1 * 3 E
ꢁ ꢃ
ꢁ ' * 1
ꢁ ꢆ
ꢂ ' * 1
9 ' ' ꢂ
, 7 , 3 3 D
, 5 , 1 * 1 D
, 7 , 3 1 D
9 ' ' ꢁ
ꢁ ꢉ
, 7 , 3 3 E
ꢁ ꢊ
, 5 , 1 * 1 E
ꢁ ꢁ
, 7 , 3 1 E
ꢁ ꢂ
6 5 , 1 *
6 5 , 1 * ' & E
ꢁ ꢄ
6 5 , 1 *
6 7 , 3 $ & D
6 5 , 1 * $ & E
ꢂ ꢋ
6 7 , 3 $ & E
ꢂ ꢅ
6 7 , 3 ' & D
6 7 , 3 ' & E
ꢂ ꢇ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
26
Rev. 1.2
Si3220/25
2. Bill of Materials
Table 15. Si3220 + Si3200 External Component Values
Component
C1, C2, C11, C12
C3, C4, C13, C14
C5, C6, C15, C16
Value
Function
100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac-sensing inputs.
10 nF, 100 V, X7R, ±20% TIP/RING compensation capacitors.
1 µF, 6.3 V, X7R, ±20%
Low-pass filter capacitors to stabilize differential and
common-mode SLIC feedback loops.
C30–C33
0.1 µF, 100 V, Y5V
0.1 µF, 10 V, Y5V
Decoupling for battery voltage supply pins.
Decoupling for analog and digital chip supply pins.
Sense resistors for TIP, RING voltage-sensing nodes.
Current limiting resistors for TIP, RING ac-sensing inputs.
Sense resistor for battery dc-sensing nodes.
Sets bias current for battery-switching circuit.
Reference resistors for internal transconductance amplifier.
Generates a high accuracy reference current.
Protection against power supply transients.
Protection against power supply transients.
Pulldown resistors.
C20–C25
R1, R2, R11, R12
R3, R4, R13, R14
R5, R15
402 kΩ, 1/10 W, ±1%
4.7 kΩ, 1/10 W, ±1%
806 kΩ, 1/10 W, ±1%
40.2 kΩ, 1/10 W, ±5%
182 Ω, 1/10 W, ±1%
40.2 kΩ, 1/10 W, ±1%
0 Ω, 1/10 W, ±5%
R6, R16
R7, R8, R17, R18
R10
R20, R22
R21, R23
15 Ω, 1/8 W, ±5%
R24, R25*
39 kΩ, 1/10 W, ±5%
*Note: R24 and R25 must be populated for each Si3220 in the system.
Rev. 1.2
27
Si3220/25
Table 16. Si3225 + Si3200 External Component Values
Component
C1, C2, C11, C12
C3, C4, C13, C14
C5, C6, C15, C16
Value
Function
100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac sensing inputs.
10 nF, 100 V, X7R, ±20% TIP/RING compensation capacitors.
1 µF, 6.3 V, X7R, ±20% Low-pass filter capacitors to stabilize differential and com-
mon mode SLIC feedback loops.
1
1
C30 , C31 , C32, C33
C20–C25
0.1 µF, 100 V, Y5V
0.1 µF, 10 V, Y5V
Decoupling for battery voltage supply pins.
Decoupling for analog and digital chip supply pins.
Sense resistors for TIP, RING dc sensing nodes.
Sense resistors for battery voltage sensing nodes.
Current limiting resistors for TIP, RING ac sensing inputs.
Sets bias current for battery switching circuit.
Reference resistors for internal transconductance amplifier.
Sense registers for ringing generator feed.
Generates a high accuracy reference current.
Feed resistor for ringing generator source.
Protection against power supply transients.
Protection against power supply transients.
Pulldown resistors.
R1, R2, R11, R12
R5, R15
402 kΩ, 1/10 W, ±1%
806 kΩ, 1/10 W, ±1%
4.7 kΩ, 1/10 W, ±1%
40.2 kΩ, 1/10 W, ±5%
182 Ω, 1/10 W, ±1%
806 kΩ, 1/10 W, ±1%
40.2 kΩ, 1/10 W, ±1%
R3, R4, R13, R14
1
1
R6 , R16
R7, R8, R17, R18
R9, R19, R20
R10
2
R21, R22
510 Ω, 2W, ±2%
R23, R25
0 Ω, 1/10 W, ±5%
15 Ω, 1/8 W, ±5%
39 kΩ, 1/10 W, ±5%
R24, R26
3
R27, R28
Notes:
1. Optional. Only required when using dual-battery architecture.
2. Example power rating.
3. R27 and R28 must be populated for each Si3225 in the system.
28
Rev. 1.2
Si3220/25
comply with relevant LSSGR and ITU requirements for
line-fault detection and reporting, and measured values
3. Functional Description
®
The Dual ProSLIC chipset is a three-chip integrated are stored in registers for later use or further
solution that provides all SLIC, codec, and DTMF calculations. The Si3220 and Si3225 also include two
detection/decoding functions needed for a complete relay drives per channel to support legacy systems
dual-channel analog telephone interface. Intended for implementing centralized test equipment.
multiple-channel long-loop (up to 18 kft) applications
A
complete audio transmit and receive path is
requiring high-density line card designs, the Dual
ProSLIC chipset provides high integration and low-
power operation for applications, such as Central Office
(CO) and digital loop carrier (DLC) enclosures. The
Dual ProSLIC chipset is also ideal for short-loop
applications requiring a space-effective solution, such
as terminal adapters, integrated access devices (IADs),
PBX/key systems, and voice-over IP systems. The
chipset meets all relevant Bellcore LSSGR, ITU, and
ETSI standards.
integrated, including DTMF generation and decoding,
tone
programmable
generation,
ac
modem/fax
impedance
tone
synthesis,
detection,
and
programmable transhybrid balance and programmable
gain attenuation. These features are software-
programmable providing a single hardware design to
meet international requirements. Digital voice data
transfer occurs over a standard PCM bus, and control
data is transferred using a standard 4-wire serial
peripheral interface (SPI). The Si3220 and Si3225 can
The Si3220/Si3225 ICs perform all battery, overvoltage, also be configured to support a 4-wire general circuit
ringing, supervision, codec, hybrid, and test interface (GCI). The Si3220 and Si3225 are available in
(BORSCHT) functions on-chip in a low-power, small- a 64-lead TQFP, and the Si3200 is available in a
footprint solution. DTMF decoding and generation, thermally-enhanced 16-lead SOIC.
phase continuous FSK (caller ID) signaling, and pulse
3.1. Dual ProSLIC Architecture
metering are also integrated. All high-voltage functions
are implemented using the Si3200 Linefeed Interface IC The Dual ProSLIC chipset is comprised of a low-voltage
allowing a highly-programmable integrated solution that CMOS device that uses a low-cost integrated linefeed
offers the lowest total system cost.
interface IC to control the high voltages needed for
operating the terminal equipment connected to the
telephone line. Figure 15 presents a simplified diagram
of the linefeed control loop circuit for controlling the TIP
and RING leads. The diagram illustrates a single-ended
model for simplicity, showing either the TIP or the RING
lead.
The internal linefeed circuitry provides programmable
on-hook voltage and off-hook loop current, reverse
battery operation, loop or ground-start operation, and
on-hook transmission. Loop current and voltage are
continuously monitored using an integrated 8-bit
monitor A/D converter. The Si3220 provides on-chip
balanced 5 REN ringing with or without a programmable The Dual ProSLIC chipset produces line voltages and
dc offset, eliminating the need for an external bulk ring currents on the TIP/RING pair using register-
generator and per-channel ringing relay. Both sinusoidal programmable settings as well as direct ac and dc
and trapezoidal ringing waveshapes are available. voltage/current sensing from the line. The Si3200 LFIC
Ringing parameters, such as frequency, waveshape, provides a low-cost interface for bridging the low-
cadence, and offset, are available in registers to reduce voltage CMOS devices to the high-voltage TIP/RING
external controller requirements. The Si3225 supports pair. Sense resistors allow the voltage and current to be
external ringing generation with ring relay driver and measured on each lead or across T-R using the low-
external ring trip sensing to address legacy systems voltage circuitry inside the Si3220 and Si3225
that implement a centralized ringing architecture. All eliminating expensive analog sensing circuitry inside
ringing options are software-programmable over a wide the high-voltage Si3200. In addition, the total power
range of parameters to address a wide variety of inside the Si3200 is constantly monitored and controlled
application requirements.
to provide optimal reliability under all operating
conditions. The sensing circuitry is calibrated for
environmental and process variations to guarantee
accuracy with standard external resistor tolerances.
The Si3220/Si3225 ICs also provide a variety of line
monitoring and subscriber loop testing functions. All
versions have the ability to generate specific dc and
audio signals and continuously monitor and store all line
voltage and current parameters. This combination of
signal generation and measurement tools allows remote
line card and loop diagnostics without requiring
additional test equipment. These diagnostic functions
Rev. 1.2
29
Si3220/25
constant current region (defined by the loop current
3.2. Power Supply Sequencing
limit, I ) is programmable from 18 to 45 mA in
LIM
To ensure proper operation, the following power
sequencing guidelines should be followed:
0.87 mA steps. The Si3220 and Si3225 exhibit a
characteristic dc impedance of 640 Ω or 320 Ω during
active mode. (See "3.4. Adaptive Linefeed" on page 33).
ꢀ V
should be allowed to reach its steady state
DD
voltage at least 20 ms before V
is allowed to
The TIP-RING voltage (V ) is offset from ground by a
BATH
OC
begin to ramp to its desired voltage.
programmable voltage (V ) to provide sufficient
CM
voltage headroom to the most positive terminal
(typically the TIP lead in normal polarity or the RING
lead in reverse polarity) for carrying audio signals. A
ꢀ Transients and oscillations with a dv/dt above 10 V/
µs on the V and V
supplies should always be
BATH
DD
avoided.
similar programmable voltage (V ) is an offset
OV
ꢀ The ramp-up time for V should be in the range of
DD
between the most negative terminal and the battery
supply rail for carrying audio signals. (See Figure 14.)
The user-supplied battery voltage must have sufficient
amplitude under all operating states to ensure sufficient
headroom. The Si3200 may be powered by a lower
2 ms to 20 ms. The ramp-up time for V
should
BATH
be in the range of 10 ms to 150 ms. Slower ramp-up
times are not recommended.
ꢀ V
rail must never be more negative than the
rail during any part of the power supply ramp-
BATL
secondary battery supply (V
) to reduce total power
V
BATL
BATH
dissipation when driving short-loop lengths.
up.
The Si3200 features an ESD clamp protection circuit
connected between the V and V rails. This
clamp protects the Si3200 against ESD damage when
the device is being handled out-of-circuit during
Loop Closure Threshold
RLOOP
DD
BATH
Constant I Region
Constant V Region
VCM
VTIP
manufacture. Precautions must be taken in the V and
DD
V
V
system power supply design. At power-up, the
BATH
VOC
VOV
and V
rails must ramp-up from 0 V to their
DD
BATH
respective target values in a linear fashion and must not
exhibit fast transients or oscillations which could cause
the ESD clamp to be activated for an extended period of
time resulting in damage to the Si3200. The resistors
shown as R20 through R23 together with capacitors
C23, C24, C30 and C31 on Figure 12 and R23 through
R26 along with capacitors C24, C25, C32 and C33 in
Figure 13 provide some measure of protection against
in-circuit ESD clamp activation by forming a filter time
constant and by providing current limiting action in case
of momentary clamp activation during power-up. These
resistors and capacitors must be included in the
VBATL
VRING
VOV
Secondary VBAT
Selected
V
VBATH
Figure 14. DC Linefeed Overhead Voltages
(Forward State)
3.3.1. Calculating Overhead Voltages
The two programmable overhead voltages (V
and
OV
V
V
) represent one portion of the total voltage between
and ground as illustrated in Figure 14. Under
normal operating conditions, these overhead voltages
are sufficiently low to maintain the desired TIP-RING
CM
BAT
application circuit, while ensuring that the V
and
DD
V
system power supplies are designed to exhibit
voltage (V ). However, there are certain conditions
BATH
OC
start-up behavior that is free of undesirable transients or
oscillations. Once the V and V are in their steady
state final values, the ESD clamp has circuitry that
prevents it from being activated by transients slower
under which the user must exercise care in providing a
battery supply with enough amplitude to supply the
required TIP-RING voltage and enough margin to
DD
BATH
accommodate these overhead voltages. The V
CM
than 10 V/µs. In the steady powered-up state, the V
voltage is programmed for a given operating condition.
Therefore, the open-circuit voltage (V varies
according to the required overhead voltage (V ) and
DD
and V
rails must therefore not exhibit transients
)
BATH
OC
resulting in a voltage slew rate greater than 10 V/µs.
OV
the supplied battery voltage (V
pay attention to the maximum V
be required for each operating state.
). The user should
BAT
3.3. DC Feed Characteristics
and V
that might
OV
CM
The Si3220 and Si3225 offer programmable constant-
voltage and constant-current operating regions as
illustrated in Figure 14. The constant voltage region
(defined by the open-circuit voltage,
programmable from 0 to 63.3 V in 1 V steps. The
In the off-hook active state, sufficient V
must be
OC
maintained to correctly power the phone from the
battery supply that is provided. Because the battery
supply depends on the state of the input supply (i.e.,
V
)
is
OC
30
Rev. 1.2
Si3220/25
charging, discharging, or battery backup mode), the side of any protection resistance placed in series with
user must decide how much loop current is required and the TIP and RING leads. If line-side sensing is desired,
determine the maximum loop impedance that can be both V
and V
must be increased by a voltage
OV
CM
driven based on the battery supply provided. The equal to R
x I
where R
is the value of each
PROT
LIM
PROT
minimum battery supply required can be calculated with protection resistor. Other safety precautions may also
the following equation:
VBAT ≥ VOC + VCM + VOV
and V are provided in Table 8 on page 14.
apply.
See "3.14.3. Linefeed Overhead Voltage Considerations
During Ringing" on page 53 for details on calculating the
overhead voltage during the ringing state.
where V
CM
OV
The Dual ProSLIC chipset uses both voltage and
current information to control TIP and RING. Sense
resistor R
The default V
value of 3 V provides sufficient
CM
overhead for a 3.1 dBm signal into a 600 Ω loop
measures dc line voltages on TIP and
DC
impedance with an I
setting of 22 mA and an ABIAS
LIM
RING; Capacitor C couples the ac line voltages on
AC
setting of 4 mA. A V
value of 4 V provides sufficient
OV
the TIP and RING leads to be measured. The Si3220
and Si3225 both use the Si3200 to drive TIP and RING
and isolate the high-voltage line from the low-voltage
CMOS devices.
headroom to source a maximum I
of 45 mA with a
LOOP
3.1 dBm audio signal and an ABIAS setting of 16 mA.
For a typical operating condition of V = –56 V and
BAT
I
= 22 mA:
LIM
The Si3220 and Si3225 measure voltage at various
nodes to monitor the linefeed current. R
and R
DC
BAT
VOC, MAX = 56 V – (3 V + 4 V) = 49 V
provide these measuring points. The sense circuitry is
calibrated on-chip to guarantee measurement accuracy.
See "3.6. Linefeed Calibration" on page 36 for details.
These conditions apply when the dc-sensing inputs
(STIPDCa/b and SRINGDCa/b) are placed on the SLIC
Si3220/
Low
Frequency
Diagnostic
Si3225
Audio
Diagnostic
Filters
Audio
Codec
Filters
Monitor A/D
A/D
A/D
DSP
D/A
D/A
SLIC DAC
Audio
Control
SLIC
Control
Σ
VBAT Sense
Audio
Control
Loop
SLIC
Control
Loop
RBAT
CAC
Si3200
RDC
TIP or
RING
Battery
Select
Control
Current
Mirror
VBATL
VBAT
VBATH
Figure 15. Simplified Dual ProSLIC Linefeed Architecture for TIP and RING Leads
(Diagram Illustrates either TIP or RING Lead of a Single Channel)
Rev. 1.2
31
Si3220/25
3.3.2. Linefeed Operation States
The linefeed interface includes eight different operating more details. The register and RAM locations used for
states as shown in Table 17. The linefeed register programming the linefeed parameters are provided in
settings (LF[2:0], linefeed register) are also listed. The Table 18. See “3.7. Loop Voltage and Current
open state is the default condition in the absence of any Monitoring” and "3.8. Power Monitoring and Power Fault
pre-loaded register settings. The device may also Detection" on page 36, and "3.8.5. Power Dissipation
automatically enter the open state if excess power Considerations" on page 39 for detailed descriptions
consumption is detected in the Si3200. See "3.8. Power and register/RAM locations for these functions.
Monitoring and Power Fault Detection" on page 36 for
Table 17. Linefeed States
Open (LF[2:0] = 000).
The Si3200 output is high-impedance. This mode can be used in the presence of line fault conditions and to
generate open-switch intervals (OSIs). The device can also automatically enter the open state if excess power
consumption is detected in the Si3200 or in the discrete bipolar transistors.
Forward Active (LF[2:0] = 001).
Linefeed is active, but audio paths are powered down until an off-hook condition is detected. The Si3220 and
Si3225 automatically enter a low-power state to reduce power consumption during on-hook standby periods.
Forward On-Hook Transmission (LF[2:0] = 010).
Provides data transmission during an on-hook loop condition (e.g., transmitting FSK caller ID information
between ringing bursts).
Tip Open (LF[2:0] = 011).
Sets the portion of the linefeed interface connected to the TIP side of the subscriber loop to high-impedance
and provides an active linefeed on the RING side of the loop for ground-start operation.
Ringing (LF[2:0] = 100).
Drives programmable ringing waveforms onto the subscriber loop (Si3220) or switches in a centralized ringing
generator by driving an external relay (Si3225).
Reverse Active (LF[2:0] = 101).
Linefeed circuitry is active, but audio paths are powered down until an off-hook condition is detected. The
Si3220 and Si3225 automatically enter a low-power state to reduce power consumption during on-hook
standby periods.
Reverse On-Hook Transmission (LF[2:0] = 110).
Provide data transmission during an on-hook loop condition.
Ring Open (LF[2:0] = 111).
Sets the portion of the linefeed interface connected to the RING side of the subscriber loop to high impedance
and provides an active linefeed on the TIP side of the loop for ground start operation.
32
Rev. 1.2
Si3220/25
Table 18. Register and RAM Locations for Linefeed Control
Parameter
Register/
RAM
Register/RAM
Bits
Programmable LSB Size
Effective
Resolution
Range
Mnemonic
Linefeed
LINEFEED
LINEFEED
RLYCON
ILIM
LF[2:0]
LFS[2:0]
See Table 17
Monitor Only
N/A
N/A
N/A
Linefeed Shadow
Battery Feed Control
Loop Current Limit
On-Hook Line Voltage
Common Mode Voltage
N/A
BATSEL
V
/V
N/A
N/A
BATH BATL
ILIM[4:0]
18–45 mA
0 to 63.3 V
0 to 63.3 V
0 to 63.3 V
0 to 63.3 V
0 to 63.3 V
0 to 63.3 V
0 to 63.3 V
0 to 63.3 V
0.875 mA
4.907 mV
4.907 mV
4.907 mV
4.907 mV
4.907 mV
4.907 mV
4.907 mV
4.907 mV
0.875 mA
1.005 V
1.005 V
1.005 V
1.005 V
1.005 V
1.005 V
1.005 V
1.005 V
VOC
VOC[14:0]
VCM
VCM[14:0]
V
V
V
Delta for Off-Hook
VOCDELTA
VOCLTH
VOCHTH
VOV
VOCDELTA[14:0]
VOCLTH[15:0]
VOCHTH[15:0]
VOV[14:0]
OC
OC
OC
Delta Threshold, Low
Delta Threshold, High
Overhead Voltage
Ringing Overhead Voltage
VOVRING
VOVRING[14:0]
V
During Battery Tracking VOCTRACK VOCTRACK[15:0]
OC
source. ILIM is a 5-bit register field, which is
programmable from 18 to 45 mA in 0.875 mA steps (i.e.,
ILIM = 0x0 corresponds to 18 mA, and ILIM= 0x1F
corresponds to 45 mA).
3.4. Adaptive Linefeed
The Si3220/Si3225 features a proprietary dc feed
design known as adaptive linefeed.
Figure 16 shows the V/I characteristics of adaptive
linefeed. Essentially, adaptive linefeed changes the
source impedance of the dc feed as well as the
apparent open-circuit voltage (VOC) in order to ensure
the ability to source extended loop lengths. The
following sections provide a detailed explanation of
adaptive linefeed.
The following equation is used to calculate VOV, VCM,
VOC, VOCLTH, VOCHTH, and VOCDELTA.
⎛
⎞
⎟
⎟
⎠
⎛
⎞
desired_voltage 512
⎛
⎞
⎜
RAMValue= DEC2HEX 2⋅CEILING⎜ROUND
⋅
⎟
⎟
⎜
⎟
⎠
⎜
⎜
1.005V
5
⎝
⎝
⎠
⎝
In the above equation, the ROUND function rounds the
result to the nearest integer while the CEILING function
rounds-up the result to the nearest integer. The
DEC2HEX function converts a decimal integer into a
hexadecimal integer.
3.4.1. Adaptive Linefeed Example
This section provides a detailed description of adaptive
linefeed operation by utilizing an example. The behavior
of adaptive linefeed is controlled by the following RAM
locations: VOV, VCM, VOC, VOCLTH, VOCHTH, and
VOCDELTA (see Equation 1). The ILIM register also
plays a role in determining the behavior of the dc feed
as it sets the current limit for the constant current
The RAM values shown in Table 19 where used to
generate the adaptive linefeed V/I curve shown in
Figure 16. Note that a battery voltage of –56 V was
assumed, as shown in Table 19.
Table 19. Adaptive Linefeed Example Values
VBAT
VOV
VCM
3 V
VOC
–48 V
ILIM
20 mA
VOCLTH
–7 V
VOCHTH
VOCDELTA
–56 V
4 V
+2 V
+6 V
Rev. 1.2
33
Si3220/25
70
60
VOCHTH
5
320 Ohms
VOCDELTA
50
40
30
4
3
1
VOCLTH
2
6
10 kOhms
2450 Ohms
1930 Ohms
1800 Ohms
20
10
0
0.005
0.01
0.015
0.02
0.025
Iloop (A)
Figure 16. Adaptive Linefeed V/I Behavior
When the Si3220/Si3225 is used with the Si3200 a dc load is connected across TIP and RING and as dc
linefeed device, the source impedance of the dc feed is current begins to flow in the dc loop, the product of the
640 Ω before the adaptive linefeed transition and 320 Ω dc loop current and the 640 Ω source impedance
after the adaptive linefeed transition, as shown in (320 Ω for a discrete bipolar transistor linefeed) causes
Figure 16. On the other hand, when the Si3220/Si3225 the VTIP/RING voltage to decline linearly with
is used with a discrete bipolar transistor linefeed, the increasing loop current. When the VTIP/RING voltage
source impedance of the dc feed is 320 Ω both before reaches the VOCLTH threshold (point 2), adaptive
and after the adaptive linefeed transition.
linefeed switches the source impedance of the dc feed
to 320 Ω and simultaneously boosts the value of VOC
by VOCDELTA (point 3). The source impedance of the
dc feed will now remain at 320 Ω until the programmed
current limit (ILIM) is reached (point 4). At point 4, the dc
feed has entered into the constant current mode of
operation.
The loop closure thresholds are programmable via the
LCROFFHK and LCRONHK RAM addresses. The
LCRLPF RAM address provides filtering of the
measured loop current, and the LCRDBI RAM address
provides de-bouncing. The LCR status bit in register
LCRRTP indicates when a loop closure event has been
detected. See “3.10. Loop Closure Detection” on Adaptive linefeed can be disabled by writing a value of
page 44 for additional details.
zero into the VOCDELTA RAM address. Writing a value
of zero to VOCDELTA simply eliminates the apparent
VOC voltage boost associated with a non-zero
VOCDELTA value. With VOCDELTA = 0 in the case of
the Si3200, the adaptive linefeed transition still changes
the source impedance from 640 Ω to 320 Ω, and there
is a corresponding discontinuity at the transition point.
3.4.2. On-Hook to Off-Hook Transition
Referring to Figure 16, point 1 represents the open-
circuit voltage (VOC = –48 V) of the dc feed. At point 1,
the source impedance of the dc feed is 640 Ω (320 Ω for
discrete bipolar transistor linefeed) and VTIP/
RING = VOC, since no current flows in the loop. When
34
Rev. 1.2
Si3220/25
In the case of the discrete bipolar linefeed, since the Therefore, the VOCLTH and VOCHTH thresholds will
source impedance is 320 Ω both before and after the automatically track the battery voltage along with
adaptive linefeed transition, the V/I curve exhibits no VOCTRACK.
discontinuity
VOCDELTA = 0.
3.4.3. Off-Hook to On-Hook Transition
at
the
transition
points
when
In order to provide an adequate level of adaptive
linefeed hysteresis between the on-hook to off-transition
and the off-hook to on-hook transition, VOCLTH is
programmed below VOCTRACK (e.g., –7 V relative to
VOCTRACK), and VOCHTH is programmed above
VOCTRACK (e.g., +2 V above VOCTRACK). Also,
VOCHTH must be less than VOV – 1 V to ensure that a
proper adaptive linefeed transition will occur in a
reduced battery scenario.
Load lines of 10 kΩ, 1930 Ω, and 1800 Ω are shown in
Figure 16. These load lines intercept the linefeed V/I
curve at the V/I point that would result if a load of that
resistance value were connected across TIP and RING.
As the dc loop is opened, the dc feed will exit the
constant current region (point 4) and enter the 320 Ω
source impedance region. As the current in the loop
collapses, the VTIP/RING voltage will linearly increase
until VOCHTH (point 5) is reached. At this point,
adaptive linefeed will transition to a source impedance
of 640 Ω (320 Ω for discrete bipolar transistor linefeed)
and decrease the VOC voltage by VOCDELTA (point 6).
3.5. Ground Start Operation
To configure the dc feed for ground start operation, it is
necessary to write the LINEFEED register with the
value corresponding to either TIP-OPEN (LF[2:0] = 011)
or RING-OPEN (LF[2:0] = 111). The TIP-OPEN and
RING-OPEN linefeed modes place the indicated lead in
the OPEN state (>150 kΩ) while the other lead remains
active.
3.4.4. VOCTRACK and Adaptive Linefeed
Hysteresis
The two thresholds, VOCLTH and VOCHTH, control
adaptive linefeed hysteresis as shown in Figure 16.
In ground start operation, an off-hook condition is
signaled by the CPE (Customer Premise Equipment) by
VOCTRACK is a RAM location and is the actual open- connecting the active lead to earth ground.
circuit voltage that is being fed to the line. VOCTRACK
The active lead presents a 640 Ω source impedance
is dependent on the measured V
voltage. The
BAT
before the adaptive linefeed transition (320 Ω for a
discrete bipolar linefeed), and 320 Ω source
behavior of VOCTRACK is as shown in the equation
below. As long as V is sufficient to supply VOC +
a
BAT
impedance after the adaptive linefeed transition, as
shown in Figure 17. As for loop start operation, the
adaptive linefeed transitions are governed by the
contents of the VOCLTH and VOCHTH RAM
addresses.
VOV + VCM, VOCTRACK is equal to the programmed
VOC. However, if V becomes too small to support
BAT
VOC + VOV + VCM, then VOCTRACK will track the
battery voltage so that the programmed VOV and VCM
are satisfied at the expense of a reduced VOC voltage.
The OPEN lead presents a high-impedance (>150 kΩ).
Figure 17 illustrates the ground-start VRING/IRING
In
the
example
of
Figure 16,
therefore,
VOCTRACK = VOC = 48 V.
behavior using VOC = 48 V and I
= 24 mA in the
LIM
The following equation describes VOCTRACK behavior:
TIP-OPEN linefeed state. The ground key current
thresholds are programmable via the LONGLOTH and
LONGHITH RAM addresses. The LONGLPF RAM
address provides filtering of the measured longitudinal
currents, and the LONGDBI RAM address provides de-
bouncing. The LONGHI status bit in register LCRRTP
indicates when a ground key event has been detected.
| VBAT |≥ VOC + VOV + VCM ⇒ VOCTRACK= VOC
| VBAT |< VOC + VOV + VCM ⇒ VOCTRACK=| VBAT | −(VOV + VCM)
The values of VOCLTH and VOCHTH are set relative to
VOCTRACK. In the example shown in Figure 16,
VOCLTH is given as –7 V and VOCHTH as +2 V. This
implies that the VOCLTH threshold is located 7 V below
the prevailing value of VOCTRACK, while the VOCHTH
threshold is located 2 V above the prevailing value of
VOCTRACK.
Upon detecting a ground key event, the linefeed
automatically transitions to the FORWARD ACTIVE (if
initially in TIP-OPEN) or REVERSE ACTIVE (if initially
in RING-OPEN). See “3.11. Ground Key Detection” on
page 45 for additional details.
Rev. 1.2
35
Si3220/25
0 mA
-0 V
24 mA
IRING
-20 V
-40 V
-48 V
VOCLTH
VOCHTH
VOC DELTA
-80 V
VRING
Figure 17. Ground Start VRING RING Behavior
/I
(V – V
) and the loop current are also reported.
RING
3.6. Linefeed Calibration
TIP
For ground start operation, the values reported are
and the current flowing in the RING lead.
An internal calibration algorithm corrects for internal and
external component errors. The calibration is initiated by
setting the CAL register bit. This bit automatically resets
upon completion of the calibration cycle.
V
RING
Table 20 lists the register set associated with the loop
monitoring functions.
The Dual ProSLIC chipsets also include the ability to
perform loop diagnostic functions as outlined in "3.32.2.
Line Test and Diagnostics" on page 95.
A calibration should be executed following system
powerup. Upon release of the chip reset, the chipset will
be in the open state, and calibration may be initiated.
Only one calibration should be necessary if the system
remains powered up.
3.8. Power Monitoring and Power Fault
Detection
To optimize Dual ProSLIC performance, the calibration
routine in “AN58: Si3220/Si3225 Programmer’s Guide”
should be followed.
The Dual ProSLIC line monitoring functions can be
used to protect the high-voltage circuitry against
excessive power dissipation and thermal overload
conditions. The Dual ProSLIC devices can prevent
thermal overloads by regulating the total power inside
the Si3200 or in each of the external bipolar transistors
(if using a discrete linefeed circuit). The DSP engine
performs all power calculations and provides the ability
to automatically transition the device into the OPEN
state and generate a power alarm interrupt when
excessive power is detected. Table 21 on page 40
describes the register and RAM locations used for
power monitoring.
3.7. Loop Voltage and Current Monitoring
The Dual ProSLIC chipset continuously monitors the
TIP and RING voltages and currents. These values are
available in registers. An internal 8-bit A/D converter
samples the measured voltages and currents from the
analog sense circuitry and translates them into the
digital domain. The A/D updates the samples at an
800 Hz rate for all inputs except VRNGNG and
IRNGNG, which are sampled at 8 kHz to provide higher
resolution for zero-crossing detection in external ringing
applications. Two derived values, the loop voltage
36
Rev. 1.2
Si3220/25
Table 20. Register and RAM Locations Used for Loop Monitoring
Parameter
Register/RAM
Mnemonic
Register/RAM
Bits
Measurement
Range
LSB Size
4.907 mV
4.907 mV
4.907 mV
Effective
Resolution
Loop Voltage Sense
VLOOP
VLOOP[15:0]
0 to 64.07 V
64.07 to 160.173 V
251 mV
628 mV
(V
– V
)
TIP
RING
TIP Voltage Sense
VTIP
VTIP[15:0]
0 to 64.07 V
64.07 to 160.173 V
251 mV
628 mV
RING Voltage Sense
VRING
VRING[15:0]
0 to 64.07 V
64.07 to 160.173 V
251 mV
628 mV
Loop Current Sense
ILOOP
VBAT
ILOOP[15:0]
VBAT[15:0]
0 to 101.09 mA
3.097 µA
4.907 mV
500 µA*
Battery Voltage Sense
0 to 63.3 V
0 to 160.173 V
251 mV
628 mV
Longitudinal Current
Sense
ILONG
VRNGNG
IRNGNG
ILONG[15:0]
VRNGNG[15:0]
IRNGNG[15:0]
0 to 101.09 mA
3.097 µA
10.172 mV
20.3 µA
500 µA*
1.302 V
2.6 mA
External Ringing Gen-
erator Voltage Sense
332.04 V
External Ringing Gen-
erator Current Sense
662.83 mA
*Note: ILOOP and ILONG are calculated values based on measured IQ1–IQ4 currents. The resulting effective resolution is
approximately 500 µA.
ITIPN
ITIPP
IRINGP
IRINGN
Q4
Q1
Q2
Q3
RBQ5
TIP
RING
RBQ6
Q8
Q7
Q10
Q6
Q5
Q9
R6*gain
R6
82.5
R7
82.5
R7*gain
1.74k
1.74k
VBAT
Figure 18. Discrete Linefeed Circuit for Power Monitoring
Rev. 1.2
37
Si3220/25
Si3200 power calculation method to work correctly.
3.8.1. Transistor Power Equations
(Using Discrete Transistors)
3.8.3. Power Filter and Alarms
When using the Si3220 or Si3225 with discrete bipolar
transistors, it is possible to control the total power of the
solution by individually regulating the power in each
discrete transistor. Figure 18 illustrates the basic
transistor-based linefeed circuit for one channel. The
power dissipation of each external transistor is
estimated based on the A/D sample values. The
approximate power equations for each external BJT are
as follows:
The power calculated during each A/D sample period
must be filtered before being compared to a user-
programmable maximum power threshold. A simple
digital low-pass filter is used to approximate the
transient thermal behavior of the package, with the
output of the filter representing the effective peak power
within the package or, equivalently, the peak junction
temperature.
For Q1, Q2, Q3, and Q4 in SOT23 and Q5 and Q6 in
SOT223 packages, the settings for thermal low-pass
filter poles and power threshold settings are (for an
ambient temperature of 70 °C) calculated as follows: If
P
P
P
P
P
P
≅ V
≅ V
≅ V
≅ V
≅ V
≅ V
x I ≅ (|V | + 0.75 V) x (I
)
Q1
Q2
Q3
Q4
Q5
Q6
CE1
CE2
CE3
CE4
CE5
CE6
Q1
TIP
Q1
x I ≅ (|V
| + 0.75 V) x (I
)
Q2
RING
Q2
x I ≅ (|V | – R7 x I ) x (I
)
Q3
BAT
Q5
Q3
the thermal time constant of the package is τ
, the
thermal
x I ≅ (|V | – R6 x I ) x (I
)
Q4
BAT
Q6
Q4
decimal values of RAM locations PLPF12, PLPF34, and
PLPF56 are given by rounding to the next integer the
value given by the following equation:
x I ≅ (|V | – |V
| – R7 x I ) x (I
)
Q5
BAT
RING
Q5
Q5
x I ≅ (|V | – |V | – R6 x I ) x (I
Q6
)
Q6
BAT
TIP
Q6
The maximum power threshold for each device is
software-programmable and should be set based on the
characteristics of the transistor package, PCB design,
and available airflow. If the peak power exceeds the
programmed threshold for any device, the power-alarm
bit is set for that device. Each external bipolar has its
own register bit (PQ1S–PQ6S bits of the IRQVEC3
register), which goes high on a rising edge of the
comparator output and remains high until the user
clears it. Each transistor power alarm bit is also
maskable by setting the PQ1E–PQ6E bits in the
IRQEN3 register.
4096
800 × τthermal
3
------------------------------------
PLPFxx (decimal value) =
× 2
Where 4096 is the maximum value of the 12-bit plus
sign RAM locations PLPF12, PLPF34, and PLPF56,
and 800 is the power calculation clock rate in Hz. The
equation is an excellent approximation of the exact
equation for τ
= 1.25 ms … 5.12 s. With the
thermal
above equations in mind, example values of the RAM
locations, PTH12, PTH34, PTH56, PLPF12, PLPF34,
and PLPF56, are as follows:
PTH12 = power threshold for Q1, Q2 = 0.3 W (0x25A)
3.8.2. Si3200 Power Calculation
PTH34 = power threshold for Q3, Q4 = 0.22 W
(0x1B5E)
When using the Si3200, it is also possible to detect the
thermal conditions of the linefeed circuit by calculating
the total power dissipated within the Si3200. This case
is similar to the transistor power equations case, with
the exception that the total power from all transistor
devices is dissipated within the same package
enclosure, and the total power result is placed in the
PSUM RAM location. The power calculation is derived
using the following equations:
PTH56 = power threshold for Q5, Q6 = 1 W (0x7D8)
PLPF12 = Q1/Q2 thermal LPF pole = 0x0012
(for SOT–89 package)
PLPF34 = Q3/Q4 thermal LPF pole = 0x008C
(for SOT–23 package)
PLPF56 = Q5/Q6 thermal LPF pole = 0x000E
(for SOT–223 package)
In the case where the Si3200 is used, thermal filtering
needs to be performed only on the total power reflected
in the PSUM RAM location. When the filter output
exceeds the total power threshold, an interrupt is
issued. The PTH12 RAM location is used to preset the
total power threshold for the Si3200, and the PLPF12
RAM location is used to preset the thermal low-pass
filter pole.
P
P
P
P
P
P
≅ (|V | + 0.75 V) x I
TIP Q1
Q1
Q2
Q3
Q4
Q5
Q6
≅ (|V
≅ (|V
| + 0.75 V) x I
Q2
RING
|+ 0.75 V) x I
BAT
Q3
≅ (|V | + 0.75 V) x I
BAT
Q4
≅ (|V | – |V
|) x I
Q5
BAT
RING
≅ (|V | – |V |) x I
Q6
BAT
TIP
PSUM = total dissipated power = P
+ P
+ P
+
Q3
Q1
Q2
P
+ P + P
Q4
Q5 Q6
Note: The Si3200 THERM pin must be connected to the
THERM a/b pin of the Si3220/Si3225 in order for the
38
Rev. 1.2
Si3220/25
When the THERM pin is connected from the Si3220 or The Si3200’s thermally-enhanced SOIC-16 package
Si3225 to the Si3200 (indicating the presence of an offers an exposed pad that improves thermal dissipation
Si3200), the resolution of the PTH12 and PSUM RAM out of the package when soldered to a topside PCB pad
locations is modified from 498 µW/LSB to 1059.6 µW/ connected to inner power planes. Using appropriate
LSB. Additionally, the τ
to accommodate the Si3200. For the Si3200, τ
value must be modified layout practices, the Si3200 can provide thermal
THERMAL
performance of 55 °C/W. The exposed path should be
THERMAL
is typically 0.7 s, assuming the exposed pad is connected to a low-impedance ground plane via a
connected to the recommended ground plane as stated topside PCB pad directly under the part. See package
in Table 1 on page 4. τ
decreases if the PCB outlines for PCB pad dimensions. In addition, an
THERMAL
layout does not provide sufficient thermal conduction. opposite-side PCB pad with multiple vias connecting it
See “AN58: Si3220/Si3225 Programmer’s Guide” for to the topside pad directly under the exposed pad will
details.
further improve the overall thermal performance of the
system. Refer to “AN55: Dual ProSLIC User Guide” for
optimal thermal dissipation layout guidelines.
Example calculations for PTH12 and PLPF12 in Si3200
mode are shown below:
The Dual ProSLIC chipset is designed with the ability to
source long loop lengths in excess of 18 kft but can also
accommodate short loop configurations. For example,
the Si3220 can operate from one of two battery supplies
depending on the operating state. When in the on-hook
PTH12 = Si3200 power threshold = 1 W (0x3B0)
PLPF12 = Si3200 thermal LPF pole = 2 (0x0010)
3.8.4. Automatic State Change Based on Power
Alarm
If either of the following situations occurs, the device state, the on-hook loop feed is generated from the
automatically transitions to the OPEN state:
ringing battery supply, generally –70 V or more. Once
the SLIC transitions to the off-hook state, a lower off-
hook battery supply (typically –24 V) supplies the
required current to power the loop if the loop length is
sufficiently short to accommodate the lower battery
supply. This battery switching method allows the SLIC
chipset to dissipate less power than when operating
from a –70 V battery supply. See “3.9. Automatic Dual
Battery Switching” for more details.
ꢀ Any of the transistor power alarm thresholds is
exceeded in the case of the discrete transistor
circuit.
ꢀ The total power threshold is exceeded when using
the Si3200.
To provide optimal reliability, the device automatically
transitions into the open state until the user changes the
state manually, independent of whether or not the power
alarm interrupt has been masked. The PQ1E–PQ6E
bits of the IRQEN3 register enable the interrupts for
each transistor power alarm, and the PQ1S to PQ6S
bits of the IRQVEC3 register are set when a power
alarm is triggered in the respective transistor. When
using the Si3200, the PQ1E bit enables the power alarm
interrupt, and the PQ1S bit is set when a Si3200 power
alarm is triggered.
In long loop applications, there is generally a single
battery supply (e.g., –48 V) available for powering the
loop in the off-hook state. When sourcing loop lengths
similar to the maximum specified service distance (e.g.,
18 kft.), most of the power is dissipated in the
impedance of the line. SLICs used in long-loop
applications must also be able to provide phone service
to customers who are located much closer to the line
card than the maximum loop length specified for the
system. This situation may cause substantial power to
be dissipated inside the SLIC chipset. A special power
offload circuit is recommended for single-battery
extended-loop applications. Refer to “AN91: Si3200
Power Off-load Circuit” for power offload circuit usage
guidelines.
3.8.5. Power Dissipation Considerations
The Dual ProSLIC devices rely on the Si3200 to power
the line from the battery supply. The PCB layout and
enclosure conditions should be designed to allow
sufficient thermal dissipation out of the Si3200, and a
programmable power alarm threshold ensures product
safety under all operating conditions. See "3.8. Power
Monitoring and Power Fault Detection" on page 36 for
more details on power alarm considerations.
Rev. 1.2
39
Si3220/25
Table 21. Register and RAM Locations Used for Power Monitoring and Power Fault Detection
Register/
RAM
Register/RAM
Bits
Measurement
Range
Resolution
Parameter
Mnemonic
Si3200 Total Power Output Monitor
Si3200 Power Alarm Interrupt Pending
Si3200 Power Alarm Interrupt Enable
PSUM
IRQVEC3
IRQEN3
PTH12
PSUM[15:0]
PQ1S
0 to 34.72 W
N/A
1059.6 µW
N/A
PQ1E
N/A
N/A
Q1/Q2 Power Alarm Threshold (discrete)
Q1/Q2 Power Alarm Threshold (Si3200)
PTH12[15:0]
0 to 16.319 W
0 to 34.72 W
498 µW
1059.6 µW
Q3/Q4 Power Alarm Threshold
Q5/Q6 Power Alarm Threshold
Q1/Q2 Thermal LPF Pole
PTH34
PTH56
PLPF12
PTH34[15:0]
PTH56[15:0]
PLPF12[15:3]
0 to 1.03 W
31.4 µW
498 µW
0 to 16.319 W
See “3.8.3. Power Filter and
Alarms”
Q3/Q4 Thermal LPF Pole
Q5/Q6 Thermal LPF Pole
PLPF34
PLPF56
PLPF34[15:3]
PLPF56[15:3]
See “3.8.3. Power Filter and
Alarms”
See “3.8.3. Power Filter and
Alarms”
Q1–Q6 Power Alarm Interrupt Pending
Q1–Q6 Power Alarm Interrupt Enable
IRQVEC3
IRQEN3
PQ1S–PQ6S
PQ1E–PQ6E
N/A
N/A
N/A
N/A
40
Rev. 1.2
Si3220/25
The BATSEL pins for both channels are controlled using
the BATSEL bit of the RLYCON register and can be
programmed to automatically switch to the lower battery
3.9. Automatic Dual Battery Switching
The Dual ProSLIC chipsets provide the ability to switch
between several user-provided battery supplies to aid
thermal management. Two specific scenarios where
this method may be required follow:
supply (V
) when the off-hook TIP-RING voltage is
BLO
low enough to allow proper operation from the lower
supply. When using the Si3220, this mode should
always be enabled to allow seamless switching
between the ringing and off-hook states. The same
switching scheme is used with the Si3225 to reduce
power by switching to a lower off-hook battery when
sourcing a short loop.
ꢀ Ringing to off-hook state transition (Si3220):
During the on-hook operating state, the Dual
ProSLIC chipset must operate from the ringing
battery supply to provide the desired ringing signal
when required. Once an off-hook condition is
detected, the Dual ProSLIC chipset must transition
to the lower battery supply (typically –24 V) to
reduce power dissipation during the active state. The
low current consumed by the Dual ProSLIC chipset
during the on-hook state results in very little power
dissipation while being powered from the ringing
battery supply, which can have an amplitude as high
as –100 V depending on the desired ringing
amplitude.
Automatic battery selection should be disabled before
using the manual battery select control bit (BSEL bit,
Register 5—RLYCON,
bit 5).
Contact
Silicon
Laboratories for information on how to disable
automatic battery selection.
Two thresholds are provided to enable battery switching
with hysteresis. The BATHTH RAM location specifies
the threshold at which the Dual ProSLIC device
switches from the low battery (V
) to the high battery
BLO
ꢀ On-hook to off-hook state, short loop feed
(Si3225): When sourcing both long and short loop
lengths, the Dual ProSLIC chipset can automatically
switch from the typical –48 V off-hook battery supply
to a lower off-hook battery supply (e.g., –24 V) to
reduce the total off-hook power dissipation. The Dual
ProSLIC chipset continuously monitors the TIP-
RING voltage and selects the lowest battery voltage
required to power the loop when transitioning from
the on-hook to the off-hook state, thus assuring the
lowest power dissipation.
(V ) due to an off-hook-to-on-hook transition. The
BATLTH RAM location specifies the threshold at which
BHI
the Si3220/Si3225 switches from V
to V
due to a
BHI
BLO
transition from the on-hook or ringing state to the off-
hook state or because the overhead during active Off-
Hook mode is sufficient to feed the subscriber loop
using a lower battery voltage.
The low-pass filter coefficient is calculated using the
following equation and is entered into the BATLPF RAM
location:
3
BATLPF = [(2πf x 4096)/800] x 2
The BATSELa and BATSELb pins switch between the
two battery voltages based on the operating state and
the TIP-RING voltage. Figure 19 illustrates the chip
connections required to implement an automatic dual
battery switching scheme. When BATSEL is pulled
Where f = the desired cutoff frequency of the filter
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of
10 Hz (0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
LOW, the desired channel is powered from the V
BLO
supply. When BATSEL is pulled HIGH, the V
supplies power to the desired channel.
source
BHI
Table 22 provides the register and RAM locations used
for programming the battery switching functions.
Rev. 1.2
41
Si3220/25
Table 22. Register and RAM Locations Used for Battery Switching
Parameter
Register/RAM
Mnemonic
Register/RAM Programmable
Bits Range
Resolution
(LSB Size)
High Battery Detect Threshold
Low Battery Detect Threshold
BATHTH
BATHTH[14:7] 0 to 160.173 V*
628 mV
(4.907 mV)
BATLTH
BATLTH[14:7]
0 to 160.173 V*
628 mV
(4.907 mV)
Ringing Battery Switch (Si3220 only)
Battery Select Indicator
RLYCON
RLYCON
BATLPF
GPO
BSEL
Toggle
Toggle
N/A
N/A
N/A
Battery Switching LPF
BATLPF[15:3]
0 to 4000h
*Note: Usable range for BATHTH and BATLTH is limited to the VBHI voltage.
Si3220
Si3225
Battery
Control
Logic
Battery
Sense
Circuit
BATSEL
SVBAT
40.2 kΩ
806 kΩ
BATSEL
Si3200
Battery
Select
Control
Linefeed
Circuitry
VBLO
VBATL
VBAT
VBATH
VBHI
Figure 19. External Battery Switching Using the Si3220/Si3225
42
Rev. 1.2
Si3220/25
When generating a high-voltage ringing amplitude using using the switch internal to the Si3200. The Si3220’s
the Si3220, the power dissipated during the OHT state GPO pin is used along with the external transistor circuit
typically increases due to operating from the ringing to switch the V
rail (the ringing voltage battery rail)
BRING
battery supply in this mode. To reduce power, the onto the Si3200’s V
pin when ringing is enabled. The
BAT
Si3220/Si3200 chipset provides the ability to GPO signal is driven automatically by the ringing
accommodate up to three separate battery supplies by cadence provided that the RRAIL bit of the RLYCON
implementing a secondary battery switch using a few register is set to 1 (signifying that a third battery rail is
low-cost external components as illustrated in Figure present).
22.
The Si3220’s BATSEL pin is used to switch between the
V
(typically –48 V) and V
(typically –24 V) rails
BHI
BLO
Si3220
806 kΩ
SVBAT
Si3200
0.1 µF
R101
CXT5401
R9
40.2 kΩ
VBAT
Q1
VBRING
VBLO
VBATH
VBATL
0.1 µF
10 kΩ
BATSEL
R102
Q2
402 kΩ
R103
D1
CXT5551
IN4003
VBHI
Figure 20. 3-Battery Switching with Si3220/Si3200
Table 23. Three-Battery Switching Components
Component
Value
Comments
D1
Q1
200 V, 200 mA
100 V PNP
1N4003 or similar
CXT5401 or
similar
Q2
100 V NPN
CXT5551 or
similar
R101
1/10 W, ± 5%
2.4 kΩ for V =3.3 V
DD
3.9 kΩ for V =5 V
DD
R102
R103
10 kΩ,1/10 W, ± 5%
402 kΩ,1/10 W,± 1%
Rev. 1.2
43
Si3220/25
and LFS field (LINEFEED Register) states can be
summarized as follows:
3.10. Loop Closure Detection
Loop closure detection is required to accurately signal a
terminal device going off-hook during the Active, On-
Hook Transmission (forward or reverse polarity), and
ringing linefeed states. The functional blocks required to
implement a loop closure detector are shown in
Figure 21, and the register set for detecting a loop
closure event is provided in Table 24. The primary input
to the system is the loop current sense value from the
voltage/current/power monitoring circuitry and is
ꢀ IQ1 = 0 if (CMH = 1 AND (LFS = 1 OR LFS = 3))
ꢀ IQ2 = 0 if (CMH = 1 AND (LFS = 5 OR LFS = 7))
The output of the ISP is the input to a programmable
digital low-pass filter that removes unwanted ac signal
components before threshold detection.
The low-pass filter coefficient is calculated using the
following equation and is entered into the LCRLPF RAM
location:
reported in the I
RAM address.
LOOP
3
LCRLPF = [(2πf x 4096)/800] x 2
The loop current (I
) is computed by the input signal
LOOP
Where f = the desired cutoff frequency of the filter.
processor (ISP) using the equations shown below.
Refer to Figure 18 on page 37 for the discrete bipolar
transistor references) used in the equation below (Q1,
Q2, Q5 and Q6 – note that the Si3200 has
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of 10
(0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
corresponding MOS transistors). The same I
LOOP
equation applies to the discrete bipolar linefeed as well
as the Si3200 linefeed device. The following equation is
conditioned by the CMH status bit in register LCRRTP
and by the linefeed state as indicated by the LFS field in
the LINEFEED register.
The output of the low-pass filter is compared to a
programmable threshold, LCROFFHK. Hysteresis is
enabled by programming
a
second threshold,
LCRONHK, to detect the loop going to an open or on-
hook state. The threshold comparator output feeds a
programmable debounce filter. The output of the
debounce filter remains in its present state unless the
input remains in the opposite state for the entire period
of time programmed by the loop closure debounce
interval, LCRDBI. There is also a loop closure mask
interval, LCRMASK, that is used to mask transients
caused when an internal ringing burst (with no offset)
ends in the presence of a high REN load. If the
debounce interval has been satisfied, the LCR bit is set
to indicate that a valid loop closure has occurred.
Iloop = IQ1 – IQ6 + IQ5 – IQ2 in TIP-OPEN or RING-OPEN
I
Q1 – IQ6 + IQ5 – IQ2
---------------------------------------------------
=
in all other states
2
If the CMHITH (RAM 36) threshold is exceeded, the
CMH bit is 1, and I is forced to zero in the
Q1
FORWARD-ACTIVE and TIP-OPEN states, or I
forced to zero in the REVERSE-ACTIVE and RING-
OPEN states. The other currents in the equation are
is
Q2
allowed to contribute normally to the I
value.
LOOP
The conditioning due to the CMH bit (LCRRTP Register)
IQ1
Input
Signal
Processor
ILOOP
IQ2
IQ5
IQ6
Digital
LPF
+
–
Loop
Closure
Mask
Debounce
Filter
LCR
LCRLPF
CMH LFS
Interrupt
Logic
LCRMASK
LCRDBI
LOOPS
Loop Closure
Threshold
LOOPE
LCROFFHK
LCRONHK
Figure 21. Loop Closure Detection Circuitry
44
Rev. 1.2
Si3220/25
Table 24. Register and RAM Locations Used for Loop Closure Detection
Parameter
Register/RAM
Mnemonic
Register/RAM Bits
Programmable
Range
LSB Size
Effective
Resolution
Loop Closure Interrupt
Pending
IRQVEC2
LOOPS
Yes/No
N/A
N/A
Loop Closure Interrupt Enable
Linefeed Shadow
IRQEN2
LINEFEED
LCRRTP
LCRDBI
LOOPE
LFS[2:0]
Yes/No
N/A
N/A
N/A
N/A
Monitor only
Monitor only
0 to 40.96 s
Loop Closure Detect Status
LCR
N/A
N/A
Loop Closure Detect Debounce
Interval
LCRDBI[15:0]
1.25 ms
1.25 ms
Loop Current Sense
ILOOP
ILOOP[15:0]
LCROFFHK[15:0]
LCRONHK[15:0]
50.54 to
101.09 mA
0 to 101.09 mA2
3.097 µA
3.097 µA
3.097 µA
500 µA1
396.4 µA
396.4 µA
Loop Closure Threshold
(on-hook to off-hook)
LCROFFHK
LCRONHK
Loop Closure Threshold
(off-hook to on-hook)
0 to 101.09 mA2
Loop Closure Filter Coefficient
Loop Closure Mask Interval
Notes:
LCRLPF
LCRLPF[15:3]
0 to 4000h
0 to 40.96s
N/A
N/A
LCRMASK
LCRMASK[15:0]
1.25 ms
1.25 ms
1. The effective ILOOP resolution is approximately 500 µA.
2. The usable range for LCRONHK and LCROFFHK is limited to 61 mA. Entering a value > 61 mA will disable threshold
detection.
The output of the ISP (I
) is the input to a
3.11. Ground Key Detection
LONG
programmable, digital low-pass filter, which removes
unwanted ac signal components before threshold
detection.
Ground key detection detects an alerting signal from the
terminal equipment during the tip open or ring open
linefeed states. The functional blocks required to
implement a ground key detector are shown in
Figure 22 on page 47, and the register set for detecting
a ground key event is provided in Table 27 on page 48.
The primary input to the system is the longitudinal
current sense value provided by the voltage/current/
power monitoring circuitry and reported in the ILONG
The low-pass filter coefficient is calculated using the
following equation and is entered into the LONGLPF
RAM location:
(2πf × 4096)
LONGLPF =
× 23
--------------------------------
800
RAM address. The I
provided the LFS bits in the linefeed register indicate
the device is in the tip open or ring open state.
value is produced in the ISP
LONG
Where f = the desired cutoff frequency of the filter.
The programmable range of the filter is from 0h (blocks
all signals) to 4000h (unfiltered). A typical value of 10
(0A10h) is sufficient to filter out any unwanted ac
artifacts while allowing the dc information to pass
through the filter.
The longitudinal current (I
) is computed as shown
LONG
in the following equation. Refer to Figure 18 on page 37
for the transistor references used in the equation (Q1,
Q2, Q5, and Q6—note that the Si3200 has
corresponding MOS transistors). The same I
equation applies to the discrete bipolar linefeed as well
as the Si3200 linefeed device.
The output of the low-pass filter is compared to the
programmable threshold, LONGHITH. Hysteresis is
LONG
enabled by programming
a
second threshold,
LONGLOTH, to detect when the ground key is released.
The threshold comparator output feeds a programmable
debounce filter.
I
Q1 – IQ6 – IQ5 + IQ2
---------------------------------------------------
=
ILONG
2
Rev. 1.2
45
Si3220/25
The output of the debounce filter remains in its present
state unless the input remains in the opposite state for
the entire period of time programmed by the loop
closure debounce interval, LONGDBI. If the debounce
interval is satisfied, the LONGHI bit is set to indicate
that a valid ground key event has occurred.
When the Si3220/25 detects a ground key event, the
linefeed automatically transitions from the TIP-OPEN
(or RING-OPEN) state to the FORWARD-ACTIVE (or
REVERSE-ACTIVE) state. However, this automatic
state transition is triggered by the LCR bit becoming
active (i.e., =1), and not by the LONGHI bit.
While I
is used to generate the LONGHI status bit,
LONG
a transition from TIP-OPEN to the FORWARD-ACTIVE
state (or from the RING-OPEN to the REVERSE-
ACTIVE state) occurs when the RING terminal (or TIP
terminal) is grounded and is based on the LCR bit and
implicitly on exceeding the LCROFFHK threshold.
As an example of ground key detection, suppose that
the Si3220/25 has been programmed with the current
values shown in Table 25.
Table 25. Settings for Ground Key Example
ILIM
21 mA
14 mA
10 mA
7 mA
LCROFFHK
LCRONHK
LONGHITH
LONGLOTH
5 mA
With the settings of Table 25, the behavior of I
,
LOOP
I
, LCR, LONGHI, and CMHIGH is as shown in
LONG
Table 26. The entries under “Loop State” indicate the
condition of the loop, as determined by the equipment
terminating the loop. The entries under “LINEFEED
Setting” indicate the state initially selected by the host
CPU (e.g., TIP-OPEN) and the automatic transition to
the FORWARD-ACTIVE state due to a ground key
event (when RING is connected to GND). The transition
from state #2 to state #3 in Table 26 is the automatic
transition from TIP-OPEN to FWD-ACTIVE in response
to LCR = 1.
46
Rev. 1.2
Si3220/25
Table 26. State Transitions During Ground Key Detection
#
1
2
3
4
5
Loop
State
LINEFEED
State
I
I
LCR LONGHI CMHIGH
LOOP
LONG
(mA)
(mA)
LOOP OPEN
LFS = 3
(TIP-OPEN)
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
RING-GND
LFS = 3
(TIP-OPEN)
22
22
21
0
–11
–11
0
RING-GND
LFS = 1
(FWD-ACTIVE)
LOOP CLOSURE
LOOP OPEN
LFS = 1
(FWD-ACTIVE)
LFS = 1
0
(FWD-ACTIVE)
IQ1
IQ2
IQ5
IQ6
Input
Signal
Processor
ILONG
Digital
LPF
+
Debounce
Filter
LONGHI
–
LONGLPF
LONGDBI
Interrupt
Logic
LFS
LONGS
Ground Key
Threshold
LONGE
LONGHITH LONGLOTH
Figure 22. Ground Key Detection Circuitry
Rev. 1.2
47
Si3220/25
Table 27. Register and RAM Locations Used for Ground Key Detection
Register/
RAM
Register/RAM
Bits
Programmable
Range
LSB
Size
Resolution
Parameter
Mnemonics
Ground Key Interrupt Pending
Ground Key Interrupt Enable
Ground Key Linefeed Shadow
Ground Key Detect Status
IRQVEC2
IRQEN2
LONGS
LONGE
Yes/No
Yes/No
N/A
N/A
N/A
N/A
LINEFEED
LCRRTP
LONGDBI
LFS[2:0]
Monitor only
Monitor only
0 to 40.96 s
N/A
N/A
LONGHI
N/A
N/A
Ground Key Detect Debounce
Interval
LONGDBI[15:0]
1.25 ms
1.25 ms
Longitudinal Current Sense
ILONG
ILONG[15:0]
Monitor only
See Table 20
396.4 µA
Ground Key Threshold
(enabled)
LONGHITH
LONG-
HITH[15:0]
0 to
101.09 mA*
3.097 µA
3.097 µA
N/A
Ground Key Threshold
(released)
LONGLOTH
LONGLPF
LON-
GLOTH[15:0]
0 to
101.09 mA*
396.4 µA
N/A
Ground Key Filter Coefficient
LONGLPF[15:3]
0 to 4000h
*Note: The usable range for LONGHITH and LONGLOTH is limited to 16 mA. Setting a value >16 mA will disable threshold
detection.
48
Rev. 1.2
Si3220/25
3.12. Ringing Generation
®
The Si3220-based Dual ProSLIC chipset provides a
balanced ringing waveform with or without dc offset.
The ringing frequency, cadence, waveshape, and dc
offset are register-programmable.
RLOOP
+
ROUT
Using a balanced ringing scheme, the ringing signal is
applied to both the TIP and the RING lines using ringing
waveforms that are 180° out of phase with each other.
The resulting ringing signal seen across TIP-RING is
twice the amplitude of the ringing waveform on either
the TIP or the RING line, which allows the ringing
circuitry to withstand half the total ringing amplitude
seen across TIP-RING.
RLOAD
VTERM
VRING
–
Figure 24. Simplified Loop Circuit During
Ringing
VRING
The following equation can be used to determine the
TIP-RING ringing amplitude required for a specific load
and loop condition:
RING
VOFF
SLIC
RLOAD
TIP
---------------------------------------------------------------------
×
VTERM = VRING
(RLOAD + RLOOP + ROUT
)
VTIP
where
R
LOOP= (0.09 Ω per foot for 26AWG wire)
GND
VCM
VTIP
ROUT = 320 Ω
V PK
and
VOFF
7000 Ω
-------------------
=
RLOAD
#REN
When ringing longer loop lengths, adding a dc offset
voltage is necessary to reliably detect a ring trip
condition (off-hook phone). Adding dc offset to the
ringing signal decreases the maximum possible ringing
amplitude. Adding significant dc offset also increases
the power dissipation in the Si3200 and may require
additional airflow or modified PCB layout to maintain
acceptable operating temperatures in the line feed
circuitry. The Dual ProSLIC chipset automatically
VOV
VRING
VBATH
Figure 23. Balanced Ringing
An internal ringing scheme provides >40 Vrms into a 5
REN load at the terminal equipment using a user-
provided ringing battery supply. The specific ringing
supply voltage required depends on the desired ringing
voltage. The ringing amplitude at the terminal
equipment also depends on the loop impedance and
the load impedance in REN. The simplified circuit in
Figure 24 shows the relationship between loop
impedance and load impedance.
applies and removes the ringing signal during V
-
OC
crossing periods to reduce noise and crosstalk to
adjacent lines. Table 28 provides a list of registers
required for internal ringing generation
Rev. 1.2
49
Si3220/25
Table 28. Register and RAM Locations Used for Ringing Generation
Parameter
Register/RAM Register/RAM Bits
Mnemonic
Programmable
Range
Resolution
(LSB Size)
Ringing Waveform
RINGCON
RINGCON
RINGCON
TRAP
TAEN
TIEN
Sinusoid/Trapezoid
Enabled/Disabled
Enabled/Disabled
N/A
N/A
N/A
Ringing Active Timer Enable
Ringing Inactive Timer
Enable
Ringing Oscillator Enable
Monitor
RINGCON
RINGEN
Enabled/Disabled
0 to 8.19 s
N/A
Ringing Oscillator Active
Timer
RINGTALO/
RINGTAHI
RINGTA[15:0]
125 µs
Ringing Oscillator Inactive
Timer
RINGTILO/
RINGTIHI
RINGTI[15:0]
LF[2:0]
0 to 8.19 s
000 to 111
125 µs
N/A
Linefeed Control
LINEFEED
(Initiates Ringing State)
On-Hook Line Voltage
Ringing Voltage Offset
Ringing Frequency
VOC
VOC[15:0]
0 to 63.3 V
0 to 63.3 V
4 to 100 Hz
1.005 V (4.907 mV)
1.005 V (4.907 mV)
RINGOF
RINGOF[15:0]
RINGFRHI/
RINGFRLO
RINGFRHI[14:3]/
RINGFRLO[14:3]
Ringing Amplitude
RINGAMP
VRNGNG
RINGAMP[15:0]
VRNGNG[15:0]
0 to 160.173 V
332.04 V
628 mV (4.907 mV)
External Ringing Generator
Voltage Sense
1.302 V
(10.172 mV)
External Ringing Generator
Current Sense
IRNGNG
IRNGNG[15:0]
662.83 mA
2.6 mA (20.3 µA)
Ringing Initial Phase
Sinusoidal
RINGPHAS
RINGPHAS[15:0]
N/A
N/A
Trapezoid
External Ringing
0 to 1.024 s
0 to 662.83 mA
31.25 µs
2.6 mA (20.3 µA)
Ringing Relay Driver Enable
(Si3225 only)
RELAYCON
RDOE
Enabled/Disabled
N/A
Ringing Overhead Voltage
Ringing Speedup Timer
VOVRING
VOVRING[15:0]
0 to 63.3 V
0 to 40.96 s
1.005 V (4.907 mV)
1.25 ms
SPEEDUPR
SPEEDUPR[15:0]
50
Rev. 1.2
Si3220/25
3.12.1. Internal Sinusoidal Ringing
3.12.2. Internal Trapezoidal Ringing
A sinusoidal ringing waveform is generated by the on- In addition to the traditional sinusoidal ringing
chip digital tone generator. The tone generator used to waveform, the Dual ProSLIC can generate a trapezoidal
generate ringing tones is a two-pole resonator with a ringing waveform similar to the one illustrated in
programmable frequency and amplitude. Since ringing Figure 26.
The
RINGFREQ,
RINGAMP,
and
frequencies are low compared to the audio band RINGPHAS RAM addresses are used for programming
signaling frequencies, the sinusoid is generated at a the ringing wave shape as follows:
1 kHz rate. The ringing generator is programmed via the
RINGFREQ, RINGAMP, and RINGPHAS registers. The
equations are as follows:
RINGPHAS = 4 x Period x 8000
15
RINGAMP = (Desired V/160.8 V) x (2 )
RINGFREQ = (2 x RINGAMP)/(t x 8000)
RISE
2πf
1000Hz
RINGFREQ = coeff × 223
RINGFREQ is a value that is added or subtracted from
the waveform to ramp the signal up or down in a linear
fashion. This value is a function of rise time, period, and
amplitude, where rise time and period are related
through the following equation for the crest factor of a
trapezoidal waveform.
⎛
⎝
⎞
⎠
--------------------
coeff = cos
DesiredVPK
---------------------------------
160.173V
1
15
1 – coeff
--
RINGAMP =
----------------------- × (2 ) ×
4
1 + coeff
3
4
1
CF2
⎛
⎞
⎠
--
----------
tRISE
=
T 1 –
⎝
RINGPHAS = 0
For example, to generate a 60 V
(87 V ), 20 Hz
rms
PK
ringing signal, the equations are as follows:
where
1
--------------
T = Period =
2π20
1000Hz
⎛
⎝
⎞
⎠
fRING
--------------------
coeff = cos
= 0.9921
CF = desired crest factor
RINGFREQ = 0.9921 × (223) = 8322461 =
0x7EFD9D
So, for a 90 V , 20 Hz trapezoidal waveform with a
crest factor of 1.3, the period is 0.05 s, and the rise time
requirement is 0.015 s.
PK
1
4
15
85
160.173
RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640)
00789
1.99211
--
---------------------
RINGAMP =
--------------------- × (2 ) ×
= 273= 0x111
15
RINGAMP = 90/160.8 x (2 ) = 18340 (0x47A5)
In addition to the variable frequency and amplitude, a
selectable dc offset (V ), which can be added to the
waveform, is included. The dc offset is defined in the
RINGOF RAM location.
RINGFREQ = (2 x RINGAMP)/(0.0153 x 8000) = 300
(0x012C)
OFF
The time registers and interrupts described in the
sinusoidal ring description also apply to the trapezoidal
ring waveform:
As with the tone generators, the ringing generator has
two timers which function as described above. They
allow on/off cadence settings up to 8 s on/8 s off. In
addition to controlling ringing cadence, these timers
control the transition into and out of the ringing state.
3.13. Internal Unbalanced Ringing
The Si3220 also provides the ability to generate a
traditional battery-backed unbalanced ringing waveform
for ringing terminating devices that require a high dc
content or for use in ground-start systems that cannot
tolerate a ringing waveform on both the TIP and RING
leads. The unbalanced ringing scheme applies the
ringing signal to the RING lead; the TIP lead remains at
the programmed VCM voltage that is very close to
ground. A programmable dc offset can be preset to
provide dc current for ring trip detection. Figure 25
illustrates the internal unbalanced ringing waveform.
To initiate ringing, the user must program the
RINGFREQ, RINGAMP, and RINGPHAS RAM
addresses as well as the RINGTA and RINGTI registers
and select the ringing waveshape and dc offset. After
this is done, TAEN and TIEN bits are set as desired.
The ringing state is invoked by a write to the linefeed
register. At the expiration of RINGTA, the Dual
®
ProSLIC turns off the ringing waveform and goes to
the on-hook transmission state. At the expiration of
RINGTI, ringing is initiated again. This process
continues as long as the two timers are enabled and the
linefeed register remains in the ringing state.
Rev. 1.2
51
Si3220/25
3.14. Ringing Coefficients
VRING
The ringing coefficients are calculated in decimals for
sinusoidal and trapezoidal waveforms. The RINGPHAS
and RINGAMP hex values are decimal to hex
conversions in 16-bit 2’s complement representations
for their respective RAM locations.
RING
DC Offset
TIP
Si3220
To obtain sinusoidal RINGFREQ RAM values, the
RINGFREQ decimal number is converted to a 24-bit 2’s
complement value. The lower 12 bits are placed in
RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are
cleared to 0. The upper 12 bits are set in a similar
manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the
sign bit, and RINGFRHI bits 2:0 are cleared to 0.
GND
VTIP
VCM
DC Offset
VOFF
-80V
VRING
VOVRING
VBATR
For
example,
the
register
values
for
RINGFREQ = 0x7EFD9D are as follows:
Figure 25. Internal Unbalanced Ringing
RINGFRHI = 0x3F78
RINGFRLO = 0x6CE8
To enable unbalanced ringing, set the RINGUNB bit of
the RINGCON register. As with internal balanced
ringing, the unbalanced ringing waveform is generated
by using one of the two on-chip tone generators
provided in the Si3220. The tone generator used to
generate ringing tones is a two-pole resonator with
programmable frequency and amplitude. Since ringing
frequencies are low compared to the audio band
signaling frequencies, the ringing waveform is
generated at a 1 kHz rate.
To obtain trapezoidal RINGFREQ RAM values, the
RINGFREQ decimal number is converted to an 8-bit, 2’s
complement value. This value is loaded into RINGFRHI.
RINGFRLO is not used.
VTIP-RING
The ringing generator is programmed via the RINGAMP,
RINGFREQ, and RINGPHAS registers. The RINGOF
register is used in to set the dc offset position around
which the RING lead will oscillate. Unbalanced ringing
VOFF
is centered at –80 V instead of V
/ 2. Use the ring
T = 1/freq
BAT
offset register (RINGOF, indirect Register 56) to position
the dc offset as desired. The dc offset is set at a dc point
equal to VCM – (–80 V + VOFF), where VOFF is the
value that is input into the RINGOF RAM location.
Positive VOFF values will cause the dc offset point to
move closer to ground (lower dc offset), and negative
VOFF values will have the opposite effect. The dc offset
can be set to any value; however, the ringing signal will
be clipped digitally if the dc offset is set to a value that is
less than half the ringing amplitude. In general, the
following equation must hold true to ensure the battery
voltage is sufficient to provide the desired ringing
amplitude:
tRISE
time
Figure 26. Trapezoidal Ringing Waveform
3.14.1. Ringing DC Offset Voltage
A dc offset voltage can be added to the Si3220’s ac
ringing waveform by programming the RINGOF RAM
location to the appropriate setting. The value of
RINGOF is calculated as follows:
VOFF
15
--------------
RINGOF =
× 2
|V
| > |V
+ (–80 V + V
) + V
|
OVRING
BATR
RING,PK
OFF
160.8
It is possible to create reverse polarity unbalanced
ringing waveforms (the TIP lead oscillates while the
RING lead stays constant) by setting the UNBPOLR bit
of the RINGCON register. In this mode, the polarity of
VOFF must also be reversed (in normal ringing polarity
VOFF is subtracted from –80 V, and in reverse polarity,
ringing VOFF is added to –80 V).
52
Rev. 1.2
Si3220/25
3.14.2. External Unbalanced Ringing
The system design is flexible to address varying loop
lengths of different applications. An ac ring trip detection
scheme cannot reliably detect an off-hook condition
when sourcing longer loop lengths, as the 20 Hz ac
impedance of an off-hook long loop is indistinguishable
from a heavily-loaded (5 REN) short loop in the on-hook
state. Therefore, a dc ring trip detection scheme is
required when sourcing longer loop lengths.
The Si3225 supports centralized, battery-backed
unbalanced ringing schemes by providing a ringing
relay driver as well as inputs from an external ring trip
circuit. Using this scheme, line-card designers can use
the Dual ProSLIC chipset in existing system
architectures with minimal system changes.
3.14.3. Linefeed Overhead Voltage Considerations
During Ringing
The Si3220 can implement either an ac or dc-based ring
trip detection scheme depending on the application. The
Si3225 allows external dc ring trip detection when using
The ringing mode output impedance allows ringing
operation without overhead voltage modification
(VOVR = 0). If an offset of the ringing signal from the
ring lead is desired, VOVR can be used for this
purpose.
a
battery-backed external ringing generator by
monitoring the ringing feed path through two sensing
inputs on each channel. By monitoring this path, the
Dual ProSLIC detects a dc current flowing in the loop
once the end equipment has gone off-hook. Table 29
3.14.4. Ringing Power Considerations
The total power consumption of the Si3220/Si3200 provides recommended register and RAM settings for
chipset using internal ringing generation is dependent various applications, and Table 30 lists the register and
on the V
supply voltage, desired ringing amplitude, RAM addresses that must be written or monitored to
DD
total loop impedance, and ac load impedance (number correctly detect a ring trip condition.
of REN). The following equations can be used to
Figure 27 illustrates the internal functional blocks that
approximate the total current required for each channel
during ringing mode:
correctly detect and process a ring trip event. The
primary input to the system is the loop current sense
(ILOOP) value provided by the loop monitoring circuitry
and reported in the ILOOP RAM location register. The
ILOOP RAM location value is processed by the ISP
block when the LFS bits in the linefeed register indicate
the device is in the ringing state. The output of the ISP
then feeds into a pair of programmable, digital low-pass
filters, one for the ac ring trip detection path and one for
the dc path. The ac path also includes a full-wave
rectifier block prior to the LPF block. The outputs of
each low-pass filter block are then passed on to a
programmable ring trip threshold (RTACTH for ac
detection and RTDCTH for dc detection). Each
threshold block output is then fed to a programmable
debounce filter to ensure a valid ring trip event. The
output of each debounce filter remains constant unless
the input remains in the opposite state for the entire
period of time set using the ac and dc ring trip debounce
interval registers, RTACDB and RTDCDB. The outputs
of both debounce filter blocks are then ORed together. If
either the ac or the dc ring trip circuits indicate that a
valid ring trip event has occurred, the RTP bit is set.
Either the ac or dc ring trip detection circuits are
disabled by setting the respective ring trip threshold
sufficiently high so that it does not trip under any
condition. A ring trip interrupt is also generated if the
RTRIPE bit is enabled.
VRING,PK
---------------------- --
+ IDD,OH
2
π
IDD,AVE
=
×
ZLOOP
VRING,PK
---------------------- --
2
π
IBAT,AVE
=
×
ZLOOP
where:
VRING,PK = VRING,RMS
× 2
ZLOOP = RLOOP + RLOAD + ROUT
R
R
R
= 7000/REN (for North America)
= loop impedance
LOAD
LOOP
= ProSLIC output impedance = 320 Ω
OUT
I
= I overhead current
DD
DD,OH
= 22 mA for V = 3.3 V
DD
= 26 mA for V = 5 V
DD
3.15. Ring Trip Detection
A ring trip event signals that the terminal equipment has
transitioned to an off-hook state after ringing has
commenced, ensuring that the ringing signal is removed
before normal speech begins. The Dual ProSLIC is
designed to implement either an ac or dc-based internal
ring trip detection scheme or a combination of both
schemes.
Rev. 1.2
53
Si3220/25
3.15.1. Ringtrip Timeout Counter
mode change (active mode). The ringtrip timeout
counter ensures ringing is exited within its time setting
(RTCOUNT x 1.25 ms/LSB, typically 200 ms).
The Dual ProSLIC incorporates a ringtrip timeout
counter, RTCOUNT, that will monitor the status of the
ringing control. When exiting ringing, the Dual ProSLIC 3.15.2. Ringtrip Debounce Interval
will allow the ringtrip timeout counter a sufficient amount
The ac and dc ring trip debounce intervals can be
calculated based on the following equations:
of time (RTCOUNT x 1.25 ms/LSB) for the mode to
switch to On-hook Transmission or Active. The mode
that is being exited to is governed by whether the
command to exit ringing is a ringing active timer
expiration (on-hook transmission) or ringtrip/manual
RTACDB = t
RTDCDB = t
(1600/RTPER)
(1600/RTPER)
debounce
debounce
RTACTH
AC Ring Trip
Threshold
LFS
_
Debounce
Filter_AC
Input
Signal
Processor
RTP
Digital
LPF
Full Wave
Rectifier
ILOOP
+
Interrupt
Logic
RTACDB
RTRIPS
RTPER
Digital
LPF
RTRIPE
+
Debounce
Filter_DC
_
DC Ring Trip
Threshold
RTDCDB
RTDCTH
Figure 27. Ring Trip Detect Processing Circuitry
54
Rev. 1.2
Si3220/25
Table 29. Recommended Values for Ring Trip Registers and RAM Addresses1
Ringing
Method
Ringing
Frequency
DC
Offset
Added?
RTPER
RTACTH
RTDCTH
RTACDB/
RTDCDB
Yes
No
800/fRING
800/fRING
2(800/
221 x RTPER
0.577(RTPER x VOFF
)
)
16–32 Hz
33–60 Hz
1.59 x VRING,PK x RTPER
32767
Internal
(Si3220)
Yes
221 x RTPER
0.577(RTPER x VOFF
32767
fRING
2(800/
fRING
)
See Note 2
No
Yes
Yes
1.59 x VRING,PK x RTPER
)
16–32 Hz
33–60 Hz
800/fRING
32767
32767
0.067 x RTPER x VOFF
0.067 x RTPER x VOFF
External
(Si3225)
2(800/
fRING
)
Notes:
1. All calculated values should be rounded to the nearest integer.
2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations.
Table 30. Register and RAM Locations Used for Ring Trip Detection
Register/RAM
Mnemonic
Register/RAM
Bits
Programmable
Range
Resolution
Parameter
Ring Trip Interrupt Pending
Ring Trip Interrupt Enable
AC Ring Trip Threshold
IRQVEC2
IRQEN2
RTACTH
RTDCTA
RTPER
RTRIPS
RTRIPE
Yes/No
Enabled/Disabled
See Table 29
See Table 29
See Table 29
N/A
N/A
N/A
RTACTH[15:0]
RTDCTH[15:0]
RTPER[15:0]
LFS[2:0]
DC Ring Trip Threshold
Ring Trip Sample Period
Linefeed Shadow (monitor only)
LINEFEED
LCRRTP
N/A
N/A
Ring Trip Detect Status
(monitor only)
RTP
N/A
AC Ring Trip Detect Debounce
Interval
RTACDB
RTDCDB
ILOOP
RTACDB[15:0]
RTDCDB[15:0]
ILOOP[15:0]
0 to 40.96 s
0 to 40.96 s
1.25 ms
1.25 ms
DC Ring Trip Detect Debounce
Interval
Loop Current Sense
(monitor only)
0 to 101.09 mA
See
Table 20
3.15.3. Loop Closure Mask
3.15.4. Si3220 Ring Trip Detection
The Dual ProSLIC implements a loop closure mask to The Si3220 provides the ability to process a ring trip
ensure mode change between ringing and active or on- event using an ac-based detection scheme. Using this
hook transmission without causing an erroneous loop scheme eliminates the need to add dc offset to the
closure detection. The loop closure mask register, ringing signal, which reduces the total power dissipation
LCRMASK, should be set such that loop closure during the ringing state and maximizes the available
detection is ignored for the time (LCRMASK 1.25 ms/ ringing amplitude. This scheme is valid for shorter loop
LSB). The programmed time is set to mask detection of lengths only since it cannot reliably detect a ring trip
transitional currents that occur when exiting the ringing event if the off-hook line impedance overlaps the on-
mode while driving a reactive load (i.e., 5 REN). A hook impedance at 20 Hz.
typical setting is 80 ms (LCRMASK = 0x40).
Rev. 1.2
55
Si3220/25
The Si3220 can also add a dc offset component to the
ringing signal and detect a ring trip event by monitoring
the dc loop current flowing once the terminal equipment
transitions to the off-hook state. Although adding dc
offset reduces the maximum available ringing amplitude
(using the same ringing supply), this method is required
to reliably detect a valid ring trip event when sourcing
longer loop lengths. The dc offset can be programmed
from 0 to 64.32 V in the RINGOF RAM address as
required to produce adequate dc loop current in the off-
hook state. Depending on the loop length and the ring
trip method, the ac or dc ring trip detection circuits are
disabled by setting their respective ring trip thresholds,
RTACTH or RTDCTH, sufficiently high so that they do
not trip under any condition.
VDD
VCC
Si3220/
Si3225
3 V/5 V Relay
(polarized or
non-polarized)
Relay
Driver
Logic
RRDa/b
TRD1a/b
TRD2a/b
GDD
3.15.5. Si3225 Ring Trip Detection
Figure 28. Dual ProSLIC Internal Relay Drive
Circuitry
The Si3225 implements an external ring trip detection
scheme when using a standard battery-backed external
ringing generator. In this application, the centralized
ringing generator produces an unbalanced ringing
signal that is distributed to individual TIP/RING pairs. A
per-channel ringing relay is required to disconnect the
Si3225 from the TIP/RING pair and apply the ringing
signal. By monitoring the ringing feed path across a ring
The internal driver logic and drive circuitry are powered
by the same V supply as the chip’s main V supply
DD
DD
(V
–V
pins). When operating external relays from
DD1
DD4
a V supply equal to the chip’s V supply, an internal
CC
DD
diode network provides protection against overvoltage
conditions from flyback spikes when the relay is
opened. Either 3 V or 5 V relays can be used in the
configuration shown in Figure 28, and either polarized
feed sense resistor (R
in Figure 31 on page 59) in
RING
series with the ringing source, the Si3225 can detect the
dc current path created when the hook switch inside the
terminal equipment closes. The internal ring trip
detection circuitry is identical to that illustrated in
Figure 27. Figure 31 illustrates the typical external ring
trip circuitry required for the Si3225. Because of the
long loop nature of these applications, a dc ring trip
detection scheme is typically used. The user can
disable the ac ring trip detection circuitry by setting the
RTACTH threshold sufficiently high so it does not trip
under any condition.
or non-polarized relays are acceptable if the V
and
CC
V
supplies are identical. The input impedance, R , of
DD
IN
the relay driver pins is a constant 11 Ω while sinking
less than the maximum rated 85 mA into the pin.
If the operating voltage of the relay (V ) is higher than
CC
the Dual ProSLIC V supply voltage, an external drive
DD
circuit is required to eliminate leakage from V to V
CC
DD
through the internal protection diode. In this
configuration, a polarized relay will provide optimal
overvoltage
protection
and
minimal
external
components. Figure 29 illustrates the required external
drive circuit, and Table 31 provides recommended
3.16. Relay Driver Considerations
The Dual ProSLIC devices include up to three
dedicated relay drivers to drive external ringing and/or
test relays. Test relay drivers TRD1a, TRD1b, TRD2a,
and TRD2b are provided in all product versions, and
ringing relay drivers RRDa and RRDb are included for
the Si3225 only. In most applications, the relay can be
driven directly from the Dual ProSLIC with no external
relay drive circuitry required. Figure 28 illustrates the
internal relay driver circuitry using a 3 V or 5 V relay.
values for R
for typical relay characteristics and V
DRV
CC
supplies. The output impedance, R
, of the relay
OUT
driver pins is a constant 63 Ω while sourcing less than
the maximum rated 28 mA out of the pin.
56
Rev. 1.2
Si3220/25
VCC
VDD
Si3220/
Si3225
Polarized
relay
IDRV
RRDa/b
TRD1a/b
TRD2a/b
Q1
RDRV
Figure 29. Driving Relays with VCC > VDD
The maximum allowable R
value can be calculated with the following equation:
DRV
(VDD,MIN – 0.6 V)(RRELAY)(βQ1,MIN
------------------------------------------------------------------------------------------------
– RSOURCE
)
MaxRDRV
=
V
CC,MAX – 0.3 V
Where βQ1,MIN ~ 30 for a 2N2222.
Table 31. Recommended RDRV Values
ProSLIC V
Relay V
Relay R
Maximum R
DRV
Recommended 5% Value
DD
CC
COIL
3.3 V ±5%
5 V ±5%
3.3 V ±5%
5 V ±5%
64 Ω
Not Required
Not Required
2718 Ω
—
178 Ω
—
3.3 V ±5%
3.3 V ±5%
3.3 V ±5%
3.3 V ±5%
5 V ±5%
5 V ±5%
178 Ω
2.7 kΩ
5.6 kΩ
8.2 kΩ
11 kΩ
9.1 kΩ
13 kΩ
18 kΩ
12 V ±10%
24 V ±10%
48 V ±10%
12 V ±10%
24 V ±10%
48 V ±10%
1028 Ω
2880 Ω
7680 Ω
1028 Ω
2880 Ω
7680 Ω
6037 Ω
8364 Ω
11092 Ω
9910 Ω
5 V ±5%
13727 Ω
18202 Ω
5 V ±5%
Rev. 1.2
57
Si3220/25
58
Rev. 1.2
Si3220/25
VOFF VRING
_
510 Ω
+
806 kΩ
806 kΩ
Relay
Phone
RING
Hook
Switch
Protection
Si3200
Si3225
TIP
VDD
Figure 31. Si3225 External Ring Trip Circuitry
3.16.1. Ringing Relay Activation During Zero
Crossings
timing sequence for a typical ringing relay control
application.
The Si3225 is for applications that use a centralized During a typical ringing sequence, the Si3225 monitors
ringing generator and a per-channel ringing relay to both the ringing relay current (IRNGNG) and the
connect the ringing signal to the TIP/RING pair. The RINGEN bit of the RINGCON register. The RINGEN bit
Si3225 has one relay driver output per channel (RRDa toggles because of pre-programmed ringing cadence or
and RRDb) that can drive a mechanical or solid-state
a
change in operating state. COUNTER0 and
DPDT relay. To reduce impulse noise that can couple COUNTER1 are restarted at each alternating zero
into adjacent lines, the relay should be closed when current crossing event, and the delay period,
there is zero voltage across the relay contacts and ZERDELAY, equal to the ringing frequency period less
opened during periods when there is zero current the desired advance firing time, D, is entered by the
through the contacts.
user. If either counter reaches the same value as
ZERDELAY, the relay control signal is enabled when the
RINGEN bit transition has already occurred. During
typical ringing bursts, the LFS bits of the linefeed
register toggle between the RINGING and OHT states
based on the pre-programmed ringing cadence. The
transition from OHT to RINGING is synchronized with
the RRD state transitions, so the ringing burst starts
immediately. The transition from RINGING to OHT is
gated by a user-programmed delay period, LFSDELAY,
3.16.2. Closing the Relay at Zero Voltage
Internal voltage monitoring circuitry closes the relay at
zero voltage with respect to the line voltage. By
observing the phase of the ringing signal and constantly
monitoring the open-circuit T-R voltage, V , the
Si3225 can detect the next time when there is zero
voltage across the relay contacts.
OC
3.16.3. Opening the Relay at Zero Current
Opening the ringing relay at zero current also is which ensures the ringing burst has ceased before
accomplished using the internal monitoring circuitry and going to the OHT state or to the ACTIVE state in
prevents arcing from excess current flow when the relay response to a linefeed state change.
contacts are opened. The current flowing through the
3.17. Polarity Reversal
ringing relay is continuously monitored in the IRNGNG
RAM address, and two internal counters (COUNTER0 The Dual ProSLIC devices support polarity reversal for
and COUNTER1) detect time elapsed since the last two message-waiting functionality and various signaling
zero current crossings based on the ringing period and modes. The ramp rate can be programmed for a smooth
predict when the next zero crossing occurs. The ringing transition or an abrupt transition to accommodate
relay current and internal counters are both updated at different application requirements. A wink function is
an 8 kHz rate. To account for the mechanical delay of provided for special equipment that responds to a
the relay, a programmable advance firing timer allows smooth ramp to V = 0 V. Table 32 illustrates the
OC
the user to initiate relay opening up to 10 ms prior to the register bits required to program the polarity reversal
zero current crossing event. Figure 30 illustrates the modes.
Rev. 1.2
59
Si3220/25
Setting the linefeed register to the opposite polarity A wink function slowly ramps down the TIP-RING
immediately reverses (hard reversal) the line polarity. voltage (V ) to 1 followed by a return to the original
OC
For example, to transition from Forward Active mode to VOC value (set in the VOC RAM location). This scheme
Reverse Active mode changes LF[2:0] from 001 to 101. lights a message-waiting lamp in certain handsets. No
Polarity reversal is accommodated in the OHT and change to the linefeed register is necessary to enable
ground start modes. The POLREV bit is a read-only bit this function. Instead, the user sets the VOCZERO bit to
that reflects if the device is in polarity reversal mode. 1 so that the TIP-RING voltage collapses to 0 V at the
For smooth polarity reversal, set the PREN bit to 1 and rate programmed by the RAMP bit. Setting the
the RAMP bit to 0 or 1 depending on the desired ramp VOCZERO bit back to 0 returns the TIP-RING voltage
rate (see Table 32). Polarity reversal is then to its normal setting. With a software timer, the user can
accomplished by toggling the linefeed register from automate the cadence of the wink function. Figure 32
forward to reverse modes as desired.
illustrates the wink function.
Table 32. Register and RAM Locations used for Polarity Reversal
Parameter
Programmable Range
Register/RAM Register/RAM
Bits
Mnemonic
LINEFEED
POLREV
Linefeed
See Table 17
Read only
LF[2:0]
Polarity Reversal Status
POLREV
VOCZERO
Wink Function
1 = Ramp to 0 V
POLREV
(Smooth transition to Voc=0V)
0 = Return to previous V
OC
Smooth Polarity Reversal Enable 0 = Disabled
1 = Enabled
PREN
RAMP
POLREV
POLREV
Smooth Polarity Reversal Ramp
Rate
0 = 1 V/125 µs
1 = 2 V/125 µs
Set VOCZERO bit to 1
Set VOCZERO bit to 0
40 50
0
10
20
30
60
70
Vcm
80
VTIP
Time (ms)
0
-10
-20
-30
-40
-50
2 V/125 µs slope
set by RAMP bit
Voc
VRING
VBAT
Vov
VTIP/RING (V)
Figure 32. Wink Function with Programmable Ramp Rate
60
Rev. 1.2
Si3220/25
Where:
3.18. Two-Wire Impedance Synthesis
ꢀ Z is the termination impedance presented to the
T
Two-wire impedance synthesis is performed on-chip to
optimally match the output impedance of the Dual
ProSLIC to the impedance of the subscriber loop thus
minimizing the receive path signal reflected back onto
the transmit path. The Dual ProSLIC chipset provides
on-chip, digitally-programmable, two-wire impedance
synthesis to meet return loss requirements against
virtually any global two-wire impedance requirement.
Real and complex two-wire impedances are realized by
a programmable digital filter block. (See Z and Z
TIP/RING pair
ꢀ R
is the series resistance caused by protection
devices
PROT
ꢀ R is the series portion of the synthesized
S
impedance
ꢀ R ||C is the parallel portion of the synthesized
P
P
impedance
The user must enter the value of R
into the
A
D
PROT
blocks in Figure 11 on page 24.)
software so the equalizer block can compensate for
additional series impedance. (See Figure 11 on page
24.) Figure 34 illustrates the simplified two-wire
impedance circuit including external protection
RP
resistors, where Z is the actual line impedance for the
L
specific geographical region. The Dual ProSLIC devices
can accomodate up to 50 Ω of series protection
impedance per leg.
RS
CP
The ac impedance generation scheme is comprised of
analog and DSP-based coefficients. To turn off the
analog coefficients (RS, ZP, and ZZ bits in the ZRS and
ZZ registers), the user can simply set the ZSDIS bit of
the ZZ register to 0. To turn off the DSP coefficients
(ZA1H1 through ZB3LO registers), each register must
be loaded with 0x00.
Figure 33. Two-Wire Impedance Synthesis
Configuration
Table 33. Two-Wire Impedance
Synthesis Limitations
Desired
Programmable Limits
Configuration
RPROT
TIP
R only
100–1000 Ω
S
R + C
R x C > 0.5 ms
S P
S
P
ZT
Dual
ProSLIC
ZL
R + R ||C
R /(R + R ) > 0.1
S S P
S
P
P
The two-wire impedance is programmed by loading the
desired real or complex impedance value into the
RING
RPROT
Si322X coefficient generator software in the format R +
S
R ||C , as shown in Figure 33. The software calculates
P
P
Figure 34. Two-Wire Impedance Simplified
Circuit
the appropriate hex coefficients and loads them into the
appropriate control registers (registers 33–52). The two-
wire impedance can be set to any real or complex value
within the boundaries set in Table 33. The actual
impedance presented to the subscriber loop varies with
series impedance from protection devices placed
between the Dual ProSLIC chipset outputs and the TIP/
RING pair according to the following equation:
3.18.1. Impedance Synthesis Initialization
and Control
The Si322x utilizes a digital IIR filter to implement SLIC
impedance synthesis. Under normal operation, the
Si322x state machine controls the clocks to this filter
automatically such that the filter clocks are turned OFF
during those times when the filter is not required. During
pulse dialing, for example, the clocks are shut OFF
during the break period and turned back ON during the
make period.
||
ZT = 2RPROT + (RS + RP CP)
When the clocks are shut OFF, the IIR filter holds the
last sample values in its storage elements. When the
Rev. 1.2
61
Si3220/25
clocks are turned back ON, the IIR filter experiences a
discontinuity in the input signal.
3.19. Transhybrid Balance Filter
The Dual ProSLIC devices provide a transhybrid
balance function via a digitally-programmable balance
filter block. (See “H” block in Figure 11.) The Dual
ProSLIC devices implement an 8-tap FIR filter and a
second-order IIR filter, both running at a 16 kHz sample
rate. These two filters combine to form a digital replica
of the reflected signal (echo) from the transmit path
By writing power-down register 124 (decimal) with
0xC0, the clocks to the digital synthesis filter are forced
to be continuously ON at all times, and the TX audio
path is also kept ON so that the IIR filter continues to
run and receive continuous signal samples from the TX
channel no matter what state the SLIC is in.
Register 124 is a protected register, which must be inputs. The user can filter settings on a per-line basis by
unlocked, then written, then locked again to prevent loading the desired impedance cancellation coefficients
unintended modification of its contents. The sequence into the appropriate registers. The Si322x Coefficient
to write register 124 is as follows:
Generator software interface is provided for calculating
the appropriate coefficients for the FIR and IIR filter
blocks.
1. 0x2, 0x6, 0xC, 0x0 -> Reg.87 (decimal)
\\unlock protected registers
The transhybrid balance filters can be disabled to
implement loopback diagnostic modes. To disable the
transhybrid balance filter (zero cancellation), set the
HYBDIS bit in the DIGCON register to 1.
2. 0xC0 -> Reg.124 (decimal)
\\force HSP (high-speed processing) clocks to ON
3. 0x2, 0x6, 0xC, 0x0 -> Reg.87 (decimal)
\\lock protected registers
Note: The user must enter values into each register location
to ensure correct operation when the hybrid balance
block is enabled.
To ensure proper device operation, the digital
impedance synthesis coefficients (registers 33-52,
decimal) should be programmed while the LINEFEED
state is set to zero (OPEN) and register 124 is set to
0x80. After loading the digital impedance synthesis
coefficients, register 124 should be set to 0xC0. The
following sequence should always be used to program
the digital impedance synthesis coefficients:
3.20. Tone Generators
Dual ProSLIC devices have two digital tone generators
that allow a wide variety of single or dual tone frequency
and amplitude combinations that spare the user the
effort of generating the required POTS signaling tones
on the PCM highway. DTMF, FSK (caller ID), call
progress, and other tones can all be generated on-chip.
The tones are sent to the receive or transmit paths.
(See Figure 11 on page 24.)
Channel A
1. 0x2, 0x6, 0xC, 0x0 → Reg. 87 (decimal) ;unlock
protected registers
2. 0x80 → Reg. 124 (decimal) ;disable clock
Channel B
3.20.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 35. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected for flexibility in creating audio signals.
Control and status register bits are placed in the figure
to indicate their association with the tone generator
architecture. The register set for tone generation is
summarized in Table 34.
3. 0x80 → Reg. 124 (decimal) ;disable clock
Both channels
4. Write registers 331–52 with the digital impedance
synthesis coefficients
Channel A
5. 0xC0 → Reg. 124 (decimal) ;enable clock
Channel B
6. 0xC0 → Reg. 124 (decimal) ;enable clock
7. 0x2, 0x6, 0xC, 0x0 → Reg. 87 (decimal) ;lock
protected registers
During device initialization, steps 1, 5, 6, and 7 should
always be performed even if the digital impedance
synthesis coefficients are not programmed.
62
Rev. 1.2
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8 kHz
Clock
8 kHz
Clock
ZEROENn
Zero Cross
OSCnEN
ENSYNCn
to TX Path
to RX Path
Enable
Zero
Cross
Logic
16-Bit
Modulo
Counter
Two-Pole
Resonant
Oscillator
OSCnTA
Expire
Signal
Routing
Register
Load
OSCnTI
Expire
Load
Logic
OSCnTA
OSCnFREQ
REL*
INT
Logic
OSCnTAEN
OSnTIS
ROUTn
OSCnTI
OSCnAMP
OSnTIE
OSnTAS
INT
Logic
OSCnTIEN
OSCnPHAS
OSnTAE
*Tone Generator 1 Only
n = "1" or "2" for Tone Generator 1 and 2, respectively
Figure 35. Tone Generator Diagram
3.20.2. Oscillator Frequency and Amplitude
Each of the two tone generators contains a two-pole
resonant oscillator circuit with programmable
frequency and amplitude, which are programmed via
RAM addresses OSC1FREQ, OSC1AMP, OSC1PHAS,
OSC2FREQ, OSC2AMP, and OSC2PHAS. The sample
rate for the two oscillators is 8000 Hz. The equations
are as follows:
1
4
--------------------- × (215 – 1) × 0.5= 1424
0.21556
1.78434
--
OSC1AMP =
= 0x590
a
14
OSC2FREQ = 0.49819 (2 ) = 8162 = 0x1FE2
1
OSC2AMP =
--------------------- × (215 – 1) × 0.5= 2370
0.50181
--
4
1.49819
coeff = cos(2π f /8000 Hz),
n
n
= 0x942
where f is the frequency to be generated;
n
14
OSCnFREQ = coeff x (2 );
OSC2PHAS = 0
n
The preceding computed values are written to the
corresponding registers to initialize the oscillators. Once
the oscillators are initialized, the oscillator control
registers can be accessed to enable the oscillators and
direct their outputs.
1
4
15
Desired Vrms
1.11 Vrms
1 – coeff
1 + coeff
--
---------------------------------------
----------------------- × (2 – 1) ×
OSCnAMP =
where Desired Vrms is the amplitude to be generated;
OSCnPHAS = 0,
FSK frequency coefficients, FSKFREQ0/1 and
FSKAMP0/1, are calculated from the oscillator
equations and changing the sample rate from 8000 Hz
to 24000 Hz.
n = 1 or 2 for oscillator 1 or oscillator 2, respectively.
For example, to generate a DTMF digit of 8, the two
required tones are 852 Hz and 1336 Hz. Assuming we
want to generate half-scale values (ignoring twist), the
following values are calculated:
3.20.3. Tone Generator Cadence Programming
Each of the two tone generators contains two timers,
one for setting the active period and one for setting the
inactive period. The oscillator signal is generated during
the active period and suspended during the inactive
period. Both the active and inactive periods can be
programmed from 0 to 8 seconds in 125 µs steps. The
active period time interval is set using OSC1TA for tone
generator 1 and OSC2TA for tone generator 2.
2π852
8000
⎛
⎝
⎞
⎠
----------------
coeff1 = cos
= 0.78434
OSC1FREQ = 0.78434(214) = 12851= 0x3233
OSC1PHAS = 0
coeff = cos (2π 1336 / 8000) = 0.49819
2
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To enable automatic cadence for tone generator 1, Figure 36 is an example of an output cadence that uses
define the OSC1TA and OSC1TI registers and set the the zero crossing feature.
OSC1TAEN and OSC1TIEN bits. This enables each of
One-shot oscillation is possible with OSC1EN and
the timers to control the state of the oscillator enable bit,
OSC1TAEN. Direct control over the cadence is
OSC1EN. The 16-bit counter counts until the active
achieved by setting the OSC1EN bit directly if
timer expires, at which time the 16-bit counter resets to
OSC1TAEN and OSC1TIEN are disabled.
zero and begins counting until the inactive timer
The operation of tone generator 2 is identical to that of
expires. The cadence continues until the user clears the
tone generator 1 using its respective control registers.
OSC1TA and OSC1TIEN control bits. Setting the
Note: Tone Generator 2 should not be enabled simulta-
ZEROEN1 bit implements the zero crossing detect
feature. This ensures that each oscillator pulse ends
without a dc component. The timing diagram in
neously with the ringing oscillator because of resource
sharing within the hardware.
Table 34. Register and RAM Locations Used for Tone Generation
Tone Generator 1
Parameter
Register/RAM
Mnemonics
Register/RAM Bits
Description/Range
(LSB Size)
Oscillator 1 Frequency
Coefficient
OSC1FREQ
OSC1AMP
OSC1PHAS
OSC1FREQ[15:3]
OSC1AMP[15:0]
OSC1PHAS[15:0]
Sets oscillator frequency
Oscillator 1 Amplitude Coeffi-
cient
Sets oscillator amplitude
Oscillator 1 Initial Phase
Coefficient
Sets initial phase
(default = 0)
Oscillator 1 Active Timer
Oscillator 1 Inactive Timer
Oscillator 1 Control
O1TALO/O1TAHI
O1TILO/O1TIHI
OMODE, OCON
OSC1TA[15:0]
OSC1TI[15:0]
0 to 8.19 s (125 µs)
0 to 8.19 s (125 µs)
FSKSSEN, OSC1FSK,
ZEROEN1, ROUT1,
Enables all Oscillator 1
parameters
ENSYNC1, OSC1TAEN,
OSC1TIEN, OSC1EN
Oscillator 1 Interrupts
IRQVEC1, IRQEN1 OS1TAS, OS1TIS, OS1TAE,
OS1TIE
Interrupt enable/status
Tone Generator 2
Parameter
Location
Register/RAM Address
Description/Range
Oscillator 2 Frequency
Coefficient
OSC2FREQ
OSC2FREQ[15:3]
Sets oscillator frequency
Oscillator 2 Amplitude Coeffi-
cient
OSC2AMP
OSC2AMP[15:0]
OSC2PHAS[15:0]
Sets oscillator amplitude
Oscillator 2 Initial Phase
Coefficient
OSC2PHAS
Sets initial phase
(default = 0)
Oscillator 2 Active Timer
Oscillator 2 Inactive Timer
Oscillator 2 Control
O2TALO/O2TAHI
O2TILO/O2TIHI
OMODE, OCON
OSC2TA[15:0]
OSC2TI[15:0]
0 to 8.19 s (125 µs)
0 to 8.19 s (125 µs)
ZEROEN2, ROUT2,
ENSYNC2, OSC2TAEN,
OSC2TIEN, OSC2EN
Enables all Oscillator 2
parameters
Oscillator 2 Interrupts
IRQVEC1, IRQEN1
OS2TAS, OS2TIS,
OS2TAE, OS2TIE
Interrupt enable/status
64
Rev. 1.2
Si3220/25
OSC1EN
0,1 ...
..., OSC1TA 0,1 ...
..., OSC1TI 0,1 ... ..., OSC1TA 0,1 ...
...
...
ENSYNC1
Tone
Gen. 1
Signal
Output
Figure 36. Tone Generator Timing Diagram
First
Ring Burst
Channel
Seizure
Data
Packet
Second
Ring Burst
Mark
Message Message
Parameter 1
Parameter 2
Parameter n Checksum
Type
Length
Message Header
Message Body
Parameter
Type
Data
Length
Data
Content
Figure 37. On-Hook Caller ID Transmission Sequence
Rev. 1.2
65
Si3220/25
3.20.4. Tone Generator Interrupts
requirements.
Both the active and inactive timers can generate an The register and RAM locations for caller ID generation
interrupt to signal “on/off” transitions to the software. are listed in Table 36. Caller ID data is entered into the
The timer interrupts for tone generator 1 can be 8-bit FSKDAT register. The data byte is double buffered
individually enabled by setting the OS1TAE and OS1TIE so that the Dual ProSLIC can generate an interrupt
bits. Timer interrupts for tone generator 2 are OS2TAE indicating the next data byte can be written when
and OS2TIE. A pending interrupt for each of the timers processing begins on the current data byte. The caller
is determined by reading the OS1TAS, OS1TIS, ID data can be transmitted in one of two modes
OS2TAS, and OS2TIS bits in the IRQVEC1 register.
controlled by the O1FSK8 register bit. When
O1FSK8 = 0 (default case), the 8-bit caller ID data is
transmitted with a start bit and stop bit to create a 10-bit
3.21. Caller ID Generation
The Dual ProSLIC devices generate caller ID signals in data sequence. If O1FSK8 = 1, the caller ID data is
compliance with various Bellcore and ITU specifications transmitted as a raw 8-bit sequence with no start or stop
as described in Table 35 by providing continuous phase bits. The value programmed into the OSC1TA register
binary frequency shift keying (FSK) modulation. determines the bit rate, and the interrupt rate is equal to
Oscillator 1 is required because it preserves phase the bit rate divided by the data sequence length (8 or 10
continuity during frequency shifts whereas Oscillator 2 bits).
does not. Figure 37 illustrates a typical caller ID
transmission sequence in accordance with Bellcore
Table 35. FSK Modulation Requirements
Parameter
ITU-T V.23 Bellcore GR-30-CORE
Mark Frequency (logic 1)
1300 Hz
1200 Hz
2200 Hz
Space Frequency (logic 0) 2100 Hz
Transmission Rate
1200 baud
Table 36. Register and RAM Locations used for Caller ID Generation
Parameter
Register/RAM Register/RAM Bits
Mnemonic
Description/Range (LSB Size)
FSK Start & Stop Bit Enable
Oscillator 1 Active Timer
FSK Data Byte
OMODE
O1TALO/O1TAHI
FSKDAT
O1FSK8
Enable/disable
0 to 2.73 s (41.66 µs)*
Caller ID data
OSC1TA[15:0]
FSKDAT[7:0]
FSK Frequency for Space
FSK Frequency for Mark
FSK Amplitude for Space
FSK Amplitude for Mark
FSK 0-1 Transition Freq, High
FSK 0-1 Transition Freq, Low
FSK 1-0 Transition Freq, High
FSK 1-0 Transition Freq, Low
FSKFREQ0
FSKFREQ1
FSKAMP0
FSKAMP1
FSK01HI
FSKFREQ0[15:3]
FSKFREQ1[15:3]
FSKAMP0[15:3]
FSKAMP1[15:3]
FSK01HI[15:3]
FSK01LO[15:3]
FSK10HI[15:3]
FSK10LO[15:3]
Audio range
Audio range
FSK01LO
FSK10HI
FSK10LO
*Note: Oscillator 1 active timer range and LSB stage valid only for FSK mode.
66
Rev. 1.2
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The pulse metering oscillator has a volume envelope
(linear ramp) on the on/off transitions of the oscillator.
The ramp is controlled by the value in the PMRAMP
RAM address, and the sinusoidal generator output is
multiplied by this volume before it is sent to the pulse
metering DAC. The volume value is incremented by the
value in PMRAMP at an 8 kHz rate. The volume will
ramp from 0 to 7FFF in increments of PMRAMP to allow
the value of PMRAMP to set the slope of the ramp. The
clip detector stops the ramp once the signal seen at the
transmit path exceeds the amplitude threshold set by
PMAMPTH, which provides an automatic gain control
(AGC) function to prevent the audio signal from clipping.
When the pulse metering signal is turned off, the
volume ramps down to 0 by decrementing according to
the value of PMRAMP. Figure 38 illustrates the
functional blocks involved in pulse metering generation,
and Table 37 presents the required register and RAM
locations that must be set to generate pulse metering
signals.
3.22. Pulse Metering Generation
The Si3220 offers an additional tone generator to
generate tones above the audio frequency band. This
oscillator generates billing tones that are typically
12 kHz or 16 kHz. The generator follows the same
algorithm as described in "3.20.1. Tone Generator
Architecture" on page 62 with the exception that the
sample rate for computation is 64 kHz instead of 8 kHz.
The equation is as follows:
2πf
64000 Hz
⎛
⎝
⎞
⎠
-------------------------
Coeff = cos
PMFREQ = coeff × (214 – 1)
Desired VPK
----------------------------------------
FullScale VPK
1
4
15
1 – coeff
1 + coeff
--
PMAMPL =
----------------------- × (2 – 1) ×
where Full Scale V = 0.5 V.
PK
Table 37. Register and RAM Locations Used for Pulse Metering Generation
Register/RAM
Mnemonic
Register/RAM
Bits
Description/Range
(LSB Size)
Parameter
PMFREQ
PMAMPL
PMRAMP
PMFREQ[15:3]
PMAMPL[15:0]
PMRAMP[15:0]
Sets oscillator frequency
Pulse Metering Frequency
Coefficient
Sets oscillator amplitude
Pulse Metering Amplitude
Coefficient
0 to PMAMPL
(full amplitude)
Pulse Metering Attack/Decay
Ramp Rate
PMTALO/PMTAHI
PMTILO/PMTIHI
PULSETA[15:0]
PULSETI[15:0]
0 to 8.19 s (125 µs)
0 to 8.19 s (125 µs)
Pulse Metering Active Timer
Pulse Metering Inactive Timer
IRQVEC1, IRQEN1
PULSTAE,
PULSTIE,
PULSTAS,
PULSTIS
Interrupt Status and control
registers
Pulse Metering, Control
Interrupt
PMAMPTH
PMAMPTH[15:0]
0 to 500 mV
Pulse Metering AGC
Amplitude Threshold
PMCON
PMCON
PMCON
PMCON
ENSYNC
TAEN
Indicates signal present
Enable/disable
PM Waveform Present
PM Active Timer Enable
PM Inactive Timer Enable
Pulse Metering Enable
TIEN
Enable/disable
PULSE1
Enable/disable
Rev. 1.2
67
Si3220/25
Decimation
Filter
ADC
12/16 kHz
Bandpass
Peak Detector
PMAMPTH
–
+
+
IBUF
ZA
DAC
+
PMRAMP
Pulse
Metering
DAC
+
+
±
x
Pulse
Metering
Oscillator
Volume
8 kHz
Clip
Logic
7FFF
or 0
Figure 38. Pulse Metering Generation Block Diagram
The detection process occurs twice within the 45 ms
minimum tone time. A digit must be detected on two
consecutive tests after a pause to be recognized as a
new digit. If all tests pass, an interrupt is generated, and
the DTMF digit value is loaded into the DTMF register
according to Table 38. If tones occur at the maximum
rate of 100 ms per digit, the interrupt must be serviced
within 85 ms so that the current digit is not overwritten
by a new one. There is no buffering of the digit
information.
3.23. DTMF Detection
On-chip DTMF detection, also known as touch tone, is
available in the Si3220 and Si3225.
It is an in-band signaling system that replaces the pulse-
dial signaling standard. In DTMF, two tones generate a
DTMF digit. One tone is chosen from the four possible
row tones, and one tone is chosen from the four
possible column tones. The sum of these tones
constitutes one of 16 possible DTMF digits. The row
and column tones and corresponding digits are shown
in Table 38.
Table 38. DTMF Row/Column Tones
DTMF detection is performed using a modified Goertzel
algorithm to compute the DFT for each of the eight 697 Hz
DTMF frequencies and their second harmonics. At the
end of the DFT computation, the squared magnitudes of
1
2
5
8
0
3
6
9
#
A
B
C
D
770 Hz
4
the DFT results for the 8 DTMF fundamental tones are
computed. The row results are sorted to determine the
852 Hz
7
strongest row frequency, and the column frequencies
941 Hz
*
are sorted as well. Upon completion of this process,
checks are made to determine if the strongest row and
column tones constitute a DTMF digit.
1209 Hz
1336 Hz 1477 Hz 1633 Hz
68
Rev. 1.2
Si3220/25
Table 39 outlines the hex codes corresponding to the The threshold for declaring the presence or absence of
detected DTMF digits.
2100 Hz energy should be based on Table 40. A
suitable threshold for most applications is >0x20,
corresponding to a level of –15 dBm.
Table 39. DTMF Hex Codes
Table 40. 2100 Hz Level vs. RAM Hex Value
Digit
1
Hex code
0x1
TIP and RING
Level
TX Path: RAM 410 (154)
or
RX Path: RAM 413 (157)
(Hex)
2
0x2
Across 600 W
(dBm)
3
0x3
4
0x4
+3
0
0x838
0x420
0x20a
0x107
0x83
5
0x5
6
0x6
–3
7
0x7
–6
8
0x8
–9
9
0x9
–12
–15
0x41
0
0xA
0xB
0xC
0xD
0xE
0xF
0x0
*
0x20
#
The following steps are used to access RAM address
410 and 413:
A
B
C
D
1. Write 0x02, 0x06, 0x0C, 0x00 to Reg. 87 (un-protect
test registers/bits)
2. Write 0x40 to Reg. 4 (access upper RAM space)
3. Write 0x02, 0x06, 0x0C, 0x00 to Reg. 87 (protect
test registers/bits)
3.24. Modem Tone Detection
4. For TX path use RAMAddress = 154 for the RX path
use RAMAddress = 157:
if (readRAM(RAMAddress) > 0x20)
Tone2100 Hz = 1;
The Dual ProSLIC devices are capable of detecting a
2100 Hz modem tone as described in ITU-T
Recommendation V.8. The detection scheme can be
implemented in both transmit and receive paths and is
enabled by programming the appropriate register bit.
The detection scheme should be disabled for power
conservation after the modem tone window has passed.
Once a valid modem tone is detected, a register bit is
set accordingly, and the user can check the results by
reading the register value. A programmable debounce
interval is provided to eliminate false detection and can
be programmed in increments of 67 ms by writing to the
appropriate register.
else Tone2100 Hz = 0;
endif
3.25. Audio Path Processing
Unlike traditional SLICs, the Dual ProSLIC devices
integrate the codec function into the same IC. The on-
chip 16-bit codec offers programmable gain/attenuation
blocks and multiple loopback modes for self testing. The
signal path block diagram is shown in Figure 11 on page
24.
The outputs of the 2100 Hz modem tone detectors are
located at RAM addresses 410 and 413 for the TX and
RX paths, respectively.
3.25.1. Transmit Path
In the transmit path, the analog signal fed by the
external ac coupling capacitors is passed through an
anti-aliasing filter before being processed by the A/D
converter. An analog mute function is provided directly
prior to the A/D converter input. The output of the A/D
converter is an 8 kHz, 16-bit wide, linear PCM data
stream. The standard requirements for transmit path
The contents of registers 410 and 413 indicate the
presence or absence of 2100 Hz energy. Table 40
indicates the relationship between the contents of these
RAM addresses and the level of the 2100 Hz energy
present in the corresponding signal path (TX or RX).
Rev. 1.2
69
Si3220/25
attenuation for signals above 3.4 kHz are part of the 3.25.4. TXEQ/RXEQ Equalizer Blocks
combined decimation filter characteristic of the A/D
The TXEQ and RXEQ blocks (see Figure 11 on page
converter. One more digital filter, THPF, is available in
the transmit path. THPF implements the high-pass
attenuation requirements for signals below 65 Hz. An
equalizer block then equalizes the transmit signal path
24) represent 4-tap filters that can be used to equalize
the transmit and receive paths, respectively. The
transmit path equalizer is controlled by the TXEQCO0-
TXEQCO3 RAM locations, and the receive path
equalizer is controlled by the RXEQCO0-RXEQCO3
RAM locations. The Si322x Coefficient Generator
software uses these filters in calculating the ac
impedance coefficients for optimal ac performance.
Refer to “AN63: Si322x Coefficient Generator User’s
Guide” for detailed information regarding the calculation
of ac impedance coefficients.
to compensate for series protection resistance, R
,
PROT
outside of the ac-sensing inputs. The linear PCM data
stream output from the equalizer block is amplified by
the transmit-path programmable gain amplifier, TPGA,
which can be programmed from –∞ to 6 dB. The DTMF
decoder receives the linear PCM data stream and
performs the digit extraction if enabled by the user. The
final step in the transmit path signal processing is the
A-law or µ-law compression, which can reduce the data
stream word width to 8 bits. Depending on the PCM
mode select register selection, every 8-bit compressed
serial data word occupies one time slot on the PCM
highway, or every 16-bit uncompressed serial data
word occupies two time slots on the PCM highway.
TPGA or RPGA
PCM
In
PCM
Out
X
3.25.2. Receive Path
M
In the receive path, the optionally-compressed 8-bit
data is first expanded to 16-bit words. The PCMF
register bit can bypass the expansion process so that
two 8-bit words are assembled into one 16-bit word.
RPGA is the receive path programmable gain amplifier,
which can be programmed from –∞ dB to 6 dB. An
8 kHz, 16-bit signal is then provided to a D/A converter.
An analog mute function is provided directly after the
D/A converter. When not muted, the resulting analog
signal is applied at the input of the transconductance
amplifier, Gm, which drives the off-chip current buffer,
where M = {0, 1/16384, 2/16384,...32767/16384}
Figure 39. TPGA and RPGA structure
3.25.5. Audio Characteristics
The dominant source of distortion and noise in both the
transmit and receive paths is the quantization noise
introduced by the µ-law or the A-law compression
process. Figure 5 on page 20 specifies the minimum
Signal-to-Noise and Distortion Ratio for either path for a
sine wave input of 200 Hz to 3400 Hz.
I
.
BUF
Both the µ-law and the A-law speech encoding allow the
audio codec to transfer and process audio signals larger
than 0 dBm0 without clipping. The maximum PCM code
is generated for a µ-law encoded sine wave of
3.17 dBm0 or an A-law encoded sine wave of
3.14 dBm0. The device overload clipping limits are
driven by the PCM encoding process. Figure 6 on page
21 shows the acceptable limits for the analog-to-analog
fundamental power transfer-function, which bounds the
behavior of the device.
3.25.3. TPGA/RPGA Gain/Attenuation Blocks
The TPGA and RPGA blocks are essentially linear
multipliers with the structure illustrated in Figure 39.
Both blocks can be independently programmed from –∞
to +6 dB (0 to 2 linear scale). The TXGAIN and RXGAIN
RAM locations are used to program each block. A
setting of 0000h mutes all audio signals; a setting of
4000h passes the audio signal with no gain or
attenuation (0 dB), and a setting of 7FFFh provides the
maximum 6 dB of gain to the incoming audio signal. The
device signal scaling assumes that dBm is always
referenced to 600 Ω. To compensate for this, the correct
RXGAIN and TXGAIN settings are given in the
coefficient generator software. The DTXMUTE and
DRXMUTE bits in the DIGCON register are also
available to allow muting of the transmit and receive
paths without requiring modifications to the TXGAIN or
RXGAIN settings.
The transmit path gain distortion versus frequency is
shown in Figure 7 on page 21. The same figure also
presents the minimum required attenuation for out-of-
band analog signals applied on the line. The presence
of a high-pass filter transfer function ensures at least
30 dB of attenuation for signals below 65 Hz. The low-
pass filter transfer function attenuates signals above
3.4 kHz. It is implemented as part of the A-to-D
converter.
70
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The receive path transfer function requirement, shown
in Figure 8 on page 22, is very similar to the transmit
path transfer function. The PCM data rate is 8 kHz; so,
no frequencies greater than 4 kHz are digitally-encoded
in the data stream. At frequencies greater than 4 kHz,
the plot in Figure 8 is interpreted as the maximum
allowable magnitude of spurious signals that are
generated when a PCM data stream representing a sine
wave signal in the range of 300 Hz to 3.4 kHz at a level
of 0 dBm0 is applied at the digital input.
3.26. System Clock Generation
The Dual ProSLIC devices generate the internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 786 kHz,
1.024 MHz, 1.536 MHz, 1.544 MHz, 2.048 MHz,
4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to
the FSYNC rate is determined by a counter clocked by
PCLK. The three-bit ratio information is transferred into
an internal register, PLL_MULT, after a device reset.
The PLL_MULT controls the internal PLL, which
multiplies PCLK to generate the rate required to run the
internal filters and other circuitry.
The group delay distortion in either path is limited to no
more than the levels indicated in Figure 9 on page 23.
The reference in Figure 9 is the smallest group delay for
a sine wave in the range of 500 Hz to 2500 Hz at
0 dBm0.
The PLL clock synthesizer settles quickly after power-
up or update of the PLL-MULT register. The PLL lock
process begins immediately after the RESET pin is
pulled high and takes approximately 5 ms to achieve
lock after RESET is released with stable PCLK and
FSYNC. However, the settling time depends on the
PCLK frequency and can be predicted based on the
following equation:
The block diagram for the voice-band signal processing
paths is shown in Figure 11 on page 24. Both the
receive and the transmit paths employ the optimal
combination of analog and digital signal processing for
maximum performance while maintaining sufficient
flexibility for users to optimize their particular application
of the device. The two-wire (TIP/RING) voice-band
interface to the device is implemented with a small
number of external components. The receive path
64
fPCLK
--------------
=
Tsettle
interface consists of a unity-gain current buffer, I
,
BUF
Note: Therefore, the RESET pin must be held low during
powerup and should only be released when both
PCLK and FSYNC signals are known to be stable.
while the transmit path interface is an ac coupling
capacitor. Signal paths, although implemented
differentially, are shown as single-ended for simplicity.
VCO
PFD
PCLK
28.672 MHz
÷2
÷2
DIV M
RESET
PLL_MULT
Figure 40. PLL Frequency Synthesizer
Rev. 1.2
71
Si3220/25
3.27. Interrupt Logic
3.28. SPI Control Interface
The control interface to the Dual ProSLIC devices is a
4-wire SPI bus modeled after microcontroller and serial
peripheral devices. The interface consists of a clock,
SCLK, chip select, CS, serial data input, SDI, and serial
data output, SDO. In addition, the Dual ProSLIC devices
include a serial data through output (SDI_THRU) to
support daisy-chain operation of up to eight devices (up
to sixteen channels). Figure 41 illustrates the daisy-
chain connections. Note that the SDITHRU pin of the
last device in the chain must not be connected to
ground (SDITHRU = 0 indicated GCI mode). The device
operates with both 8-bit and 16-bit SPI controllers.
Each SPI operation consists of a control byte, an
address byte (of which only the seven LSBs are used
internally), and either one or two data bytes depending
on the width of the controller and whether the access is
to an 8-bit register or 16-bit RAM address. Bytes are
always transmitted MSB first. The variations of usage
on this four-wire interface are as follows:
The Dual ProSLIC devices are capable of generating
interrupts for the following events:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Loop current/ring ground detected
Ring trip detected
Ground Key detected
Power alarm
DTMF digit detected
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
Pulse metering active timer expired
Pulse metering inactive timer expired
RAM address access complete
Receive path modem tone detected
Transmit path modem tone detected
ꢀ Continuous clocking. During continuous clocking,
the data transfers are controlled by the assertion of
the CS pin. CS must be asserted before the falling
edge of SCLK on which the first bit of data is
expected during a read cycle and must remain low
for the duration of the 8-bit transfer (command/
address or data), going high after the last rising of
SCLK after the transfer.
The interface to the interrupt logic consists of six
registers. Four interrupt status registers (IRQ0–IRQ3)
contain 1 bit for each of the above interrupt functions.
These bits are set when an interrupt is pending for the
associated resource. Three interrupt mask registers
(IRQEN1–IRQEN3) also contain 1 bit for each interrupt
function. For interrupt mask registers, the bits are active
high. Refer to the appropriate functional description text
for operational details of the interrupt functions.
When a resource reaches an interrupt condition, it
signals an interrupt to the interrupt control block. The
interrupt control block sets the associated bit in the
interrupt status register if the mask bit for that interrupt
is set. The INT pin is a NOR of the bits of the interrupt
status registers. Therefore, if a bit in the interrupt status
registers is asserted, IRQ asserts low. Upon receiving
the interrupt, the interrupt handler should read interrupt
status registers to determine which resource requests
service. All interrupt bits in the interrupt status registers
IRQ0–IRQ3 are cleared following a register read
operation. If the interrupt status registers are non-zero,
the INT pin remains asserted.
ꢀ Clock during transfer only. In this mode, the clock
is cycling only during the actual byte transfers. Each
byte transfer consists of eight clock cycles in a return
to “1” format.
ꢀ SDI/SDO wired operation. Independent of the
clocking options described, SDI and SDO can be
treated as two separate lines or wired together if the
master is capable of tri-stating its output during the
data byte transfer of a read operation.
ꢀ Soft reset. The SPI state machine resets whenever
CS asserts during an operation on an SCLK cycle
that is not a multiple of eight. This is a mechanism
for the controller to force the state machine to a
known state when the controller and the device are
out of synchronization.
As shown in the application schematics in Figure 12 on
page 25 and Figure 13 on page 26, a pulldown resistor
is required on the SDO pin to ensure proper operation.
A pullup resistor is not allowed on the SDO pin.
72
Rev. 1.2
Si3220/25
The control byte has the following structure and is presented on the SDI pin MSB first:
7
6
5
4
3
2
1
0
BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3]
See Table 41 for bit definitions.
Table 41. SPI Control Interface
7
6
BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is
only valid for write operations since it would cause contention on the SDO pin during a
read.
R/W
Read/Write Bit.
0 = Write operation.
1 = Read operation.
5
REG/RAM Register/RAM Access Bit.
0 = RAM access.
1 = Register access.
4
Reserved
3:0
CID[3:0] Indicates the channel that is targeted by the operation. Note that the 4-bit channel value is
provided LSB first. The devices reside on the daisy chain such that device 0 is nearest to
the controller, and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 41.)
As the CID information propagates down the daisy chain, each channel decrements the
CID by 1. The SDI nodes between devices reflect a decrement of 2 per device since each
device contains two channels. The device receiving a value of 0 in the CID field responds
to the SPI transaction. (See Figure 42.) If a broadcast to all devices connected to the chain
is requested, the CID does not decrement. In this case, the same 8-bit or 16-bit data is pre-
sented to all channels regardless of the CID values.
Rev. 1.2
73
Si3220/25
SDI0
SDI
SDO
CS
Channel 0
CS
CPU
SDI1
Dual ProSLIC #1
SDO
SDI
Channel 1
SPI Clock
SCLK
SDITHRU
SDI2
SDI
Channel 2
CS
SDI3
Dual ProSLIC #2
SDO
Channel 3
SCLK
SDITHRU
SDI4
SDI14
SDI
Channel 14
CS
SDI15
Dual ProSLIC #8
SDO
Channel 15
SCLK
SDITHRU
Figure 41. SPI Daisy-Chain Mode
74
Rev. 1.2
Si3220/25
In Figure 42, the CID field is zero. As this field is pass through the chain without permutation.
decremented (in LSB to MSB order), the value
decrements for each SDI down the line. The BRDCST,
R/W, and REG/RAM bits remain unchanged as the
control word passes through the entire chain. The odd
SDIs are internal to the device and represent the SDI to
SDI_THRU connection between channels of the same
device. A unique CID is presented to each channel, and
the channel receiving a CID value of zero is the target of
the operation (channel 0 in this case). The last line of
Figure 42 illustrates that in Broadcast mode, all bits
Figures 43 and 44 illustrate WRITE and READ
operations to register addresses via an 8-bit SPI
controller. These operations are performed as a 3-byte
transfer. CS is asserted between each byte, which is
required for CS to be asserted before the first falling
edge of SCLK after the DATA byte to indicate to the
state machine that one byte only should be transferred.
The state of SDI is a “don’t care” during the DATA byte
of a read operation.
SPI Control Word
BRDCST
REG/RAM Reserved
CID[0]
CID[1]
CID[2]
CID[3]
R/W
A
0
0
0
0
B
B
B
B
C
C
C
C
0
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
SDI0
A
SDI1 (Internal)
SDI2
A
A
SDI3 (Internal)
0
0
A
A
B
B
C
C
0
1
1
0
0
0
0
0
SDI 14
SDI15 (Internal)
1
A
B
C
D
E
F
G
SDI0-15
Figure 42. Sample SPI Control Word to Address Channel 0
CS
SCLK
SDI
CONTROL
ADDRESS
DATA [7:0]
Hi-Z
SDO
Figure 43. Register Write Operation via an 8-Bit SPI Port
CS
SCLK
SDI
CONTROL
ADDRESS
X X X X X X X X
Data [7:0]
SDO
Figure 44. Register Read Operation via an 8-Bit SPI Port
Rev. 1.2
75
Si3220/25
Figures 45 and 46 illustrate WRITE and READ move into the data register in the SPI for shifting out
operations to register addresses via a 16-bit SPI during the DATA portion of the SPI transfer. This is the
controller. These operations require a 4-byte transfer data loaded into the data buffer in response to the
arranged as two 16-bit words. The absence of CS going previous RAM address read request. Therefore, there is
high after the eighth bit of data indicates to the SPI state a one-deep pipeline nature to RAM address READ
machine that eight more SCLK pulses follow to operations. At the completion of the DATA portion of the
complete the operation. For a WRITE operation, the last READ cycle, the ADDRESS is transferred to the
eight bits are ignored. For a read operation, the 8-bit channel-based address buffer register, and a RAM
data value repeats so that the data is captured during address is logged for that channel. The RAMSTAT bit in
the last half of a data transfer if required by the each channel is polled to monitor the status of RAM
controller.
address accesses that are serviced twice per sample
period at dedicated windows in the DSP algorithm.
During register accesses, the CONTROL, ADDRESS,
and DATA are captured in the SPI module. At the A RAM access interrupt in each channel indicates that
completion of the ADDRESS byte of a READ access, the pending RAM access request is serviced. For a
the contents of the addressed register move into the RAM access, the ADDRESS and DATA is transferred
data register of the SPI data register. At the completion from the SPI registers to the address and data buffers in
of the DATA byte of a WRITE access, the data is the appropriate channel. The RAM WRITE request is
transferred from the SPI to the addressed register.
logged. As for READ operations, the status of the
pending request is monitored by either polling the
RAMSTAT bit for the channel or enabling the RAM
access interrupt for the channel. By keeping the
address, data buffers, and RAMSTAT register on a per-
channel basis, RAM address accesses can be
scheduled for both channels without interface.
Figures 47–50 illustrate the various cycles for accessing
RAM addresses. RAM addresses are 16-bit entities;
therefore, the accesses always require four bytes.
During RAM address accesses, the CONTROL,
ADDRESS, and DATA are captured in the SPI module.
At the completion of the ADDRESS byte of a READ
access, the contents of the channel-based data buffer
CS
SCLK
X X X X X X X X
SDI
CONTROL
ADDRESS
Data [7:0]
Hi - Z
SDO
Figure 45. Register Write Operation via a 16-Bit SPI Port
CS
SCLK
SDI
X X X X X X X X
Data [7:0]
X X X X X X X X
Data [7:0]
CONTROL
ADDRESS
SDO
Same byte repeated twice.
Figure 46. Register Read Operation via a 16-Bit SPI Port
76
Rev. 1.2
Si3220/25
CS
SCLK
SDI
CONTROL
ADDRESS
DATA [15:8]
DATA [7:0]
SDO
Hi-Z
Figure 47. RAM Write Operation via an 8-Bit SPI Port
CS
SCLK
SDI
CONTROL
ADDRESS
x x x x x x x x
x x x x x x x x
DATA [15:8]
DATA [7:0]
SDO
Figure 48. RAM Read Operation via an 8-Bit SPI Port
CS
SCLK
SDI
CONTROL
ADDRESS
Data [15:8]
Data [7:0]
Hi - Z
SDO
Figure 49. RAM Write Operation via a 16-Bit SPI Port
CS
SCLK
SDI
CONTROL
ADDRESS
Data [15:8]
Data [7:0]
SDO
Figure 50. RAM Read Operation via a 16-Bit SPI Port
Rev. 1.2
77
Si3220/25
3.29. PCM Interface
The Dual ProSLIC devices contain
a
flexible slots. DTX data is high-impedance except for the
programmable interface for the transmission and duration of the 8-bit PCM transmit. DTX returns to high-
reception of digital PCM samples. PCM data transfer is impedance on the negative edge of PCLK during the
controlled by the PCLK and FSYNC inputs, PCM Mode LSB or on the positive edge of PCLK following the LSB.
Select, PCM Transmit Start Count (PCMTXHI/ This is based on the setting of the PCMTRI bit of the
PCMTXLO), and PCM Receive Start Count (PCMRXHI/ PCM Mode Select register. Tristating on the negative
PCMRXLO) registers. The interface can be configured edge allows the transmission of data by multiple
to support from 4 to 128 8-bit timeslots in each frame. sources in adjacent timeslots without the risk of driver
This corresponds to PCLK frequencies of 256 kHz to contention. In addition to 8-bit data modes, a 16-bit
8.192 MHz in power-of-2 increments. (768 kHz, mode is provided for testing. This mode can be
1.536 MHz, and 1.544 MHz are also available for T1 activated via the PCMF bits of the PCM Mode Select
and E1 support.) Timeslots for data transmission and register.
Setting
the
PCMTXHI/PCMTXLO
or
reception are independently configured with the PCMRXHI/PCMRXLO register greater than the number
PCMTXHI, PCMTXLO, PCMRXHI, and PCMRXLO.
of PCLK cycles in a sample period stops data
transmission because neither PCMTXHI/PCMTXLO nor
PCMRXHI/PCMRXLO equal the PCLK count. Figures
51–54 illustrate the usage of the PCM highway interface
to adapt to common PCM standards.
Special consideration must be given to the PCM
Receive Start Count (PCMRXHI / PCMRXLO) registers.
Changing the PCMRXHI (Reg. 57), PCMRXLO (Reg.
56) on-the-fly while the Si3220/25 is actively passing
audio can cause the digital impedance synthesis block As shown in the application schematics in Figures 12
to perform improperly producing an audible loud white and 13, a pulldown resistor is required on the DTX pin.
noise signal across TIP and RING.
A pullup resistor is not allowed on the DTX pin.
Additionally, the PCLK frequency should be chosen
such that there is at least one empty timeslot (hi-Z
timeslot) per 8 kHz frame. If a PCLK is chosen such that
DTX has valid data during the entire frame, choose the
next higher valid PCLK frequency to ensure one or
more empty timeslots in each frame. If an application
requires heavy capacitive loading on the DTX pin, or
more than eight Si322x devices connected to the same
PCM bus, consult your local Silicon Laboratories sales
representative to determine what value of pulldown
resistor should be used.
To ensure proper device operation, the RX timeslot
registers (PCMRXHI and PCMRXLO, registers 56–57)
should be set during the initialization procedure
immediately after power-up and prior to both enabling
the PCM bus and setting the linefeed to the active state.
The TX timeslot registers (PCMTXHI and PCMTXLO,
registers 54–55) may be changed at any time to
establish audio connections on the PCM bus.
Setting the correct starting point of the data configures
the part to support long FSYNC and short FSYNC
variants, IDL2 8-bit, 10-bit, and B1 and B2 channel time
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PCLK_CNT
DRX
MSB
MSB
LSB
LSB
DTX
HI-Z
HI-Z
Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
78
Rev. 1.2
Si3220/25
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PCLK_CNT
DRX
MSB
MSB
LSB
LSB
DTX
HI-Z
HI-Z
Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
PCLK
FSYNC
PCLK_CNT
DRX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
MSB
MSB
LSB
DTX
HI-Z
HI-Z
LSB
Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
3.30. PCM Companding
The Dual ProSLIC devices support both µ-255 Law (µ- Table 42 on page 81 and Table 43 on page 82 define
Law) and A-Law companding formats in addition to the µ-Law and A-Law encoding formats.
Linear Data mode. The data format is selected via the
The Dual ProSLIC devices also support a 16-bit linear
PCMF bits of the PCM Mode Select register. µ-Law
data format with no companding. This Linear mode is
mode is more commonly used in North America and
typically used in systems that convert to another
Japan, and A-Law is primarily used in Europe and other
companding format, such as adaptive differential PCM
countries. These 8-bit companding schemes follow a
(ADPCM) or systems that perform all companding in an
segmented curve formatted as a sign bit (MSB) followed
external DSP. The data format is 2s complement with
by three chord bits and four step bits. A-Law typically
MSB first (sign bit). Transmitting and receiving data via
uses a scheme of inverting all even bits while µ-Law
Linear mode requires two continuous time slots. An 8-bit
does not. Dual ProSLIC devices also support A-Law
Linear mode enables 8-bit transmission without
with inversion of even bits, inversion of all bits, or no bit
companding.
inversion by programming the ALAW bits of the PCM
Mode Select register to the appropriate setting.
Rev. 1.2
79
Si3220/25
PCLK
FSYNC
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16 17 18
PCLK_CNT
DRX
MSB
MSB
LSB
LSB
DTX
HI-Z
HI-Z
Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC
80
Rev. 1.2
Si3220/25
Table 42. µ-Law Encode-Decode Characteristics*
Segment #Intervals X Interval Size Value at Segment Endpoints
Number
Digital Code
Decode Level
8
16 X 256
8159
.
.
.
4319
4063
10000000b
10001111b
8031
4191
2079
1023
495
231
99
7
6
5
4
3
2
1
16 X 128
16 X 64
16 X 32
16 X 16
16 X 8
.
.
.
2143
2015
10011111b
10101111b
10111111b
11001111b
11011111b
11101111b
.
.
.
1055
991
.
.
.
511
479
.
.
.
239
223
.
.
.
103
95
16 X 4
.
.
.
35
31
33
15 X 2
.
.
.
3
1
0
__________________
1 X 1
11111110b
11111111b
2
0
*Note: Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
Rev. 1.2
81
Si3220/25
Table 43. A-Law Encode-Decode Characteristics1,2
Segment
Number
#intervals X interval size Value at segment endpoints Digital Code
Decode Level
7
16 X 128
4096
3968
.
10101010b
10100101b
4032
.
2176
2048
2112
1056
528
264
132
66
6
16 X 64
16 X 32
16 X 16
16 X 8
16 X 4
32 X 2
.
.
.
1088
1024
10110101b
10000101b
10010101b
11100101b
11110101b
11010101b
5
.
.
.
544
512
4
.
.
.
272
256
3
.
.
.
136
128
2
.
.
.
68
64
1
.
.
.
2
0
1
Notes:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values.
2. Digital code includes inversion of even-numbered bits. Other available formats include inversion of odd bits, inversion
of all bits, or no bit inversion. See "3.30. PCM Companding" on page 79 for more details.
82
Rev. 1.2
Si3220/25
If GCI mode is selected, the following pins must be tied
to the correct state to select one of eight subframe
timeslots in the GCI frame (described below). These
pins must remain in this state while the Dual ProSLIC is
operating. Selecting a particular subframe causes that
individual Dual ProSLIC device to transmit and receive
on the appropriate subframe in the GCI frame, which is
initiated by an FSYNC pulse. No further register settings
are needed to select which subframe a device uses,
and the subframe for a particular device cannot be
changed while in operation.
3.31. General Circuit Interface
The Dual ProSLIC devices also contain an alternate
communication interface to the SPI and PCM control
and data interface. The general circuit interface (GCI) is
used for the transmission and reception of both control
and data information onto a GCI bus. The PCM and GCI
interfaces are both four-wire interfaces and share the
same pins. The SPI control interface is not used as a
communication interface in the GCI mode but rather as
hard-wired channel selector pins. The selection
between PCM and GCI modes is performed out of reset
using the SDITHRU pin. Tables 44 and 45 illustrate how
to select the communication mode and how the pins are
used in each mode.
Table 46. GCI Mode Subframe Selection
SDI SDO
CS
GCI Subframe 0 Selected
(Voice channels 1–2)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
Table 44. PCM or GCI Mode Selection
SDITHRU SCLK
Mode Selected
GCI Mode—1x PCLK (2.048 MHz)
GCI Mode—2x PCLK (4.096 MHz)
PCM Mode
GCI Subframe 1 Selected
(Voice channels 3–4)
0
1
0
1
0
1
0
0
0
1
0
1
x
GCI Subframe 2 Selected
(Voice channels 5–6)
Note: Values shown are the states of the pins at the rising
GCI Subframe 3 Selected
(Voice channels 7–8)
edge of RESET.
GCI Subframe 4 Selected
(Voice channels 9–10)
Table 45. Pin Functionality in PCM or GCI Mode
Pin Name
PCM Mode
GCI Mode
GCI Subframe 5 Selected
(Voice channels 11–12)
CS
SPI Chip Select
Channel Selector,
bit 0
GCI Subframe 6 Selected
(Voice channels 13–14)
SCLK
SDI
SPI Clock Input
PCLK Rate
Selector
GCI Subframe 7 Selected
(Voice channels 15–16)
SPI Serial Data Input Channel Selector,
bit 2
In GCI mode, the PCLK input requires either a
2.048 MHz or a 4.096 MHz clock signal, and the
FSYNC input requires an 8 kHz frame sync signal. The
overall unit of data used to communicate on the GCI
highway is a frame 125 µs in length. Each frame is
initiated by a pulse on the FSYNC pin whose rising
edge signifies the beginning of the next frame. In 2x
PCLK mode, the user sees twice as many PCLK cycles
during each 125 µs frame versus 1x PCLK mode. Each
frame consists of eight fixed timeslot subframes that are
assigned by the subframe select pins as described
above (SDI, SDO, and CS). Within each subframe are
four channels (bytes) of data including two voice data
channels, B1 and B2, one Monitor channel, M, used for
initialization and setup of the device, and one Signaling
and Control channel, SC, used for communicating the
status of the device and initiating commands. Within the
SC channel are six Command/Indicate (C/I) bits and two
SDO
SPI Serial Data
Output
Channel Selector,
bit 1
SDITHRU SPI Data Throughput
pin for Daisy Chaining
Operation (Connects
to the SDI pin of the
PCM/GCI Mode
Selector
subsequent device in
the daisy chain)
FSYNC
PCM Frame Sync
Input
GCI Frame Sync
Input
PCLK
DTX
PCM Input Clock
GCI Input Clock
PCM Data Transmit GCI Data Transmit
PCM Data Receive GCI Data Receive
DRX
Note: This table denotes pin functionality after the rising
edge of RESET and mode selection.
Rev. 1.2
83
Si3220/25
handshaking bits, MR and MX. The C/I bits indicate
status and command communication while the
Table 47. Subframe Selection 16-Bit GCI Mode
handshaking bits Monitor Receive, MR, and Monitor
Transmit, MX, exchange data in the Monitor channel.
SDI
SDO
Figure 55 illustrates the contents of a GCI highway GCI Subframe 0 Selected
1
1
frame.
(Voice channels 0–1)
3.31.1. 16-Bit GCI Mode
GCI Subframe 1 Selected
(Voice channels 2–3)
1
0
0
0
1
0
In addition to the standard 8-bit GCI mode, the Dual
ProSLIC devices also offer a 16-bit GCI mode for
passing 16-bit voice data to the upstream host
processor. This mode can be used for testing purposes
or for passing non-companded voice data to an
upstream DSP for further processing.
GCI Subframe 2 Selected
(Voice channels 4–5)
GCI Subframe 3 Selected
(Voice channels 6–7)
In 16-bit GCI mode, both of the 8-bit voice data
channels (B1 and B2 in Figure 56) of each subframe are
required to pass the 16-bit voice data to the host. Each
125 µs frame can, therefore, accommodate up to eight
voice channels (the Dual ProSLIC can accommodate up
to sixteen voice channels in 8-bit GCI mode). Table 47
describes the GCI mode subframe selection for 16-bit
GCI mode.
3.31.2. Monitor Channel
The Monitor channel is used for initialization and setup
of the Dual ProSLIC devices. It is also used for general
communication with the Dual ProSLIC by allowing read
and write access to the Dual ProSLIC devices registers.
Use of the monitor channel requires manipulation of the
125 µs = 1 Frame
FS
SF0
SF1
SF2
SF3
SF4
SF5
SF6
SF7
Sub-Frame
8
8
B2
1
8
SC
3
B1
0
M
2
1
1
Channel
C/I
MR MX
Figure 55. Time-Multiplexed GCI Highway Frame Structure
84
Rev. 1.2
Si3220/25
125 µs = 1 Frame
FS
CH0
CH1
CH2
CH3
Sub-Frame
16
16
B2
16
B1
6
1
1
8
Unused
M
C/I MR MX
Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode
1st Byte
2nd Byte
3rd Byte
MX
Transmitter
MX
MR
MR
Receiver
ACK
1st Byte
ACK
2nd Byte
ACK
3rd Byte
125 µs
Figure 57. Monitor Handshake Timing
Rev. 1.2
85
Si3220/25
The Idle state is achieved by the MX and MR bits being By correctly manipulating the MX and MR bits, a
held inactive for two or more frames. When a transmission sequence can continue from the beginning
transmission is initiated by a host device, an active state specified address until an invalid memory location is
is seen on the downstream MX bit. This signals the Dual reached. To end a transmission sequence, the host
ProSLIC that a transmission has begun on the Monitor processor must signal an End-of-Message (EOM) by
channel and it should begin accepting data from it. After placing the downstream MX and MR bits inactive for two
reading the data on the monitor channel, the Dual consecutive frames. The transmission can also be
ProSLIC acknowledges the initial transmission by stopped by the Dual ProSLIC by signaling an abort. This
placing the upstream MR bit in an active state. The data is signaled by placing the upstream MR bit inactive for
is received, and the upstream MR becomes active in the at least two consecutive cycles in response to the
frame immediately following the downstream MX downstream MX bit going active. An abort is signaled by
activation. The upstream MR then remains active until the Dual ProSLIC for the following reasons:
either the next byte is received or an end of message is
ꢀ
A read or write to an invalid memory address is
attempted.
detected (signaled by the downstream MX being held
inactive for two or more consecutive frames). Upon
receiving acknowledgement from the Dual ProSLIC that
the initial data was received (signaled by the upstream
MR bit transitioning from an active to an inactive state),
the host device places the downstream MX bit in the
inactive state for one frame and then either transmits
another byte by placing the downstream MX bit in an
active state again or signals an end of message by
leaving the downstream MX bit inactive for a second
frame.
ꢀ
ꢀ
An invalid command sequence is received.
A data byte was not received for at least two
consecutive frames.
ꢀ
ꢀ
ꢀ
A collision occurs on the Monitor data bytes while
the Dual ProSLIC is transmitting data.
Downstream monitor byte not $FF while upstream
monitor byte is transmitting.
MR/MX protocol violation.
Whenever the Dual ProSLIC aborts due to an invalid
When the host is performing a write command, the host command sequence, the state of the Dual ProSLIC
only manipulates the downstream MX bit, and the Dual does not change. If a read or write to an invalid memory
ProSLIC only manipulates the upstream MR bit. If a address is attempted, all previous reads or writes in that
read command is performed, the host initially transmission sequence are valid up to the read or write
manipulates the downstream MX bit to communicate to the invalid memory address. If an end-of-message is
the command but then manipulates the downstream MR detected before
a valid command sequence is
bit in response to the Dual ProSLIC responding with the communicated, the Dual ProSLIC returns to the idle
requested data. Similarly, the Dual ProSLIC initially state and remains unchanged.
manipulates its upstream MR bit to receive the read
The data presented to the Dual ProSLIC in the
command and then manipulates its upstream MX bit to
downstream Monitor bits must be present for two
respond with the requested data. If the host is
consecutive frames to be considered valid data. The
transmitting data, the Dual ProSLIC always transmits a
Dual ProSLIC is designed to ensure it has received the
$FF value on its Monitor data byte. While the Dual
same data in two consecutive frames. If it does not, it
ProSLIC is transmitting data, the host should always
does not acknowledge receipt of the data byte and waits
transmit a $FF value on its Monitor byte. If the Dual
until it does receive two consecutive identical data bytes
ProSLIC is transmitting data and detects a value other
before acknowledging to the transmitter that it has
than a $FF on the downstream Monitor byte, the Dual
received the data. If the transmitter attempts to signal
ProSLIC signals an abort.
transmission of a subsequent data byte by placing the
For read and write commands, an initial address must downstream MX bit in an inactive state while the Dual
be specified. The Dual ProSLIC responds to a read or a ProSLIC is still waiting to receive a valid data byte
write command at this address and then subsequently transmission of two consecutive identical data bytes,
increments this address after every register access. In the Dual ProSLIC signals an abort and ends the
this manner, multiple consecutive registers can be read transmission. Figure 58 shows a state diagram for the
or written in one transmission sequence.
Receiver Monitor channel for the Dual ProSLIC.
Figure 59 shows a state diagram for the Transmitter
Monitor channel for the Dual ProSLIC.
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Idle
MR = 1
MX * LL
Initial
State
M X
1stByte
Received
MR = 0
M X
Abort
MR = 1
ABT
M X
M X
Any
State
M X
M X
Byte
Valid
Wait
for LL
MX * LL
MR = 0
MR = 0
MX * LL
M X
MX * LL
M X
M X
nth byte
received
MR = 1
Wait
for LL
MR = 0
New Byte
MR = 1
MX * LL
M X
MR: MR bit calculated and transm itted on data upstream (DTX) line.
MX: MX bit received data downstream (DRX) line.
LL: Last look of m onitor byte received on DRX line.
ABT: Abort indication to internal source.
Figure 58. Dual ProSLIC Monitor Receiver State Diagram
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MR * MXR
MXR
MR * MXR
MR * MXR
Idle
MR = 1
Wait
MX = 1
Abort
MX = 1
Initial
State
MR * RQT
MR
MR * RQT
MR
1st Byte
MX = 0
EOM
MX = 1
MR * RQT
nth Byte
ack
MR
MX = 1
MR
MR * RQT
Wait for
ack
MR * RQT
CLS/ABT
MX = 0
Any State
MR: MR bit received on DRX line.
MX: MX bit calculated and expected on DTX line.
MXR: MX bit sam pled on DTX line.
CLS: Collision within the m onitor data byte on DTX
line.
RQT: Request for transm ission from internal source.
ABT: Abort request/indication.
Figure 59. Dual ProSLIC Monitor Transmitter State Diagram
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Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using
the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the receiver for
correct communication with the Dual ProSLIC. Devices that do not accept this “best case” timing scenario will
not be able to communicate with the Dual ProSLIC.
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Monitor Data Downstream
Data to be
written to
$11
Data to be Data to be Data to be
$FF
$FF
$91
$91
$01
$01
$10
$10
$FF $FF
written to
$10
written to
$10
written to
$11
125 µs
1 Frame
MX Downstream Bit
MR Downstream Bit
EOM Signalled
Monitor Data Upstream
$FF $FF
$FF $FF
$FF
$FF
$FF
$FF
$FF
$FF
$FF
$FF
$FF
$FF
MX Upstream Bit
MR Upstream Bit
EOM
Acknowledge
= Acknowledgement of data reception
Figure 61. Example Write to Registers $10 and $11 in Channel 0 of the Dual ProSLIC
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3.31.3. Programming the Dual ProSLIC Using the
Monitor Channel
Immediately after the last bit of the CID command is
received, the Dual ProSLIC responds with a fixed two-
byte identification code as follows:
The Dual ProSLIC devices use the monitor channel to
Transfer status or operating mode information to and
from the host processor. Communication with the Dual
ProSLIC should be in the following format:
MSB
7
LSB
0
Bit
6 5
0 0
0 1
4
A
1
3 2 1
0 0 0
1 1 1
Byte 1: Device Address Byte
Byte 2: Command Byte
Address Byte
Command Byte
1
1
0
0
Byte 3: Register Address Byte
Bytes 4-n: Data Bytes
Bytes n+1, N+2: EOM
A = 1: Channel A is the source
A = 0: Channel B is the source
3.31.4. Device Address Byte
The device address byte identifies which device
receives the particular message. This address must be
the first byte sent to the Dual ProSLIC at the beginning
of each transmission sequence. The device address
byte has the following structure:
Upon sending the two-byte CID command, the Dual
ProSLIC sends an EOM signal (MR = MX = 1) for two
consecutive frames. When C = 0, B must be 0, or the
Dual ProSLIC signals an abort due to an invalid
command. In this mode, only bit C is programmable.
3.31.6. Command Byte
MSB
LSB
0
The command byte has the following structure:
7
1
6
0
5
0
4
3
2
0
1
0
MSB
RW
LSB
A
B
C
CMD[6:0]
A = 1:
A = 0:
B = 1:
B = 0:
C = 1:
C = 0:
Channel A receives the command.
Channel A does not receive the command.
Channel B receives the command.
RW = 1: A Read operation is performed from the Dual
ProSLIC
Channel B does not receive the command. RW = 0: A Write operation is performed to the Dual
ProSLIC
Normal command follows.
CMD[6:0] = 0000001: Read or Write from the Dual
ProSLIC
Channel identification command.
When C = 1, bits A and B are channel enable bits.
When these bits are set to 1, the corresponding
CMD[6:0] = 0000010-1111111: Reserved
channels receive the command in the next command 3.31.7. Register Address Byte
byte. The channels with corresponding bits set to 0
ignore the subsequent command byte.
The register address byte has the following structure:
MSB LSB
3.31.5. Channel Identification (CID) Command
The lowest programmable bit of the device address
byte, C, enables a special channel identification
command to identify itself by software. When C = 0, the
structure of this command is as follows:
ADDRESS[7:0]
This byte contains the actual 8-bit address of the
register to be read or written.
A = 1: Channel A is the destination
A = 0: Channel B is the destination
3.31.8. SC Channel
The downstream and upstream SC channels are
continuously carrying I/O information to and from the
Dual ProSLIC during every frame. The upstream
processor has immediate access to the receive
(downstream) and transmit (upstream) data present on
the Dual ProSLIC digital I/O port when used in GCI
mode. The SC channel consists of six C/I bits and two
handshaking bits as described in the tables below. The
functionality of the handshaking bits is defined in the
MSB
LSB
0
Bit
7
1
0
6 5
0 0 A 0 0 0
0 0 0 0 0
4 3 2 1
Address Byte
Command Byte
0
0
0
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monitor channel section. This section defines the Figure 63 illustrates the transmission protocol for the C/I
functionality of the six C/I bits whether they are being bits within the downstream SC channel. New data
transmitted to the GCI bus via the DTX pin (upstream) received by either channel must be present and match
or received from the GCI bus via the DRX pin for two consecutive frames to be considered valid.
(downstream). The structure of the SC channel is When a new command is communicated via the
shown in Figure 62.
downstream C/I bits, this data must be sent for at least
two consecutive frames to be recognized by the Dual
ProSLIC.
LSB
MSB
The current state of the C/I bits is stored in a primary
register, P. If the received C/I bits are identical to the
current state, no action is taken. If the received C/I bits
differ from those in register P, the new set of C/I bits is
loaded into secondary register S, and a latch is set.
When the next set of C/I bits is received during the
frame that immediately follows, the following rules
apply:
7
6
5
4
3
2
1
0
CI2A CI1A CI0A CI2B CI1B CI0B MR
MX
Figure 62. SC Channel Structure
3.31.9. Downstream (Receive) SC Channel Byte
The first six bits in the downstream SC channel control
both channels of the Dual ProSLIC where the C/I bits
are defined as follows:
ꢀ
ꢀ
ꢀ
If the received C/I bits are identical to the contents of
register S, the stored C/I bits are loaded into register
P, and a valid C/I bit transition is recognized. The
latch is reset, and the Dual ProSLIC responds
accordingly to the command represented by the new
C/I bits.
CI2A, CI1A, CI0A
CI2B, CI1B, CI0B
MR, MX
Used to select operating mode for
channel A
Used to select operating mode for
channel B
If the received C/I bits differ from both the contents of
register S and the contents of register P, the newly-
received C/I bits are loaded into register S, and the
latch remains set. This cycle continues as long as
any new set of C/I bits differs from the contents of
registers S and P.
Monitor channel handshake bits
Table 48. Programming Operating Modes Using
Downstream SC Channel C/I Bits
If the newly-received C/I bits are identical to the
contents of register P, the contents of register P
remain unchanged, and the latch is reset.
Channel Specific C/I bits
Dual ProSLIC Operating
Mode
CI2x
0
CI1x
0
CI0x
0
Open (high impedence,
no line monitoring)
0
0
0
1
1
0
Forward Active
Forward On-Hook Trans-
mission
0
1
1
1
1
0
0
1
1
0
1
0
Ground Start (Tip Open)
Ringing
Reverse Active
Reverse On-Hook Trans-
mission
1
1
1
Ground Start (Ring
Open)
Note: x = A or B, corresponding to Channel A or
Channel B.
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Receive New
C/I Code
Yes
= P?
No
P: C/I Primary Register Contents
S: C/I Secondary Register Contents
Store in S
Receive New
C/I Code
Yes
Yes
Load C/I Register
With New C/I Bits
= S?
No
= P?
No
Figure 63. Protocol for Receiving C/I Bits in the Dual ProSLIC
When the Dual ProSLIC is set to GCI mode at appropriate thresholds and control the linefeed
initialization, the default setting ignores the downstream transitions, the downstream SC channel byte should be
SC channel byte and allows linefeed state commands to updated accordingly once the interrupt bit is read from
be directed through the monitor channel. This default the upstream SC channel byte. To disable the automatic
configuration is enabled by initializing the GCILINE bit transitions, the user must set the GCILINE bit. Enabling
of the PCMMODE register to 0, which prevents the Dual this manual mode requires the host processor to read
ProSLIC from transitioning between linefeed operating the upstream SC channel information and provide the
states due to invalid data that may exist within the appropriate downstream SC channel byte command to
downstream SC channel byte. To transfer direct linefeed program the correct linefeed state.
control to the downstream SC channel, the user must
Table 49 presents the automatic linefeed state
set the GCILINE bit to 1. Once the GCILINE bit has
transitions and their associated registers that cause the
been set, the Dual ProSLIC follows the commands that
transition.
are contained in the downstream SC channel byte as
The transition to the OPEN state stemming from power
described in Figure 62.
alarm detection is intended to protect the Dual ProSLIC
The Dual ProSLIC architecture also enables automatic
circuit in the event that too much power is dissipated in
transitions between linefeed operating states to reduce
the Si3200 LFIC. This alarm is typically due to a fault in
the amount of interaction required between the host
the application circuit or on the subscriber loop but can
processor and the Dual ProSLIC. When a GCI bus is
be caused by intermittent power spikes depending on
implemented, the user must ensure that these
the threshold to which the alarm is set. The user can re-
automatic linefeed state transitions are consistent with
initialize the linefeed operating state that was in effect
the linefeed commands contained within the
just prior to the power alarm by toggling the downstream
SC channel byte to the OPEN state for two consecutive
downstream SC channel byte.
In normal operation, these automatic linefeed state cycles and then resetting the downstream SC channel
transitions are accompanied by the setting of a byte to the intended linefeed state for two consecutive
threshold detection flag and an interrupt bit, if enabled. cycles. If the Dual ProSLIC continues to automatically
To allow the Dual ProSLIC to automatically detect the transition to the OPEN state, the power alarm threshold
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might be set incorrectly. If this problem persists after the represent a valid transfer. The upstream C/I bits are
power alarm settings are verified, a system fault is defined as follows:
probable, and the user should take measures to
diagnose the problem.
CI2A, CI1A, CI0A Monitors status data for channel A
3.31.10. Upstream (Transmit) SC Channel Byte
CI2B, CI1B, CI0B Monitors status data for channel B
The upstream SC channel byte looks similar to the
downstream SC channel byte except that the
MR, MX
Monitor channel handshake bits
(see Monitor Channel section)
information quickly transfers the most time-critical
information from the Dual ProSLIC to the GCI bus. Each
upstream SC channel byte transfer from the Dual
ProSLIC lasts for at least two consecutive frames to
Table 49. Automatic Linefeed State Transitions
Initiating Action
Automatic Linefeed State
Transition
Detection/Control Bits Interrupt Enable/Status
Bits
Loop closure detected On-hook active → off-hook active,
Off-hook active → on-hook active
LCR (Register 9)
RTP (Register 9)
LOOPE, LOOPS
(Register 16/19)
Ring trip detected
Ringing → off-hook active
RTRIPE, RTRIPS
(Register 16/19)
Ringing burst
cadence
Ringing → on-hook transmission
On-hook transmission → ringing
T1EN, T2EN
(Register 23)
RINGT1E, RINGT2E,
RINGT1S, RINGT2S
(Register 15/18)
Power alarm detected
Any state → open
PQ1DL (RAM 50)
PQ1E, PQ1S
(Registers 17/20)
Table 50. Monitored Data via Upstream SC Channel C/I Bits
C/I Bit
Information Provided
Mirrored Register Bits
Context
CI2A
Interrupt information on
channel A
IRQ0[0]+
IRQ0[1]+
IRQ0[2]
CI2A = 0: No interrupt on channel A
CI2A = 1: Interrupt present on channel A
CI1A
CI0A
Hook status information
on channel A
LCRRTP[0]
(LCR bit)
CI1A = 0: Channel A is on-hook
CI1A = 1: Channel A is off-hook
Ground key information
on channel A
LCRRTP[2]
(LONGHI bit)
CI0A = 0: No longitudinal current detected
CI0A = 1: Longitudinal current detected in chan-
nel A
CI2B
Interrupt information on
channel B
IRQ0[4]+
IRQ0[5]+
IRQ0[6]
CI2A = 0: No interrupt on channel B
CI2A = 1: Interrupt present on channel B
CI1B
CI0B
Hook status information
on channel B
LCRRTP[0]
(LCR bit)
CI1A = 0: Channel B is on-hook
CI1A = 1: Channel B is off-hook
Ground key information
on channel B
LCRRTP[2]
(LONGHI bit)
CI0A = 0: No longitudinal current detected
CI0A = 1: Longitudinal current detected in chan-
nel B
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The interrupt information for channels A and B is a ꢀ A third digital loopback takes the digital stream at the
single bit that indicates that one or more interrupts might
exist on the respective channel. Each of the individual
interrupt flags (see registers 18–20) can be individually
masked by writing the appropriate bit in registers 21–23
to ignore specific interrupts. When using the GCI mode,
the user should verify that each of the desired interrupt
bits are set so the upstream SC channel byte includes
the required interrupt functions.
output of the µ-Law/A-Law expander and feeds it
back to the input of the µ-Law/A-Law compressor.
(See DLM1 path in Figure 11.) This path verifies that
the host is connected correctly with the Dual
ProSLIC through the PCM interface and that the
PCLK and FSYNC signals are correctly set. This
mode also can test the µ-Law/A-Law companding
process. The signal path starts with 8-bit PCM data
input to the receive path and ends with 8-bit PCM
data at the output of the transmit path. The user can
also connect directly to the 16-bit data to eliminate
the µ-Law/A-Law companding process when testing
the PCM interface.
3.32. System Testing
The Dual ProSLIC devices include a complete suite of
test tools to test the functionality of the line card and
detect fault conditions present on the TIP/RING pair.
Using one of the loopback test modes with the signal
generation and measurement tools eliminates the need
for per-line test relays and centralized test equipment.
3.32.2. Line Test and Diagnostics
The Dual ProSLIC devices provide a variety of signal
generation and measurement tools that facilitate fault
detection and parametric diagnostics on the TIP/RING
3.32.1. Loopback Modes
Three loopback test options are available for the Dual pair and line card functionality verification. The Dual
ProSLIC devices:
ProSLIC generates test signals, measures the
appropriate voltage/current/signal levels, and processes
the results to provide a meaningful result to the user.
Interaction is required from the host microprocessor to
load the test parameters into the appropriate registers,
initiate the test(s), and read the results from the
registers. In some cases, the host processor might also
be required to perform some simple mathematics to
achieve the results. Software modules are available to
simplify integration of the diagnostics functions into the
system. The need for test relays and a separate test
head is eliminated in most applications. To address
legacy applications, all versions of the Dual ProSLIC
include test-in and test-out relay drivers to switch in a
centralized test card.
ꢀ
The codec loopback path encompasses almost
entirely the electronics of both the transmit and
receive paths. The analog signal at the output of the
receive path is fed back to the input of the transmit
path through a feedback path on the analog side of
the audio codec. Both the impedance synthesis and
transhybrid balance functions are disabled in this
mode. (See DLM3 path in Figure 11 on page 24.)
The signal path starts with 8-bit PCM data input to
the receive path and ends with 8-bit PCM data at the
output of the transmit path. The user can bypass the
companding process and interface directly to the 16-
bit data.
ꢀ
A second digital loopback takes the receive path
digital stream and routes it back to the transmit path
via the transhybrid feedback path. (See DLM2 path
through block H in Figure 11.) This mode
The Dual ProSLIC line test and diagnostics capabilities
are categorized into three sections: signal generation
tools, measurement tools, and diagnostics capabilities.
Using these signal generation and measurement tools,
a variety of other diagnostic functions can be performed
to meet the unique requirements of specific
applications. Table 51 summarizes the ranges and
capabilities of the signal generation and measurement
tools.
characterizes the transhybrid filter response. The
transhybrid block can also be disabled (set to unity
gain) in this mode for diagnosing the digital gain
blocks and filter stages in both transmit and receive
paths. The signal path starts with 8-bit PCM data
input to the receive path and ends with 8-bit PCM
data at the output of the transmit path. The user can
bypass the companding process and interface
directly to the 16-bit data.
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Table 51. Summary of Signal Generation and Measurement Tools
Function
Range
Accuracy/Resolution
Comments
Signal Generation Tools
18 to 45 mA
DC Current Generation
DC Voltage Generation
Audio Tone Generation
Ringing Signal Generation
0.875 mA
1.005 V
—
0 to 63.3 V
200 to 3400 Hz
4 to 15 Hz
16 to 100 Hz
±5%
±1%
Measurement Tools
8-Bit dc/Low-Frequency
Monitor A/D Converter
High Range:
0 to 160.173 V
0 to 101.09 mA
800 Hz update rate
628 mV
396.4 µA
ac , ac , and dc
rms PK
post-processing blocks
Low Range: 0 to 64.07 V
0 to 50.54 mA
251 mV
198.2 µA
Programmable Timer
0 to 8.19 s
3 to 400 Hz
0 to 2.5 V
125 µs
—
AC Low-Pass Filter
16-Bit Audio A/D Converter
Transmit Path Notch Filter
38 µV
—
300 to 3400 Hz
Single or dual notch,
≥90 dB attenuation
Transmit Path Bandpass Filter
300 to 3400 Hz
—
3.32.3. Signal Generation Tools
ꢀ Diagnostics mode ringing generation. The Dual
ProSLIC devices can generate an internal low-level
ringing signal to test for the presence of REN without
causing the terminal equipment to ring audibly. This
ringing signal can be either balanced or unbalanced
depending on the state of the RINGUNB bit of the
RINGCON register. This feature is also available
with the Si3225 provided that sufficient battery
voltage is present.
ꢀ TIP/RING dc signal generation. The Dual ProSLIC
line feed D/A converter can program a constant
current linefeed from 18–45 mA in 0.87 mA steps
with a ±10% total accuracy. In addition, the open-
circuit TIP/RING voltage can be programmed from 0
to 63 V in 1 V steps. The linefeed circuitry can also
generate a controlled polarity reversal.
ꢀ Tone generation. The Dual ProSLIC devices can
generate single or dual tones over the entire audio
band and can direct them into either the transmit or
receive path depending on the diagnostic
requirements. Ringing signals from 4–100 Hz can
also be generated.
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PEAK
DETECT
DIAGPK
VTIP
VRING
VLOOP
VLONG
ILOOP
ILONG
DIAGDCCO
DIAGDC
DIAGAC
LPF
DIAGACCO
VRING,EXT
IRING,EXT
FULL WAVE
RECTIFY
LPF
Figure 64. SLIC Diagnostic Filter Structure
ꢁ VLONG = (VTIP+VRING)/2 = longitudinal voltage
3.32.4. Measurement Tools
ꢁ ILOOP = ITIP-IRING = metallic (loop) current
ꢁ ILONG = (ITIP+IRING)/2 = longitudinal current
ꢀ 8-Bit monitor A/D converter. This 8-bit A/D
converter monitors all dc and low-frequency voltage
and current data from TIP to ground and RING to
ground. Two additional values, TIP – RING and
TIP + RING, are calculated and stored in on-chip
registers to analyze metallic and longitudinal effects.
The A/D operates at an 800 Hz update rate to allow
measurement bandwidth from dc to 400 Hz. A dual-
range capability allows high-voltage/high-current
measurement in the high range but can also
measure lower voltages and currents with a tighter
resolution.
ꢁ VRING, EXT = ringing voltage when using an external
ringing source (Si3225 only)
ꢁ IRING,EXT = ringing current when using an external
ringing source (Si3225 only)
The SLIC diagnostic capability consists of a peak detect
block and two filter blocks, one for dc and one for ac.
The topology is illustrated in Figure 64.
The peak detect filter block reports the magnitude of the
largest positive or negative value without sign. The dc
filter block consists of a single pole IIR low-pass filter
with a coefficient held in the DIAGDCCO RAM location.
The filter output is read from the DIAGDC RAM location.
The ac filter block consists of a full-wave rectifier
followed by a single-pole IIR low-pass filter with a
coefficient held in the DIAGACCO RAM location. The
peak value is read from the DIAGPK RAM location. The
peak value is cleared and the filters are flushed on the
0-1 transition of the SDIAG bit and when the input
source changes. The user can write 0 to the DIAGPK
RAM location to get peak information for a specific time
interval.
ꢀ Programmable bandpass filter. A bandpass filter
discriminates certain frequency ranges, such as
ringing frequencies and 50 Hz/60 Hz induction, from
nearby or crossed power leads.
ꢀ SLIC diagnostics filter. Several post-processing
filter blocks monitor peak dc and ac characteristics of
the Monitor A/D converter outputs and values
derived from these outputs. Setting the SDIAG bit in
the DIAG register enables the filters. There are
separate filters for each channel, and their control is
independent. These filters require DSP processing,
which is available only when voice band processing
is not being performed. If an off-hook or ring trip
condition is detected while the SDIAG bit is set, the
bit is cleared, and the diagnostic information is not
processed.
ꢀ 16-bit audio A/D converter. The A/D converter
portion of the audio codec is made available for
processing test data received back through the
transmit audio path. The audio path offers a 2.5 V
peak voltage measurement capability and a coarse
attenuation stage for scenarios where the incoming
signal amplitude must be attenuated by as much as
3 dB to bring it into the allowable input range without
clipping.
The following parameters can be selected as inputs
to the diagnostic block by setting the SDIAG bits in
the DIAG register to values 0–7 corresponding to the
order below:
ꢁ VTIP = voltage on the TIP lead
ꢁ VRI NG = voltage on the RING lead
ꢁ VLOOP = VTIP-VRING = metallic (loop) voltage
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ꢀ Programmable timer. The Dual ProSLIC devices
incorporate several digital oscillator circuits to
program the on and off times of the ringing and
pulse-metering signals. The tone generation
oscillator can be used to program a time period for
averaging specific measured test parameters.
The power averaging filter time constant is absolute
value programmable, and the average power result is
read from the TESTAVO RAM location.
3.32.5. Diagnostics Capabilities
ꢀ Foreign voltages test. The Dual ProSLIC devices
can detect the presence of foreign voltages
ꢀ Transmit audio path diagnostics filter. Transmit
path audio diagnostics are facilitated by
according to GR-909 requirements of ac voltages >
10 V and dc voltages > 6 V from T-G or R-G. This
test is performed when it has been determined that a
hazardous voltage is not present on the line.
implementing a sixth-order IIR filter followed by peak
detection and power estimation blocks. This filter
can be programmed to eliminate or amplify specific
signals for the purpose of measuring the peak
amplitude and power content of individual
components in the audio spectrum. Figure 11 on
page 24 illustrates the location of the diagnostics
filter block.
The sixth order IIR filter operates at an 8 kHz sample
rate and is implemented as three second-order filter
stages in cascade. Each second-order filter offers
five fully-programmable coefficients (a1, a2, b0, b1,
and b2) with 25-bit precision by providing several
user-accessible registers. Each filter stage is
implemented with the following format:
ꢀ Resistive faults (leakage current) test. Resistive
fault conditions are measured from T-G, R-G, or T-R
for dc resistance per GR-909 specifications. If the dc
resistance is < 150 kΩ, it is considered a resistive
fault. To perform this test, program the Dual ProSLIC
chipset to generate a constant open-circuit voltage,
and measure the resulting current. The resistance is
then calculated.
ꢀ Receiver off-hook test. Uses a similar procedure
as described in the resistive faults test above but is
measured across T-R only. In addition, two
measurements must be performed at different open-
circuit voltages to verify the resistive linearity. If the
calculated resistance has more than 15%
nonlinearity between the two calculated points and
the voltage/current origin, it is determined to be a
resistive fault.
(b0 + b1z–1 + b2z–2
-------------------------------------------------------
)
H(z) =
(1 – a1z–1 – a2z–2
)
If any of the second-order filter stages are not
required, they can be programmed to H(z) = 1 by
setting a1 = 0, a2 = 0, b0 = 1, b1 = 0, and b2 = 0.
This flexible filter block can be programmed with the
following characteristics:
ꢀ Ringers (REN) test. Verifies the presence of REN at
the end of the TIP/RING pair per GR-909
specifications. It can be implemented by generating
a 20 Hz ringing signal between 7 V
and 17 V
rms
rms
and measuring the 20 Hz ac current using the 8-bit
monitor ADC. The resistance (REN) can then be
calculated using the software module. The
acceptable REN range is >0.175 REN (<40 kΩ) or
<5 REN (>1400 Ω). A returned value of <1400 Ω is
determined to be a resistive fault from T-R, and a
returned value >40 kΩ is determined to be a loop
with no handset attached.
ꢁ Single notch. Used for measuring noise/distortion in
the presence of a single tone. 90 dB attenuation is
provided at the notched frequency. Implemented by
placing two 0s on the unit circle at the notch frequency
and two poles inside the unit circle at the notch
frequency.
ꢁ Dual notch. Used for measuring noise/distortion in the
presence of dual tones.
ꢁ Single notch/single peak. Used for measuring a
particular harmonic in the presence of a single tone.
ꢁ Dual notch/single peak. Used to measure a particular
intermodulation product in the presence of dual tones.
ꢀ AC line impedance measurement. Determines the
ac loop impedence across T-R. It can be
implemented by sending out multiple discrete tones,
one at a time, and measuring the returned amplitude
with the hybrid balance filter disabled. By calculating
the voltage difference between the initial amplitude
and the received amplitude and dividing the result by
the audio current, the line impedance can then be
calculated.
Because each second-order filter stage is fully-
programmable, there are many other possible filter
implementations.
The IIR filter output is measured for power and peak
post-processing. The peak measurement window
duration is programmable by entering a value into the
TESTWLN RAM address. The peak value (TESTPKO)
is updated at the end of each window period. Power
measurement is performed by using a single-pole IIR
filter to average the output of the sixth-order IIR filter.
98
Rev. 1.2
Si3220/25
ꢀ Line capacitance measurement. Implemented like
the ac line impedance measurement test above, but
the frequency band of interest is between 1 kHz and
3.4 kHz. Knowing the synthesized two-wire
impedance of the Dual ProSLIC, the roll-off effect
can be used to calculate the ac line capacitance.
ꢀ Ringing voltage verification. Verifies that the
desired ringing signal is correctly applied to the TIP/
RING pair and can be measured in the 8-bit monitor
ADC, which senses low-frequency signals directly
across T-R.
ꢀ Idle channel noise measurement. Given any
transmission mode with no tone generated and the
hybrid balance filter turned off, the voice band
energy can be measured through the normal audio
path and read through the appropriate register.
ꢀ Harmonic distortion measurement. Detects the
power content of a particular harmonic. It can be
implemented by programming two of the IIR
diagnostics filter stages to provide a notch at the
fundamental frequency and a peak at the harmonic
of interest. Performing this procedure on all relevant
harmonics individually and summing the results
provides the total harmonic distortion.
ꢀ Intermodulation distortion measurement (two-
tone method). Measures the intermodulation
distortion product in the presence of two tones. It can
be implemented by programming the three IIR
diagnostic filter stages to provide two notches at the
two tone frequencies and a peak at the frequency of
interest.
Rev. 1.2
99
Si3220/25
4. Pin Descriptions: Si3220/25
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SVBATa
RPOa
RPIa
GPOa
CS
SVBATa
RPOa
RPIa
RRDa
CS
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SDITHRU
SDI
3
3
SDITHRU
SDI
RNIa
4
RNIa
4
RNOa
CAPPa
CAPMa
QGND
IREF
5
SDO
RNOa
CAPPa
CAPMa
QGND
IREF
5
SDO
6
SCLK
VDD4
GND4
INT
SCLK
VDD4
GND4
INT
6
7
7
Si3220
64-Lead TQFP
(epad)
Si3225
64-Lead TQFP
(epad)
8
8
9
9
CAPMb
CAPPb
RNOb
RNIb
10
11
12
13
14
15
16
PCLK
GND3
VDD3
DTX
CAPMb
CAPPb
RNOb
RNIb
10
11
12
13
14
15
16
PCLK
GND3
VDD3
DTX
RPIb
DRX
RPIb
DRX
RPOb
SVBATb
FSYNC
RESET
RPOb
SVBATb
FSYNC
RESET
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Symbol
Input/
Output
Description
Pin Number(s)
Si3220 Si3225
SVBATa,
SVBATb
I
O
I
Battery Sensing Input.
Analog current input used to sense battery voltage.
1, 16
2,15
1, 16
2,15
RPOa, RPOb
Transconductance Amplifier External Resistor Connec-
tion.
RPIa,
RPIb
Transconductance Amplifier External Resistor Connec-
tion.
3, 14
4, 13
3, 14
4, 13
RNIa,
RNIb
I
Transconductance Amplifier Resistor Connection.
RNOa, RNOb
O
Transconductance Amplifier Resistor Connection.
5, 12
6, 11
5, 12
6, 11
CAPPa,
CAPPb
Differential Capacitor.
Capacitor used in low-pass filter to stabilize SLIC feedback
loops.
CAPMa,
CAPMb
Common Mode Capacitor.
Capacitor used in low-pass filter to stabilize SLIC feedback
loops.
7, 10
8
7, 10
8
QGND
Component Reference Ground.
Return path for differential and common-mode capacitors. Do
not connect to system ground.
100
Rev. 1.2
Si3220/25
Symbol
Input/
Output
Description
Pin Number(s)
Si3220 Si3225
9
9
IREF
I
I
IREF Current Reference.
Connects to an external resistor to provide a highly-accurate
reference current. Return path for IREF resistor should be
routed to QGND pin.
17, 64
17, 64
STIPDCb,
STIPDCa
TIP Sense.
Analog current input senses dc voltage on TIP side of sub-
scriber loop.
18, 63
19, 62
18, 63 STIPACb, STI-
PACa
I
I
TIP Transmit Input.
Analog input senses ac voltage on TIP side of subscriber loop.
19, 62
20, 61
21, 60
22, 59
23, 58
SRINGACb,
SRINGACa
RING Transmit Input.
Analog input senses ac voltage on RING side of subscriber
loop.
20, 61
21, 60
22, 59
23, 58
SRINGDCb,
SRINGDCa
I
RING Sense.
Analog current input senses dc voltage on RING side of sub-
scriber loop.
ITIPNb,
ITIPNa
O
O
O
Negative TIP Current Control.
Analog current output provides dc current return path to V
from TIP side of the loop.
BAT
BAT
IRINGNb,
IRINGNa
Negative RING Current Control.
Analog current output provides dc current return path to V
from RING side of the loop.
ITIPPb,
ITIPPa
Positive TIP Current Control.
Analog current output drives dc current onto TIP side of sub-
scriber loop in normal polarity. Also modulates ac current onto
TIP side of loop.
24, 37,
42, 57
24, 37,
42, 57
V
V
,V
,
Supply Voltage.
Power supply for internal analog and digital circuitry. Connect
DD2 DD3
,V
DD4 DD1
all V pins to the same supply and decouple to adjacent GND
DD
pin as close to the pins as possible.
25, 38,
41, 56
25, 38,
41, 56
GND2,GND3,
GND4,GND1
Ground.
Ground connection for internal analog and digital circuitry.
Connect all pins to low-impedance ground plane.
26, 55
26, 55
IRINGPb,
IRINGPa
O
Positive RING Current Control.
Analog current output drives dc current onto RING side of sub-
scriber loop in reverse polarity. Also modulates ac current onto
RING side of loop.
27,54
27,54
THERMb,
THERMa
I
Temperature Sensor.
Senses Internal temperature of Si3200. Connect to THERM pin
of Si3200 or to V when using discrete linefeed circuit.
DD
29, 51
29, 51
TRD1b,
TRD1a
O
Test Relay Driver Output.
Drives test relays for connecting loop test equipment.
Rev. 1.2
101
Si3220/25
Symbol
Input/
Output
Description
Pin Number(s)
Si3220 Si3225
28, 52,
53
NC
No Internal Connection.
Leave unconnected or connect to ground plane.
28, 52
RTRPb,
RTRPa
I
External Ring Trip Sensing Input.
Used to sense ring-trip condition when using centralized ring
generator. Connect to low side of ring sense resistor.
30, 50
31, 48
30, 50
31, 48
TRD2b,
TRD2a
O
O
Test Relay Driver Output.
Drives test relays for connecting loop test equipment.
RRDb, RRDa
Ring Relay Driver Output.
Connects an external centralized ring generator to the sub-
scriber loop.
GPOb, GPOa
O
General Purpose Output Driver.
Used as a relay driver or as a second battery select pin when
using a third battery supply.
32, 49
35
32, 49
35
BATSELb,
BATSELa
O
I
Battery Voltage Select Pin.
Switches between high and low external battery supplies.
DRX
Receive PCM Data.
Input data from PCM/GCI bus.
36
36
DTX
O
I
Transmit PCM Data.
Output data to PCM/GCI bus.
39
39
PCLK
RESET
PCM Bus Clock.
Clock input for PCM/GCI bus timing.
33
33
I
Reset.
Active low. Hardware reset used to place all control registers in
a known state. An internal pulldown resistor asserts this pin low
when not driven externally.
34
40
34
40
FSYNC
INT
I
Frame Sync.
8 kHz frame synchronization signal for PCM/GCI bus. May be
short or long pulse format.
O
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed
operation.
43
44
45
43
44
45
SCLK
SDO
SDI
I
O
I
Serial Port Bit Clock Input.
Controls serial data on SDO and latches data on SDI.
Serial Port Data Out.
Serial port control data output.
Serial Port Data In.
Serial port control data input.
102
Rev. 1.2
Si3220/25
Symbol
Input/
Output
Description
Pin Number(s)
Si3220 Si3225
46
46
SDITHRU
O
Serial Data Daisy Chain.
Enables multiple devices to use a single CS for serial port con-
trol. Connect SDITHRU pin from master device to SDI pin of
slave device. An internal pullup resistor holds this pin high dur-
ing idle periods.
47
47
53
CS
I
I
Chip Select.
Active low. When inactive, SCLK and SDI are ignored, and
SDO is high impedance. When active, serial port is operational.
BLKRNG
Ring Generator Sensing Input.
Senses ring-trip condition when using centralized ring genera-
tor. Connect to high side of ring sense resistor. Shared by
channels a and b.
epad
epad
GND
Exposed Die Paddle Ground.
Connect to a low-impedance ground plane via top side PCB
pad directly under the part. See Package Outlines: 64-Pin
TQFP for PCB pad dimensions.
Rev. 1.2
103
Si3220/25
5. Pin Descriptions: Si3200
Si3200
16-Lead SOIC
(epad)
TIP
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ITIPP
ITIPN
RING
VBAT
VBATH
VBATL
GND
THERM
IRINGP
IRINGN
NC
NC
BATSEL
VDD
Pin #(s)
Symbol
TIP
Input/
Output
Description
TIP Output.
1
I/O
—
Connect to the TIP lead of the subscriber loop.
2, 10, 11
NC
No Internal Connection.
Do not connect to any electrical signal.
3
4
RING
VBAT
I/O
—
RING Output.
Connect to the RING lead of the subscriber loop.
Operating Battery Voltage.
Si3200 internal system battery supply. Connect SVBATa/b pin from Si3220/
25 and decouple with a 0.1 µF/100 V filter capacitor.
5
6
V
—
—
High Battery Voltage.
Connect to the system ringing battery supply. Decouple with a 0.1 µF/100 V
filter capacitor.
BATH
V
Low Battery Voltage.
BATL
Connect to lowest system battery supply for off-hook operation driving short
loops. An internal diode prevents leakage current when operating from
V
.
BATH
7
8
GND
VDD
—
—
Ground.
Connect to a low-impedance ground plane.
Supply Voltage.
Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply.
Decouple locally with a 0.1 µF/10 V capacitor.
9
BATSEL
I
Battery Voltage Select.
Connect to the BATSEL pin of the Si3220 or Si3225 through an external
resistor to enable automatic battery switching. No connection is required
when used with the Si3225 in a single battery system configuration.
104
Rev. 1.2
Si3220/25
Pin #(s)
12
Symbol
IRINGN
IRINGP
THERM
ITIPN
Input/
Output
Description
I
I
Negative RING Current Control.
Connect to the IRINGN lead of the Si3220 or Si3225.
13
Positive RING Current Drive.
Connect to the IRINGP lead of the Si3220 or Si3225.
14
O
I
Thermal Sensor.
Connect to THERM pin of Si3220 or Si3225.
15
Negative TIP Current Control.
Connect to the ITIPN lead of the Si3220 or Si3225.
16
ITIPP
I
Positive TIP Current Control.
Connect to the ITIPP lead of the Si3220 or Si3225.
epad
GND
Exposed Die Paddle Ground.
For adequate thermal management, the exposed die paddle should be sol-
dered to a PCB pad that is connected to low-impedance inner and/or back-
side ground planes using multiple vias. See “7. Package Outline: 16-Pin
ESOIC” for PCB pad dimensions.
Rev. 1.2
105
Si3220/25
6. Package Outline: 64-Pin TQFP
Figure 65 illustrates the package details for the Dual ProSLIC. Table 52 lists the values for the dimensions shown
in the illustration.
Figure 65. 64-Pin Thin Quad Flat Package (TQFP)
Table 52. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
—
Nom
—
Max
1.20
0.15
1.05
0.27
0.20
Min
Nom
0.50 BSC
0.60
—
Max
A
A1
e
0.05
0.95
0.17
0.09
—
L
0.45
—
0.75
0.20
0.20
0.08
0.08
7°
A2
1.00
aaa
bbb
ccc
ddd
Θ
b
0.22
—
—
c
—
—
—
D, E
D1, E1
D2, E2
Notes:
12.00 BSC
10.00 BSC
6.00
—
—
0°
3.5°
5.85
6.15
1. All dimensions are shown in millimeters unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. This package outline conforms to JEDEC MS-026, variant ACD-HD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020B specification for Small Body
Components.
106
Rev. 1.2
Si3220/25
7. Package Outline: 16-Pin ESOIC
Figure 66 illustrates the package details for the Si3200. Table 53 lists the values for the dimensions shown in the
illustration.
16
9
8
h
E
H
0.010
GAUGE PLANE
θ
1
L
B
Bottom Side
Exposed Pad
2.3 x 3.6 mm
Detail F
D
C
A
See Detail F
A1
e
γ
Seating Plane
Weight: Approximate device weight is 0.15 grams.
Figure 66. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package
Table 53. Package Diagram Dimensions
Millimeters
Symbol
Min
1.35
0
.33
.19
Max
1.75
0.15
.51
.25
10.00
4.00
A
A1
B
C
D
E
e
9.80
3.80
1.27 BSC
H
h
L
γ
θ
5.80
.25
.40
—
6.20
.50
1.27
0.10
8º
0º
Rev. 1.2
107
Si3220/25
8. Silicon Labs Si3220/25 Support Documentation
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
“AN39: Connecting the Si321x and Si322x ProSLIC to the W&G PCM-4”
“AN55: Dual ProSLIC User Guide”
“AN58: Si3220/Si3225 Programmer's Guide”
“AN63: Si322x Coefficient Generator User's Guide”
“AN64: Dual ProSLIC LINC User Guide”
“AN68: 8-Bit Microcontroller Board Hardware Reference Guide”
“AN73: Si3220/Si3225 System Demonstration Kit User's Guide”
“AN74: SiLINKPS-EVB User's Guide”
“AN75: Si322x Dual ProSLIC Demo PBX and GR-909 Testing Software Guide”
“AN86: Ringing / Ringtrip Operation and Architecture on the Si3220/Si3225”
“AN88: Dual ProSLIC Line Card Design”
“AN91: Si3200 Power Offload Circuit”
Si3220PPT0-EVB Data Sheet
Si3225PPT0-EVB Data Sheet
Note: Refer to www.silabs.com for a current list of support documents for this chipset.
108
Rev. 1.2
Si3220/25
9. Dual ProSLIC Selection Guide
Part Number
Description
On-Chip External
Pulse
Lead-Free/
RoHS
Compliant
Temp
Range
Package
Ringing
Ringing Metering
Support
o
Si3200-X-FS Linefeed interface
Si3200-X-GS Linefeed interface
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
0 to 70 C
SOIC-16
o
–40 to 85 C SOIC-16
o
Si3220-X-FQ
Si3220-X-GQ
Si3225-X-FQ
Si3225-X-GQ
Notes:
Dual ProSLIC
Dual ProSLIC
Dual ProSLIC
Dual ProSLIC
ꢁ
ꢁ
ꢁ
0 to 70 C
TQFP-64
o
ꢁ
–40 to 85 C TQFP-64
o
ꢁ
ꢁ
0 to 70 C
TQFP-64
o
–40 to 85 C TQFP-64
1. “X” denotes product revision.
2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
Table 54. Evaluation Kit Ordering Guide
Item
Supported Dual
ProSLIC
Description
Linefeed Interface
Si3220PPTX-EVB
Si3220PPT0-EVB
Si3220DCX-EVB
Si3220DC0-EVB
Si3225PPTX-EVB
Si3225PPT0-EVB
Si3225DCX-EVB
Si3225DC0-EVB
Si3220
Si3220
Si3220
Si3220
Si3225
Si3225
Si3225
Si3225
Eval Board, Daughter Card
Eval Board, Daughter Card
Daughter Card Only
Discrete
Si3200
Discrete
Si3200
Discrete
Si3200
Discrete
Si3200
Daughter Card Only
Eval Board, Daughter Card
Eval Board, Daughter Card
Daughter Card Only
Daughter Card Only
Rev. 1.2
109
Si3220/25
DOCUMENT CHANGE LIST
Revision 1.1 to Revision 1.2
ꢀ
Updated power supply characteristics in Table 3 and
Table 4.
ꢀ
Added note to Tables 15 and 16 to clarify SDO
and DTX pulldown requirements when multiple
Si3220/25s are connected to the same SPI or PCM
bus.
ꢀ
Updated "9. Dual ProSLIC Selection Guide" on page
109.
110
Rev. 1.2
Si3220/25
NOTES:
Rev. 1.2
111
Si3220/25
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: ProSLICinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, ISOmodem, and ProSLIC are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
112
Rev. 1.2
相关型号：
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