SI3227-A-FQ [SILICON]
SLIC, PQFP64, ROHS COMPLIANT, MS-026ACD, TQFP-64;
| 型号： | SI3227-A-FQ |
| 厂家： | 
SILICON |
| 描述： | SLIC, PQFP64, ROHS COMPLIANT, MS-026ACD, TQFP-64 CD 电信 电信集成电路 |
| 文件： | 总38页 (文件大小：669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3226/7
Si3208/9
DUAL PROSLIC® WITH DC-DC CONTROLLER
Features
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Performs all BORSCHT functions
Ideal for short- or long-loop applicationsꢀ On-hook transmission
Internal balanced or unbalanced ringingꢀ Loop or ground start operation
Low power consumption
ꢀ Low-power sleep mode
ꢀ Smooth polarity reversal
Software-programmable parameters: ꢀ DTMF generator/decoder
ꢁ Ringing frequency, amplitude,
cadence, and waveshape
ꢁ Two-wire ac impedance
ꢀ
ꢀ
A-Law/µ-Law companding,
linear PCM
PCM and SPI bus digital interfaces
with programmable interrupts
GCI/IOM-2 mode support
3.3 V operation
GR-909 loop diagnostics
Audio diagnostics with loopback
Pb-free/RoHS-compliant packaging
ꢁ Transhybrid balance
ꢁ DC current loop feed (10–45 mA)
ꢁ Loop closure and ring trip thresholds
ꢁ Ground key detect threshold
Integrated dc-dc controller
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Wideband CODEC (Si3227)
Applications
ꢀ
ꢀ
Customer Premises Equipment (CPE) ꢀ Private Branch Exchange (PBX)
Ordering Information
Optical Network Terminals (ONT)
ꢀ
Cable EMTAs, ATAs, VoIP
Gateways
See page 33.
Description
Patents pending
The Dual ProSLIC® is a family of low-voltage CMOS devices that integrate both
SLIC and CODEC functionality into a single IC. In combination with a linefeed IC
(LFIC), they provide a complete two-channel analog telephone interface in
accordance with all relevant LSSGR, ITU, and ETSI specifications. The Dual
ProSLIC devices (Si3226/7) operate from a single 3.3 V supply and interface to
standard PCM/SPI or GCI bus digital interfaces. The LFICs (Si3208/9) perform all
high-voltage functions and operate from a 3.3 V supply as well as high-voltage
battery supplies. The Si3208 is rated for –110 V, and the Si3209 is rated for –
135 V. The Dual ProSLIC devices are available in a 64-pin thin quad flat package
(TQFP), and the LFICs are available in a 40-pin, quad flat no-lead package
(QFN).
Functional Block Diagram
Si3226/7
Si32068/9
CODEC
SLIC
Linefeed
Control
PCM/
GCI
Interface
FSYNC
DRX
DTMF &
Tone Gen
TIP
ADC
DTX
Channel 1
RING
Caller ID
Linefeed
Monitor
CS
SDI
DAC
SPI
Control
Interface
Ringing
Generator
SDO
SCLK
INT
SLIC
Linefeed
Control
CODEC
DSP
TIP
Line Diagnostics
ADC
RST
Channel 2
RING
Linefeed
Monitor
DAC
PCLK
DC-DC Controllers
PLL
VBAT
DC-DC BOM
VDC
Preliminary Rev. 0.33 6/07
Copyright © 2007 by Silicon Laboratories
Si3226/7 Si3208/9
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si3226/7
Si3208/9
2
Preliminary Rev. 0.33
Si3226/7
Si3208/9
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.4. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.5. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.6. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.7. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.8. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.9. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.10. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.11. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.12. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.13. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.14. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.15. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.16. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.17. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.18. PCM Interface and Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.19. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.20. Metallic Loop Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Pin Descriptions: Si3226/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6. Pin Descriptions: Si3208/9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
9. Package Outline: 40-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Preliminary Rev. 0.33
3
Si3226/7
Si3208/9
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter
Symbol
Test Condition
Value
Unit
°C
Operating Temperature Range
Storage Temperature Range
T
–40 to 85
–55 to 150
A
T
°C
STG
2
Thermal Resistance, Typical
θ
25
1.6
32
°C/W
W
JA
TQFP-64
3
Continuous Power Dissipation
TQFP-64
P
T = 85 °C
A
D
2
Thermal Resistance, Typical
QFN-40
θ
°C/W
W
JA
4
Continuous Power Dissipation
QFN-40
P
T = 85 °C
1.7
D
A
Si3226/7
Supply Voltage
V
V
–0.5 to 4.0
–0.3 to 3.6
V
V
DD1 – DD4
Digital Input Voltage
V
IND
Si3208
Supply Voltage
V
–0.5 to 4.0
+0.4 to –110
+0.4 to –118
±100
V
V
DD
V
Continuous
BAT
5
Battery Supply Voltage
Pulse < 10 µs
V
TIP, RING Current
Supply Voltage
I
, I
mA
TIP RING
Si3209
V
–0.5 to 4.0
+0.4 to –135
+0.4 to –143
±100
V
V
DD
Continuous
5
High Battery Supply Voltage
V
BAT
Pulse < 10 µs
V
TIP, RING Current
I
, I
mA
TIP RING
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet.
2. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of at least equal size and that multiple vias are added to enable heat transfer between the top-side
copper surface and a large internal/bottom copper plane.
3. Operation of the Si3226 or Si3227 above 125 °C junction temperature may degrade device reliability.
4. Si3208 and Si3209 are equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction
temperature exceeds the thermal shutdown threshold. The thermal shutdown threshold should normally be set to 145
°C; when in the ringing state the thermal shutdown may be set to 200 °C. For optimal reliability long term operation of
the Si3208/Si3209 above 150 °C junction temperature should be avoided.
5. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.
4
Preliminary Rev. 0.33
Si3226/7
Si3208/9
Table 2. Recommended Operating Conditions
Parameter
Symbol
Test
Min*
Typ
Max*
Unit
Condition
o
Ambient Temperature
T
F-grade
G-grade
0
25
25
3.3
3.3
—
70
C
A
o
Ambient Temperature
T
–40
3.13
3.13
–9
85
C
A
Supply Voltage, Si3226/7
Supply Voltage, Si3208/Si3209
Battery Voltage, Si3208
Battery Voltage, Si3209
V
–V
3.47
3.47
–110
–135
V
V
V
V
DD1
DD4
V
DD
VBAT
VBAT
–9
—
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
Table 3. 3.3 V Power Supply Characteristics1
(VDD = 3.3 V, TA = 0 to 70 ºC for F-Grade, –40 to 85 ºC for G-Grade)
Parameter
High Impedance,
Symbol
Test Condition
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
2.4
0
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
V and V = Hi-Z
DD
T
R
Reset
RST = 0
I
I
I
I
I
I
I
I
VBAT
High Impedance,
Open Current
I
V and V = Hi-Z
9.7
0.6
15
DD
VBAT
T
R
Forward/Reverse Sleep,
On-hook Current
I
V
= –48 V
DD
TR
TR
1.2
24
VBAT
Forward/Reverse Active,
On-hook Current
I
V
= –48 V
DD
1.2
43
VBAT
Forward/Reverse Active,
Off-hook Current
I
I
= 30 mA
DD
LOOP
R
= 50 Ω
LOAD
3.1 + I
VBAT
LOOP
Forward/Reverse OHT,
On-hook Current
I
V
= –48 V
TR
43
1.6
DD
VBAT
Tip/Ring Open,
On-hook Current
I
V or V = –48 V
23
DD
T
R
V or V = Hi-Z
R
T
0.6
VBAT
Ringing Current
I
V
= 55 V
+ 0 V
DC
26
DD
TR
RMS
balanced, sinusoidal, f = 20 Hz
= 5 REN = 1400 Ω
2.3 + I
VBAT
AVE
R
LOAD
Notes:
1. All specifications are for a single channel of Si3226/7 using Si3208/9 linefeed IC and based on measurements with all
channels in the same operating state.
2. ILOOP is the dc current in the subscriber loop during the off-hook state.
3. IAVE is the average of the full-wave rectified current in the subscriber loop during ringing (IAVE = IPEAK x 2/π).
Preliminary Rev. 0.33
5
Si3226/7
Si3208/9
Table 4. AC Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Overload Level
Test Condition
Min
Typ
Max
Unit
TX/RX Performance
2.5
Figure 6
—
—
—
—
—
—
V
PK
Overload Compression
2-Wire – PCM
2-Wire – PCM or PCM – 2-Wire:
200 Hz to 3.4 kHz
1
Single Frequency Distortion
–65
dB
dB
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
—
—
—
–65
—
Signal-to-(Noise + Distortion)
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Figure 5
2
Ratio
Active off-hook, and OHT, any Z
T
Audio Tone Generator Signal-to-
Distortion Ratio
0 dBm0, Active off-hook, and
46
—
—
—
—
dB
dB
2
OHT, any Z
T
Intermodulation Distortion
–41
2
Gain Accuracy
2-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
V
– V
= 3.3 V ± 5%
DD4
–0.2
—
—
0.2
dB
—
DD1
Attenuation Distortion vs. Freq.
Group Delay vs. Frequency
0 dBm 0
See AN317
3
Gain Tracking
1014 Hz sine wave,
—
—
reference level –10 dBm
Signal level:
3 dB to –37 dB
—
—
—
—
—
—
0.25
0.5
dB
dB
dB
µs
–37 dB to –50 dB
–50 dB to –60 dB
—
1.0
Round-Trip Group Delay
1014 Hz, Within same time-slot
450
500
Crosstalk between channels
TX or RX to TX
0 dBm0,
300 Hz to 3.4 kHz
300 Hz to 3.4 kHz
—
—
26
26
—
—
30
30
–75
–75
—
dB
dB
dB
dB
TX or RX to RX
4
2-Wire Return Loss
200 Hz to 3.4 kHz
300 Hz to 3.4 kHz
4
Transhybrid Balance
—
Noise Performance
C-Message weighted
Psophometric weighted
RX and TX, dc to 3.4 kHz
5
Idle Channel Noise
—
—
40
8
12
–78
—
dBrnC
dBmP
dB
–80
—
PSRR from V
–V
DD4
DD1
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 Ω, ZS = 600 Ω synthesized using RS register
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
6
Preliminary Rev. 0.33
Si3226/7
Si3208/9
Table 4. AC Characteristics (Continued)
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
Longitudinal Performance
200 Hz to 1 kHz
Longitudinal to Metallic/PCM
Balance (forward or reverse)
58
53
40
60
58
—
—
—
—
dB
dB
dB
1 kHz to 3.4 kHz
Metallic/PCM to Longitudinal Bal-
ance
200 Hz to 3.4 kHz
Longitudinal Impedance
200 Hz to 3.4 kHz at TIP or RING
—
—
50
—
—
Ω
Longitudinal Current per Pin
Active off-hook
30
mA
200 Hz to 3.4 kHz
DC Current
Differential
Common Mode
—
—
—
—
—
—
45
30
45
mA
mA
mA
Differential + Common Mode
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 Ω, ZS = 600 Ω synthesized using RS register
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
Preliminary Rev. 0.33
7
Si3226/7
Si3208/9
Table 5. Linefeed Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
= 430 Ω
Min
Typ
Max
Unit
Maximum Loop Resistance
R
R
—
—
2000
Ω
LOOP
DC,MAX
I
= 18 mA, V
= –52V
LOOP
BAT
DC Loop Current Accuracy
I
= 18 mA
—
—
—
—
10
4
%
V
LIM
DC Open Circuit Voltage
Accuracy
Active Mode; V = 48 V,
OC
V
– V
TIP
RING
DC Differential Output
Resistance
R
I
< I
160
—
—
—
640
4
Ω
DO
LOOP
LIM
DC On-Hook Voltage
Accuracy—Ground Start
V
R
I
<I ; V wrt ground,
RING
V
OHTO
ROTO
RING LIM
V
= –51 V
RING
DC Output
Resistance—Ground Start
I
<I ; RING to ground
160
400
—
—
—
—
—
—
640
—
10
10
4
Ω
kΩ
%
RING LIM
DC Output Resistance—
Ground Start
R
TIP to ground
TOTO
Loop Closure Detect
Threshold Accuracy
I
I
= 13 mA
= 13 mA
THR
THR
Ground Key Detect
Threshold Accuracy
—
%
Ring Trip
AC detection,
—
mA
Threshold Accuracy
V
= 70 Vpk, no offset,
RING
I
= 80mA
TH
DC detection,
—
—
—
—
1
3
mA
mA
20 V dc offset, I = 13 mA
TH
DC Detection,
48 V DC offset, R
= 1500 Ω
loop
Ringing Amplitude
V
Open circuit, V
= –110 V
108
99
—
—
—
—
V
V
RING
BAT
PK
PK
5 REN load, R
= 0 Ω,
LOOP
V
= –110 V, R = 160 Ω
BAT
DO
Open Circuit, V
= –135 V
133
121
—
—
—
—
V
V
BAT
PK
PK
5 REN load, R
= 0 Ω,
LOOP
V
= –130 V, R = 160 Ω
BAT
DO
Sinusoidal Ringing Total
Harmonic Distortion
R
—
2
—
%
THD
Ringing Frequency Accuracy
Ringing Cadence Accuracy
Calibration Time
f = 16 Hz to 100 Hz
—
—
—
—
—
—
—
2
1
50
%
ms
ms
%
Accuracy of ON/OFF times
↑CAL to ↓CAL bit
TBD
4
Loop Voltage Sense
Accuracy
Accuracy of boundaries for
each output Code;
V
– V
= 48 V
TIP
RING
*Note: Ringing amplitude is set for 93 V peak and measured at TIP-RING using no series protection resistance.
8
Preliminary Rev. 0.33
Si3226/7
Si3208/9
Table 5. Linefeed Characteristics (Continued)
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Loop Current
Symbol
Test Condition
Min
Typ
Max
Unit
Accuracy of boundaries for
each output code;
—
7
10
%
Sense Accuracy
I
= 18 mA
LOOP
Power Alarm
Power Threshold = 300 mW
—
—
25
%
Threshold Accuracy
*Note: Ringing amplitude is set for 93 V peak and measured at TIP-RING using no series protection resistance.
Table 6. Monitor ADC Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Differential Nonlinearity
(8-bit resolution)
DNLE
—
—
1
LSB
Integral Nonlinearity
(8-bit resolution)
INLE
—
—
—
—
1
5
LSB
%
Gain Error
Table 7. Si3208/Si3209 Characteristics
(VDD = 3.13 to 3.47 V, VBAT = –15 to –130 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
– V (Forward)
Min
Typ Max Unit
TIP/RING Pull-down Transistor
Saturation Voltage
V
V
RING
V
CM
BAT
– V
(Reverse)
BAT
TIP
V
= 2.5 V
PK
AC
I
I
= 22 mA
= 60 mA
⎯
⎯
3
⎯
⎯
3.5
V
V
OUT
OUT
TIP/RING Pull-up Transistor
Saturation Voltage
V
GND – V
(Forward)
(Reverse)
OV
TIP
GND – V
RING
V
= 2.5 V
PK
AC
I
I
= 22 mA
= 60 mA
⎯
⎯
3
⎯
⎯
3.5
V
V
OUT
OUT
OPEN State TIP/RING Leakage Current
I
R = 0Ω
⎯
⎯
150
µA
LKG
L
Preliminary Rev. 0.33
9
Si3226/7
Si3208/9
Table 8. DC Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
Low Level Input Voltage
V
0.7 x V
—
—
—
—
5.25
0.3 x V
—
V
V
V
IH
DD
V
IL
DD
High Level Output
Voltage
V
I = 4 mA
V
– 0.6
DD
OH
O
Low Level Output
Voltage
V
DTX, SDO, INT,
SDITHRU:
—
—
0.4
V
OL
I = –4 mA
O
GPIO1 a/b, GPIO2 a/b:
—
35
—
—
—
—
50
63
11
—
0.72
—
I = –40 mA
O
SDITHRU internal pullup
resistance
kΩ
Ω
Relay Driver Source
Impedance
R
V
V
–V = 3.13 V
DD4
IO < 28 mA
—
OUT
DD1
Relay Driver Sink
Impedance
R
–V = 3.13 V
—
Ω
IN
L
DD1
DD4
IO < 85 mA
Input Leakage Current
I
10
µA
Table 9. Switching Characteristics—General Inputs1
(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)
Parameter
Rise Time, RESET
RESET Pulse Width, GCI Mode
Symbol
Min
—
Typ
—
Max
Unit
t
5
ns
µs
µs
r
2,3
t
t
33/PCLK
33/PCLK
—
—
—
rl
rl
3
RESET Pulse Width, SPI Daisy Chain Mode
—
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VDD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 kΩ per device.
3. The minimum RESET pulse width is 33/PCLK frequency (i.e. 33/8.192 MHz = 4 µs).
10
Preliminary Rev. 0.33
Si3226/7
Si3208/9
Table 10. Switching Characteristics—SPI
(VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)
Parameter
Cycle Time SCLK
Symbol
Test Conditions
Min
62
—
Typ
—
Max
—
Unit
ns
t
c
Rise Time, SCLK
t
—
25
ns
r
Fall Time, SCLK
t
—
—
25
ns
f
Delay Time, SCLK Fall to SDO Active
t
—
—
20
ns
d1
d2
Delay Time, SCLK Fall to SDO
Transition
t
t
—
—
20
ns
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
—
25
20
25
20
220
—
—
—
—
—
—
—
4
20
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
d3
t
su1
Hold Time, CS to SCLK Rise
t
h1
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time between Chip Selects
SDI to SDITHRU Propagation Delay
t
su2
t
h2
t
cs
t
d4
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V
tc
tr
tf
SCLK
CS
tsu1
th1
tcs
tsu2
th2
SDI
td1
td3
td2
SDO
td4
SDITHRU
Figure 1. SPI Timing Diagram
Preliminary Rev. 0.33
11
Si3226/7
Si3208/9
Table 11. Switching Characteristics—PCM Highway Interface
(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)
1
1
1
Parameter
Symbol
Test
Conditions
Units
Min
Typ
Max
PCLK Period
t
122
—
3906
ns
p
Valid PCLK Inputs
—
—
—
—
—
—
—
—
512
768
—
—
—
—
—
—
—
—
kHz
kHz
1.024
1.536
1.544
2.048
4.096
8.192
MHz
MHz
MHz
MHz
MHz
MHz
2
FSYNC Period
t
—
40
—
—
—
—
—
125
50
—
—
60
µs
%
fs
PCLK Duty Cycle Tolerance
FSYNC Jitter Tolerance
Rise Time, PCLK
t
dty
t
±120
25
ns
ns
ns
ns
ns
jitter
t
—
r
Fall Time, PCLK
t
—
25
f
Delay Time, PCLK Rise to DTX Active
t
t
—
20
d1
d2
Delay Time, PCLK Rise to DTX
Transition
—
20
Delay Time, PCLK Rise to DTX
Tristate
t
—
—
20
ns
d3
3
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
FSYNC Pulse Width
t
25
20
25
20
—
—
—
—
—
—
—
ns
ns
ns
ns
su1
t
h1
t
—
su2
t
—
h2
t
t
125 µs–t
p
wfs
p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O – 0.4 V, VIL = 0.4 V.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Spec applies to PCLK fall to DTX tristate when that mode is selected.
12
Preliminary Rev. 0.33
Si3226/7
Si3208/9
tr
tf
tp
PCLK
th1
twfs
tsu1
tfs
FSYNC
tsu2
th2
DRX
DTX
td2
td1
td3
Figure 2. PCM Highway Interface Timing Diagram
Table 12. Switching Characteristics—GCI Highway Serial Interface
(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
1
Symbol
Test
Conditions
Min
Typ
Max
Units
Parameter
PCLK Period (2.048 MHz PCLK Mode)
PCLK Period (4.096 MHz PCLK Mode)
t
t
—
—
—
40
—
—
—
—
—
—
25
20
25
20
488
244
125
50
—
—
—
ns
ns
µs
%
p
p
2
FSYNC Period
t
—
fs
PCLK Duty Cycle Tolerance
FSYNC Jitter Tolerance
t
60
±120
25
25
20
20
20
—
dty
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
jitter
Rise Time, PCLK
t
—
r
Fall Time, PCLK
t
—
f
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
t
t
t
—
d1
d2
d3
—
3
Delay Time, PCLK Rise to DTX Tristate
—
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
FSYNC Pulse Width
t
—
su1
t
—
—
h1
t
—
—
su2
t
—
—
h2
t
t /2
—
—
wfs
p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V and VIL = 0.4 V.
Rise and fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
Preliminary Rev. 0.33
13
Si3226/7
Si3208/9
tr
tf
tp
PCLK
th1
tsu1
tfs
FSYNC
tsu2
th2
Frame 0,
Bit 0
DRX
DTX
td1
td2
td3
Frame 0,
Bit 0
Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)
tr
tf
tc
PCLK
th1
tfs
tsu1
FSYNC
tsu2
th2
Frame 0,
Bit 0
DRX
DTX
td1
td3
td2
Frame 0,
Bit 0
Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode)
14
Preliminary Rev. 0.33
Si3226/7
Si3208/9
Acceptable
Figure 5. Transmit and Receive Path SNDR
9
8
7
6
5
4
Fundamental
Output Power
(dBm0)
Acceptable
Region
3
2.6
2
1
0
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
Figure 6. Overload Compression Performance
Preliminary Rev. 0.33
15
Si3226/7
Si3208/9
2. Typical Application Circuits
V B R N G
V B A T
R B N V G
V B A T b
V B R N G
R B N V G
E G N D
E G N D
V B A T
V B A T a
b
a
V B A T
V B A T
V C C
V B A T b
V B A T a
V C
D
G N
C
V D D R E G
V D D A
N D G D
N D G A
D V D A
V D D D
V D D C
S V D C
D V D D
D V D C
D
G N
D
G N
16
Preliminary Rev. 0.33
Si3226/7
Si3208/9
4
3
6
1
Preliminary Rev. 0.33
17
Si3226/7
Si3208/9
4
3
6
1
18
Preliminary Rev. 0.33
Si3226/7
Si3208/9
V D D
N D D G
A G N D
V B A T a
V B A T b
_ 1
_ 2
V B A T
V B A T
Preliminary Rev. 0.33
19
Si3226/7
Si3208/9
20
Preliminary Rev. 0.33
Si3226/7
Si3208/9
Preliminary Rev. 0.33
21
Si3226/7
Si3208/9
22
Preliminary Rev. 0.33
Si3226/7
Si3208/9
Preliminary Rev. 0.33
23
Si3226/7
Si3208/9
24
Preliminary Rev. 0.33
Si3226/7
Si3208/9
When in the active state, each ProSLIC channel
operates in one of three dc linefeed operating regions: a
4. Functional Description
®
The Dual ProSLIC chipset includes the Si3226/7 low- constant-voltage region, a constant-current region, or a
voltage IC and the Si3208/9 high-voltage linefeed IC. resistive region, as shown in Figure 11. The constant-
The Dual ProSLIC provides all SLIC, codec, DTMF voltage region has a low resistance, typically 160 Ω.
detection, and signal generation functions needed for The constant-current region approximates infinite
two complete analog telephone interfaces. The Dual resistance.
ProSLIC performs all battery, over-voltage, ringing,
I_ILIM
supervision, codec, hybrid, and test (BORSCHT)
functions; it also supports extensive metallic loop testing
capabilities.
I_RFEED
I_VLIM
ILOOP (mA)
The Si3226 provides a standard voice-band (200 Hz–
3.4 kHz) audio codec. The Si3227 provides an audio
CODEC with both wideband (50 Hz–7 kHz) and
standard voice-band (200 Hz– 3.4 kHz) modes. The
wideband mode provides an expanded audio band with
a 16 kHz sample rate for enhanced audio quality while
the standard voice-band mode provides standard
telephony audio compatibility. The Si3226/7 provides
two independent, programmable, dc-dc converter
controllers, each of which reacts to line conditions to
provide the optimal battery voltage required for each
line-state.
V_ILIM
Resistive Region
V_RFEED
V_VLIM
Constant V Region
VTR(V)
Figure 11. Dual ProSLIC DC Feed
Characteristics
The linefeed chips (Si3208/9) provide programmable
on-hook voltage, programmable off-hook loop current,
reverse battery operation, loop or ground start
operation, and on-hook transmission. Loop current and
voltage are continuously monitored using an A/D
converter in the Si3226/7. The Si3208 supports battery
voltages up to 110 V, sufficient for most ringing signals.
The Si3209 supports battery voltages up to 130 V for
higher-voltage ringing applications.
4.2. Linefeed Operating States
The linefeed interface includes eight different register-
programmable operating states as listed in Table 16.
The Open state is the default condition in the absence
of any preloaded register settings. The device may also
automatically enter the open state in the event of a
linefeed fault condition.
The Dual ProSLIC supports balanced 5 REN ringing
with or without a programmable dc offset. The available
offset, frequency, waveshape, and cadence options are
designed to ring the widest variety of terminal devices
and to reduce external controller requirements.
4.3. Line Voltage and Current Monitoring
The Dual ProSLIC continuously monitors the TIP, RING,
and battery voltages and currents via an on-chip ADC
and stores the resulting values in individual register
addresses. Additionally, the loop voltage (V –V
),
A complete audio transmit and receive path is
integrated, including ac impedance and hybrid gain.
These features are software-programmable, allowing a
single hardware design to meet global requirements.
Digital voice data transfer occurs over a standard PCM
bus. Control data is transferred using a standard SPI.
TIP
RING
loop current, and longitudinal current values are
calculated based on the TIP and RING measurements
and are stored in unique register locations for further
processing. The ADC updates all registers at a rate of
2 kHz or greater.
The Si3226/7 is available in a 64-pin TQFP; the Si3208
is available in a 32-pin QFN, and the Si3209 is available
in a 40-pin QFN or a 48-pin eTQFP.
4.4. Power Monitoring and Power Fault
Detection
The Dual ProSLIC's line monitoring functions are used
to continuously protect the linefeed IC (LFIC) against
excessive power conditions. The LFIC contains an on-
chip, analog sensing diode that provides real-time
temperature data to the Si3226/7 and turns off the LFIC
when a preset threshold is exceeded. The LFIC status
is reflected in a Si3226/7 register bit.
4.1. DC Feed Characteristics
Dual ProSLIC internal linefeed circuitry provides
completely programmable dc feed characteristics.
Linefeed characteristics for each channel are
independently configurable.
Preliminary Rev. 0.33
25
Si3226/7
Si3208/9
If the Si3226/7 detects a fault condition or overpower
condition on any channel, it automatically sets that
channel to the open state and generates a "power
alarm" interrupt. The interrupt can be masked, but the
automatic transition to open cannot be masked. The
various power alarms and linefeed faults supporting
automatic intervention are described below.
4.5. Thermal Overload Shutdown
If the LFIC die temperature exceeds the maximum
junction temperature threshold, TJmax, of 145 °C or
200 ºC or other programmed temperature threshold
range, the LFIC has the ability to shut itself down to a
low-power state without any assistance from the
Si3226/7. The thermal shutdown circuit contains a
sufficient amount of hysteresis and/or turn-on delay time
1. LFIC total power exceeded.
2. Power exceeded in one or more transistors of a LFIC so as to remain shut down during a power cross event,
internal transistor group (if capable of measuring
individual power consumption).
where 50 Hz or 60 Hz, 600 V, is connected to TIP and/
or RING.
3. Excessive foreign current or voltage on TIP and/or
RING.
4. LFIC thermal shutdown event; this event is
automatically performed, and no intervention by the
Si3226/7 is required.
Table 16. Linefeed Operating States
Linefeed State
Description
Open
Output is high-impedance, and all line supervision functions are powered down. Audio is
powered down. This is the default state after powerup or following a hardware reset. This
state can also be used in the presence of line fault conditions and to generate open switch
intervals (OSIs). This state is used in line diagnostics mode as a high-Z state during line-
feed testing. A power fault condition may also force the device into the open state.
Forward Active
Reverse Active
Linefeed circuitry and audio are active. In Forward Active state, the TIP lead is more posi-
tive than the RING lead; in Reverse Active state, the RING lead is more positive than the
TIP lead. Loop closure and ground key detect circuitry are active.
Forward OHT
Reverse OHT
Provides data transmission during an on-hook loop condition (e.g., transmitting caller ID
data between ringing bursts). Linefeed circuitry and audio are active. In Forward OHT
state, the TIP lead is more positive than the RING lead; in Reverse OHT state, the RING
lead is more positive than the TIP lead.
TIP Open
Provides an active linefeed on the RING lead and sets the TIP lead to high impedance
(>400 kΩ) for ground start operation in forward polarity. Loop closure and ground key
detect circuitry are active.
RING Open
Provides an active linefeed on the TIP lead and sets the RING lead to high impedance
(>400 kΩ) for ground start operation in reverse polarity. Loop closure and ground key
detect circuitry are active.
Ringing
Drives programmable ringing signal onto TIP and RING leads with or without dc offset.
Line Diagnostics
The channel selected is put into diagnostic mode. In this mode, the selected channel has
special diagnostic resources available.
4.6. Power Dissipation Considerations
4.7. Loop Closure Detection
The Dual ProSLIC is designed to source loops up to The Dual ProSLIC provides a completely programmable
20 kft as well as short loop applications. The LFIC loop closure detection mechanism. The loop closure
provides all battery sourcing functions and is, therefore, detection scheme provides two unique thresholds to
the determining factor regarding power dissipation in a allow hysteresis, and also includes a programmable
specific application. The Dual ProSLIC provides an on- debounce filter to eliminate false detection. A loop
chip dc-dc controller that can dynamically reduce the closure detect status bit provides continuous status, and
battery supply to ideally match the required line feed a maskable interrupt bit is also provided.
voltage.
26
Preliminary Rev. 0.33
Si3226/7
Si3208/9
4.8. Ground Key Detection
4.13. Tone Generators
The Dual ProSLIC includes two digital tone generators
that allow a wide variety of single- or dual-tone
frequency and amplitude combinations. Each tone
generator has its own set of registers that hold the
desired frequency, amplitude, and cadence to allow
generation of DTMF and call progress tones for different
requirements. The tones can be directed to either
receive or transmit paths.
The Dual ProSLIC provides a ground key detect
mechanism using a programmable architecture similar
to the loop closure scheme. The ground key detect
scheme provides two unique thresholds to allow
hysteresis and also includes a programmable debounce
filter to eliminate false detection. A ground key detect
status bit provides continuous status, and a maskable
interrupt bit is also provided.
4.14. DTMF Detection
4.9. Ringing Generation
In DTMF, two tones generate a DTMF digit. One tone is
chosen from the four possible row tones, and one tone
is chosen from the four possible column tones. The sum
of these tones constitutes one of 16 possible DTMF
digits. The Dual ProSLIC performs DTMF detection
using an algorithm to compute the DFT for each of the
eight DTMF frequencies and their second harmonics. At
the end of the DFT computation, the squared
magnitudes of the DFT results for the 8 DTMF
fundamental tones are computed. The row and column
results are sorted to determine the strongest tones, and
checks are made to determine if the strongest row and
column tones constitute a DTMF digit.
The Dual ProSLIC provides the ability to generate a
programmable sinusoidal or trapezoidal ringing
waveform, with or without dc offset. The ringing
frequency, wave shape, cadence, and offset are all
register-programmable. Using
a
balanced ringing
scheme, the ringing signal is applied to both the TIP and
RING leads using dual ringing waveforms that are 180°
out of phase with each other. The resulting ringing
signal seen across TIP-RING is twice the amplitude of
the ringing waveform on either the TIP or RING lead,
which allows the ringing circuitry to be forced to
withstand only half the total ringing amplitude seen
across TIP-RING.
4.15. DC-DC Controller
4.10. Polarity Reversal
The controller converts a single positive dc input voltage
into an independent negative battery voltage for each
channel. The controller operates a dc-dc converter
circuit that converts a single positive dc input voltage
into an independent negative battery voltage for each
channel. In addition to eliminating external high-voltage
power supplies, the dc-dc controller allows the Dual
ProSLIC to dynamically control the battery voltage to
the minimum required for any given operating state
according to the programmed linefeed parameters.
The Dual ProSLIC supports polarity reversal for
message waiting and various other signaling modes.
The ramp rate can be programmed for a smooth or
abrupt transition to accommodate different application
requirements.
4.11. Two-Wire Impedance Synthesis
The ac two-wire impedance synthesis is generated on-
chip using a DSP-based scheme to optimally match the
output impedance of the Dual ProSLIC to the
impedance of the subscriber loop and minimize the
receive path signal reflected back onto the transmit
path. Most real or complex two-wire impedances can be
generated by using the coefficient generator software to
simulate the desired line conditions and generate the
required register coefficients.
4.16. Wideband Audio
The Si3226 supports a narrowband (200 Hz–3.4 kHz)
audio codec. The Si3227 supports
a software-
selectable wideband (50 Hz–7 kHz) and narrowband
(200 Hz–3.4 kHz) audio codec. The Si3227 wideband
mode provides an expanded audio band at a 16-bit,
16 kHz sample rate for enhanced audio quality while
maintaining standard telephony audio compatibility.
Wideband audio samples are transmitted and received
on the PCM interface using two consecutive 8 kHz
frames.
4.12. Transhybrid Balance Filter
The trans-hybrid balance function is implemented on-
chip using a DSP-based scheme to effectively cancel
the reflected receive path signal from the transmit path.
The coefficient generator software is used to optimize
the filter coefficients.
Preliminary Rev. 0.33
27
Si3226/7
Si3208/9
4.17. SPI Control Interface
4.20. Metallic Loop Testing
The controller interface to the Dual ProSLIC is a 4-wire
interface modeled after microcontroller and serial
peripheral devices. The interface consists of a clock
(SCLK), chip select (CS), serial data input (SDI), and
serial data output (SDO). In addition, the Dual ProSLIC
devices feature a serial data through output (SDITHRU)
to support operation of up to eight devices (up to 16
channels) using a single chip select line. The device
operates with both 8-bit and 16-bit SPI controllers.
The Dual ProSLIC includes the ability to detect multiple
fault conditions within the line card as well as on the T/R
pair.
1. Hazardous Potential Test—This test checks for ac
voltage >50 V
or dc voltage >135 V on T-G or R-
rms
G. If a hazardous voltage is encountered, test access
MUST release within two seconds of the time when it
was initiated using a preset threshold.
2. Foreign ElectroMotive Force Test—Checks T-G or
4.18. PCM Interface and Companding
R-G for ac voltage >10 V , dc voltage >6 V. Uses
rms
same threshold as for hazardous voltage test.
The Dual ProSLIC contains a flexible, programmable
interface for the transmission and reception of digital
PCM samples. PCM data transfer is controlled by the
PCM clock (PCLK) and frame sync (FSYNC) inputs as
well as the PCM Mode Select, PCM Transmit Start, and
PCM Receive Start settings.
3. Resistive Faults Test—Checks for dc resistance from
T-R, T-G or R-G. Any measurement <150 kΩ is
considered a resistive fault.
4. Receiver-Off-Hook Test—Distinguishes between a
T-R resistive fault and an off-hook condition.
The interface can be configured to support from four to
128 8-bit time slots in each 125 µs frame,
corresponding to a PCM clock (PCLK) frequency range
of 256 kHz to 8.192 MHz. 1.544 MHz is also supported.
5. Ringers Test—Checks for the presence of REN
across T-R. Result are >0.175REN and <5REN for a
valid load.
6. AC Line Impedance (line length)—T-R, T-G, and
R-G. Generate a tone at several specific frequencies
(audio band) and measure the reflected signal
amplitude (complex spectrum) that comes back (with
transhybrid balance filter disabled). The reflected
signal is then used to calculate the line impedance
based on certain assumptions of wire gauge, etc.
The Dual ProSLIC supports both µ-255 Law (µ-Law)
and A-law companding formats in addition to 16-bit
linear data mode with no companding.
4.19. General Circuit Interface
The
Dual
ProSLIC
supports
an
alternative
communication interface to the SPI and PCM control
and data interface. The General Circuit Interface (GCI)
is used for transmission and reception of both control
and data information onto a GCI bus. The PCM and GCI
interfaces are both 4-wire interfaces and share the
same pins. In GCI mode, the four-wire SPI control
interface is used as hard-wired channel selector pins.
The selection between PCM and GCI modes is
performed when coming out of reset using the
SDITHRU pin.
7. Line Capacitance—T-R, T-G, R-G. Generate a linear
ramp function with polarity reversal, and measure
the time constant.
8. Ringer Capacitance—This test uses the same
procedure as the ringer test above but also
measures the V/I phase relationship of the received
signal (dc path) and then subtracts the delay to
calculate the ringer capacitance.
9. Ringing Voltage Verification—Uses current voltage
sensing capability.
10.Test-In Diagnostics—The Dual ProSLIC can switch
in a preset load impedance to test the SLIC/codec
functionality using a known set of conditions.
28
Preliminary Rev. 0.33
Si3226/7
Si3208/9
5. Pin Descriptions: Si3226/7
Table 17. Si3226/7 Pin Descriptions
Pin
Symbol
I/O
Description
Number
1
2
SRINGDCa
SRINGACa
STIPACa
I
RING DC Sense Input.
RING AC Sense Input.
TIP AC Sense Input.
TIP DC Sense Input.
I
I
3
4
STIPDCa
CAPPa
I
5
I/O
I/O
I
Metallic Loop Filter Capacitor-Positive Terminal.
Metallic Loop Filter Capacitor-Negative Terminal.
Battery Sensing Input.
6
CAPMa
7
SVBATa
8
SVDC
I
DC-DC Input Power Rail Sensor.
9
GPIO3a / PWROa
I/O
I/O
General Purpose I/O / Power Offloading Output.
10
GPIO2a / SRINGCa /
TRD2a
General Purpose I/O / TIP Course Sense Input / Test Relay
Driver.
11
GPIO1a / STIPCa / TRD1a
I/O
General Purpose I/O / TIP Course Sense Input / Test Relay
Driver.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CS
I
Chip Select Input.
FSYNC
SDI
I
Frame Sync Clock Input.
I
Serial Port Data Input.
HVCLKa
SCLK
O
Line-Driver IC Clock Output.
Serial Port Bit Clock Input.
Line-Driver IC Data Output
Serial Data Daisy Chain Output.
Serial Port Data Output.
I
HVDATA
SDITHRU
SDO
O
O
O
DCFFa
SDCHa
SDCLa
DCDRVa
VDDC
I/O
DC-DC BJT Drive Monitor.
DC-DC Current Monitor Input-High Terminal.
DC-DC Current Monitor Input-Low Terminal.
DC-DC Drive Output.
I
I
I/O
PWR
O
DC-DC Switch Driver Power Supply.
DC-DC Drive Output.
DCDRVb
SDCLb
SDCHb
DCFFb
GNDD
VDDD
I
DC-DC Current Monitor Input-Low Terminal.
DC-DC Current Monitor Input-High Terminal.
DC-DC BJT Drive Monitor.
Digital Ground.
I
I/O
GND
PWR
I
Digital Supply Voltage.
PCLK
PCM Bus Clock Input.
HVCLKb
O
Line-Driver IC Clock Output.
Preliminary Rev. 0.33
29
Si3226/7
Si3208/9
Table 17. Si3226/7 Pin Descriptions (Continued)
Pin
Symbol
I/O
Description
Number
33
34
35
36
37
38
DTXEN
DTX
O
O
I
Transmit PCM Enable Output.
Transmit PCM Data Output.
Receive PCM Data Input.
Interrupt Output.
DRX
INT
O
I
RST
Reset Input.
VDDREG
I/O
I/O
Regulated Core Power Supply.
39
GPIO1b / STIPCb / TRD1b
General Purpose I/O / TIP Course Sense Input / Test Relay
Driver.
40
GPIO2b / SRINGCb /
TRD2b
I/O
General Purpose I/O / TIP Course Sense Input / Test Relay
Driver.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GPIO3b / PWROb
SVBATb
CAPMb
CAPPb
STIPDCb
STIPACb
SRINGACb
SRINGDCb
DRINGb
URINGb
DTIPb
I/O
General Purpose I/O / Power Offloading Output.
Battery Sensing Input.
I
I/O
I/O
I
Differential Loop Filter Capacitor-Negative Term.
Differential Loop Filter Capacitor-Positive Term.
TIP DC Sense Input.
I
TIP AC Sense Input.
I
RING AC Sense Input.
I
RING DC Sense Input.
O
RING Pull-Down Current Driver Output.
RING Pull-Up Current Driver Output.
TIP Pull-Down Current Driver Output.
TIP Pull-Up Current Driver Output.
Line Driver IC Bias Current Output.
Longitudinal Balance Calibration Capacitor.
Current Reference Input.
O
O
UTIPb
O
IBIASb
O
CAPLB
IREF
O
I
QGND
I
Quiet Ground Reference Input.
Analog Ground.
GNDA
GND
PWR
I/O
O
VDDA
Analog Supply Voltage.
ISNS
Line Current Sense Input.
IBIASa
Line Driver IC Bias Current Output.
TIP Pull-Up Current Driver Output.
TIP Pull-Down Current Driver Output.
RING Pull-Up Current Driver Output.
RING Pull-Down Current Driver Output.
UTIPa
O
DTIPa
O
URINGa
DRINGa
O
O
30
Preliminary Rev. 0.33
Si3226/7
Si3208/9
6. Pin Descriptions: Si3208/9
Table 18. Si3208/9 Pin Descriptions
QFN Pin #
1
Symbol
IC
I/O
Description
Internal connection; leave to float.
No Connect.
2
NC
3
RING_1
NC
I/O
I/O
Ring Channel 1 Input/Output.
No Connect.
4
5
TIP_1
NC
Tip Channel 1 Input/Output.
6
No Connect.
7
IC
Internal connection; leave to float.
Negative Ring Current Control Channel 1 Input.
Positive Ring Current Control Channel 1 Input.
Negative Tip Current Control Channel 1 Input.
Positive Tip Current Control Channel 1 Input.
Current Bias Channel 1 Input.
Current Sense Output.
8
IRINGN_1
IRINGP_1
ITIPN_1
ITIPP_1
IBIAS_1
ISNS
I
9
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I
I
I
O
VDD
I
IC Supply Voltage Input.
HVCLK_1
HVDATA
HVCLK_2
DGND
IBIAS_2
ITIPP_2
ITIPN_2
IRINGP_2
IRINGN_2
IC
I
High-Voltage IC Clock Channel 1 Input.
High-Voltage IC Data Input/Output.
High-Voltage IC Clock Channel 2 Input.
Digital Ground.
I/O
I
I
I
I
I
I
I
Current Bias Channel 2 Input.
Positive Tip Current Control Channel 1 Input.
Negative Tip Current Control Channel 2 Input.
Positive Ring Current Control Channel 2 Input.
Negative Ring Current Control Channel 2 Input.
Internal connection; leave to float.
No Connect.
NC
TIP_2
NC
I/O
I/O
Tip Channel 2 Input/Output.
No Connect.
RING_2
NC
Ring Channel 2 Input/Output.
No Connect.
IC
Internal connection; leave to float.
Internal connection; leave to float.
Operating Battery Voltage Channel 2 Input.
No Connect.
IC
VBAT_2
NC
I
IC
Internal connection; leave to float.
Preliminary Rev. 0.33
31
Si3226/7
Si3208/9
Table 18. Si3208/9 Pin Descriptions (Continued)
QFN Pin #
Symbol
NC
I/O
Description
35
36
No Connect.
AGND
IC
I
Analog Ground.
37
Internal connection; leave to float.
Internal connection; leave to float.
Operating Battery Voltage Channel 1 Input.
Internal connection; leave to float.
38
IC
39
VBAT_1
IC
I
40
epad
Exposed Die Attach Paddle.
For adequate thermal management, the exposed die paddle
should be soldered to a printed circuit board pad that is connected
to an electrically-isolated low-impedance inner layer and/or back-
side thermal plane(s) using multiple thermal vias. Do not connect
this pad to ground.
32
Preliminary Rev. 0.33
Si3226/7
Si3208/9
7. Ordering Guide
Device
Description
Wideband
Audio
Package
Temp Range
Si3226-X-FQ
Si3226-X-GQ
Si3227-X-FQ
Si3227-X-GQ
Si3208-X-FM
Si3208-X-GM
Si3209-X-FM
Si3209-X-GM
Notes:
Dual ProSLIC
Dual ProSLIC
No
No
Yes
Yes
—
TQFP-64
TQFP-64
TQFP-64
TQFP-64
QFN-40
QFN-40
QFN-40
QFN-40
0 to 70 °C
–40 to 85 °C
0 to 70 °C
Dual ProSLIC
Dual ProSLIC
–40 to 85 °C
0 to 70 °C
110 V Dual LFIC
110 V Dual LFIC
135 V Dual LFIC
135 V Dual LFIC
—
–40 to 85 °C
0 to 70 °C
—
—
–40 to 85 °C
1. All devices are lead-free and RoHS compliant.
2. “X” denotes product revision (A, B, C, etc.).
3. Add an R at the end of the device to denote tape and reel options.
Preliminary Rev. 0.33
33
Si3226/7
Si3208/9
8. Package Outline: 64-Pin TQFP
Figure 12 illustrates the package details for the Si3226/7. Table 19 lists the values for the dimensions shown in the
illustration.
Figure 12. 64-Pin Thin Quad Flat Package (TQFP)
34
Preliminary Rev. 0.33
Si3226/7
Si3208/9
Table 19. 64-Pin TQFP Package Dimensions
Dimension
Min
—
Nom
Max
1.20
0.15
1.05
0.27
0.20
A
A1
A2
b
—
0.05
0.95
0.17
0.09
—
1.00
0.22
c
—
D
12.00 BSC.
10.00 BSC.
0.50 BSC.
12.00 BSC.
10.00 BSC.
0.60
D1
e
E
E1
L
0.45
—
0.75
0.20
0.20
0.08
0.08
7°
aaa
bbb
ccc
ddd
Q
—
—
—
—
—
—
—
0°
3.5°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant ACD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for small body components.
Preliminary Rev. 0.33
35
Si3226/7
Si3208/9
9. Package Outline: 40-Pin QFN
Figure 13 illustrates the package details for the Si3208/9. Table 20 lists the values for the dimensions shown in the
illustration.
Figure 13. 40-Pin QFN Package
Table 20. 40-Pin QFN Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.90
Max
1.00
0.05
0.30
Dimension
Min
4.10
0.30
0.03
—
Nom
4.30
0.40
0.05
—
Max
4.40
0.50
0.08
0.10
0.10
0.08
0.10
A
E2
L
A1
0.02
b
0.25
L1
D
6.00 BSC.
4.30
aaa
bbb
ccc
ddd
D2
4.10
4.40
—
—
e
E
0.50 BSC.
6.00 BSC.
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD-2.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for small body components.
36
Preliminary Rev. 0.33
Si3226/7
Si3208/9
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.32
ꢀ Added Si3208 and Si3209.
ꢀ Removed Si3203, Si3205, and Si3206.
ꢀ Added pin-outs and package drawings for Si3208
and Si3209.
ꢀ Updated pin-out for Si3226.
ꢀ Updated bill of materials.
ꢀ Updated “2. Typical Application Circuits” and added
dc-dc converter schematics.
ꢀ Updated tables.
Revision 0.32 to Revision 0.33
ꢀ Changed package type for Si3208.
ꢀ Deleted QFN-32 drawing.
ꢀ Updated dc-dc converter schematic.
ꢀ Updated bills of materials.
ꢀ Updated max V
values.
BAT
ꢀ Updated thermal shutdown thresholds.
ꢀ Updated Si3208/9 pin descriptions.
Preliminary Rev. 0.33
37
Si3226/7
Si3208/9
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: ProSLICinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders.
38
Preliminary Rev. 0.33
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