SI3400 [SILICON]
FULLY-INTEGRATED 802.3-COMPLIANT PD INTERFACE AND SWITCHING REGULATOR; 完全集成的802.3标准的PD接口和开关稳压器
| 型号： | SI3400 |
| 厂家： | 
SILICON |
| 描述： | FULLY-INTEGRATED 802.3-COMPLIANT PD INTERFACE AND SWITCHING REGULATOR |
| 文件： | 总20页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3400
Si3401
FULLY-INTEGRATED 802.3-COMPLIANT PD INTERFACE
AND SWITCHING REGULATOR
Features
ꢀ
ꢀ
IEEE 802.3 standard-compliant ꢀ Support non-isolated and
solution, including pre-standard
(legacy) PoE support
isolated switching topologies
Comprehensive protection
circuitry
ꢁ Transient overvoltage
protection
ꢁ Undervoltage lockout
ꢁ Early power-loss indicator
ꢁ Thermal shutdown protection
ꢁ Foldback current limiting
Programmable classification
circuit
ꢀ
Highly-integrated IC enables
compact solution footprints
ꢁ Minimal external components
ꢁ Integrated diode bridges and
transient surge suppressor
ꢁ Integrated switching regulator
controller with on-chip power
FET
Ordering Information:
See Ordering Guide on page
page 17.
ꢀ
ꢁ Integrated dual current-limited
hotswap switch
ꢀ
ꢀ
Low-profile 5 x 5 mm 20-pin QFN
Pb-Free and RoHS-compliant
Pin Assignments
5 x 5 mm QFN
(Top View)
Applications
ꢀ
Voice over IP telephones and ꢀ Point-of-sale terminals
20
19
18
17
16
15
adapters
Wireless access points
Security cameras
ꢀ
ꢀ
ꢀ
Internet appliances
Network devices
High power applications (Si3401)
ꢀ
ꢀ
1
2
3
4
EROUT
SSFT
14
13
12
11
CT1
VNEG
(PAD)
CT2
Description
VDD
VPOSF
SP1
ISOSSFT2
The Si3400 and Si3401 integrate all power management and control
functions required in a Power-over-Ethernet (PoE) powered device (PD)
application. The Si3400 and Si3401 convert the high voltage supplied over
the 10/100/1000BASE-T Ethernet connection into a regulated, low-voltage
output supply. The optimized architectures of the Si3400 and Si3401
minimize the solution footprint, reduce external BOM cost, and enable the
use of low-cost external components while maintaining high performance.
The Si3400 and Si3401 integrate the required diode bridges and transient
surge suppressors, thus enabling direct connection of ICs to the Ethernet
RJ-45 connector. The switching power FET and all associated functions are
also integrated. The integrated switching regulator supports isolated
(flyback) and non-isolated (buck) converter topologies. The Si3400 and
Si3401 support IEEE STD™ 802.3-2005 (future instances are referred to as
802.3) compliant solutions as well as pre-standard products, all in a single
IC. Standard external resistors connected to the Si3400 and Si3401 provide
the proper 802.3 signatures for the detection function and programming of
the classification mode. Startup circuits ensure well-controlled initial
operation of both the hotswap switch and the voltage regulator. The Si3400
and Si3401 are available in low-profile, 20-pin, 5 x 5 mm QFN packages.
While the Si3400 is designed for applications up to 10 W, the Si3401 is
optimized for higher power applications (up to approximately 15 W). See
also “AN313: Using the Si3400/01 in High Power Applications” for more
information.
5
6
7
8
9
10
Notes:
1. Pin VSSA added on revisions CZ
and higher.
2. Pin ISOSSFT added on revisions
CZ and higher. Function available
on revision E silicon. For Rev CZ,
or to disable this feature on
Revision E, tie this pin to VDD.
Rev. 0.9 8/07
Copyright © 2007 by Silicon Laboratories
Si3400/Si3401
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si3400/Si3401
Functional Block Diagram
VPOSF VPOSS RDET RCL
SSFT VDD
ISOSSFT
Detection
&
Switcher
Control
EROUT
FB
CT1
CT2
Classification
Hotswap
Control
&
Common
Bias
SP1
SP2
Hotswap
Switch
Switching
FET
SWO
&
Current limit
VNEG
HSO
VSS1 VSS2
PLOSS
VSSA
2
Rev. 0.9
Si3400/Si3401
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2. PD Hotswap Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3. Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev. 0.9
3
Si3400/Si3401
1. Electrical Specifications
Table 1. Absolute Maximum Ratings (DC)1
Type
Description
Rating
–60 to 60
–60 to 60
–0.3 to 60
–0.3 to 60
–0.3 to 60
–0.3 to 60
–60 to 0.3
–0.3 to 60
–0.3 to 5
Unit
Voltage
CT1 to CT2
SP1 to SP2
2
VPOS
HSO
VSS1 or VSS2
SWO
2
PLOSS to VPOS
RDET
V
RCL
2
SSFT to VPOS
–5 to 0.3
EROUT to VSS1, VSS2, or VSSA
FB to VPOS
–0.3 to VDD+0.3
–5 to 0.3
RIMAX to VSS1, VSS2, or VSSA
VSS1 to VSS2 or VSSA
VDD to VSS1, VSS2, or VSSA
RCL
–0.3 to VDD+0.3
–0.3 to 0.3
–0.3 to 5
Current
0 to 100
RDET
0 to 1
CT1, CT2, SP1, SP2
–400 to 400
–400 to 400
0 to 400
2
VPOS
HSO
mA
PLOSS
–0.5 to 5
VDD
0 to 2
SWO
0 to 400
VSS1, VSS2, or VSSA
Storage
–400 to 0
–65 to 150
–40 to 85
Ambient
Temperature
°C
Operating
Notes:
1. Unless otherwise noted, all voltages referenced to VNEG. Permanent device damage may occur if the maximum ratings
are exceeded. Functional operation should be restricted to those conditions specified in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may adversely affect device
reliability.
2. VPOS is equal to VPOSF and VPOSS tied together for test condition purposes.
4
Rev. 0.9
Si3400/Si3401
Table 2. Absolute Maximum Ratings (Transient)1
Transient surge defined in IEC60060 as a 1000 V impulse of either polarity applied across CT1–CT2 or SP1–SP2. The shape of
the impulse shall have a 300 ns full rise time and a 50 µs half fall time, with 201 Ω source impedance.
Type
Description
Rating
–82 to 82
–82 to 82
–0.7 to 80
–0.7 to 80
–0.7 to 80
–0.7 to 80
–80 to 0.7
–0.7 to 80
–5 to 5
Unit
Voltage
CT1 to CT2
SP1 to SP2
2
VPOS
HSO
V
VSS1, VSS2, or VSSA
SWO
2
PLOSS to VPOS
RDET
Current
CT1, CT2, SP1, SP2
A
2
VPOS
–5 to 5
3
ESD
HBM, all pins
–2 to 2
kV
Notes:
1. Unless otherwise noted, all voltages referenced to VNEG. Permanent device damage may occur if the maximum ratings
are exceeded. Functional operation should be restricted to those conditions specified in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may adversely affect device
reliability.
2. VPOS is equal to VPOSF and VPOSS tied together for test condition purposes.
3. For more information regarding system-level ESD tolerance, refer to “AN315: Robust Electrical Surge Immunity for PoE
PDs through Integrated Protection”.
Table 3. Recommended Operating Conditions
Description
|CT1 – CT2| or |SP1 – SP2|
Ambient Operating Temperature
Symbol
VPORT
TA
Min
2.8
Typ
—
Max
57
Units
V
–40
25
85
°C
Note: Unless otherwise noted, all voltages referenced to VNEG. All minimum and maximum specifications are guaranteed
and apply across the recommended operating conditions. Typical values apply at nominal supply voltage and ambient
temperature unless otherwise noted.
Rev. 0.9
5
Si3400/Si3401
Table 4. Electrical Characteristics
Parameter
Description
Detection
Min
2.7
14
—
30
62
—
—
0
Typ
—
—
—
—
—
—
—
—
—
—
—
—
2
Max
11
22
42
36
79
10
25
4
Unit
Classification
UVLO Turn Off
UVLO Turn On
Transient Surge
VPORT < 10 V
VPORT = 57 V
Class 0
V
VPORT
1
µA
µA
Input Offset Current
Diode bridge leakage
Class 1
9
12
20
30
44
3.1
—
2
Class 2
17
26
36
—
—
mA
IPORT Classification
Class 3
Class 4
3
36 V < VPORT < 57 V
Inrush
mA
mA
IPORT Operating Current
130
4
Current Limit
350 (Si3400)
470 (Si3401)
525
550
Operating
—
mA
Hotswap FET On-Resistance +
36 V < VPORT < 57 V
0.5
—
1.4
Ω
R
SENSE
Power loss VPORT Threshold
Switcher Frequency
27
—
—
30
350
50
33
—
—
V
kHz
5
Maximum Switcher Duty Cycle
ISOSSFT connected to
VDD
%
Switching FET On-Resistance
0.3
—
—
1.23
—
0.86
—
Ω
6
Regulated Feedback @ pin FB
DC Avg.
V
6
Regulated Output Voltage Tolerance
Output voltage tolerance @
VOUT
–5
5
%
Notes:
1. Transient surge defined in IEC60060 as a 1000 V impulse of either polarity applied to CT1–CT2 or SP1–SP2. The
shape of the impulse shall have a 300 ns full rise time and a 50 µs half fall time with 201 Ω source impedance.
2. The classification currents are guaranteed only when recommended RCLASS resistors are used, as specified in
Table 10.
3. IPORT includes full operating current of switching regulator controller.
4. The PD interface includes dual-level input current limit. At turn-on, before the HSO load capacitor is charged, the
current limit is set at the inrush level. After the capacitor has been charged within ~1.25 V of VNEG, the operating
current limit is engaged. This higher current limit remains active until the UVLO lower limit has been tripped or until the
hotswap switch is sufficiently current-limited to cause a foldback of the HSO voltage.
5. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated Designs” for more information.
6. Applies to non-isolated applications only (VOUT on schematic in Figure 1).
6
Rev. 0.9
Si3400/Si3401
Table 4. Electrical Characteristics (Continued)
Parameter
VDD accuracy @ 0.8 mA
Softstart charging current
Thermal Shutdown
Description
Min
4.5
—
Typ
—
Max
5.5
—
Unit
V
36 V < VPORT < 57 V
Junction temperature
12
µA
ºC
—
160
—
—
Thermal Shutdown Hysteresis
Notes:
—
25
ºC
1. Transient surge defined in IEC60060 as a 1000 V impulse of either polarity applied to CT1–CT2 or SP1–SP2. The
shape of the impulse shall have a 300 ns full rise time and a 50 µs half fall time with 201 Ω source impedance.
2. The classification currents are guaranteed only when recommended RCLASS resistors are used, as specified in
Table 10.
3. IPORT includes full operating current of switching regulator controller.
4. The PD interface includes dual-level input current limit. At turn-on, before the HSO load capacitor is charged, the
current limit is set at the inrush level. After the capacitor has been charged within ~1.25 V of VNEG, the operating
current limit is engaged. This higher current limit remains active until the UVLO lower limit has been tripped or until the
hotswap switch is sufficiently current-limited to cause a foldback of the HSO voltage.
5. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated Designs” for more information.
6. Applies to non-isolated applications only (VOUT on schematic in Figure 1).
Table 5. Total Power Dissipation
Description
Power Dissipation
Power Dissipation*
Condition
Min
—
Typ
1.2
0.7
Max
—
Units
W
VPORT = 50 V, V
= 5 V, 2 A
OUT
OUT
VPORT = 50 V, V
bridges bypassed
= 5 V, 2 A w/ diode
—
—
W
*Note: Silicon Laboratories recommends the on-chip diode bridges be bypassed when output power requirements are >10 W
(Si3401) or in thermally-constrained applications. For more information, see “AN313: Using the Si3400 and Si3401 in
High Power Applications”.
Table 6. Package Thermal Characteristics
Parameter
Symbol
Test Condition
Typ
Units
Thermal resistance
(junction to ambient)
θ
Still air; assumes a minimum of
nine thermal vias are connected
to a 2 in heat spreader plane for
44
°C/W
JA
2
the package “pad” node
(VNEG).
Rev. 0.9
7
Si3400/Si3401
2. Typical Application Schematics
To
Ethernet PHY
C5
C4
R3
R2
RJ-45
C3
FB
CT1
CT2
SP1
D1
Si3400
Si3401
SP2
L1
R1
SWO
EROUT
RDET
RCL
C6
R4
C2
C1
C7
Figure 1. Schematic—Class 0 with Non-Isolated 5 V Output*
*Note: This is a simplified schematic. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated
Designs” for more details and complete application schematics.
Table 7. Component Listing—Class 0 with 5 V Output
Item
Type
Value
Toler.
Rating
Notes
C1
Capacitor
15 µF
20%
100 V
Switcher supply capacitor. Several paral-
lel capacitors are used for lower ESR.
C2
C3
Capacitor
Capacitor
0.1 µF
20%
20%
100 V
10 V
PD input supply capacitor.
1000 µF
Switcher load capacitor - 1000 µF in par-
allel with and X5R 22 µF for lower ESR.
C4
C5
C6
C7
R1
R2
R3
R4
D1
L1
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Diode
0.1 µF
0.1 µF
20%
10%
10%
10%
1%
16 V
16 V
VDD bypass capacitor.
Softstart capacitor.
3.3 nF
16 V
Compensation capacitor.
Compensation capacitor.
Detection resistor.
150 pF
25.5 kΩ
7.32 kΩ
2.87 kΩ
30.1 kΩ
16 V
1/16 W
1/16 W
1/16 W
1/16 W
100 V
3.5 A
1%
Feedback resistor divider.
Feedback resistor divider.
Feedback compensation resistor.
Schottky diode; part no. PDS5100.
Coilcraft part no. DO5010333.
1%
1%
Inductor
33 µH
20%
8
Rev. 0.9
Si3400/Si3401
To Ethernet PHY
D1
D2
D3
T1
R5
RJ-45
R6
SWO
C8
CT1
CT2
SP1
SP2
RDET
ISOSSFT
VDD
PS2911
C3
Si3400
Si3401
R2
R4
C4
EROUT
R1
R8
R3
RCL
C2
C1
R7
C5
C7
Figure 2. Schematic—Class 1 with Isolated 5.0 V Output*
*Note: This is a simplified schematic. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated
Designs” for more details and complete application schematics.
Table 8. Components—Class 1 with Isolated 5.0 V Output
Item
Type
Value
Toler.
Rating
Notes
C1
Capacitor
15 µF
20%
100 V
Switcher supply capacitor. Several paral-
lel capacitors are used for lower ESR.
C2
C3
Capacitor
Capacitor
0.1 µF
20%
20%
100 V
10 V
PD input supply capacitor.
1100 µF
Switcher load capacitor. 100 µF in parallel
1000 µF and optional 1 µH inductor for
additional filtering.
C4
C5
C7
C8
Capacitor
Capacitor
Capacitor
Capacitor
15 nF
220 nF
0.1 µF
1 µF
10%
10%
20%
20%
16 V
16 V
16 V
16 V
Feedback compensation.
Feedback compensation.
VDD bypass capacitor.
Isolated mode soft start (tie ISOSSFT to
VDD if this feature is not used).
R1
R2
Resistor
Resistor
25.5 kΩ
4.99 kΩ
100 Ω
10 kΩ
2.05 kΩ
36.5 kΩ
12.1 kΩ
127 Ω
10 A
1%
1%
1%
1%
1%
1%
1%
1%
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
1/16 W
40 V
Detection resistor.
Pull-up resistor.
R3
Resistor
Feedback compensation resistor.
Feedback compensation resistor.
Pull-up resistor.
R4
Resistor
R5
Resistor
R6
Resistor
Feedback resistor divider.
Feedback resistor divider.
Classification resistor.
R7
Resistor
R8
Resistor
D1
Diode
Schottky diode; part no. PN PDS1040.
Snubber diode (1N4148)
Snubber diode (DFLT15A)
Coilcraft part number FA2672 (5 V).
D2
Diode
1 A
100 V
9 A
D3
Diode
15 V
T1
Transformer
Optocoupler
Voltage reference
40 µH
PS2911
TLV431
Rev. 0.9
9
Si3400/Si3401
The Si3400 and Si3401 are designed to operate with
both 802.3-compliant Power Sourcing Equipment (PSE)
3. Functional Description
The Si3400 and Si3401 consist of two major functions: and pre-standard (legacy) PSEs that do not adhere to
a hotswap controller/interface and a complete pulse- the 802.3 specified inrush current limits. The Si3400
width-modulated switching regulator (controller and and Si3401 are compatible with compliant and legacy
power FET).
PSEs because they use two levels for the hotswap
current limits. By setting the initial inrush current limit to
a low level, a PD based on the Si3400 or Si3401
3.1. Overview
The hotswap interfaces of the Si3400 and Si3401 minimizes the current drawn from either a compliant or
provide the complete front end of an 802.3-compliant legacy PSE during startup. After powering up, the
PD. The Si3400 and Si3401 also include two full diode Si3400 and Si3401 automatically switch to a higher-
bridges, a transient voltage surge suppressor, detection level current limit, thereby allowing the PD to consume
circuit, classification current source, and dual-level up to 12.95 W (the max power allowed by the 802.3
hotswap current limiting switch. This high level of specification).
integration enables direct connection to the RJ-45
The inrush current limit specified by the 802.3 standard
connector, simplifies system design, and provides
can generate high transient power dissipation in the PD.
significant advantages for reliability and protection. The
By properly sizing the devices and implementing on-
Si3400 and Si3401 require only four standard external
chip thermal protection, the Si3400 and Si3401 can go
components (detection resistor, optional classification
through multiple turn-on sequences without overheating
resistor, load capacitor, and input capacitor) to create a
the package or damaging the device. The switching
fully 802.3-compliant interface. For more information
regulator power MOSFET has been conservatively
about supporting higher-power applications, see
designed and sized to withstand the high peak currents
“AN313: Using the Si3400 and Si3401 in High Power
created when converting a high-voltage, low-current
Applications” and “AN314: Power Combining Circuit for
PoE for up to 18.5 W Output”.
supply into
a
low-voltage, high-current supply.
Excessive power cycling or short circuit faults will
engage the thermal overload protection to prevent the
onboard power MOSFETs from exceeding their safe
and reliable operating ranges.
The Si3400 and Si3401 integrate a complete pulse-
width modulated switching regulator that includes the
controller and power FET. The switching regulator
utilizes a constant frequency pulse-width modulated
controller optimized for all possible load conditions in
PoE applications. The regulator integrates a low on-
resistance (Ron) switching power MOSFET that
minimizes power dissipation, increases overall regulator
efficiency, and simplifies system design. An integrated
error amplifier, precision reference, and programmable
soft-start current source provide the flexibility of using a
non-isolated buck regulator topology or an isolated
flyback regulator topology.
3.2. PD Hotswap Controller
The Si3400 and Si3401 hotswap controllers change
their mode of operation based on the input voltage
applied to the CT1 and CT2 pins or the SP1 and SP2
pins, the 802.3-defined modes of operation, and internal
controller requirements. Table 9 defines the modes of
operation for the hotswap interface.
PLOSS
VPOSF VPOSS
RDET
ISOSSFT
SSFT
DETECTION
CONTROL
10V
5V
IABS
ITC
CENTRAL BIAS
BANDGAP REF
SWITCHER
STARTUP & BIAS
POWER LOSS
DETECTOR
0V
ON
1.32V
VREF
12V
DIODE BRIDGES
OFF
AND PROTECTION
HOTSWAP
CONTROL
CT2/SP2
CT1/SP1
CLASSIFICATION
CONTROL
39V
32V
ON
OFF
CURRENT
LIMIT
12V
22V
ON
HI/LO
OFF
HSO
VNEG
RCL
Figure 3. Hotswap Block Diagram
10
Rev. 0.9
Si3400/Si3401
As an added benefit, the transient surge suppressor,
when tripped, actively disables the hotswap interface
and switching regulator, preventing downstream circuits
from encountering the high-energy transients.
Table 9. Hotswap Interface Modes
Input Voltage (|CT1-
CT2| or |SP1-SP2|)
Si3400 and Si3401
Mode
3.2.2. Detection
0 V to 2.7 V
2.7 V to 11 V
11 V to 14 V
Inactive
In order to identify a device as a valid PD, a PSE will
apply a voltage in the range of 2.8 V to 10 V on the
cable and look for the 25.5 kΩ signature resistor. The
Si3400 and Si3401 will react to voltages in this range by
connecting an external 25.5 kΩ resistor between VPOS
and VNEG. This external resistor and internal low-
leakage control circuitry create the proper signature to
alert the PSE that a valid PD has been detected and is
ready to have power applied. The internal hotswap
switch is disabled during this time to prevent the
switching regulator and attached load circuitry from
generating errors in the detection signature.
Detection signature
Detection turns off and
internal bias starts
14 V to 22 V
22 V to 42 V
Classification signature
Transition region
42 V up to 57 V
Switcher operating mode
(hysteresis limit based on
rising input voltage)
57 V down to 36 V
Switcher operating mode
(hysteresis limit based on
falling input voltage)
Since the Si3400 and Si3401 integrate the diode
bridges, the IC can compensate for the voltage and
resistance effects of the diode bridges. The 802.3
specification requires that the PSE use a multi-point,
∆V/∆I measurement technique to remove the diode-
induced dc offset from the signature resistance
measurement. However, the specification does not
address the diode's nonlinear resistance and the error
induced in the signature resistor measurement. Since
the diode's resistance appears in series with the
signature resistor, the PD system must find some way of
compensating for this error. In systems where the diode
bridges are external, compensation is difficult and
suffers from errors. Since the diode bridges are
integrated in the Si3400 and Si3401, the IC can easily
compensate for this error by offsetting resistance across
all operating conditions and thus meeting the 802.3
requirements. An added benefit is that this function can
be tested during the IC’s automated testing step,
guaranteeing system compliance when used in the final
PD application. For more information about supporting
higher-power applications (above 12.95 W), see
“AN313: Using the Si3400 and Si3401 in High Power
Applications” and “AN314: Power Combining Circuit for
PoE for up to 18.5 W Output”.
3.2.1. Rectification Diode Bridges and
Surge Suppressor
The 802.3 specification defines the input voltage at the
RJ-45 connector of the PD with no reference to polarity.
In other words, the PD must be able to accept power of
either polarity at each of its inputs. This requirement
necessitates the use of two sets of diode bridges, one
for the CT1 and CT2 pins and one for the SP1 and SP2
pins to rectify the voltage. Furthermore, the standard
requires that a PD withstand a high-voltage transient
surge consisting of a 1000 V common-mode impulse
with 300 ns rise time and 50 µs half fall time. Typically,
the diode bridge and the surge suppressor have been
implemented externally, adding cost and complexity to
the PD system design.
The diode bridge* and the surge suppressor have been
integrated into the Si3400 and Si3401, thus reducing
system cost and design complexity.
*Note: Silicon Laboratories recommends that on-chip diode
bridges be bypassed when >10 W of output power is
required.
By integrating the diode bridges, the Si3400 and Si3401
gain access to the input side of the diode bridge.
Monitoring the voltage at the input of the diode bridges
instead of the voltage across the load capacitor
provides the earliest indication of a power loss. This true
early power loss indicator, PLOSS, provides a local
microcontroller time to save states and shut down
gracefully before the load capacitor discharges below
the minimum 802.3-specified operating voltage of 36 V.
Integration of the surge suppressor enables
optimization of the clamping voltage and guarantees
protection of all connected circuitry.
3.2.3. Classification
Once the PSE has detected a valid PD, the PSE may
classify the PD for one of five power levels or classes. A
class is based on the expected power consumption of
the powered device. An external resistor sets the
nominal class current that can then be read by the PSE
to determine the proper power requirements of the PD.
When the PSE presents a fixed voltage between 15.5 V
and 20.5 V to the PD, the Si3400 and Si3401 assert the
class current from VPOS through the RCL resistor.
Rev. 0.9
11
Si3400/Si3401
The resistor values associated with each class are
shown in Table 10.
Table 10. Class Resistor Values
Class
Usage
Power Levels
Nominal Class
Current
RCL Resistor (1%,
1/16 W)
0
Default
0.44 W to 12.95 W
< 4 mA
> 1.33 kΩ
(or open circuit)
1
2
3
4
Optional
Optional
Optional
Reserved
0.44 W to 3.84 W
3.84 W to 6.49 W
6.49 W to 12.95 W
Reserved
10.5 mA
18.5 mA
28 mA
127 Ω
69.8 Ω
45.3 Ω
30.9 Ω
40 mA
The 802.3 specification limits the classification time to 3.2.5. Dual Current Limit and Switcher Turn-On
75 ms to limit the power dissipated in the PD. If the PSE
The Si3400 and Si3401 implement dual current limits.
classification period exceeds 75 ms and the die
While the hotswap MOSFET is charging the switcher
temperature rises above the thermal shutdown limits,
supply capacitor, the Si3400 and Si3401 maintain a low
the thermal protection circuit will engage and disable
current limit. The switching regulator is disabled until the
the classification current source in order to protect the
voltage across the hotswap MOSFET becomes
Si3400 and Si3401. The Si3400 and Si3401 stay in
sufficiently low, indicating the switcher supply capacitor
classification mode until the input voltage exceeds 22 V
is almost completely charged. When this threshold is
(the upper end of its classification operation region).
reached, the switcher is activated, and the hotswap
3.2.4. Under Voltage Lockout
current limit is increased. This threshold also has
hysteresis to prevent systemic oscillation as the
switcher begins to draw current and the current limit is
increased, which allows resistive losses in the cable to
effectively decrease the input supply.
The 802.3 standard specifies the PD to turn on when
the line voltage rises to 42 V and for the PD to turn off
when the line voltage falls to 30 V. The PD must also
maintain a large on-off hysteresis region to prevent
wiring losses between the PSE and the PD from The Si3400 and Si3401 stay in a high-level current limit
causing startup oscillation.
mode until the input voltage drops below the UVLO turn-
off threshold or excessive power is dissipated in the
hotswap switch. This dual level current limit allows the
system designer to design powered devices for use with
both legacy and compliant PoE systems.
The Si3400 and Si3401 incorporate an undervoltage
lockout (UVLO) circuit to monitor the line voltage and
determine when to apply power to the integrated
switching regulator. Before the power is applied to the
switching regulator, the hotswap switch output (HSO) An additional feature of the dual current limit circuitry is
pin is high-impedance and typically follows VPOS as foldback current limiting in the event of a fault condition.
the input is ramped (due to the discharged switcher When the current limit is switched to the higher level,
supply capacitor). When the input voltage rises above 400 mA of current can be drawn by the PD. Should a
the UVLO turn-on threshold, the Si3400 and Si3401 fault cause more than this current to be consumed, the
begin to turn on the internal hotswap power MOSFET. voltage across the hotswap MOSFET will increase to
The switcher supply capacitor begins to charge up clamp the maximum amount of power consumed. The
under the current limit control of the Si3400 and Si3401, power dissipated by the MOSFET can be very high
and the HSO pin transitions from VPOS to VNEG. The under this condition. If the fault is very low impedance,
Si3400 and Si3401 include hysteretic UVLO circuits to the voltage across the hotswap MOSFET will continue
maintain power to the load until the input voltage falls to rise until the lower current limit level is engaged,
below the UVLO turn-off threshold. Once the input further reducing the dissipated power. If the fault
voltage falls below 30 V, the internal hotswap MOSFET condition remains, the thermal overload protection
is turned off.
circuitry will eventually engage and shut down the
hotswap interface and switching regulator. The foldback
current limiting occurs much faster than the thermal
overload protection and is, therefore, necessary for
comprehensive protection of the hotswap MOSFET.
12
Rev. 0.9
Si3400/Si3401
3.2.6. Power Loss Indicator
security cameras. In these applications, there is no
explicit need for dc isolation between the switching
regulator output and the hotswap interface. An isolated
system must be used when the powered device
interfaces with other self-powered equipment or has
external conductors accessible to the user or other
applications. For proper operation, the regulated output
supply of the switching regulator must not have a dc
electrical path to the hotswap interface or switching
regulator primary side. Isolated applications include
point-of-sale terminals where the user can touch the
grounded metal chassis.
A situation can occur in which power is lost at the input
of the diode bridge and the hotswap controller does not
detect the fault due to the VPOS to VNEG capacitor
maintaining the voltage. In such a situation, the PD can
remain operational for hundreds of microseconds
despite the PSE having removed the line voltage. If it is
recognized early enough, the time from power loss to
power failure can provide valuable time to gracefully
shut down an application.
Due to integration of the diode bridges, the Si3400 and
Si3401 are able to instantaneously detect the removal
of the line voltage and provide that early warning signal
to the PD application. The PLOSS pin is an open drain
output that pulls up to VPOS when a line voltage greater
than 27 V is applied. When the line voltage falls below
27 V, the output becomes high-impedance, allowing an
external pull-down resistor to change the logic state of
PLOSS. The benefit of this indicator is that the powered
device may include a microcontroller that can quickly
save its memory or operational state before draining the
supply capacitors and powering itself down. This feature
can help improve overall manageability in applications,
such as wireless access points.
The application determines the converter topology. An
isolated application will require a flyback transformer-
based switching topology while
a
non-isolated
application can use an inductor-based buck converter
topology. In the isolated case, dc isolation is achieved
through a transformer in the forward path and a voltage
reference plus opto-isolator in the feedback path. The
application circuit shown in Figure 2 is an example of
such a topology. The non-isolated application in
Figure 1 makes use of a single inductor as the energy
conversion element, and the feedback signal is directly
supplied into the internal error amplifier. As can be seen
from the application circuits, the isolated topology has
an increased number of components, thus increasing
the bill of materials (BOM) and system footprint.
3.3. Switching Regulator
Power over Ethernet (PoE) applications fall into two
broad categories, isolated and non-isolated. Non- To optimize cost and ease implementation, each
isolated systems can be used when the powered device application should be evaluated for its isolated or non-
is self-contained and does not provide external isolated requirements.
conductors to the user or another application. Non-
isolated applications include wireless access points and
EROUT
VPOSF VPOSS
SSFT
FB
SWO
PULSE-
WIDTH
MODULATOR
ERROR
AMPLIFIER
SWITCH
DRIVE
OSCILLATOR
IABS
ITC
SWITCHER
STARTUP & BIAS
VREF
HSO
VDD
VSSA
ISOSSFT
VSS1
VSS2
Figure 4. Switcher Block Diagram
Rev. 0.9
13
Si3400/Si3401
3.3.1. Switcher Startup
The PWM controls the switching FET drive circuitry. A
significant advantage of integrating the switching power
FET onto the same monolithic IC as the switching
regulator controller is the ability to precisely adjust the
drive strength and timing to the FET's sizable gate,
resulting in high regulator efficiency. Furthermore,
current-limiting circuitry prevents the switching FET
from sinking too much current, dissipating too much
power, and becoming damaged. Thermal overload
protection provides a secondary level of protection.
The switching regulator is disabled until the hotswap
interface has both identified itself to the PSE and
charged the supply capacitor needed to filter the
switching regulator's high-current transients. Once the
supply capacitor is charged, the hotswap controller
engages the internal bias currents and supplies used by
the switcher. Additionally, the soft-start current begins to
charge the external soft-start capacitor.
The voltage developed across the soft-start capacitor
serves as the error amplifier's reference in the non-
isolated application. Ramping this voltage slowly allows
the switching regulator to bring up the regulated output
voltage in a controlled manner. Controlling the initial
startup of the regulated voltage restrains power
dissipation in the switching FET and prevents overshoot
and ringing in the output supply voltage.
The flexibility of the Si3400 and Si3401's switching
regulator allows the system designer to realize either
the isolated or non-isolated application circuitry using a
single device. In operation, the integration of the
switching FET allows tighter control and more efficient
operation than a general-purpose switching regulator
coupled with a general-purpose external FET.
3.3.3. Flyback Snubber
In the isolated mode, a capacitor connected between
pins ISOSSFT and VSSA slowly ramps the duty cycle Extremely high voltages can be generated by the
clamp in the PWM circuit. Tie this pin to VDD if not inductive kick associated with the leakage inductance of
used.
the primary side of the flyback transformer used in
isolated applications.
3.3.2. Switching Regulator Operation
Refer to “AN296: Using the Si3400/01 PoE PD
Controller in Isolated and Non-Isolated Designs” for
more information on the snubber.
The switching regulator of the Si3400 and Si3401 is
constant-frequency, pulse-width-modulated (PWM), and
controller integrated with switching power FETs
optimized for the output power range defined by the
802.3 specification.
Once the hotswap interface has ensured proper turn-on
of the switching regulator controller, the switcher is fully
operational. An internal free-running oscillator and
internal precision voltage reference are fed into the
pulse-width modulator. The output of the error amplifier
(either internal for non-isolated applications or external
for isolated applications) is also routed into the PWM
and determines the slicing of the oscillator.
14
Rev. 0.9
Si3400/Si3401
4. Pin Descriptions
20
19
18
17
16
15
1
2
3
4
EROUT
SSFT
14
13
12
11
CT1
VNEG
(PAD)
CT2
VDD
VPOSF
SP1
ISOSSFT
5
6
7
8
9
10
Table 11. Si3400 and Si3401 Pin Descriptions (Top View)
Pin#
Name
Description
1
EROUT
Error-amplifier output and PWM input; directly connected to opto-coupler in isolated application.
Soft-start output pin ramps voltage across external soft-start capacitor to allow switcher to ramp
output slowly.
2
3
4
5
6
SSFT
VDD
5 V supply rail for switcher; provides drive for opto-coupler.
Isolated mode soft start enable input. Tie to VDD for non-isolated applications. Connect a
0.1 µF capacitor between this pin and VSSA for isolated applications.
ISOSSFT
PLOSS
RDET
Early power loss indicator; open drain output is pulled to VPOS when VPORT is applied.
Input pin for external precision detection resistor; also used for establishing absolute current ref-
erence.
7
8
HSO
RCL
Hotswap switch output; connects to VNEG through hotswap switch.
Input pin for external precision classification resistor; float if optional RCLASS is unused.
Rectified high-voltage supply, negative rail. Must be connected to thermal PAD node (VNEG)
on package bottom. This thermal pad must be connected to VNEG (pin #9) as well as a 2 in2
heat spreader plane using a minimum of nine thermal vias.
9, Pad
VNEG
10
11
12
13
14
15
16
17
18
19
20
SP2
SP1
High-voltage supply input from spare pair; polarity-insensitive.
High-voltage supply input from spare pair; polarity-insensitive.
Rectified high-voltage supply, positive rail (force node)
High-voltage supply input from center tap of Ethernet transformer; polarity-insensitive.
High-voltage supply input from center tap of Ethernet transformer; polarity-insensitive.
Analog ground.
VPOSF
CT2
CT1
VSSA
VPOSS
VSS1
SWO
VSS2
FB
Rectified high-voltage supply, positive rail sense node.
Negative supply rail for switcher; externally tied to HSO.
Switching transistor output; drain of switching N-FET.
Negative supply rail for switcher; externally tied to HSO.
Regulated feedback input in non-isolated application.
Rev. 0.9
15
Si3400/Si3401
5. Package Outline
Figure 5 illustrates the package details for the Si3400 and Si3401. Table 12 lists the values for the dimensions
shown in the illustration.
Figure 5. 20-Lead Quad Flat No-Lead Package (QFN)
Table 12. Package Dimensions
Dimension
Min
0.80
0.00
0.25
Nom
0.85
Max
0.90
0.05
0.35
A
A1
b
0.02
0.30
D
5.00 BSC.
2.70
D2
e
2.60
2.80
0.80 BSC.
5.00 BSC.
2.70
E
E2
L
2.60
0.50
0.00
—
2.80
0.60
0.10
0.10
0.10
0.08
0.10
0.55
L1
aaa
bbb
ccc
ddd
—
—
—
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VHHB-1.
16
Rev. 0.9
Si3400/Si3401
6. Ordering Guide
1,2
Package
Temp Range
Recommended
Part Number
3
Maximum Output Power
Si3400-X-GM
Si3401-X-GM
Notes:
20-pin QFN,
Pb-free; RoHS compliant
–40 to 85 °C
–40 to 85 °C
< 10 W
20-pin QFN,
Pb-free; RoHS compliant
14 to 16 W
1. “X” denotes product revision.
2. Add an “R” at the end of the part number to denote tape and reel option.
3. Refer to “AN313: Using the Si3400/01 in High Power Applications” and “AN314: Power Combining Circuit for
PoE for up to 18.5 W Output” for more information about using the Si3400 and Si3401 in higher power
applications.
Rev. 0.9
17
Si3400/Si3401
Revision 0.7 to Revision 0.8
DOCUMENT CHANGE LIST
ꢀ ISOSSFT (pin 4) added throughout document.
Revision 0.3 to Revision 0.4
ꢀ Updated Figures 1 and 2 for addition of ISOSSFT
ꢀ Updated Figure 2 on page 9.
pin. Function available on Revision E and higher.
ꢁ R9 now correctly connected to VNEG; RIMAX now
Revision 0.8 to Revision 0.9
connects to VDD.
ꢀ Added Table 6, “Package Thermal Characteristics,” ꢀ Updated throughout document to support Revision
on page 7.
E.
ꢀ Updated Figure 3 on page 10.
ꢀ Added Regulated Output Voltage Tolerance
specification to Table 4, for non-isolated applications
only.
ꢀ Updated Table 4 on page 6.
ꢁ Updated switcher frequency specification to 350 kHz.
ꢀ Added “pad” notes to VNEG pin under Description
section in Table 11 on page 15.
ꢀ Updated Figure 1, Figure 2, and Table 7 for Rev. E
BOM changes.
ꢀ Nominal class resistor values updated for Rev. E in
ꢀ Updated Table 7, “Component Listing—Class 0 with
5 V Output,” on page 8 and Table 8, “Components—
Class 1 with Isolated 5.0 V Output,” on page 9.
ꢁ Updated recommended BOMs.
Table 10.
Revision 0.4 to Revision 0.5
ꢀ Updated Table 4 on page 6.
ꢁ Updated test condition for VDD current.
ꢁ Updated minimum value of switcher FET on resistance.
ꢀ Updated Table 8 on page 9 and Table 10 on
page 12.
ꢁ Updated Rclass information.
ꢀ Updated “5. Package Outline” and Table 12,
“Package Dimensions,” on page 16.
ꢁ Replaced package drawing and dimensions table.
Revision 0.5 to Revision 0.6
ꢀ Added Si3401.
ꢀ Updated Figure 1 on page 8.
ꢀ Updated Table 7 on page 8.
ꢀ Updated "6. Ordering Guide" on page 17.
Revision 0.6 to Revision 0.7
ꢀ Added VSSA pin throughout document for product
revisions beginning with Rev D.
ꢀ Updated Table 2 specs (for ESD).
ꢀ Updated Table 4 specs (for current limits).
ꢀ Updated Table 5 specs (for power dissipation).
ꢀ Updated Figure 1 and Table 7.
ꢀ Updated Figure 2 and Table 8.
ꢀ Updated Figure 4 and Table 11.
18
Rev. 0.9
Si3400/Si3401
NOTES:
Rev. 0.9
19
Si3400/Si3401
CONTACT INFORMATION
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400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: PoEinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
20
Rev. 0.9
相关型号：
SI3402-A-GMR
Switching Regulator, Current-mode, 0.68A, 350kHz Switching Freq-Max, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHB-1, QFN-20
SILICON
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