SI3406-A-GM [SILICON]
Power Supply Support Circuit,;
| 型号： | SI3406-A-GM |
| 厂家： | 
SILICON |
| 描述： | Power Supply Support Circuit, |
| 文件： | 总36页 (文件大小：1055K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3406x Family Data Sheet
Fully-Integrated IEEE 802.3-Compliant POE+ PD Interface and
High-Efficiency Switching Regulators with Transistor Bypass,
Sleep, Wake, and LED Drive
KEY FEATURES
• Type 1 (PoE) or Type 2 (PoE+) power
• Full IEEE 802.3at compliance
• Synchronous secondary FET driver
• Current mode dc-dc converter
• Tunable switching frequency
The Si3406x family integrates all power management and control functions required in
a Power-over-Ethernet Plus (PoE+) powered device (PD) application. These devices
convert the high voltage supplied over the 10/100/1000BASE-T Ethernet connection to
a regulated, low-voltage output supply. The optimized architecture of this device family
minimizes the solution footprint and external BOM cost and enables the use of low-cost
external components while maintaining high performance. The Si3406x family integra-
tes the required diode bridges and transient surge suppressor, thus enabling direct
connection of the IC to the Ethernet RJ-45 connector. The switching power FET and all
associated functions are also integrated. The integrated, current mode controlled
switching regulator supports isolated or non-isolated flyback and buck converter topolo-
gies. The switching frequency for the regulator is tunable with a simple external resistor
value to help avoid unwanted harmonics for better emissions control. A synchronous
driver is provided to optionally drive a secondary side FET to improve efficiency of pow-
er conversion. Connection to the PSE switch is maintained during sleep by an optional
automated maintain-power-signature (MPS) signal.
• Auxiliary transformer winding support
• Auxiliary adapter support
• Internal hotswap and switching FET bypass
support
• Automated maintain-power-signature (MPS)
support
• Sleep mode augmented with wake pin,
mode control, and LED driver
• 120 V Absolute Max voltage performance
• Extended –40 to +85 °C temperature
• Compact ROHS-compliant 5 mm x 5 mm
QFN Package
These devices fully support the IEEE 802.3at specification for the cases of single or
two event classification. Standard external resistors provide the proper IEEE 802.3 sig-
natures for the detection function and programming of the classification mode, and in-
ternal startup circuits ensure well-controlled soft-start initial operation of both the hots-
wap switch and the voltage regulator.
APPLICATIONS
• Voice over IP telephones
• Wireless access points
• Security and surveillance IP cameras
• Lighting luminaires
The Si34061 and Si34062 add main transformer bias winding support for ultra-high-effi-
ciency operation.
The Si34061 includes support for external augmentation or full bypass of the internal
hotswap and/or switching FET for best power handling and thermal management at the
high end of Class 4, plus offers a further boost in power conversion efficiency when
needed.
• Point-of-sale terminals
• Internet appliances
• Network devices
The Si34062 includes support for sleep modes with wake function, as well as LED drive
capability. These features can be utilized to minimize standby current, control sleep
and wake states, and provide application status information using a solid or blinking
LED.
The Si3406 is available in a low-profile, 20-pin, 5 x 5 mm QFN package, and the
Si34061 and Si34062 are available in low-profile, 24-pin, 5 x 5 mm QFN packages.
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.5
Si3406x Family Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si3406x Ordering Guide
Ordering Part Number
Package
Temperature Range (Ambient)
Applications
5 x 5 mm 20-QFN
Pb-free, RoHS-compliant
5 x 5 mm 24-QFN
Si3406-A-GM
–40 to 85 °C Extended
All Purposes
Any high-power, high-efficiency
uses, such as Wireless Access
Points and IP Cameras
Si34061-A-GM
Si34062-A-GM
–40 to 85 °C Extended
–40 to 85 °C Extended
Pb-free, RoHS-compliant
5 x 5 mm 24-QFN
IP Phones or other uses with
Sleep/Green mode
Pb-free, RoHS-compliant
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Preliminary Rev. 0.5 | 2
Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Power over Ethernet (PoE) Line-Side Interface. . . . . . . . . . . . . . . . . . . 5
2.2.1 Surge Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.2 Telephony Protection . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.3 Detection and Classification . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Hotswap Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 HSSW State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.1 External HSSW FET Driver . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 DC to DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5.1 Average Current Sensing, Overcurrent, and Low-Current Detection. . . . . . . . . . 9
2.5.2 Sync FET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 External HSSW FET Driver . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 Tunable Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.9 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.10 Extended Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.11 External Wall Support . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3. Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .21
6. Packaging
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Package Outline: Si3406 . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.2 Land Pattern: Si3406 . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.3 Package Outline: Si34061/62. . . . . . . . . . . . . . . . . . . . . . . . .29
6.4 Land Pattern: Si34061/62 . . . . . . . . . . . . . . . . . . . . . . . . . .31
7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1 Si3406 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
7.2 Si34061 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . .33
7.3 Si34062 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Preliminary Rev. 0.5 | 3
Si3406x Family Data Sheet
System Overview
2. System Overview
The following Block Diagrams will give the designer a sense for the internal arrangement of functional blocks, plus their relationships to
external pins. The Block Diagrams are followed by a description of the features of these integrated circuits.
2.1 Block Diagrams
RFREQ
RDET
V11
VDD
VPOS
CT1
11V
REGULATOR
5V
REGULATOR
250kHz
OSCs
fixed: 250kHz
adjustable: 100...500kHz
THERMAL
PROTECTION
IBIAS
FBH
VPOS-1.32V
FBL
VSS+1.32V
CT2
SP1
Start
DETECTION
EROUT
PoE
CONTROLLER
250kHz
CLASS
&
MPS
SWO
VSS
DC/DC
SW
CURRENT
THERMAL
PROTECTION
MODE
PWM
SP2
HOT-SWAP
CONTROLLER
TVS
CONTROLLER
100V
VNEG
HSSW
IAVG
ISNS
HSO
V11
DRV
SYNCL
RCL
nT2P
nSLEEP
Figure 2.1. Si3406 Block Diagram
RFREQ
RDET
VT15
V11
VDD
AUX
WINDING
SUPPORT
VPOS
CT1
11V
REGULATOR
5V
REGULATOR
250kHz
OSCs
fixed: 250kHz
adjustable: 100...500kHz
THERMAL
PROTECTION
IBIAS
FBL
VSS+1.32V
CT2
SP1
Start
DETECTION
EROUT
SWO
PoE
CONTROLLER
250kHz
CLASS
&
MPS
DC/DC
SW
CURRENT
THERMAL
PROTECTION
MODE
PWM
VSS
SP2
HOT-SWAP
CONTROLLER
TVS
CONTROLLER
100V
V11
DRV
EXTGD
VNEG
HSSW
IPK
SWISNS
ISNS
IAVG
HSO
V11
SYNCL
DRV
RCL
EXTHSW
ASUP
nT2P
nSLEEP
Figure 2.2. Si34061 Block Diagram
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Preliminary Rev. 0.5 | 4
Si3406x Family Data Sheet
System Overview
RFREQ
RDET
VT15
V11
VDD
AUX
WINDING
SUPPORT
VPOS
CT1
11V
REGULATOR
5V
REGULATOR
250kHz
OSCs
fixed: 250kHz
adjustable: 100...500kHz
THERMAL
PROTECTION
IBIAS
FBH
VPOS-1.32V
FBL
VSS+1.32V
CT2
SP1
Start
DETECTION
EROUT
PoE
CONTROLLER
250kHz
CLASS
&
MPS
SWO
VSS
DC/DC
SW
CURRENT
THERMAL
PROTECTION
MODE
PWM
SP2
HOT-SWAP
CONTROLLER
TVS
CONTROLLER
100V
VNEG
HSSW
IAVG
ISNS
HSO
V11
DRV
SYNCL
RCL
WAKE
MODE
LED
nT2P
nSLEEP
Figure 2.3. Si34062 Block Diagram
2.2 Power over Ethernet (PoE) Line-Side Interface
The PoE line interface consists of diode bridges, internal surge protection, and the protocol interface support for detection and classifi-
cation.
Internal diode bridge maximum current is given by the specification, IRECT. If the application needs to consume more current from the
power interface, an external diode bridge has to be used. The external bridge should be connected in parallel to the internal bridge and
the designer must ensure that the internal bridge will not conduct significant current by using low-voltage-drop external diodes.
The chip features active protection against surge transients and accidentally applied telephony voltages.
2.2.1 Surge Protection
The surge protection circuit is activated if the VPOS-VNEG voltage exceeds TPROT and the hotswap switch is off (dc-dc is not pow-
ered). If the hotswap switch is on, the surge power is sunk in the dcdc’s capacitance.
The internal surge protection can be overridden with an external TVS if higher than specified surge conditions need be tolerated. The
external surge device must be connected in parallel to the internal one; therefore, the designer must ensure that the external surge
protection will activate prior to the internal surge protection.
2.2.2 Telephony Protection
The Si3406x provides protection against telephony ringing voltage. The telephony ringing is much longer than the surge pulse but it has
less energy, therefore, the Si3406x has a switch parallel with the supply (VPOS and VNEG). When the protection circuit is activated, it
turns ON the telephony switch; the ringing energy then dissipates on this switch and ringing generator resistance (> 400 Ω).
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Preliminary Rev. 0.5 | 5
Si3406x Family Data Sheet
System Overview
2.2.3 Detection and Classification
When si3406x is connected to the Ethernet cable it has to provide a characteristic resistance (~25 kΩ) to the PSE in a given voltage
range (2.7–10.1 V). This is called detection. After thePSE detects the PD, the PSE increases the voltage above the classification
threshold 14.5 V. Then, the PD provides the classification current to inform the PSE about its required power class (Class 1, 2, 3, or 4).
Type 1 PSEs cannot provide enough power for a Class4 PD. Type 2 PSEs have additional voltage steps before switching on the PD.
After an initial classification voltage pulse, the Type 2 PSE reduces the voltage below the mark threshold level (10 V) then raises it up
again to the Class event range. Last, before switching ON the DCDC it reduces the voltage again. This sequence is recognized by the
si3406x and its pull down its nT2P pin to inform the application about the higher available power; otherwise, the application will need to
operate in a reduced power consumption state (Type 1) if the PSE is incapable of delivering Class 4 power.
Figure 2.4. Powered Device Voltages
2.3 Hotswap Switch
The internal hotswap switch (HSSW) is turned on (conducting) when the PoE interface voltage goes above VUVLO_R. It provides limited
inrush current until the dcdc side capacitor is charged. The hotswap switch turns off (open) if voltage on the HSSW switch (HSO-VNEG)
is greater than VHSSW_OFF
.
In overload, the hotswap switch goes into current-limiting mode with a current limit of IOVL. It will turn back ON after TWAITHSSW elap-
ses and the dc-dc input capacitor is recharged, meaning the HSO-VNEG voltage is less than VHSSW_ON
.
The hotswap switch (if it is in the on state and conducting) can detect if the current is lower than IMPSth. In this case, the chip turns on
MPS pulse generation, which ensures that the PSE will not disconnect.
With the Si34061, an external hotswap switch can be used to improve efficiency and reduce thermal stress in high current applications.
For Class 3 applications, using an external hotswap switch is recommended; for Class 4, it is mandatory because the internal hotswap
switch otherwise generates significant heat. When an external hotswap switch is used, intelligent switch control ensures that inrush cur-
rent limiting and automatic MPS request of the internal switch are still supported.
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Preliminary Rev. 0.5 | 6
Si3406x Family Data Sheet
System Overview
2.4 HSSW State Machine
The HSSW operates as simple 4-state state machine:
Figure 2.5. Hotswap Switch 4-State Machine
Note: Internal signal names are shown in this Figure, not to be confused with external pin names. For the below discussion, ILOAD is
the switch current, and VHSSW is the voltage drop of the switch. In other words, VHSSW = HSO – VNEG. All the voltage, current and
time limits of the above diagram are typical values.
OFF State
HSSW turn-on is controlled by UVLO, the undervoltage lockout feature. When UVLO is engaged, the HSSW is OFF. In this state, the
HSSW is in idle mode, VNEG and HSO pins are disconnected. In normal operation, a complete detect/classification procedure pre-
cedes the HSSW turn-on, and the control of this sequence is implemented in the state machine logic of the chip.
INRUSH State
After the controller enables the HSSW, the block starts operation in the INRUSH state. In this state the switch itself is not directly turned
on, but operating in a closed-loop current limit mode to avoid high current peaks during the charging of the primary bypass cap of the dc
to dc converter.
If the VHSSW voltage drops below 380 mV (meaning the bypass cap is 99% charged), the HSSW will change state to ON either in
Type1 classification immediately, or in Type2 classification if the HSSW has been in the INRUSH state for at least 80 ms.
ON State
In ON state, the HSSW switch is directly turned on. The HSSW circuit continuously monitors VHSSW. HSSW will change to OVERLOAD
state if VHSSW voltage increases over 3.6 V for at least 140 µs.
OVERLOAD State
In OVERLOAD state the HSSW operates in closed-loop low current limit mode. If the VHSSW voltage drops below 360 mV again, and
the HSSW has been in the OVERLOAD state for at least 80 ms, the HSSW will change back to the ON state.
2.4.1 External HSSW FET Driver
An external HSSW FET may be used to improve thermal operation of an Si34061 at very high power loading levels (the top end of
Class 4).
With the Si34061, the chip automatically detects if the EXTHSW pin is connected to VNEG or to a FET gate at startup. If the external
hotswap FET driver will not be used, the EXTHSW pin must be tied to VNEG.
For further information on using an external HSSW FET, please refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404
PoE PD Controller In Isolated and Non-Isolated Designs".
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Preliminary Rev. 0.5 | 7
Si3406x Family Data Sheet
System Overview
2.5 DC to DC Converter
The dc-to-dc converter is current-controlled for easier compensation and more robust protection of circuit magnetics. The controller has
the following features:
• High- and low-side feedback (supports buck and flyback topologies).
• <1 Ω internal switching FET
• Driver for optional synchronous rectification
• Overcurrent detection
• Low current detection
• Cycle skipping at low current and short circuit conditions
• Optional external switching FET driver (Si34061)
• Automatic non-overlap control
VPOS
VDD
VPOS
1.32V
VDD
gmh
100µS
SOFT START
VEROUT LIMIT
FBH
RESET
PD
CSOFTS
SHORT
DETECT
IPEAK
EROUT
FBL
LOOP COMP
PD
LIMIT
gmpeak
50µS
SHORT
DETECT
SLOPE
COMPENSATION
gml
100µS
IAVG LIMIT
BLANKING
TIME
COMP
COMP
1.32V
270mV
CLIPPING
1:1072
SWO
VDD
OR
R
S
Q
Q
VSS
COMP
VDD
DRV
50mV
V11
DRV
OSC
LOW CURRENT
DETECT
SYNCL
NON OVERLAP
DRIVER
ISNS
LPF
AND
Figure 2.6. Si3406x DC-DC Converter
When the internal switching FET is used with the converter, internal peak current detection is employed. When the EXTGD pin and an
external FET are used with Si34061, an external current sense resistor is used to measure the peak current connected to the SWISNS
pin. Changing that resistor allows the application to set the converter maximum peak current to protect the magnetic components (like
the transformer) from saturation.
Feedback to the dcdc converter can be provided in three ways:
• High side, referenced to VPOS, connected to FBH pin (buck converter)
• Low side, referenced to VSS, connected to FBL pin (nonisolated flyback)
• Directly to EROUT pin by a voltage to current converter (isolated flyback)
The EROUT pin provides current output (if FBL or FBH is used) and voltage input. Also, the loop compensation impedance is connec-
ted to EROUT. The active voltage range is VEROUT, which is proportional to the converter peak current.
The converter startup is not configurable; soft start is accomplished by internal circuitry. Soft start time is TSOFTSTART. The intelligent
soft start circuit dynamically adjusts the soft start time depending on the connected load.
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Preliminary Rev. 0.5 | 8
Si3406x Family Data Sheet
System Overview
2.5.1 Average Current Sensing, Overcurrent, and Low-Current Detection
The application average current is sensed by an external resistor (RSENSE) connected between VSS and ISNS. Overcurrent is detected
and triggered when the voltage on the sense resistor exceeds VISNS_OVC. Sizing the resistor allows the designer to set the overcurrent
limit according to application needs. When overcurrent is triggered, the dcdc controller goes into reset until the overcurrent resolves.
When the overcurrent is no longer present, the controller starts up again with softstart.
This external sense resistor is also used to detect a low current situation. When the voltage on the sense resistor goes below VISNS_LC
,
the dcdc controller disables the sync FET and the external hotswap switch, allowing very low current consumption—the internal hots-
wap switch then measures the chip current internally. If the average current is lower than the PoE maintain power signature (MPS) limit,
and if automatic sleep mode is enabled, the chip turns on the MPS generation. See the sleep mode section for further detail.
2.5.2 Sync FET Driver
With the Si3406x family, an optional synchronous rectifying FET may be used in place of an output rectifier diode for improved power
conversion efficiency.
A gate driver is provided for this purpose. The synchronous rectifying FET driver is enabled by default in Si3406x configurations, but, if
a synchronous FET is not used in the design, the SYNCL pin must not be connected (do not connect SYNCL to any power or ground
rail). The synchronous rectifying FET driver is disabled only when the dcdc converter measures low average current (meaning lower
than VISNS_LC on ISNS). This ensures low sleep mode current consumption.
2.6 External HSSW FET Driver
An external HSSW FET may be used to improve thermal operation of an Si34061 at very high power loading levels (the top end of
Class 4).
With the Si34061, the chip automatically detects if the EXTHSW pin is connected to VNEG or to a FET gate at startup. If the external
hotswap FET driver will not be used, the EXTHSW pin must be tied to VNEG.
For further information on using an external HSSW FET, please refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404
PoE PD Controller In Isolated and Non-Isolated Designs".
2.7 Tunable Oscillator
The dcdc frequency can be fixed to 250 kHz or tunable by an external resistor.
The tuning resistor must be connected between the RFREQ pin and VPOS. If RFREQ is shorted to VPOS, the fixed frequency oscillator
will provide the clock, FOSCINT, to the dcdc converter; otherwise, the resistor will determine the frequency as shown in the curve below.
Figure 2.7. RFREQ Frequency Selector Diagram
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Preliminary Rev. 0.5 | 9
Si3406x Family Data Sheet
System Overview
2.8 Regulators
The chip provides a 5 V output to power LEDs or optocouplers. This is a closed-loop regulator, which ensures accurate output voltage.
The 5 V regulator is supplied by an internal 11 V open loop regulator, which also provides power for the external FET gate drivers. The
11 V regulator is supplied by a coarse regulator, which is also open-loop. With the Si34061 and Si34062, the VT15 pin can be used to
supply this regulator from an optional auxiliary transformer winding. The advantage of doing so is additional power saving since the
external FET drivers’ current is not generated from the PoE 50 V but, rather, from a transformer-provided 12–16 V. The application
must be designed to ensure that the absolute maximum rating voltage for the VT15 pin is not exceeded.
2.9 Sleep Mode
The Si3406, Si34061, and Si34062 have automatic (consumption-based) and non-automatic sleep modes. When SLEEPb is tied to
ground, the automatic sleep mode is enabled, meaning that if the current consumption is lower than IMPSth, the chip will automatically
generate MPS pulses to the PSE. If SLEEPb is tied to VDD, then it will not generate MPS pulses, and the PSE will disconnect if total
application current consumption drops below 5–10 mA.
For non-automatic sleep mode, tie SLEEPb high at initial startup (right after the hotswap switch turns on). The chip turns OFF automatic
mode, but pulling SLEEPb low will force MPS generation as long as the pin is held low. Using this mode, the designer can control MPS
generation.
2.10 Extended Sleep Mode
In the Si34062, an extended sleep mode is available which includes LED, WAKE, and MODE pin support. The LED pin drives a light
emitting diode to (for example) illuminate a button on the primary side of the application. The WAKE pin triggers wakeup, and the
MODE button controls if MPS generation is enabled in sleep. In the Si34062 case, nSLEEP is used to initiate sleep.
The sleep mode is initiated by a negative transition on nSLEEP. It is latched at that negative transition event together with MODE, so
their status is kept until wakeup even if the input changes on these pins due to the secondary side losing power. MPS generation is
enabled if MODE = 0 at the nSLEEP transition. The following figure shows the Si34062 sleep mode behavior.
Chip Awake,
DCDC Runs
NSLEEP Neg.Edge
Low
Turn MPS
Generation ON
Mode?
High
Chip Sleep,
DCDC Off
Figure 2.8. Si34062 Extended Sleep Mode Behavior
Refer to Figure 3.3 Si34062 ISO Flyback Application Diagram on page 13, which shows shows the connectivity for the Si34062 with
the extended sleep mode.
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Preliminary Rev. 0.5 | 10
Si3406x Family Data Sheet
System Overview
2.11 External Wall Support
The Si3406x supports using a wide voltage range of external wall adapters as a primary or secondary supply. For details on options
and supported modes of adapter connection, please refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404 PoE PD
Controller In Isolated and Non-Isolated Designs".
RASUP
VAUX
12V-57V
VPOS
ASUP
HSO
VPOS
C
100k
SWO
VSS
From PSE
Si34061
RISNS
ISNS
HSO
HSO
VNEG
VNEG
Figure 2.9. Example Auxiliary Wall Adapter Connection
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Preliminary Rev. 0.5 | 11
Si3406x Family Data Sheet
Application Examples
3. Application Examples
The following diagrams demonstrate the ease of use and straightforward BOM of the Si3406x Powered Device ICs. Detailed reference
designs are available in Evaluation KIT User Guides. Also refer to "AN1130: Using the Si3406/Si34061/Si34062 PoE+ and Si3404 PoE
PD Controller In Isolated and Non-Isolated Designs".
VPOS
VOUT
RFREQ
CIN
RSENSE
COUT
CDET
VSS
syncFET
RFREQ
VPOS
RDET
HSO ISNS VSS
SWO
ct1
RDET
VSS
CT1
ct2
R1
R2
SYNCL
CT2
Si3406
FBL
SP1
sp1
EROUT
SP2
RCLASS
RCLASS
sp2
RCOMP
CCOMP
VNEG
VDD
C
VSS
VSS
VSS
VNEG
Figure 3.1. Si3406 Non-ISO Flyback Application Diagram
VPOS
VOUT
RFREQ
VSS
CIN
COUT
VIN
syncFET
GNDI
RFREQ
VPOS
VSS SWO
RDET
RDET
VT15
BIAS
CT1
CT2
SP1
SP2
CDET
Si34061
VSS
SYNCL
VDD
RCLASS
RCLASS
VDD
C
VIN
VNEG EXTHSW
HSO
ISNS EROUT
VSS
GNDI
VSS
RCOMP1
R1
R2
CCOMP1
RCOMP2
CCOMP2
RSENSE
VNEG
TLV431
EXTHSW
GNDI
VSS
VSS
*GNDI = ISOLATED GROUND
GNDI
Figure 3.2. Si34061 ISO Flyback Application Diagram
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Preliminary Rev. 0.5 | 12
Si3406x Family Data Sheet
Application Examples
VPOS
VOUT
RFREQ
VSS
CIN
COUT
syncFET
CDET
GNDI
ct1
BIAS
RFREQ
VPOS
VSS SWO
VT15
RDET
RDET
CT1
CT2
SP1
SP2
ct2
VSS
SYNCL
VDD
sp1
wake
mode
nsleep
Si34062
WAKE
MODE
NSLEEP
VDD
C
sp2
RCLASS
VSS
GNDI
RCLASS
VNEG
EROUT
LED
HSO ISNS
VSS
RCOMP1
LED
R1
R2
RCOMP2
CCOMP2
VNEG
CCOMP1
VDD
TLV431
GNDI
RSENSE
VSS
VSS
'wake'
GNDI
VOUT
wake
VDD
VOUT
GNDI
GNDI
VSS
mode
VDD
SLEEP
GNDI
VSS
VOUT
nsleep
GNDI
*GNDI = ISOLATED GROUND
VSS
Figure 3.3. Si34062 ISO Flyback Application Diagram
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Preliminary Rev. 0.5 | 13
Si3406x Family Data Sheet
Electrical Specifications
4. Electrical Specifications
Table 4.1. Absolute Maximum Ratings1
Type
Description
CT1–CT2 or SP1–SP2
Min
–100
–0.7
–0.7
–1
Max
100
100
120
1
Units
V
V
V
V
VNEG-VSS, VPOS- VNEG, HSO2, RDET3
SWO-VSS
ISNS, SWISNS
Voltage
Low Voltage pins: FBH3, EROUT, FBL,
NSLEEP, RCL2, RFREQ3, ASUP3, WAKE,
MODE, LED
–0.7
–0.7
6
V
V
Mid Voltage pins: SYNCL,VT15, EXTGD,
EXTHSW
18
Other Mid Voltage pin: V11
CT1, CT2, SP1, SP2, VPOS
CT1, CT2, SP1, SP2
–0.7
–TBD
–0.2
–65
12
TBD
0.2
V
A
A
Peak Current
DC Current4
Storage Temperature
150
85
Temperature
°C
Ambient Operating Temperature
–40
Note:
1. Unless otherwise noted, all voltages referenced to VSS. Permanent device damage may occur if the maximum ratings are excee-
ded. Functional operation should be restricted to those conditions specified in the operational sections of this data sheet. Expo-
sure to absolute maximum rating conditions for extended periods may adversely affect device reliability.
2. Voltage referenced to VNEG.
3. Voltage referenced to VPOS.
4. Higher dc current is possible in the application, but only utilizing external bridge diodes. Refer to reference design documentation
and AN1130 for further details.
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Preliminary Rev. 0.5 | 14
Si3406x Family Data Sheet
Electrical Specifications
Table 4.2. Recommended Operating Conditions
Symbol
Parameter (Condition)
Min
Typ
Max
Unit
VPORT
|CT1 – CT2| or |SP1 – SP2|
2.7
—
57
V
VNEG-VSS, VNEG-HSO, VPOS-
VSS
VHV_OP
2.7
—
—
57
0
V
V
VPOS referred low voltage pins:
RFREQ, RDET, FBH
VLV_OP
–5.5
VSS referred low voltage pins: VDD,
FBL, EROUT, ASUP, nSLEEP,
nT2P, ASUP, WAKE, MODE, LED
VLV_OP
0
3
—
—
5.5
—
V
V
VOH_DIG
VOH of ASUP and nT2P relative to
VSS.
VSS referred current sensing pins:
ISNS, SWISNS
VISNS_OP
–0.5
0
—
—
0.5
5.5
13
V
V
V
V
VNEG referred low voltage pins:
RCL
VLV_OP
VSS referred medium voltage pins
SYNCL, EXTGD, EXTHSW
VMV_OP
0
—
VSS referred medium voltage pin
VT151
VMV_VT15
12
14.5
16.5
On chip rectifier current on CT1,
CT2, SP1, SP2—steady state2
IRECT
VRECT
IRECT_PK
IAVG
—
—
—
—
—
—
1.8
—
176
—
mA
V
On chip rectifier voltage @ 200 mA,
2 diodes
Peak rectifier current Max 75 ms 5%
Duty Cycle3
231
600
683
mA
mA
mA
Allowable continuous current on
SWO, VSS, HSO, VNEG
—
Peak current on SWO, VSS, HSO,
VNEG Max 75 ms 5% Duty Cycle
IPEAK
—
Note:
1. VMV_VT15 is relevant for Si34061 and Si34062 only when an external auxiliary winding from the primary side of the transformer is
being used to improve power conversion efficiency. This can be left undriven, in which case an internal regulator will be used.
2. For Class 3 and above operation, use external diode bridge rectifiers to bypass the internal input diode bridge rectifiers.
3. The IEEE 802.3at specification allows for higher peak current for transients.
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Preliminary Rev. 0.5 | 15
Si3406x Family Data Sheet
Electrical Specifications
Table 4.3. Electrical Characteristics
Symbol
PoE PROTOCOL
Detection
VDET
Parameter (Condition)
Min
Typ
Max
Unit
Detection Voltage (at VPORT
)
2.7
—
10.1
V
Classification
VRESET
Classification Reset (at VPORT
)
0
14.5
0
—
—
—
—
—
—
—
2.81
20.5
4
V
VCLASS
Classification Voltage (at VPORT
Class 0 (RCLASS > 681 Ω)
)
V
mA
mA
mA
mA
mA
Class 1 (RCLASS = 140 Ω @ 1%)
Class 2 (RCLASS = 75 Ω @ 1%)
Class 3 (RCLASS = 48.7 Ω @ 1%)
Class 4 (RCLASS = 33.2 Ω @ 1 %)
9
12
IPortCLASS
17
26
36
20
30
44
Type 2 Classification
VMARK
Mark event voltage (at VPORT
Mark event current
)
6.9
—
10.1
4
V
IMARK
0.25
TBD
mA
Power On and UVLO
VUVLO_R
VUVLO_F
Hotswap closed and converter on
Hotswap open and converter off
—
—
37
32
—
—
V
V
Thermal Characteristics
Tshd
Thermal shutdown
—
—
160
20
—
—
°C
°C
THYST
Thermal shutdown hysteresis
On-Chip Transient Voltage Suppression/Protection
TVS protection activation voltage
TPROT
100
—
—
V
(VPOS-VNEG)
Hotswap Switch
Iinrush
Inrush current
100
—
170
—
200
600
—
mA
mA
mV
V
Maximum continuous operating cur-
rent
IMAXHSSW
VHSSW_ON
VHSSW_OFF
Switch ON voltage
—
380
3.5
Switch OFF voltage, HSSW goes to
overload cycle
—
—
Switch current limit in OVERLOAD
State
IOVL
8.7
14
—
10.5
20
12.4
26
mA
mA
mA
MPS signal request current level
threshold
IMPSth
External hotswap driver peak current
on EXTHSW pin
IEXT_DRV
—
10
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Preliminary Rev. 0.5 | 16
Si3406x Family Data Sheet
Electrical Specifications
Symbol
Parameter (Condition)
Min
Typ
Max
Unit
External hotswap driver voltage on
EXTHSW pin
VEXT_DRV
9
11
—
V
Wait time in OVERLOAD and type 2
inrush
TWAITHSSW
RONHSSW
80
96
116
2.9
ms
Ω
Internal hotswap drain-source resist-
ance while ON
0.65
1.5
DC-DC
ISWOPEAK
Peak current limit of internal FET
(SWO pin)
2.1
9
—
2.7
13
A
V
External FET driver voltage (EXTGD
pin)
VEXTGD
11
External FET driver peak current
(EXTGD pin)
IEXTGD
FOSCINT
FOSCEXT
DUC
—
—
—
250
—
500
—
mA
kHz
kHz
%
Using internal Oscillator
Using external Oscillator, tunable on
pin RFREQ
100
—
500
75
Output duty cycle of PWM
TBD
10.7
DCDC UVLO level (Minimum adapt-
er voltage)
VDCDCUVLO
10.2
11.3
V
FBH (referenced to VPOS) and FBL
(referenced to VSS) reference volt-
age
VFBREF
—
1.32
—
V
Operating voltage range of error in-
put
VEROUT
VISNS_OVC
VISNS_LC
1
—
4
V
Overcurrent limit voltage on ISNS
(ref. to VSS)
—
—
–270
–30
—
—
mV
mV
Low current limit voltage on ISNS
(ref. to VSS)
VSWISNSMAX
TSOFTSTART
RONDCDC
External FET current sense
Startup time
—
—
—
240
4
—
—
mV
ms
Ω
Internal DCDC switching FET drain-
source resistance while ON
0.9
1.2
Regulators
Override internal regulator with
transformer winding
VT15
13
—
16.5
V
VDD
VDDILIM
CREG
High accuracy 5 V
DC current limit of VDD
4.85
9.7
—
5.1
11.2
100
5.46
12.9
—
V
mA
nF
Filter capacitor on VDD and V11
LED pin max current, reduces
VDDILIM
IMAXLED
—
2
5
—
—
mA
mA
Digital output max current (NT2P),
reduces VDDILIM
IMAXDO
2.5
Power Dissipation
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Preliminary Rev. 0.5 | 17
Si3406x Family Data Sheet
Electrical Specifications
Symbol
PINTMAX
PMAX
Parameter (Condition)
DC-DC max power internal FET
Total chip power
Min
—
Typ
1.2
Max
1.5
Unit
W
—
TBD
TBD
W
Operating current (VPORT 57 V; 250
kHz)
IPortOP
—
3
4
mA
Package Thermal Characteristics
θJA-EFF
θJA-EFF
QFN20
QFN24
—
—
44
—
—
C°/W
C°/W
TBD
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Preliminary Rev. 0.5 | 18
Si3406x Family Data Sheet
Pin Descriptions
5. Pin Descriptions
Si3406 Pinout
(Top View)
Si34061 Pinout
(Top View)
Si34062 Pinout
(Top View)
20 19
24 23 22 21
16 15
20 19 18 17
20 19
24 23 22 21
1
2
3
4
5
6
18 VT15
FBH
EROUT
FBL
1
2
3
4
5
6
18 VT15
ISNS
EROUT
FBL
CT1
14
13
12
17
FBH
1
2
3
4
nT2P
17
16
15
14
13
nT2P
CT1
CT2
16
CT1
EROUT
FBL
VNEG
(ePad)
VNEG
(ePad)
VNEG
(ePad)
VPOS
VDD
CT2
VDD
15
14
13
CT2
VPOS
11 SP1
EXTHSW
VPOS
VDD
LED
ASUP
SP1
WAKE
SP1
7
8
9
10 11 12
5
6
7
8
9
10
7
8
9
10 11 12
Table 5.1. Pin Descriptions
Dir. Vrange
'06
'061
'062
Name
Ref
Description
Pins
Pins
Pins
24
1
24
SWISNS
ISNS
VSS
VSS
I
I
0–0.5 External FET peak current sense resistor voltage input
-0.5–0 Chip average current sense resistor input
20
1
1
2
3
FBH
VPOS
VSS
I
0–5
0–5
0–5
High side (VPOS referred) dcdc feedback (buck converter)
Error amplifier current output, compensation impedance input
2
2
3
EROUT
FBL
IO
I
3
VSS
Low side (ground referenced) dcdc feedback (flyback convert-
er)
4
4
5
4
5
VDD
LED
VSS
VSS
O
O
O
I
0–5
0–5
5V regulator output
Output to drive sleep LED
EXTHSW VNEG
0–11 External hotswap switch drive
6
WAKE
ASUP
nSLEEP
RDET
HSO
VSS
VSS
0–5
0–5
0–5
Wakeup from sleep mode
6
7
I
AUX auxiliary adapter present
Sleep, with pull-up, driven by open drain
5
6
7
8
9
7
8
VSS
I
8
VPOS
VNEG
VNEG
VPOS
IO
IO
IO
IO
0–100 Detection resistor
9
9
0–100 Hotswap switch output
10
11
10
11
RCL
0–5
0–5
Classification resistor
RFREQ
Oscillator frequency tuning resistor, tie to VPOS to select de-
fault freq
10
11
12
13
14
12
13
14
15
16
12
13
14
15
16
SP2
SP1
SP1
SP2
—
I
I
0 - 100 High-voltage supply input from spare pair; polarity-insensitive
0–100 High-voltage supply input from spare pair; polarity-insensitive
0–100 Rectified high-voltage supply positive rail
VPOS
CT2
IO
I
CT1
CT2
0–100 High-voltage supply input from main pair; polarity-insensitive
0 - 100 High-voltage supply input from main pair; polarity-insensitive
CT1
I
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Preliminary Rev. 0.5 | 19
Si3406x Family Data Sheet
Pin Descriptions
'06
'061
'062
Name
Ref
Dir. Vrange
Description
Pins
Pins
Pins
15
17
18
19
20
21
17
18
19
20
nT2P
VT15
VSS
VSS
VSS
VSS
VSS
O
I
0–5
Type II classification was successful
0–16.5 Dcdc transformer bias winding input
16
17
SYNCL
V11
O
IO
O
0–11 Gate driver for synchronous rectification FET
0–11 11 V regulator output for filter cap.
EXTGD
0–11 External FET gate drive.
When internal switching FET is in use, tie to VSS.
21
22
MODE
SWO
VSS
VSS
VSS
—
I
0–5
Controls MPS and LED switch behavior
18
19
22
23
O
0–120 Internal dcdc switch output (NMOS drain)
23
IO
IO
0
0
Dcdc converter primary ground
ePad
ePad
ePad
VNEG
—
Rectified high voltage supply ground
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Preliminary Rev. 0.5 | 20
Si3406x Family Data Sheet
Pin Descriptions
5.1 Detailed Pin Descriptions
Table 5.2. Circuit Equivalent and Description of Die Pads
Detailed Description
Pin Name
Circuit Detail
External dcdc switching FET peak current sense resistor input. The maxi-
mum current of the switching FET should correspond to voltage VSWISN-
SWISNS
.
SMAX
Average current sense resistor input. The resistor value will set the maxi-
mum allowed average current for the application. The overcurrent threshold
voltage VISNS_OVC. Note that this pin voltage goes below VSS.
ISNS
High side dcdc feedback input. Need to be tied to VPOS when not used.
See VFBREF.
FBH
dcdc converter error output; current out, voltage sense. Loop compensating
impedance should be connected here.
EROUT
IEROUT = (VFBH – VFBREF) x 50 μA or
IEROUT = (VFBL – VFBREF) x 50 μA
Low side dcdc feedback input. Need to be tied to VSS when not used. See
VFBREF
FBL
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Preliminary Rev. 0.5 | 21
Si3406x Family Data Sheet
Pin Descriptions
Pin Name
Detailed Description
Circuit Detail
Regulated 5 V relative to VSS. There is no foldback characteristic, reaching
VDDILIM the output voltage decreases.
VDD
The regulator needs CREG external capacitance.
LED driver output Max current is IMAXLED
LED
WAKE
ASUP
Wake-up input pin for sleep mode, used only in Si34062.
Auxiliary supply adapter is present. Enables the operation of the dcdc con-
troller without PoE supply being present.
nSLEEP
Sleep function input, see description in Sleep mode section.
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Preliminary Rev. 0.5 | 22
Si3406x Family Data Sheet
Pin Descriptions
Pin Name
Detailed Description
Circuit Detail
Classification resistor input. For class 0 this pin can be left floating. Pin is
active only at time of classification.
RCL
Used for adjusting the oscillator frequency.
RFREQ
The frequency is inversely proportional to the value of the connected resis-
tor.
SP1, SP2
CT1, CT2
Main power inputs, goes to diode bridge producing VPOS and VNEG.
VPOS,
VNEG
Main chip power output generated by the diode bridge. Note that VNEG
(the ePad on the bottom of the chip) also provides thermal relief.
Pin main function is digital output; it is low if Type 2 classification was suc-
cessful and the application is allowed to draw class 4 current.
nT2P
Output current is IMAXDO, but the load (e.g. an LED) should connected to
VDD not VSS; otherwise, it can cause false operation.
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Preliminary Rev. 0.5 | 23
Si3406x Family Data Sheet
Pin Descriptions
Pin Name
Detailed Description
Circuit Detail
Hotswap Switch Output. The switch shorts the VNEG and HSO pins, and in-
cludes several other functions. See hotswap switch section for details.
HSO
EXTGD: Optional external switch driver of the dc/dc converter. When the in-
ternal switch is used this pin should be tied to VSS. This driver controls the
external switch with 10 V logic level, relative to VSS.
EXTGD,
SYNCL
SYNCL: Optional synchronous rectifier switch driver of the dc/dc converter.
When not used the pin must be left floating. This driver controls the external
synchronous switch with 10 V logic level, relative to VSS.
Optional external hotswap switch output. The maximum current of the inter-
nal hotswap switch is IMAXHSSW, for higher currents an external NMOS FET
should be used parallel to the internal HSSW (VNEG-HSO). When EXTGD
is not used the pin should be tied to VNEG. This driver controls the external
switch with 10 V logic level, relative to VNEG.
EXTHSW
The user has to tie the RDET resistor between this pin and VPOS. During
detection, a high voltage switch pulls down RDET to VNEG. After detection,
the reference block uses RDET as absolute chip current reference, forcing
–750 mV relative to VPOS, creating 30 µA for the internal blocks.
RDET
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Preliminary Rev. 0.5 | 24
Si3406x Family Data Sheet
Pin Descriptions
Pin Name
Detailed Description
Circuit Detail
VT15 is input for an optional 15 V supply generated by an auxiliary trans-
former bias winding. If the bias winding voltage is lower than VT15, the in-
ternal 15 V coarse regulator will provide the current for the 11 V regulator.
VT15,
V11
The V11 pin is for filtering capacitor for the 11 V regulator. A capacitor of
value CREG is required.
MODE
MPS mode control, used in Si34062.
SWO
Dcdc converter switching transistor drain output, Vmax = 120 V.
VSS
DC-DC converter ground.
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Preliminary Rev. 0.5 | 25
Si3406x Family Data Sheet
Packaging
6. Packaging
6.1 Package Outline: Si3406
The figure below illustrates the package details for the Si3406. The table lists the values for the dimensions shown in the illustration.
Figure 6.1. 20-Pin, QFN Package
Table 6.1. Package Diagram Dimensions
Dimension
Min
0.80
0.00
0.25
Nom
0.85
Max
0.90
0.05
0.35
A
A1
b
0.02
0.30
D
5.00 BSC.
2.70
D2
e
2.60
2.80
0.80 BSC.
5.00 BSC.
2.70
E
E2
L
2.60
0.50
0.00
—
2.80
0.60
0.10
0.10
0.10
0.08
0.10
0.55
L1
aaa
bbb
ccc
ddd
—
—
—
—
—
—
—
—
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Preliminary Rev. 0.5 | 26
Si3406x Family Data Sheet
Packaging
Dimension
Min
Nom
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VHHB-1.
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Preliminary Rev. 0.5 | 27
Si3406x Family Data Sheet
Packaging
6.2 Land Pattern: Si3406
The figure below illustrates the land pattern details for the Si3406. The table lists the values for the dimensions shown in the illustration.
Figure 6.2. 20-Pin, QFN Land Pattern
Table 6.2. Land Pattern Dimensions
Dimension
Max
4.70
4.70
0.35
2.80
1.00
2.80
0.80
C1
C2
X1
X2
Y1
Y2
e
Note:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60mm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.5 | 28
Si3406x Family Data Sheet
Packaging
6.3 Package Outline: Si34061/62
The figure below illustrates the package details for the Si34061/62. The table lists the values for the dimensions shown in the illustra-
tion.
Figure 6.3. 24-Pin, QFN Package
Table 6.3. Package Diagram Dimensions
Symbol
Min
0.80
0.00
0.25
Nom
0.85
Max
0.90
0.05
0.35
A
A1
b
0.02
0.30
A3
D
0.20 REF
5.00 BSC.
0.65 BSC.
5.00 BSC.
e
E
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Preliminary Rev. 0.5 | 29
Si3406x Family Data Sheet
Packaging
Symbol
D2
Min
2.90
2.90
0.35
0.20
Nom
3.00
3.00
0.40
—
Max
3.10
3.10
0.45
—
E2
L
K
aaa
bbb
ccc
ddd
eee
fff
0.15
0.10
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.5 | 30
Si3406x Family Data Sheet
Packaging
6.4 Land Pattern: Si34061/62
The figure below illustrates the land pattern details for the Si34061/62. The table lists the values for the dimensions shown in the illus-
tration.
Figure 6.4. 24-Pin, QFN Land Pattern
Table 6.4. Land Pattern Dimensions
Dimension
mm
4.90
4.90
0.35
3.10
0.85
3.10
0.65
C1
C2
X1
X2
Y1
Y2
e
Note:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted
2. This land pattern design is based on the IPC-7351 guidelines
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release
2. The stencil thickness should be 0.125 mm (5 mils)
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.5 | 31
Si3406x Family Data Sheet
Top Markings
7. Top Markings
7.1 Si3406 Top Marking
Figure 7.1. Si3406 Top Marking
Table 7.1. Si3406 Top Marking Explanation
Mark Method:
Pin 1 Mark:
Laser
Circle = 0.50 mm Diameter (Lower-Left Corner)
2.0 Point (28 mils)
Font Size:
Line 1 Mark Format:
Line 2 Mark Format:
Device Part Number
Si3406
Device Type
A = Device Revision A
G = Extended temperature range
M = QFN package
Line 3 Mark Format:
Line 4 Mark Format:
TTTTTT
Manufacturing Trace Code (assigned at assembly)
Assembly Year
YY = Year
WW = Work Week
Assembly Week
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Preliminary Rev. 0.5 | 32
Si3406x Family Data Sheet
Top Markings
7.2 Si34061 Top Marking
Figure 7.2. Si34061 Top Marking
Table 7.2. Si34061 Top Marking Explanation
Mark Method:
Pin 1 Mark:
Laser
Circle = 0.50 mm Diameter (Lower-Left Corner)
2.0 Point (28 mils)
Font Size:
Line 1 Mark Format:
Line 2 Mark Format:
Device Part Number
Si34061
Device Type
A = Device Revision A
G = Extended temperature range
M = QFN package
Line 3 Mark Format:
Line 4 Mark Format:
TTTTTT
Manufacturing Trace Code (assigned at assembly)
Assembly Year
YY = Year
WW = Work Week
Assembly Week
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Preliminary Rev. 0.5 | 33
Si3406x Family Data Sheet
Top Markings
7.3 Si34062 Top Marking
Figure 7.3. Si34062 Top Marking
Table 7.3. Si34062 Top Marking Explanation
Mark Method:
Pin 1 Mark:
Laser
Circle = 0.50 mm Diameter (Lower-Left Corner)
2.0 Point (28 mils)
Font Size:
Line 1 Mark Format:
Line 2 Mark Format:
Device Part Number
Si34062
Device Type
A = Device Revision A
G = Extended temperature range
M = QFN package
Line 3 Mark Format:
Line 4 Mark Format:
TTTTTT
Manufacturing Trace Code (assigned at assembly)
Assembly Year
YY = Year
WW = Work Week
Assembly Week
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Preliminary Rev. 0.5 | 34
Si3406x Family Data Sheet
Revision History
8. Revision History
Revision 0.5
February, 2018
• Updated 2. System Overview and 3. Application Examples.
• Added theory of operation and application content.
Updated Table 4.1 Absolute Maximum Ratings1 on page 14, Table 4.2 Recommended Operating Conditions on page 15, and Table
4.3 Electrical Characteristics on page 16.
•
• Clarified multiple parameters.
• Added 5.1 Detailed Pin Descriptions.
• Added 6. Packaging including outline and land pattern.
Revision 0.1
August, 2016
• Initial release.
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Preliminary Rev. 0.5 | 35
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
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