SI3461-E01-GMR [SILICON]
Power Management Circuit;
| 型号： | SI3461-E01-GMR |
| 厂家： | 
SILICON |
| 描述： | Power Management Circuit |
| 文件： | 总24页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3461
SINGLE-PORT IEEE 802.3AT POE/POE+ PSE INTERFACE
Features
Pin Assignments
TM
IEEE-compliant disconnect
Inrush current control
Short-circuit output fault
protection
LED status signal (detect,
power good, output fault)
IEEE 802.3at compliant PSE
Autonomous operation requires
no host processor interface
Si3461
Complete reference design
available, including Si3461
controller and schematic:
1
2
10
9
UNH Interoperability Test Lab
CLSMARK
DC1
STATUS
ISENSE
RST
report available
Low-cost BOM
Compact PCB footprint
Operates directly from a +50 V
isolated supply
Supports up to 30 W maximum
output power (Class 4)
Extended operating range
3
8
VDD
GND
(–40 to +85 °C)
7
4
5
DC2
VSENSE
DETA
11-Pin Quad Flat No-Lead
6
CLSMODE
(QFN) package
Tiny 3x3 mm PCB footprint;
Robust 3-point detection algorithm
eliminates false detection events
11-pin QFN (3x3 mm)
RoHS-compliant
Top View—Pads on bottom of package
Applications
IEEE 802.3at endpoints and
Set-top boxes
midspans
FTTH media converters
Environment A and B PSEs
Embedded PSEs
Cable modem and DSL
gateways
Description
The Si3461 is a single-port power management controller for IEEE
802.3at-compliant Power Sourcing Equipment (PSE). The Si3461 can
be powered from a 50 V input using a shunt regulator, or, to save
power, it can be powered from 50 V and 3.3 V power supplies. The
IEEE-required Powered Device (PD) detection feature uses a robust
3-point algorithm to avoid false detection events. The Si3461's
reference design kit also provides full IEEE-compliant classification
and PD disconnect. Intelligent protection circuitry includes input under-
voltage lockout (UVLO), classification-based current limiting, and
output short-circuit protection. The Si3461 is designed to operate
completely independently of host processor control. An LED status
signal is provided to indicate the port status, including detection,
power good, and output fault event information. The Si3461 is pin-
programmable to support four available power levels, endpoint and
mid-span applications, and auto-retry or restart after disconnect
functions. A comprehensive reference design kit is available (Si3461-
EVB), including a complete schematic and bill of materials.
Rev. 1.0 5/10
Copyright © 2010 by Silicon Laboratories
Si3461
Si3461
2
Rev. 1.0
Si3461
TABLE OF CONTENTS
Section
Page
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Si3461 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1. Si3461-EVB Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. PSE Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Typical Si3461-EVB Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4. Si3461-EVB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.2. Operating Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
5. Operating Mode Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.1. Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.2. Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.3. Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.4. Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.5. Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.6. UVLO and OVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.7. Status LED Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6.1. Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6.2. External Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6.3. Input DC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7. Si3461 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
9. Package Outline: 11-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
9.1. Solder Paste Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
9.2. PCB Landing Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
9.3. Marking Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Rev. 1.0
3
Si3461
1. Typical Application Schematic
+50V
VIN
+
+50V
Optional 3.3V regulator
VDD
+3.3V
Detect
&
Mark
VOUT
48 V
VDD
CLSMARK
DC1
DC2
CLSMODE
PSE
output
Classification
&
Gate drive
Si3461
(to port
magnetics)
DETA
VSENSE
RST
ISENSE
STATUS
DETECT
FAULT
GND
PGOOD
GND
-
GND
Note: Refer to the Si3461-EVB User Guide for complete schematic details
Figure 1. Si3461 Typical Application Schematic
4
Rev. 1.0
Si3461
2. Si3461 Electrical Specifications
The following specifications apply to the Si3461 controller. Refer to Tables 4 and 5 and the Si3461-EVB User's
Guide and schematics for additional details about the electrical specifications of the Si3461-EVB reference design.
Table 1. Recommended Operating Conditions
Symbol
Test Conditions
Min
Typ
Max
Unit
Description
T
–40
—
25
75
+85
—
°C
Operating Temperature Range
Thermal Impedance
A
No airflow
°C/W
JA
During all operating modes
(detect, classification, disconnect)
VDD
2.7
3.3
3.6
V
VDD Input Supply Voltage
Table 2. Absolute Maximum Ratings*
Parameter
Conditions
Max Rating
Unit
–55 to +125
–65 to +150
–0.3 to 5.8
–0.3 to 4.2
°C
°C
V
Ambient Temperature Under Bias
Storage Temperature
VDD > 2.2 V
Voltage on RST or any I/O pin with respect to GND
Voltage on VDD with respect to GND
V
Maximum Total Current through VDD
and GND
500
100
mA
mA
Maximum Output Current into CLSMARK, DC1,
DC2, CLSMODE, STATUS, ISENSE, RST,
VSENSE, DETA (any I/O pin)
Human Body Model
–2 kV to +2 kV
260
V
ESD Tolerance
Soldering, 10 seconds maximum
°C
Lead Temperature
*Note: Stresses above those listed in this table may cause permanent device damage. This is a stress rating only, and
functional operation of the devices at these or any conditions above those indicated in the operational listings of this
specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Rev. 1.0
5
Si3461
Table 3. Electrical Characteristics*
Symbol
Test Conditions
Min
Typ
Max
Unit
Description
Digital Pins: CLSMARK, DC1, DC2, CLSMODE, STATUS (Output mode), RST
I
= –3 mA
= –10 µA
0.7 x VDD
VDD – 0.1
—
—
—
—
OH
V
V
V
Output High Voltage
Output Low Voltage
OH
I
OH
I
= 8.5 mA
= 10 µA
—
—
—
—
0.6
0.1
OL
V
OL
I
OL
V
Any digital pin
Any digital pin
0.7 x VDD
V
V
Input High Voltage
Input Low Voltage
Input Leakage Current
IH
V
I
—
—
—
0.6
—
IL
V
= 0 V
IN
±1
µA
IL
Analog Pins: ISENSE, VSENSE, DETA, STATUS (Input mode)
—
—
5
—
—
pF
µA
Input Capacitance
I
±1
Input Leakage Current
IL
*Note: VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified.
6
Rev. 1.0
Si3461
2.1. Si3461-EVB Performance Characteristics
When implemented according to the recommended external component and layout guidelines for the Si3461-EVB,
the Si3461 enables the following performance specifications in single-port PSE applications. Refer to the Si3461-
EVB User's Guide and schematics for details.
Table 4. Selected Electrical Specifications (Si3461-EVB)
Typ1
Symbol
Test Conditions
Min
Max
Unit
Description
Power Supplies
VIN Input Supply
Range
VIN
–40 to +85 °C
ambient range
45
—
50
42
60
3.3
49
57
45
V
V
V
V
V
VIN Input UVLO
Voltage
UVLO
OVLO
VDD
UVLO turn-off
voltage at VIN
VIN Input OVLO
Voltage
OVLO turn-off
voltage at VIN
57
—
VDD Supply Voltage
Range
Si3461 supply
voltage range
3.15
—
3.45
—
Output Supply
Voltage
VOUT
PSE output
voltage at VIN = 50 V and
IOUT = 350 mA
Supply Current
IIN
Current into the VDD node
(not including shunt regulator)
—
—
8.0
10.5
—
mA
V
Detection Specifications
Detection Voltage
VDET
Detection point 1
Detection point 2
Detection point 3
4.0
8.0
4.0
Detection Current
IDET
Short circuit
—
—
3
mA
Minimum Signature
Resistance
RDETmin
15
17
19
k
Maximum Signature
Resistance
RDETmax
26.5
29
33
k
Classification Specifications
Classification Voltage
VCLASS
ICLASS
0 mA < ICLASS < 45 mA
15.5
55
—
20.5
95
V
Classification Cur-
rent Limit
Measured with 100
75
mA
across VOUT
Notes:
1. Typical specifications are based on an ambient operating temperature of 25 °C and VIN = +50 V unless otherwise
specified.
2. Absolute classification current limits are configurable. See “5.2. Classification” and "5.3. Power-Up" on page 13.
3. Typical ICUT values are adjusted according to the input voltage to provide power limiting with approximately 5% margin
against the 802.3 requirements. The maximum ICUT values are consistent with the IEEE requirement that Icut
maximum is less than 400 mA at the minimum allowed Vout of 44 V or 684 mA for PoE+ mode at the minimum allowed
Vout of 50 V.
4. Overload current is within limits, typically in less than 1 ms.
Rev. 1.0
7
Si3461
Table 4. Selected Electrical Specifications (Si3461-EVB) (Continued)
Typ1
—
Symbol
ICLASS REGION
Test Conditions
Min
Max
Unit
Description
Classification
Current Region
_
Class 0
Class 1
Class 2
Class 3
Class 4
0
8
5
mA
mA
mA
mA
mA
V
—
13
21
31
45
10
9
16
25
35
7
—
—
—
Mark Voltage
Mark Current
VMARK
8.5
—
IMARK_LIM
Short circuit
—
mA
Protection and Current Control
Overload Current
Threshold2,3
ICUT
Class 0 and
Class 4 PoE
15,400/VOUT 16,170/VOUT 17,600/VOUT mA
Class 1
4,000/VOUT
7,000/VOUT
4,200/VOUT
7,350/VOUT
4,600/VOUT
8,000/VOUT
mA
mA
Class 2
Class 3
15,400/VOUT 16,170/VOUT 17,600/VOUT mA
30,000/VOUT 31,500/VOUT 34,200/VOUT mA
Class 4 PoE+
Overload Current
Limit4
ILIM
Class 0/1/2/3 and Class 4
PoE; Output = 100 across
VOUT
400
425
450
mA
ILIM PoE+
684
50
750
60
825
75
mA
ms
Class 4 PoE+; Output = 50
across VOUT
Overload Time
TLIM
Class 0/1/2/3 and Class 4
PoE; Output = 100 across
VOUT
Class 4 PoE+;
Output = 50 across VOUT
14
5
17
20
10
ms
Disconnect Current
IMIN
Disconnect current
7.5
mA
Efficiency
—
—
System Efficiency
(PIN @ VIN) to
93
%
(POUT @ VOUT
)
Notes:
1. Typical specifications are based on an ambient operating temperature of 25 °C and VIN = +50 V unless otherwise
specified.
2. Absolute classification current limits are configurable. See “5.2. Classification” and "5.3. Power-Up" on page 13.
3. Typical ICUT values are adjusted according to the input voltage to provide power limiting with approximately 5% margin
against the 802.3 requirements. The maximum ICUT values are consistent with the IEEE requirement that Icut
maximum is less than 400 mA at the minimum allowed Vout of 44 V or 684 mA for PoE+ mode at the minimum allowed
Vout of 50 V.
4. Overload current is within limits, typically in less than 1 ms.
8
Rev. 1.0
Si3461
2.2. PSE Timing Characteristics
When implemented in accordance with the recommended external components and layout guidelines, the Si3461
controller enables the following typical performance characteristics in single-port PSE applications. Refer to the
Si3461-EVB applications note, schematics, and user's guide for more details.
Table 5. PSE Timing
Description
Symbol
Test Conditions
Min
Typ
Max
Unit
—
Endpoint Detection
Delay Cycle
Time from PD connection to port to
completion of detection process.
t
90
—
460
—
ms
DET_CYCLE
Detection Time
Time required to measure PD
signature resistance.
t
90
60
ms
ms
DETECT
—
—
—
—
Classification Delay
Cycle
Class 0/1/2/3;
Time from successful detect mode
to classification complete.
t
CLASS_CYCLE
Class 4, two event classification;
Time from successful detect mode
to classification complete.
99
ms
—
—
—
—
—
—
Classification Time
Class 0/1/2/3 and Class 4 PoE;
Class 4 PoE+
30
69
ms
ms
t
CLASS
Power-Up Turn-On
Delay
Class 0/1/2/3 and Class 4 PoE;
Time from when a valid detection is
76
ms
completed until V
power is
OUT
applied
t
PWRUP
—
—
Class 4 PoE+;
Time from when a valid detection is
112
ms
s
completed until V
power is
OUT
applied
—
—
—
—
Midspan Detect Back-
off Time
t
2.0
BOM
Error Delay Time
Time from error to restart of detec-
tion in auto-restart mode.
T
2.0
—
s
ed
—
Disconnect Delay
350
ms
t
DC_DIS
Note: These typical specifications are based on an ambient operating temperature of 25 °C and VIN = +50 V.
Rev. 1.0
9
Si3461
3. Typical Si3461-EVB Waveforms
Note: Voltages are negative going with respect to the positive input.
Powering a PoE+ Device
Powering a PoE Device
Detection Time
Ch1: PoE output voltage referenced to the +50V rail
Ch1: PoE output voltage referenced to the +50V rail
Ch1: PoE output voltage referenced to the +50V rail
Mark Pulse
Detection
Detection
g
Two event classification
Classification
TDETECT
Power-on
Power-on
Classification and Power-up
Delay PoE+
Classification and Power-up
Delay PoE
Midspan Backoff after bad
Classification result
Ch1: PoE output voltage referenced to the +50V rail
Ch1: PoE output voltage referenced to the +50V rail
Detection
Detection
tCLASS_CYCLE
tCLASS_CYCLE
tBOM
Classification
tPWRUP
Classification
tPWRUP
PoE+ Current Limit Response
PoE Current Limit Response
Overload During Classification
tLIM
tLIM
PoE+
PoE
Figure 2. Typical Si3461-EVB Waveforms
10
Rev. 1.0
Si3461
4. Si3461-EVB Functional Description
In combination with low-cost external components, the Si3461 controller provides a complete PSE solution for
embedded PoE applications. The Si3461-EVB reference design operates from a +50 V isolated power supply and
delivers power to the powered device through a FET switch without controlling the output voltage while in the
power-on state.
Refer to the Si3461-EVB User's Guide and schematics for descriptions in the following sections.
The basic sequence of applying power is shown in Figure 3. Following is the description of the function that must
be performed in each phase.
Ch1: PoE output voltage referenced to the +50V rail
-2.8V
-10V
Detection
-15.5V
-20.5V
Classification
-44V
Power-on
-57V
tCLASS_CYCLE
tPWRUP
tDET_CYCLE
Figure 3. Basic Power-up Sequence
Rev. 1.0
11
Si3461
4.1. Reset State
At power-up or if reset is held low, the Si3461 is in an inactive state with the pass FET Q4 off.
4.2. Operating Mode Configuration
At power-up, the Si3461 reads the voltage on the STATUS pin, which is set by a DIP switch and a resistor network.
The STATUS pin voltage level configures all of the Si3461's operating modes as summarized in Table 6.
Table 6. Operating Modes1,2,3,4
STATUS
Operating Mode
Restart Action on Fault or
Pin Voltage (V)
PSE Type
Midspan/
Endpoint
Available
Power (W)
Overload Event Condition
< 0.122
1
1
1
2
1
1
1
2
1
1
1
2
1
1
1
2
Midspan
Midspan
Midspan
Midspan
Midspan
Midspan
Midspan
Midspan
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Restart after disconnection
Restart after disconnection
Restart after disconnection
Restart after disconnection
Auto restart after 2 s
4
7
0.122 to 0.338
0.338 to 0.548
0.548 to 0.756
0.756 to 0.961
0.961 to 1.162
1.162 to 1.366
1.366 to 1.575
1.575 to 1.784
1.784 to 1.990
1.990 to 2.196
2.196 to 2.407
2.407 to 2.618
2.618 to 2.838
2.838 to 3.044
> 3.044
15.4
30
4
Auto restart after 2 s
7
Auto restart after 2 s
15.4
30
4
Auto restart after 2 s
Restart after disconnection
Restart after disconnection
Restart after disconnection
Restart after disconnection
Auto restart after 2 s
7
15.4
30
4
Auto restart after 2 s
7
Auto restart after 2 s
15.4
30
Auto restart after 2 s
Notes:
1. After power-up, the STATUS pin drives the base of an NPN transistor that controls an LED.
2. There is a trade-off in selecting the mode setting resistor values between voltage step accuracy and additional worst-
case supply current. For high-value resistors, the base current will alter the voltage steps while low-value resistors may
place higher load on the STATUS pin while driving the LED. The suggested resulting parallel resistance used by the
Si3461-EVB is 2.0 k.
3. Each mode setting resistor should be connected either to GND or +3.3 V through the DIP switch. Care should be taken
not to short the +3.3 V supply to GND.
4. A reset is required after a DIP switch position change for the new mode to take effect.
12
Rev. 1.0
Si3461
5. Operating Mode Sequencing
5.1. Detection
After power-up the Si3461 enters the detection state with the pass FET off. Prior to turning the FET on, a valid
detection sequence must take place.
According to the IEEE specifications, the detection process consists of sensing a nominal 25 k signature
resistance in parallel with up to 0.15 µF of capacitance. To eliminate the possibility of false detection events, the
Si3461-EVB reference design performs a robust 3-point detection sequence by varying the voltage across the load
that connects to the +50 V supply rail and returns to GND via D3, Q14, R26, and R37. R37 serves as a current
sensing resistor, and the Si3461 monitors the voltage drop across it during the detection process.
At the beginning of the detection sequence, V
is at zero; then, it is varied from 4 to 8 V and then back to 4 V for
OUT
20+20+50 ms at each respective level. If the PD's signature resistance is in the RGOOD range of 17 to 29 k, the
Si3461 proceeds to classification and power-up. If the PD resistance is not in this range, the detection sequence
repeats continuously.
Detection is sequenced approximately every 400 ms for endspan and 2.2 seconds for midspan configurations and
repeats until RGOOD is sensed, indicating a valid PD has been detected. The STATUS LED (D2) is flashed at a
rate of about 1.5 Hz to indicate the PSE is searching for a valid PD.
5.2. Classification
After a valid PD is detected, the PSE interrogates the PD to find its power requirement. This procedure is called
classification and may be carried out in different ways. The Si3461 implements the one-event classification for
Type1 PDs and the two-event classification for Type2 PDs.
For one-event classification, the pass FET Q4 is turned on and programmed for an output voltage of 18 V with a
current limit of 75 mA for 30 ms. For the two-event classification, the 18 V pulse is output twice with an 8.5 V
amplitude mark pulse for 10 ms between the two classification pulses. The current measured at the ISENSE input
during the classification process determines the class level of the PD (refer to Table 4 on page 7 for current
ranges).
If the Si3461-EVB has 30 W of available power, it attempts to classify a Type2 PD first by the two-event method. If
the detected class is other than Class 4 or there is less than 30 W of power available, the Si3461 tries to classify a
Type1 PD using the one-event method.
If the class level of the PD is not within the supported range as set by the initial voltage on the Si3461's STATUS
pin (refer to the Operating Mode Configuration section above), an error is declared, and the LED blinks rapidly at a
10 Hz rate. This is referred to as classification-based power denial. If the class level is in the supported range, the
Si3461 proceeds to power-up. This is referred to as classification-based power granting.
If the classification level is at a greater power than can be supported based on the voltage read by the STATUS pin
during start-up, an error condition is reported by flashing the LED at a 10 Hz rate for two seconds before the state
machine goes back to the detection cycle.
5.3. Power-Up
After successful classification, the pass FET is turned on with an initial current limit of 425 mA (for all PD classes),
and the respective ILIM values (indicated in Table 4) take effect after the FET is fully turned on. After power-up is
complete, power is applied to V
as long as there is not an overcurrent fault, disconnect, or input undervoltage
OUT
(UVLO) or overvoltage (OVLO) condition. The STATUS LED is continuously lit when power is applied.
If the output power exceeds the level of the power requested during classification, the Si3461 will declare an error
and shut down the port, flashing the LED rapidly to indicate the error. Depending on the initial voltage on the
STATUS pin, the Si3461 will wait either 2.2 seconds or until the PD has been disconnected before it enters the
detection phase again to look for a valid load.
Rev. 1.0
13
Si3461
5.4. Overload Protection
The Si3461 implements a two-level overload protection scheme. The output current is limited to ILIM, and the
output is shut down if the current exceeds ICUT for more than 60 ms. If current limitation persists for more than
15 ms in case of PoE+ Class 4 loads, the output is shut down to protect the pass FET. Current limit values are
dynamically set according to the power level granted during the classification process and the effective output
voltage (refer to Table 4 on page 7 for current limit values).
A special 425 mA current limit applies until the FET is fully turned on. If the FET does not fully turn on in the first
75 ms due to an overload condition, an error is declared. The maximum time that the 425 mA inrush current is
supplied is about 70 ms due to a 5 ms period to initially ramp the FET gate voltage.
The overload protection is implemented using a timer with a timeout set to 60 ms. If the output current exceeds the
I
threshold, the timer counts up; otherwise, if the output current drops below ICUT, the timer counts down
CUT
towards zero at 1/16th the rate. If the timer reaches the set timeout, an overcurrent fault is declared; the channel is
shut down (by turning off the external pass FET), and the status LED flashes rapidly at a rate of 10 Hz.
If the Si3461 was configured in the “automatic restart” mode during start-up, it will automatically resume the
detection process after 2.2 seconds. In the “restart after disconnect” mode of operation, the status LED will flash
rapidly, and the Si3461 will not resume detection until it senses a resistance higher than 150 k. This condition can
normally be achieved by removing the Ethernet cable from the Si3461-EVB's RJ-45 jack labeled “PoE”. Then, the
detection process begins; the status LED blinks at a rate of 1.5 Hz, and the Si3461 is allowed to go into
classification and power-up mode if a valid PD signature resistance is detected.
5.5. Disconnect
The Si3461 implements a robust disconnect algorithm. If the output current level drops below 7.5 mA typical for
more than 350 ms, the Si3461 declares a PD disconnect event, and the pass FET is turned off. The Si3461
automatically resumes the detection process after 500 ms.
5.6. UVLO and OVLO
The Si3461-EVB reference design is optimized for 50 V nominal input voltages (44 V minimum to 57 V maximum).
If the input voltage drops below 42 V, a UVLO condition is declared, which generates the error condition (LED
flashing rapidly). An undervoltage event is a fault condition reported through the status LED as a rapid blinking of
10 flashes per second. In the same way, if the input voltage exceeds 60 V, an OVLO condition is declared. In both
cases, the output is shut down.
The UVLO and OVLO conditions are continuously monitored in all operating states.
5.7. Status LED Function
During the normal detection sequence, the STATUS LED flashes at approximately 1.5 times per second as the
detection process continues. After successful power up, the LED glows continuously. If there is an error condition
(i.e., class level is beyond programmed value or a fault or over current condition has been detected), the LED
flashes rapidly at 10 times per second. This occurs for two seconds for normal error delay, and the detection
process will automatically start again after 2.2 s unless a “restart after disconnect condition” was set during the
initial configuration. Power will not be provided until an open circuit condition is detected. Once the Si3461-EVB
detects an open circuit condition, the LED blinks at 1.5 times per second.
If the Powered Device (PD) is disconnected so that a disconnect event occurs, the LED will start flashing at 1.5
times per second once the detect process resumes.
14
Rev. 1.0
Si3461
6. Design Considerations
6.1. Isolation
The Si3461-EVB's PSE output power at VOUT is not isolated from the input power source (VIN). Isolation of PSE
output power requires that the input be isolated from earth ground. Typically, an ac-to-dc power supply is used to
provide the 50 V power so the output of this supply is isolated from earth ground.
6.2. External Component Selection
Detailed notes on external component selection are provided in the Si3461-EVB User's Guide schematics and
BOM. In general, these recommendations must be followed closely to ensure output power stability, surge
protection (surge protection diode), and overall IEEE 802.3 compliance.
6.3. Input DC Supply
The Si3461-EVB reference design requires an isolated 50 V nominal dc input voltage (with a minimum of 44 V and
a maximum of 57 V).
The input power supply should be rated for at least 10% higher power level than the output power level chosen.
This is primarily to account for the losses in the current-sensing resistor, the pass FET, and the series protection
diode of the Si3461-EVB reference design. For example, to support a Class 0 PSE, the input supply should be
capable of supplying at least 16.94 W (15.4 W x 1.10 = 16.94 W).
The power supply also needs to be able to source 425 mA for 60 ms for normal operation or 885 mA for 15 ms for
high power (PoE+) operation.
The Si3461-EVB reference design does not regulate the output voltage during the power-on state; therefore, the
input dc supply should meet the ripple and noise specifications of the IEEE 802.3 standard.
The Si3461-EVB reference design includes an optional 3.3 V shunt regulator that uses the 50 V input to generate
the 3.3 V supply voltage for the Si3461 controller. Alternatively, an external 3.3 V power source may be used.
Rev. 1.0
15
Si3461
7. Si3461 Pin Descriptions
Si3461 pin functionality is described in Table 7. Note that the information applies to the Si3461 device pins, while
the Si3461-EVB User's Guide describes the inputs and outputs of the evaluation system.
Refer to the complete Si3461-EVB schematics and BOM listing for information about the external components
needed for the complete PSE application circuit.
Si3461
1
2
3
4
5
10
9
CLSMARK
DC1
STATUS
ISENSE
RST
8
VDD
GND
7
DC2
VSENSE
DETA
6
CLSMODE
11-pin QFN (3x3 mm)
Top View—Pads on bottom of package
Table 7. Si3461 Pin Functionality
Pin #
Pin Name
Pin Type
Pin Function
Logic high on this output increases the current capability of the
detection circuitry while used for mark pulse generation. Refer to
the Si3461-EVB schematics.
1
CLSMARK
Digital output
This is a PWM output providing the dc control voltage for the
detection circuitry. It is also combined with the DC2 output in a
ratio of 1:256 to provide the gate control voltage of the pass FET.
2
DC1
Digital output
3
4
VDD
DC2
Power
3.3 V power supply input.
This is a PWM output that (combined with the DC1 output) pro-
vides the gate control voltage of the pass FET with high resolution.
Digital output
This is an open drain output. When high, it enables the feedback
path controlling the 18 V classification voltage.
5
6
CLSMODE
DETA
Digital output
Analog input
DETA is an analog input pin. During the detection process, the
DC1 pin duty cycle is varied to generate filtered dc voltages
across the load, and the voltage drop across a current sensing
resistor is measured through the DETA input.
7
8
VSENSE
RST
Analog input
Digital input
VSENSE is an analog input used for sensing the input dc voltage.
Active low reset input. When low, it places the Si3461 device into
an inactive state. When pulled high, the device begins the detec-
tion process sequence.
ISENSE is an analog input connected to a current sense resistor
for output current sensing.
9
ISENSE
Analog input
16
Rev. 1.0
Si3461
Table 7. Si3461 Pin Functionality (Continued)
Pin #
Pin Name
STATUS
GND
Pin Type
Analog in/Digital out
GND
Pin Function
At power-up, the voltage on this pin is sensed to configure the
PSE available power, mid span/end span timing mode and the
device's restart behavior when a fault condition is detected. Refer
to "4.2. Operating Mode Configuration" on page 12.
After reading the voltage present at this pin at power-up, the
STATUS pin becomes a digital output used to control an external
LED, which indicates when a detect, power good, or output fault
condition has occurred. Logic high turns the LED on, and logic low
turns the LED off. Refer to "5.7. Status LED Function" on page 14.
10
11
Ground connection for the Si3461.
Rev. 1.0
17
Si3461
8. Ordering Guide
Ordering Part Number
Description
Package
Information
Temperature Range
(Ambient)
Si3461-E02-GM
Single-port PSE controller
11-pin,
–40 to 85 °C
3 x 3 mm QFN.
RoHS compliant
Si3461-KIT
Si3461 evaluation board and reference
design kit
Evaluation board
N/A
Notes:
1. Add R to part number to denote tape-and-reel option (e.g., Si3461-E02-GMR).
2. The ordering part number above is not the same as the device mark. See "9.3. Marking Specification" on page 22 for
more information.
18
Rev. 1.0
Si3461
9. Package Outline: 11-Pin QFN
Figure 4 illustrates the package details for the Si3461. Table 8 lists the values for the dimensions shown in the
illustration. The Si3461 is packaged in an industry-standard, 3x3 mm, RoHS-compliant, 11-pin QFN package.
Figure 4. QFN-11 Package Drawing
Table 8. Package Diagram Dimensions
Dimension
Min
0.80
0.03
Nom
0.90
Max
1.00
0.11
A
A1
A3
b
0.07
0.25 REF
0.25
0.18
1.30
0.30
1.40
D
3.00 BSC.
1.35
D2
e
0.50 BSC.
3.00 BSC.
2.25
E
E2
L
2.20
.45
—
2.30
.65
.55
aaa
bbb
ddd
eee
—
0.15
0.15
0.05
0.08
—
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-243, variation VEED except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Rev. 1.0
19
Si3461
9.1. Solder Paste Mask
b
0.10 mm
0.50 mm
0.35 mm
LT
0.50 mm
0.30 mm
0.20 mm
0.35 mm
L
0.30 mm
0.20 mm
E2
0.70 mm
0.60 mm
0.20 mm
0.30 mm
k
e
E
Figure 5. Solder Paste Mask
20
Rev. 1.0
Si3461
9.2. PCB Landing Pattern
b
0.10 mm
0.35 mm
LT
0.50 mm
0.30 mm
0.20 mm
L
E2
0.20 mm
0.30 mm
k
0.10 mm
e
E
Figure 6. Typical QFN-11 Landing Diagram
Rev. 1.0
21
Si3461
9.3. Marking Specification
The top of the Si3461 package is marked as shown in Figure 7.
6102
ETTT
YWW+
Figure 7. QFN 11 Top Marking
Table 9. Top Marking Explanation
Line 1 Marking:
Pin 1 Identifier
Circle = 0.25 mm Diameter
Product ID
6102
61 = Si3461; 02 = Firmware Revision 02
Line 2 Marking:
Line 3 Marking:
ETTT = Trace Code
Assembly trace code
E = Product revision
TTT = Assembly trace code
YWW = Date Code
Assigned by the Assembly contractor.
Y = Last Digit of Current Year (ex: 2009 = 9)
WW = Current Work Week
Lead-Free Designator
+
22
Rev. 1.0
Si3461
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated "9.3. Marking Specification" on page 22.
Revision 0.2 to Revision 0.3
Updated "8. Ordering Guide" on page 18.
Revision 0.3 to Revision 1.0
Updated firmware revision to 02.
Updated Table 3 on page 6
Made consistent with firmware revision 02.
Corrected previous errors for IOH and VIL values.
Updated Table 4 on page 7
Added min OVLO and max UVLO limits.
Updated IIN so as not to include the shunt regulator
current.
Updated ICUT values to be consistent with IEEE
specification.
Updated Table 6 on page 12.
Update suggested parallel resistance at status pin in
Note 2.
Rev. 1.0
23
Si3461
CONTACT INFORMATION
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Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
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24
Rev. 1.0
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