SI4030 [SILICON]
Remote control;
| 型号： | SI4030 |
| 厂家： | 
SILICON |
| 描述： | Remote control |
| 文件： | 总58页 (文件大小：1351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4030/31/32-B1
Si4030/31/32 ISM TRANSMITTER
Features
Frequency range
Ultra low power shutdown mode
Wake-up timer
Integrated 32 kHz RC or 32 kHz
XTAL
Integrated voltage regulators
Configurable packet handler
TX 64 byte FIFO
240–930 MHz (Si4031/32)
900–960 MHz (Si4030)
Output Power Range
+1 to +20 dBm (Si4032)
–8 to +13 dBm (Si4030/31)
Low Power Consumption
Si4032
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
85 mA @ +20 dBm
Si4030/31
Ordering Information:
30 mA @ +13 dBm
See page 53.
Data Rate = 0.123 to 256 kbps
FSK, GFSK, and OOK modulation
Power Supply = 1.8 to 3.6 V
Pin Assignments
Si4030/31/32
Low BOM
Power-on-reset (POR)
Applications
20 19 18 17
VDD_RF
TX
1
16
Remote control
Home security & alarm
Telemetry
Personal data logging
Toy control
Wireless PC peripherals
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
2
15 SCLK
14 SDI
13 SDO
12 VDD_DIG
11 NC
NC
3
4
5
GND
PAD
NC
NC
6
7
8
9
10
Description
Silicon Laboratories’ Si4030/31/32 devices are highly integrated, single-chip
wireless ISM transmitters. The high-performance EZRadioPRO® family includes a
complete line of transmitters, receivers, and transceivers allowing the RF system
designer to choose the optimal wireless part for their application.
Patents pending
The Si4030/31/32 offers advanced radio features including continuous frequency
coverage from 240–960 MHz with adjustable power output levels of –8 to
+13 dBm on the Si4030/31 and +1 to +20 dBm on the Si4032. Power adjustments
are made in 3 dB steps. The Si4030/31/32’s high level of integration offers
reduced BOM cost while simplifying the overall system design. The Si4032’s
Industry leading +20 dBm output power ensures extended range and improved
link performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte TX FIFO, and automatic packet handling reduce overall current
consumption and allow the use of lower-cost system MCUs. An integrated
temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs
further reduce overall system cost and size.
The direct digital transmit modulation and automatic PA power ramping ensure
precise transmit modulation and reduced spectral spreading ensuring compliance
with global regulations including FCC, ETSI, and ARIB regulations.
An easy-to-use calculator is provided to quickly configure the radio settings,
simplifying customer's system design and reducing time to market.
Rev 1.1 1/10
Copyright © 2010 by Silicon Laboratories
Si4030/31/32
Si4030/31/32-B1
Functional Block Diagram
2
Preliminary Rev. 0.1
Si4030/31/32-B1
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.1. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.2. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.3. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.4. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.1. TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.5. Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.6. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
7. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
7.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
7.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
7.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
7.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
7.7. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
9. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
10. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
11. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
12. Pin Descriptions: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Preliminary Rev. 0.1
3
Si4030/31/32-B1
14. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
14.1. Si4030/31/32 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
14.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
15. Package Outline: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
16. PCB Land Pattern: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4
Preliminary Rev. 0.1
Si4030/31/32-B1
LIST OF FIGURES
Figure 1. SPI Timing..................................................................................................................15
Figure 2. SPI Timing—READ Mode..........................................................................................16
Figure 3. SPI Timing—Burst Write Mode ..................................................................................16
Figure 4. SPI Timing—Burst Read Mode..................................................................................16
Figure 5. State Machine Diagram..............................................................................................17
Figure 6. TX Timing...................................................................................................................21
Figure 7. Frequency Deviation ..................................................................................................25
Figure 8. FSK vs. GFSK Spectrums..........................................................................................27
Figure 9. Microcontroller Connections.......................................................................................30
Figure 10. PLL Synthesizer Block Diagram...............................................................................31
Figure 11. FIFO Threshold........................................................................................................34
Figure 12. Packet Structure.......................................................................................................35
Figure 13. Multiple Packets in TX Packet Handler....................................................................36
Figure 14. Operation of Data Whitening, Manchester Encoding, and CRC ..............................37
Figure 15. Manchester Coding Example...................................................................................37
Figure 16. POR Glitch Parameters............................................................................................39
Figure 17. General Purpose ADC Architecture .........................................................................41
Figure 18. Temperature Ranges using ADC8...........................................................................43
Figure 19. WUT Interrupt and WUT Operation..........................................................................46
Figure 20. Si4031 Reference Design Schematic ......................................................................48
Figure 21. 20-Pin Quad Flat No-Lead (QFN) ............................................................................54
Figure 22. PCB Land Pattern ....................................................................................................55
Preliminary Rev. 0.1
5
Si4030/31/32-B1
LIST OF TABLES
1
Table 1. DC Characteristics ......................................................................................................7
1
Table 2. Synthesizer AC Electrical Characteristics ...................................................................8
1
Table 3. Transmitter AC Electrical Characteristics ...................................................................9
1
Table 4. Auxiliary Block Specifications ...................................................................................10
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ...................................11
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ..............................................11
Table 7. Absolute Maximum Ratings ........................................................................................12
Table 8. Operating Modes ........................................................................................................14
Table 9. Serial Interface Timing Parameters ............................................................................15
Table 10. Operating Modes Response Time ............................................................................17
Table 11. Frequency Band Selection .......................................................................................23
Table 12. Packet Handler Registers .........................................................................................36
Table 13. POR Parameters ......................................................................................................39
Table 14. Temperature Sensor Range .....................................................................................42
Table 15. Register Descriptions ...............................................................................................50
Table 16. Package Dimensions ................................................................................................54
Table 17. PCB Land Pattern Dimensions .................................................................................56
Preliminary Rev. 0.1
6
Si4030/31/32-B1
1. Electrical Specifications
Table 1. DC Characteristics1
Parameter
Symbol
Conditions
Min Typ Max Units
Supply Voltage Range
Power Saving Modes
VDD
1.8
—
3.0
15
3.6
50
V
IShutdown
RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF2
nA
IStandby Low Power Digital Regulator ON (Register values retained)
and Main Digital Regulator, and RC Oscillator OFF
—
—
—
—
—
450
1
800
—
nA
µA
µA
µA
µA
ISleep
ISensor-LBD
ISensor-TS
IReady
RC Oscillator and Low Power Digital Regulator ON
(Register values retained) and Main Digital Regulator OFF
Main Digital Regulator and Low Battery Detector ON,
Crystal Oscillator and all other blocks OFF2
1
—
Main Digital Regulator and Temperature Sensor ON,
Crystal Oscillator and all other blocks OFF2
1
—
Crystal Oscillator and Main Digital Regulator ON,
all other blocks OFF. Crystal Oscillator buffer disabled
800
—
TUNE Mode Current
ITune
Synthesizer and regulators enabled
—
—
8.5
85
—
—
mA
mA
TX Mode Current
—Si4032
ITX_+20
txpow[2:0] = 111 (+20 dBm)
Using Silicon Labs’ Reference Design. TX current
consumption is dependent on match and board layout.
TX Mode Current
—Si4030/31
ITX_+13
txpow[2:0] = 111 (+13 dBm)
Using Silicon Labs’ Reference Design. TX current
consumption is dependent on match and board layout.
—
—
30
18
—
—
mA
mA
ITX_+1
txpow[2:0] = 011 (+1 dBm)
Using Silicon Labs’ Reference Design. TX current
consumption is dependent on match and board layout.
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on
page 13.
Preliminary Rev. 0.1
7
Si4030/31/32-B1
Table 2. Synthesizer AC Electrical Characteristics1
Parameter
Symbol
Conditions
Min
Typ
Max Units
Synthesizer Frequency
Range—Si4031/32
F
240
—
930
MHz
SYN
Synthesizer Frequency
Range—Si4030
F
900
—
960
MHz
SYN
Synthesizer Frequency
Resolution
F
Low Band, 240–480 MHz
High Band, 480–960 MHz
—
—
156.25
312.5
—
—
—
Hz
Hz
V
RES-LB
RES-HB
REF_LV
2
F
Reference Frequency
f
When using external reference signal
driving XOUT pin, instead of using
0.7
1.6
2
Input Level
crystal. Measured peak-to-peak (V
)
PP
2
Synthesizer Settling Time
t
Measured from exiting Ready mode with
XOSC running to any frequency.
Including VCO calibration.
—
—
200
2
—
4
µs
LOCK
2
Residual FM
F
Integrated over 250 kHz bandwidth
kHz
RMS
RMS
(500 Hz lower bound of integration)
2
Phase Noise
L(f )
F = 10 kHz
F = 100 kHz
F = 1 MHz
F = 10 MHz
—
—
—
—
–80
–90
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
M
–115
–130
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on
page 13.
8
Preliminary Rev. 0.1
Si4030/31/32-B1
Table 3. Transmitter AC Electrical Characteristics1
Parameter
TX Frequency
Symbol
Conditions
Min
Typ
Max Units
F
240
—
930
MHz
TX
Range—Si4031/32
TX Frequency
F
900
—
960
MHz
TX
Range—Si4030
2
FSK Data Rate
DR
0.123
0.123
±0.625
±0.625
—
—
—
256
40
kbps
kbps
kHz
kHz
kHz
FSK
2
OOK Data Rate
DR
OOK
Modulation Deviation
∆f1
∆f2
∆f
860–960 MHz
240–860 MHz
±320
±160
—
Modulation Deviation
0.625
—
RES
2
Resolution
Output Power
P
P
+1
–8
+20
+13
dBm
dBm
TX
TX
3
Range —Si4032
Output Power
—
3
Range—Si4030/31
2
TX RF Output Steps
P
P
controlled by txpow[2:0]
—
—
3
2
—
—
dB
dB
RF_OUT
2
TX RF Output Level
–40 to +85 C
RF_TEMP
Variation vs. Temperature
TX RF Output Level
Variation vs. Frequency
P
Measured across any one
frequency band
—
—
—
1
—
—
dB
RF_FREQ
2
Transmit Modulation
B*T
Gaussian Filtering Bandwith Time
Product
0.5
—
2
Filtering
2
Spurious Emissions
P
P
P
= 13 dBm,
OUT
–54
dBm
OB-TX1
Frequencies <1 GHz
1–12.75 GHz, excluding harmonics
—
—
—
—
—
—
–54
–42
–42
dBm
dBm
dBm
OB-TX2
2
Harmonics
P
P
Using reference design TX matching
network and filter with max output
power. Harmonics reduce linearly with
output power.
2HARM
3HARM
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on
page 13.
3. Output power is dependent on matching components and board layout.
Preliminary Rev. 0.1
9
Si4030/31/32-B1
Table 4. Auxiliary Block Specifications1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Temperature Sensor
Accuracy
TS
After calibrated via sensor offset
register tvoffs[7:0]
—
0.5
—
°C
A
2
Temperature Sensor
Sensitivity
TS
—
—
5
50
250
—
—
—
mV/°C
mV
S
2
Low Battery Detector
LBD
RES
2
Resolution
Low Battery Detector
LBD
—
—
µs
CT
2
Conversion Time
Microcontroller Clock
Output Frequency
F
Configurable to 30 MHz,
15 MHz, 10 MHz, 4 MHz,
3 MHz, 2 MHz, 1 MHz, or
32.768 kHz
32.768K
30M
Hz
MC
General Purpose ADC Res- ADC
olution
—
—
—
8
4
—
—
—
bit
mV/bit
µs
ENB
RES
2
General Purpose ADC Bit
Resolution
ADC
2
Temp Sensor & General
Purpose ADC Conversion
Time
ADC
305
CT
2
30 MHz XTAL Start-Up time
t
Using XTAL and board layout in
reference design. Start-up time
will vary with XTAL type and
board layout.
—
600
97
—
µs
fF
30M
30 MHz XTAL Cap
30M
—
—
RES
2
Resolution
2
32 kHz XTAL Start-Up Time
t
—
—
6
—
—
sec
32k
32 kHz XTAL Accuracy
32K
Using 20 ppm 32 kHz Crystal
100
ppm
RES
2
using 32 kHz XTAL
32 kHz Accuracy using
Internal RC Oscillator
32KRC
—
2500
—
ppm
RES
2
POR Reset Time
t
—
—
16
—
—
ms
µs
POR
2
Software Reset Time
t
100
soft
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on
page 13.
10
Preliminary Rev. 0.1
Si4030/31/32-B1
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)
Parameter
Symbol
Conditions
Min
—
Typ
—
—
—
—
—
—
—
Max Units
Rise Time
Fall Time
T
T
0.1 x V to 0.9 x V , C = 5 pF
8
8
ns
ns
pF
V
RISE
FALL
DD
DD
L
0.9 x V to 0.1 x V
C = 5 pF
—
DD
DD,
L
Input Capacitance
C
V
—
1
IN
Logic High Level Input Voltage
Logic Low Level Input Voltage
Input Current
V
V
– 0.6
—
0.6
100
—
IH
DD
V
V
IL
IN
I
0<V < V
–100
– 0.6
DD
nA
V
IN
DD
Logic High Level Output
Voltage
V
I
<1 mA source, V =1.8 V
OH DD
OH
Logic Low Level Output Voltage
V
I
<1 mA sink, V =1.8 V
—
—
0.6
V
OL
OL
DD
Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions"
section on page 13.
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
Parameter
Symbol
Conditions
0.1 x V to 0.9 x V ,
DD
Min
Typ
Max
Units
Rise Time
Fall Time
T
—
—
8
ns
RISE
DD
C = 10 pF, DRV<1:0>=HH
L
T
0.9 x V to 0.1 x V
—
—
8
1
ns
FALL
DD
DD,
C = 10 pF, DRV<1:0>=HH
L
Input Capacitance
C
V
—
—
—
pF
V
IN
Logic High Level Input Voltage
Logic Low Level Input Voltage
Input Current
V
– 0.6
DD
IH
V
—
–100
5
—
0.6
100
25
V
IL
I
0<V < V
DD
—
nA
µA
mA
mA
mA
mA
V
IN
IN
Input Current If Pullup is Activated
Maximum Output Current
I
V =0 V
—
INP
IL
I
DRV<1:0>=LL
DRV<1:0>=LH
DRV<1:0>=HL
DRV<1:0>=HH
0.1
0.9
1.5
1.8
0.5
2.3
3.1
3.6
—
0.8
3.5
4.8
5.4
—
OmaxLL
OmaxLH
OmaxHL
OmaxHH
I
I
I
Logic High Level Output Voltage
Logic Low Level Output Voltage
V
I
< I
source,
V
– 0.6
DD
OH
OH Omax
V
=1.8 V
DD
V
I
< I sink,
—
—
0.6
V
OL
OL Omax
V
=1.8 V
DD
Note: All specifications guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions"
section on page 13.
Preliminary Rev. 0.1
11
Si4030/31/32-B1
Table 7. Absolute Maximum Ratings
Parameter
Value
Unit
V
V
to GND
–0.3, +3.6
–0.3, +8.0
–0.3, +6.5
DD
Instantaneous V
to GND on TX Output Pin
V
RF-peak
Sustained V
to GND on TX Output Pin
V
RF-peak
Voltage on Digital Control Inputs
Voltage on Analog Inputs
–0.3, V + 0.3
V
DD
–0.3, V + 0.3
V
DD
Operating Ambient Temperature Range T
–40 to +85
30
C
C/W
C
C
A
Thermal Impedance
JA
Junction Temperature T
+125
J
Storage Temperature Range T
–55 to +125
STG
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX
matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device.
12
Preliminary Rev. 0.1
Si4030/31/32-B1
1.1. Definition of Test Conditions
Production Test Conditions:
T = +25 °C
A
V
= +3.3 VDC
DD
TX output power measured at 915 MHz
External reference signal (XOUT) = 1.0 V at 30 MHz, centered around 0.8 VDC
PP
Production test schematic (unless noted otherwise)
All RF output levels referred to the pins of the Si4030/31/32 (not the RF module)
Qualification Test Conditions:
T = –40 to +85 °C
A
V
= +1.8 to +3.6 VDC
DD
Using 4032, 4031, or 4030 reference design or production test schematic
All RF output levels referred to the pins of the Si4030/31/32 (not the RF module)
Preliminary Rev. 0.1
13
Si4030/31/32-B1
2. Functional Description
The Si4030/31/32 are ISM wireless transmitters with continuous frequency tuning over their specified bands which
encompasses 240–960 MHz. The wide operating voltage range of 1.8–3.6 V and low current consumption makes
the Si4030/31/32 an ideal solution for battery powered applications.
The RF carrier is generated by an integrated VCO and Fractional-N PLL synthesizer. The synthesizer is
designed to support configurable data rates, output frequency, frequency deviation, and Gaussian filtering at any
frequency between 240–960 MHz. The transmit FSK data is modulated directly into the data stream and can be
shaped by a Gaussian low-pass filter to reduce unwanted spectral content.
The Si4032’s PA output power can be configured between +1 and +20 dBm in 3 dB steps, while the Si4030/31's
PA output power can be configured between –8 and +13 dBm in 3 dB steps. The PA is single-ended to allow for
easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and ramp-down control to
reduce unwanted spectral spreading. The +20 dBm power amplifier of the Si4032 can also be used to compensate
for the reduced performance of a lower cost, lower performance antenna or antenna with size constraints due to a
small form-factor. Competing solutions require large and expensive external PAs to achieve comparable
performance.
The Si4030/31/32 is designed to work with a microcontroller, crystal, and a few external components to create a
very low cost system. Voltage regulators are integrated on-chip which allows for a wide operating supply voltage
range from +1.8 to +3.6 V. A standard 4-pin SPI bus is used to communicate with an external microcontroller.
Three configurable general purpose I/Os are available. A complete list of the available GPIO functions is available
in “AN466: Si4030/31/32 Register Descriptions.”
2.1. Operating Modes
The Si4030/31/32 provides several operating modes which can be used to optimize the power consumption for a
given application.
Table 8 summarizes the operating modes of the Si4030/31/32. In general, any given operating mode may be
classified as an active mode or a power saving mode. The table indicates which block(s) are enabled (active) in
each corresponding mode. With the exception of the SHUTDOWN mode, all can be dynamically selected by
sending the appropriate commands over the SPI. An “X” in any cell means that, in the given mode of operation,
that block can be independently programmed to be either ON or OFF, without noticeably impacting the current
consumption. The SPI circuit block includes the SPI interface hardware and the device register space. The 32 kHz
OSC block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal oscillator and wake-up timer. AUX
(Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector.
Table 8. Operating Modes
Mode Name
Circuit Blocks
Digital LDO
SPI
32 kHz OSC AUX
30 MHz
XTAL
PLL
PA
I
VDD
SHUTDOWN
OFF
(Register contents
lost)
OFF
OFF
OFF
OFF
OFF
OFF
15 nA
STANDBY
SLEEP
ON
ON
ON
ON
ON
ON
ON
OFF
ON
X
OFF
X
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF 450 nA
(Register contents
retained)
OFF
OFF
1 µA
1 µA
SENSOR
READY
ON
X
X
OFF 800 µA
OFF 8.5 mA
TUNING
TRANSMIT
X
X
ON
X
X
ON
ON
ON
30 mA*
*Note: Using Si4030/31 at +13 dBm using recommended reference design.
14
Preliminary Rev. 0.1
Si4030/31/32-B1
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si4030/31/32 communicates with the host MCU over a standard 3-wire SPI interface: SCLK, SDI, and nSEL.
The host MCU can read data from the device on the SDO output pin. A SPI transaction is a 16-bit sequence which
consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA)
as demonstrated in Figure 1. The 7-bit address field is used to select one of the 128, 8-bit control registers. The
R/W select bit determines whether the SPI transaction is a read or write transaction. If R/W = 1 it signifies a WRITE
transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the
Si4030/31/32 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9. The
SCLK rate is flexible with a maximum rate of 10 MHz.
Data
Address
MSB
LSB
RW A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 xx xx RW A7
SDI
SCLK
nSEL
Figure 1. SPI Timing
Table 9. Serial Interface Timing Parameters
Symbol
Parameter
Min (nsec)
Diagram
t
Clock high time
Clock low time
40
40
20
20
20
20
50
20
50
80
CH
t
CL
DS
DH
DD
SCLK
t
Data setup time
tSS
tCL tCH
tDS tDH tDD
tSH tDE
t
t
Data hold time
SDI
Output data delay time
Output enable time
Output disable time
Select setup time
Select hold time
SDO
t
t
EN
DE
tEN
tSW
nSEL
t
SS
SH
t
t
Select high period
SW
To read back data from the Si4030/31/32, the R/W bit must be set to 0 followed by the 7-bit address of the register
from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored n the SDI pin when R/W = 0. The
next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data
read from the selected register will be available on the SDO output pin. The READ function is shown in Figure 2.
After the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the
last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
Preliminary Rev. 0.1
15
Si4030/31/32-B1
First Bit
Last Bit
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X
SDI
A6 A5 A4 A3 A2 A1 A0
SCLK
First Bit
Last Bit
SDO
D7 D6 D5 D4 D3 D2 D1 D0
nSEL
Figure 2. SPI Timing—READ Mode
The SPI interface contains a burst read/write mode which allows for reading/writing sequential registers without
having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An example burst write
transaction is illustrated in Figure 3 and a burst read in Figure 4. As long as nSEL is held low, input data will be
latched into the Si4030/31/32 every eight SCLK cycles.
First Bit
Last Bit
RW
=1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X =X =X =X =X =X =X =X =X
SDI
A6 A5 A4 A3 A2 A1 A0
SCLK
nSEL
Figure 3. SPI Timing—Burst Write Mode
First Bit
Last Bit
RW
=0
D7 D6 D5 D4 D3 D2 D1 D0
=X =X =X =X =X =X =X =X
SDI
A6 A5 A4 A3 A2 A1 A0
SCLK
First Bit
SDO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
nSEL
Figure 4. SPI Timing—Burst Read Mode
16
Preliminary Rev. 0.1
Si4030/31/32-B1
3.2. Operating Mode Control
There are three primary states in the Si4030/31/32 radio state machine: SHUTDOWN, IDLE, and TX (see
Figure 5). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five
different configurations/options for the IDLE state which can be selected to optimize the chip to the applications
needs. "Register 07h. Operating Mode and Function Control 1" controls which operating mode/state is selected
with the exception of SHUTDOWN which is controlled by SDN pin 20. The TX state may be reached automatically
from any of the IDLE states by setting the txon bit in "Register 07h. Operating Mode and Function Control 1."
Table 10 shows each of the operating modes with the time required to reach TX mode as well as the current
consumption of each mode.
The Si4030/31/32 includes a low-power digital regulated supply (LPLDO) which is internally connected in parallel
to the output of the main digital regulator (and is available externally at the VR_DIG pin). This common digital
supply voltage is connected to all digital circuit blocks including the SPI and register space. The LPLDO has
extremely low quiescent current consumption but limited current supply capability; it is used only in the IDLE-
STANDBY and IDLE-SLEEP modes. The main digital regulator is automatically enabled in all other modes.
SHUTDOWN
IDLE*
TX
*Five Different Options for IDLE
Figure 5. State Machine Diagram
Table 10. Operating Modes Response Time
State/Mode
Shut Down State
Idle States:
Response Time to TX
Current in State/Mode [µA]
16.8 ms
15 nA
Standby Mode
800 µs
800 µs
800 µs
200 µs
200 µs
450 nA
1 µA
1 µA
800 µA
8.5 mA
Sleep Mode
Sensor Mode
Ready Mode
Tune Mode
TX State
NA
Si4032:
85 mA @ +20 dBm,
Si4030/31:
30 mA @ +13 dBm
Preliminary Rev. 0.1
17
Si4030/31/32-B1
3.2.1. SHUTDOWN State
The SHUTDOWN state is the lowest current consumption state of the device with nominally less than 15 nA of
current consumption. The SHUTDOWN state may be entered by driving the SDN pin (Pin 20) high. The SDN pin
should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the
registers are lost and there is no SPI access.
When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN.
3.2.2. IDLE State
There are five different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and
Function Control 1". All modes have a tradeoff between current consumption and response time to TX mode. This
tradeoff is shown in Table 10. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will
default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the
SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock correctly.
3.2.2.1. STANDBY Mode
STANDBY mode has the lowest current consumption of the five IDLE states with only the LPLDO enabled to
maintain the register values. In this mode the registers can be accessed in both read and write mode. The
STANDBY mode can be entered by writing 0h to "Register 07h. Operating Mode and Function Control 1". If an
interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current
consumption. Additionally, the ADC should not be selected as an input to the GPIO in this mode as it will cause
excess current consumption.
3.2.2.2. SLEEP Mode
In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up
the radio at specified intervals. See "7.6. Wake-Up Timer" on page 45 for more information on the Wake-Up-Timer.
SLEEP mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an
interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current
consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess
current consumption.
3.2.2.3. SENSOR Mode
In SENSOR Mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the
LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in "Register 07h.
Operating Mode and Function Control 1". See "7.4. Temperature Sensor" on page 42 and "7.5. Low Battery
Detector" on page 44 for more information on these features. If an interrupt has occurred (i.e., the nIRQ pin = 0) the
interrupt registers must be read to achieve the minimum current consumption.
3.2.2.4. READY Mode
READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption. In this
mode the Crystal oscillator remains enabled reducing the time required to switch to TX mode by eliminating the
crystal start-up time. READY mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function
Control 1". To achieve the lowest current consumption state the crystal oscillator buffer should be disabled in
“Register 62h. Crystal Oscillator Control and Test.”
3.2.2.5. TUNE Mode
In TUNE Mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give
the fastest response to TX mode as the PLL will remain locked but it results in the highest current consumption.
This mode of operation is designed for frequency hopping spread spectrum systems (FHSS). TUNE mode is
entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set
xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator.
18
Preliminary Rev. 0.1
Si4030/31/32-B1
3.2.3. TX State
The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h. Operating
Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition between
states from enabling the crystal oscillator to ramping up the PA. The following sequence of events will occur
automatically when going from STANDBY mode to TX mode by setting the txon bit.
1. Enable the main digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the vcocal bit is “0”, default value is “1”).
5. Wait until PLL settles to required transmit frequency (controlled by timer).
6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit packet.
Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to setting
the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled.
3.2.4. Device Status
D7
D6
D5
D4
D3
D2
D1
D0 POR Def.
Add R/W Function/Description
02 Device Status
R
ffovfl ffunfl Reserved Reserved freqerr
cps[1] cps[0]
—
The operational status of the chip can be read from "Register 02h. Device Status".
Preliminary Rev. 0.1
19
Si4030/31/32-B1
3.3. Interrupts
The Si4030/31/32 is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown
below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers
03h–04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change
in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable
Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the
interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the
status may still be read at anytime in the Interrupt Status registers.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/Descript
ion
03
04
R
R
Interrupt Status 1
ifferr
itxffafull
itxffaem Reserved iext ipksent Reserved Reserved
ilbd ichiprdy ipor
enfferr entxffafull entxffaem Reserved enext enpksent Reserved Reserved
—
—
Interrupt Status 2 Reserved Reserved Reserved Reserved iwut
05 R/W Interrupt Enable 1
00h
01h
06 R/W Interrupt Enable 2 Reserved Reserved Reserved Reserved enwut enlbd enchiprdy enpor
See “AN466: Si4030/31/32 Register Descriptions” for a complete list of interrupts.
20
Preliminary Rev. 0.1
Si4030/31/32-B1
3.4. System Timing
The system timing for TX mode is shown in Figure 6. The figures demonstrate transitioning from STANDBY mode
to TX mode through the built-in sequencer of required steps. The user only needs to program the desired mode,
and the internal sequencer will properly transition the part from its current mode.
The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow for bias
settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 µs. The
total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. Under certain applications, the PLL T0
time and the PLL CAL may be skipped for faster turn-around time. Contact applications support if faster turnaround
time is desired.
XTAL Settling
TX Packet
Time
600us
Figure 6. TX Timing
Preliminary Rev. 0.1
21
Si4030/31/32-B1
3.5. Frequency Control
For calculating the necessary frequency register settings it is recommended that customers use Silicon Labs’
Wireless Design Suite (WDS) or the EZRadioPRO Register Calculator worksheet (in Microsoft Excel) available on
the product website. These methods offer a simple method to quickly determine the correct settings based on the
application requirements. The following information can be used to calculated these values manually.
3.5.1. Frequency Programming
In order to transmit an RF signal, the desired channel frequency, f
, must be programmed into the
carrier
Si4030/31/32. Note that this frequency is the center frequency of the desired channel. The carrier frequency is
rd
generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3
order) ∆Σ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the
desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer
part (N) and a fractional part (F).In a generic sense, the output frequency of the synthesizer is as follows:
fOUT 10MHz(N F)
The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Offset
(fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the synthesizer,
FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is
discussed further in "3.5.4. Frequency Deviation" on page 24. Also, a fixed offset can be added to fine-tune the
carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the fc[15:0] register will
determine the fractional component. The equation for selection of the carrier frequency is shown below:
fcarrier 10MHz(hbsel 1)(N F)
fc[15:0]
fTX 10MHz*(hbsel 1)*( fb[4:0] 24
)
64000
D7
D6
D5
D4
D3
D2
D1
D0 POR Def.
Add R/W Function/Description
73 R/W
Frequency Offset 1
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1] fo[0]
fo[9] fo[8]
fb[1] fb[0]
fc[9] fc[8]
00h
00h
35h
BBh
74 R/W
Frequency Offset 2
75 R/W Frequency Band Select
sbsel
fc[14]
hbsel
fc[13]
fb[4]
fb[3]
fb[2]
76 R/W
77 R/W
Nominal Carrier
Frequency 1
fc[15]
fc[7]
fc[12]
fc[11]
fc[10]
fc[2]
Nominal Carrier
Frequency 0
fc[6]
fc[5]
fc[4]
fc[3]
fc[1] fc[0]
80h
The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connecting a ÷2
divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h.
Frequency Band Select". This effectively partitions the entire 240–960 MHz frequency range into two separate
bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If
a higher value is written into the register, it will default to a value of 23. The integer part has a fixed offset of 24
added to it as shown in the formula above. Table 11 demonstrates the selection of fb[4:0] for the corresponding
frequency band.
After selection of the fb (N) the fractional component may be solved with the following equation:
fTX
fc[15:0]
fb[4:0] 24 *64000
10MHz*(hbsel 1)
fb and fc are the actual numbers stored in the corresponding registers.
22
Preliminary Rev. 0.1
Si4030/31/32-B1
Table 11. Frequency Band Selection
fb[4:0] Value
N
Frequency Band
hbsel=0
hbsel=1
0
1
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
240–249.9 MHz
250–259.9 MHz
260–269.9 MHz
270–279.9 MHz
280–289.9 MHz
290–299.9 MHz
300–309.9 MHz
310–319.9 MHz
320–329.9 MHz
330–339.9 MHz
340–349.9 MHz
350–359.9 MHz
360–369.9 MHz
370–379.9 MHz
380–389.9 MHz
390–399.9 MHz
400–409.9 MHz
410–419.9 MHz
420–429.9 MHz
430–439.9 MHz
440–449.9 MHz
450–459.9 MHz
460–469.9 MHz
470–479.9 MHz
480–499.9 MHz
500–519.9 MHz
520–539.9 MHz
540–559.9 MHz
560–579.9 MHz
580–599.9 MHz
600–619.9 MHz
620–639.9 MHz
640–659.9 MHz
660–679.9 MHz
680–699.9 MHz
700–719.9 MHz
720–739.9 MHz
740–759.9 MHz
760–779.9 MHz
780–799.9 MHz
800–819.9 MHz
820–839.9 MHz
840–859.9 MHz
860–879.9 MHz
880–899.9 MHz
900–919.9 MHz
920–939.9 MHz
940–960 MHz
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Preliminary Rev. 0.1
23
Si4030/31/32-B1
3.5.2. Easy Frequency Programming for FHSS
While Registers 73h–77h may be used to program the carrier frequency of the Si4030/31/32, it is often easier to
think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may
be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change
frequency by programming a single register. Once the channel step size is set, the frequency may be changed by
a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h–77h,
as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative
to the nominal setting. The Frequency Hopping Step Size (fhs[7:0]) is set in increments of 10 kHz with a maximum
channel step size of 2.56 MHz. The Frequency Hopping Channel Select Register then selects channels based on
multiples of the step size.
Fcarrier Fnom fhs[7 :0]( fhch[7 :0]10kHz)
For example, if the nominal frequency is set to 900 MHz using Registers 73h–77h, the channel step size is set to
1 MHz using "Register 7Ah. Frequency Hopping Step Size," and "Register 79h. Frequency Hopping Channel
Select" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and channel
step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change
the frequency.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/Description
79 R/W Frequency Hopping Channel fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0]
Select
00h
7A R/W
Frequency Hopping Step
Size
fhs[7]
fhs[6]
fhs[5]
fhs[4]
fhs[3]
fhs[2]
fhs[1]
fhs[0]
00h
3.5.3. Automatic State Transition for Frequency Change
If registers 79h or 7Ah are changed in TX mode, the state machine will automatically transition the chip back to
TUNE and change the frequency. This feature is useful to reduce the number of SPI commands required in a
Frequency Hopping System. This in turn reduces microcontroller activity, reducing current consumption. The
exception to this is during TX FIFO mode. If a frequency change is initiated during a TX packet, then the part will
complete the current TX packet and will only change the frequency for subsequent packets.
3.5.4. Frequency Deviation
The peak frequency deviation is configurable from ±0.625 to ±320 kHz. The Frequency Deviation (∆f) is controlled
by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier frequency setting.
When enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency
deviation will remain in increments of 625 Hz. When using frequency modulation the carrier frequency will deviate
from the nominal center channel carrier frequency by ±∆f:
f fd[8:0]625Hz
f
fd[8 : 0]
f = peak deviation
625Hz
24
Preliminary Rev. 0.1
Si4030/31/32-B1
f
fcarrier
Time
Figure 7. Frequency Deviation
The previous equation should be used to calculate the desired frequency deviation. If desired, frequency
modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency;
see "4.1. Modulation Type" on page 27 for further details.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/Description
71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0]
72 R/W Frequency Deviation fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0]
00h
20h
Preliminary Rev. 0.1
25
Si4030/31/32-B1
3.5.5. Frequency Offset Adjustment
A frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment is
implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to
get a negative offset it is necessary to take the twos complement of the positive offset number. The offset can be
calculated by the following:
DesiredOffset 156.25Hz(hbsel 1) fo[9:0]
DesiredOffset
fo[9:0]
156.25Hz(hbsel 1)
The adjustment range in high band is ±160 kHz and in low band it is ±80 kHz. For example to compute an offset of
+50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band mode the fo[9:0]
register should be set to 360h.
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
Add R/W Function/Descript
ion
73 R/W
74 R/W
Frequency Offset
Frequency Offset
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1] fo[0]
fo[9] fo[8]
00h
00h
3.5.6. TX Data Rate Generator
The data rate is configurable between 0.123–256 kbps. For data rates below 30 kbps the ”txdtrtscale” bit in register
70h should be set to 1. When higher data rates are used this bit should be set to 0.
The TX date rate is determined by the following formula in kbps:
txdr15:0 1 MHz
---------------------------------------------------
DR_TX (kbps) =
216 + 5 txdtrtscale
DR_TX(kbps) 216 + 5 txdtrtscale
----------------------------------------------------------------------------------------
txdr[15:0] =
1 MHz
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/Description
6E R/W
6F R/W
TX Data Rate 1
TX Data Rate 0
txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8]
0Ah
AAh
txdr[7]
txdr[6] txdr[5] txdr[4]
txdr[3]
txdr[2] txdr[1] txdr[0]
26
Preliminary Rev. 0.1
Si4030/31/32-B1
4. Modulation Options
4.1. Modulation Type
The Si4030/31/32 supports three different modulation options: Gaussian Frequency Shift Keying (GFSK),
Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it
provides the best performance and cleanest modulation spectrum. Figure 8 demonstrates the difference between
FSK and GFSK for a Data Rate of 64 kbps. The time domain plots demonstrate the effects of the Gaussian filtering.
The frequency domain plots demonstrate the spectral benefit of GFSK over FSK. The type of modulation is
selected with the modtyp[1:0] bits in "Register 71h. Modulation Mode Control 2." Note that it is also possible to
obtain an unmodulated carrier signal by setting modtyp[1:0] = 00.
modtyp[1:0]
Modulation Source
00
01
10
11
Unmodulated Carrier
OOK
FSK
GFSK (enable TX Data CLK when direct mode is used)
TX Modulation Time Domain Waveforms -- FSK vs. GFSK
1.5
TX Modulation Spectrum -- FSK vs GFSK (Continuous PRBS)
-20
1.0
0.5
-40
-60
-80
0.0
-0.5
-1.0
-100
-20
-1.5
1.0
-40
-60
0.5
0.0
-80
-0.5
-1.0
-100
-250 -200 -150 -100
-50
0
50
100
150
200
250
0
50
100 150 200 250 300 350 400 450 500
time, usec
freq, KHz
DataRate
64000.0
TxDev
BT_Filter
0.5
ModIndex
1.0
32000.0
Figure 8. FSK vs. GFSK Spectrums
Preliminary Rev. 0.1
27
Si4030/31/32-B1
4.2. Modulation Data Source
The Si4030/31/32 may be configured to obtain its modulation data from one of three different sources: FIFO mode,
Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from several
different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode Control
2."
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/Description
71 R/W
Modulation Mode
Control 2
trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0]
00h
dtmod[1:0]
Data Source
00
01
10
11
Direct Mode using TX Data via GPIO pin (GPIO configuration required)
Direct Mode using TX Data via SDI pin (only when nSEL is high)
FIFO Mode
PN9 (internally generated)
4.2.1. FIFO Mode
In FIFO mode, the transmit data is stored in integrated FIFO register memory. The FIFOs are accessed via
"Register 7Fh. FIFO Access," and are most efficiently accessed with burst read/write operation as discussed in
"3.1. Serial Peripheral Interface (SPI)" on page 15.
In TX mode, the data bytes stored in FIFO memory are "packaged" together with other fields and bytes of
information to construct the final transmit packet structure. These other potential fields include the Preamble, Sync
word, Header, CRC checksum, etc. The configuration of the packet structure in TX mode is determined by the
Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler Registers (see Table 12 on
page 36). If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into
FIFO memory; no other fields (such as Preamble or Sync word are automatically added to the bytes stored in FIFO
memory). For further information on the configuration of the FIFOs for a specific application or packet size, see "6.
Data Handling and Packet Handler" on page 34.
When in FIFO mode, the chip will automatically exit the TX State when either the ipksent or ipkvalid interrupt
occurs. The chip will return to the IDLE mode state programmed in "Register 07h. Operating Mode and Function
Control 1". For example, the chip may be placed into TX mode by setting the txon bit, but with the pllon bit
additionally set. The chip will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this
interrupt event occurs, the chip will clear the txon bit and return to TUNE mode, as indicated by the set state of the
pllon bit. If no other bits are additionally set in register 07h (besides txon initially), then the chip will return to the
STANDBY state.
28
Preliminary Rev. 0.1
Si4030/31/32-B1
4.2.2. Direct Mode
For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be desirable to
use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely.
In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real time" (i.e.,
not stored in a register for transmission at a later time). A variety of pins may be configured for use as the TX Data
input function.
Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is desired (only
the TX Data input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0]
field, and various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field.
trclk[1:0]
TX Data Clock Configuration
00
01
10
11
No TX Clock (only for FSK)
TX Data Clock is available via GPIO (GPIO needs programming accordingly as well)
TX Data Clock is available via SDO pin (only when nSEL is high)
TX Data Clock is available via the nIRQ pin
The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing
purposes.
4.2.2.1. Direct Synchronous Mode
In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In direct
synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external device that is
providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal to the programmed
data rate. The external modulation source (e.g., MCU) must accept this TX Clock signal as an input and respond
by providing one bit of TX Data back to the RFIC, synchronous with one edge of the TX Clock signal. In this
fashion, the rate of the TX Data input stream from the external source is controlled by the programmed data rate of
the RFIC; no TX Data bits are made available at the input of the RFIC until requested by another cycle of the TX
Clock signal. The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored
internally for later transmission).
All modulation types (FSK/GFSK/OOK) are valid in TX direct synchronous mode. As will be discussed in the next
section, there are limits on modulation types in TX direct asynchronous mode.
4.2.2.2. Direct Asynchronous Mode
In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream. Instead,
the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data applied to its TX
Data input pin, at whatever rate it is supplied. This means that there is no longer a need for a TX Clock output
signal from the RFIC, as there is no synchronous "handshaking" between the RFIC and the external data source.
The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for
later transmission).
It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode. The chip
still internally samples the incoming TX Data stream to determine when edge transitions occur; however, rather
than sampling the data at a pre-programmed data rate, the chip now internally samples the incoming TX Data
stream at its maximum possible oversampling rate. This allows the chip to accurately determine the timing of the bit
edge transitions without prior knowledge of the data rate. (Of course, it is still necessary to program the desired
peak frequency deviation.)
Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not available
in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data rate, and thus
cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming data.
One advantage of this mode that it saves a microcontroller pin because no TX Clock output function is required.
The primary disadvantage of this mode is the increase in occupied spectral bandwidth with FSK (as compared to
GFSK).
Preliminary Rev. 0.1
29
Si4030/31/32-B1
4.2.2.3. Direct Mode using SPI or nIRQ Pins
In certain applications it may be desirable to minimize the connections to the microcontroller or to preserve the
GPIOs for other uses. For these cases it is possible to use the SPI pins and nIRQ as the modulation clock and
data. The SDO pin can be configured to be the data clock by programming trclk = 10. If the nSEL pin is LOW then
the function of the pin will be SPI data output. If the pin is high and trclk[1:0] is 10 then during TX mode the data
clock will be available on the SDO pin. If trclk[1:0] is set to 11 and no interrupts are enabled in registers 05 or 06h,
then the nIRQ pin can also be used as the TX data clock.
The SDI pin can be configured to be the data source in TX mode if dtmod[1:0] = 01. In a similar fashion, if nSEL is
LOW the pin will function as SPI data-in. If nSEL is HIGH then in TX mode it will be the data to be modulated and
transmitted. Figure 9 demonstrates using SDI and SDO as the TX data and clock:
TX on
command
TXoff
command
TX on
command
TX off
command
TX mode
TX mode
nSEL
SPI input
don’t care
don’t care
SPI input
MOD input
SPI input
don’t care
don’t care
SPI input
MOD output
SPI input
SDI
Data CLK
Output
Data CLK
Output
SPI output
SPI output
SPI output
SPI output
SPI output
SDO
Figure 9. Microcontroller Connections
If the SDO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by
programming Reg 0Eh bit 3.
4.2.3. PN9 Mode
In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The primary
purpose of this mode is for use as a test mode to observe the modulated spectrum without having to provide data.
30
Preliminary Rev. 0.1
Si4030/31/32-B1
5. Internal Functional Blocks
This section provides an overview some of the key blocks of the internal radio architecture.
5.1. Synthesizer
An integrated Sigma Delta (Σ∆) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided
on-chip. The Si4031/32 and Si4030 cover different frequencies. This section discusses the frequency range
covered by all EZRadioPRO devices. Using a Σ∆ synthesizer has many advantages; it provides flexibility in
choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly
to the loop in the digital domain through the fractional divider which results in very precise accuracy and control
over the transmit deviation.
Depending on the part, the PLL and - modulator scheme is designed to support any desired frequency and
channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz
(High band). The transmit data rate can be programmed between 0.123–256 kbps, and the frequency deviation
can be programmed between ±1–320 kHz. These parameters may be adjusted via registers as shown in "3.5.
Frequency Control" on page 22.
Selectable
Divider
Fref = 10 M
TX
PFD
CP
LPF
VCO
N
TX
Modulation
Delta-
Sigma
Figure 10. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip
inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the
desired output frequency band. The modulus of this divider stage is controlled dynamically by the output from the
- modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of
312.5 Hz anywhere in the range between 240–960 MHz.
5.1.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and
fb[4:0] fields in "Register 75h. Frequency Band Select." The VCO integrates the resonator inductor, tuning varactor,
so no external VCO components are required.
The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not
be desirable so the VCO calibration may be skipped by setting the appropriate register.
5.2. Power Amplifier
The Si4032 contains an internal integrated power amplifier (PA) capable of transmitting at output levels between –1
and +20 dBm. The Si4030/31 contains a PA which is capable of transmitting output levels between –8 to +13 dBm.
The PA design is single-ended and is implemented as a two stage class CE amplifier with a high efficiency when
transmitting at maximum power. The PA efficiency can only be optimized at one power level. Changing the output
power by adjusting txpow[2:0] will scale both the output power and current but the efficiency will not be constant.
The PA output is ramped up and down to prevent unwanted spectral splatter.
Preliminary Rev. 0.1
31
Si4030/31/32-B1
5.2.1. Output Power Selection
With the Si4032, the output power is configurable in 3 dB steps with the txpow[2:0] field in "Register 6Dh. TX
Power." Extra output power can allow the use of a cheaper, smaller antenna reducing the overall BOM cost. The
higher power setting of the chip achieves maximum possible range, but of course comes at the cost of higher TX
current consumption. However, depending on the duty cycle of the system, the effect on battery life may be
insignificant. Contact Silicon Labs Support for help in evaluating this tradeoff.
The +13 dBm output power of the Si4030/31 is targeted at systems that require lower output power. The PA still
offers high efficiency and a range of output power from –8 to +13 dBm.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/Description
6D R/W TX Power
txpow[2]
txpow[1] txpow[0]
07h
txpow[2:0]
000
Si4032 Output Power
+1 dBm
001
+2 dBm
010
+5 dBm
011
+8 dBm
100
+11 dBm
101
+14 dBm
110
+17 dBm
111
+20 dBm
txpow[2:0]
000
Si4030/31 Output Power
–8 dBm
001
–5 dBm
010
–2 dBm
011
+1 dBm
100
+4 dBm
101
+7 dBm
110
+10 dBm
111
+13 dBm
32
Preliminary Rev. 0.1
Si4030/31/32-B1
5.3. Crystal Oscillator
The Si4030/31/32 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs
when a suitable parallel resonant crystal is used. The design is differential with the required crystal load
capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-
chip is the 30 MHz crystal.
The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance
requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is
programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load Capacitance." The total
internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit is a
coarse shift in frequency but is not binary with xlc[6:0].
The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing the on-
chip temperature sensor and suitable control software, the temperature dependency of the crystal can be
canceled.
The typical value of the total on-chip capacitance Cint can be calculated as follows:
Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift
Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal
can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value
of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning. Additional information on
calculating Cext and crystal selection guidelines is provided in “AN417: Si4x3x Family Crystal Oscillator.”.
The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of
the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for the entire
system and the BOM cost is reduced. The available clock frequencies and GPIO configuration are discussed
further in "7.2. Microcontroller Clock" on page 40.
The Si4030/31/32 may also be driven with an external 30 MHz clock signal through the XOUT pin. When driving
with an external reference or using a TCXO, the XTAL load capacitance register should be set to 0.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/Description
09 R/W Crystal Oscillator Load
Capacitance
xtalshift
xlc[6]
xlc[5]
xlc[4]
xlc[3]
xlc[2]
xlc[1]
xlc[0]
40h
5.4. Regulators
There are a total of four regulators integrated onto the Si4030/31/32. With the exception of the digital regulator, all
regulators are designed to operate with only internal decoupling. The digital regulator requires an external 1 µF
decoupling capacitor. All regulators are designed to operate with an input supply voltage from +1.8 to +3.6 V. The
output stage of the of PA is not connected internally to a regulator and is connected directly to the battery voltage.
A supply voltage should only be connected to the VDD pins. No voltage should be forced on the digital regulator
output.
Preliminary Rev. 0.1
33
Si4030/31/32-B1
6. Data Handling and Packet Handler
The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the
modem to operate with packet formats without a preamble or other legacy packet structures contact customer
support.
6.1. TX FIFO
A 64 byte FIFO is integrated into the chip for TX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to
access the FIFO. A burst write, as described in "3.1. Serial Peripheral Interface (SPI)" on page 15, to address 7Fh
will write data to the TX FIFO.
TX FIFO
TX FIFO Almost Full
Threshold
TX FIFO Almost Empty
Threshold
Figure 11. FIFO Threshold
The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches
these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this register
corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO crosses
this threshold limit, an interrupt to the microcontroller is generated so the chip can enter TX mode to transmit the
contents of the TX FIFO. The second threshold for TX is the FIFO almost empty Threshold, txaethr[5:0]. When the
data being shifted out of the TX FIFO drops below the almost empty threshold an interrupt will be generated. The
microcontroller will need to switch out of TX mode or fill more data into the TX FIFO. The transceiver can be
configured so that when the TX FIFO is empty it will automatically exit the TX state and return to one of the low
power states. When TX is initiated, it will transmit the number of bytes programmed into the packet length field
(Reg 3Eh). When the packet ends, the chip will return to the state specified in register 07h. For example, if 08h is
written to address 07h then the chip will return to the STANDBY state. If 09h is written then the chip will return to
the READY state.
34
Preliminary Rev. 0.1
Si4030/31/32-B1
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/D
escription
08 R/W Operating & Reserved Reserved Reserved Reserved autotx Reserved Reserved ffclrtx
00h
Function
Control 2
7C R/W
7D R/W
TX FIFO
Control 1
Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0]
Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0]
37h
04h
TX FIFO
Control 2
The TX FIFO may be cleared or reset with the ffclrtx bit in “Register 08h. Operating Mode and Function Control 2.”
All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and
“Register 06h. Interrupt Enable 2,” on page 59. If the interrupts are not enabled the function will not generate an
interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers.
6.2. Packet Configuration
When using the FIFO, automatic packet handling may be enabled for the TX mode. "Register 30h. Data Access
Control" through “Register 3Eh. Packet Length,” on page 79 control the configuration for Packet Handling. The
usual fields for network communication (such as preamble, synchronization word, headers, packet length, and
CRC) can be configured to be automatically added to the data payload. The fields needed for packet generation
normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data
payload greatly reduces the amount of communication between the microcontroller and the Si4030/31/32 and
reduces the required computational power of the microcontroller.
The general packet structure is shown in Figure 12. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable
lengths to accommodate different applications. The most common CRC polynominals are available for selection.
Data
CRC
Preamble
1-512 Bytes
1-4 Bytes
0 or 2
Bytes
Figure 12. Packet Structure
An overview of the packet handler configuration registers is shown in Table 12.
6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field before
returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the FIFO the
microcontroller needs to command the chip to re-enter TX mode. Figure 14 provides an example transaction where
the packet length is set to three bytes.
Preliminary Rev. 0.1
35
Si4030/31/32-B1
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
This will be sent in the first transmission
}
}
}
This will be sent in the second transmission
This will be sent in the third transmission
Figure 13. Multiple Packets in TX Packet Handler
Table 12. Packet Handler Registers
Add R/W Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
30
31
32
33
34
36
37
38
39
3A
3B
3C
3D
3E
R/W
R
Data Access Control
EzMAC status
Reserved
0
lsbfrst
crcdonly
skip2ph
enpactx
encrc
crc[1]
pktx
crc[0]
8Dh
—
Reserved
Reserved Reserved Reserved Reserved
Reserved
pksent
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Header Control 2
Preamble Length
Sync Word 3
skipsyn
hdlen[2]
hdlen[1]
hdlen[0]
fixpklen
synclen[1] synclen[0] prealen[8]
22h
08h
2Dh
D4h
00h
00h
00h
00h
00h
00h
00h
prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0]
sync[31]
sync[23]
sync[15]
sync[7]
sync[30]
sync[22]
sync[14]
sync[6]
sync[29]
sync[21]
sync[13]
sync[5]
sync[28]
sync[20]
sync[12]
sync[4]
sync[27]
sync[19]
sync[11]
sync[3]
txhd[27]
txhd[19]
txhd[11]
txhd[3]
sync[26]
sync[18]
sync[10]
sync[2]
sync[25]
sync[17]
sync[9]
sync[1]
txhd[25]
txhd[17]
txhd[9]
sync[24]
sync[16]
sync[8]
sync[0]
txhd[24]
txhd[16]
txhd[8]
Sync Word 2
Sync Word 1
Sync Word 0
Transmit Header 3
Transmit Header 2
Transmit Header 1
Transmit Header 0
Transmit Packet Length
txhd[31]
txhd[23]
txhd[15]
txhd[7]
txhd[30]
txhd[22]
txhd[14]
txhd[6]
txhd[29]
txhd[21]
txhd[13]
txhd[5]
txhd[28]
txhd[20]
txhd[12]
txhd[4]
txhd[26]
txhd[18]
txhd[10]
txhd[2]
txhd[1]
txhd[0]
pklen[7]
pklen[6]
pklen[5]
pklen[4]
pklen[3]
pklen[2]
pklen[1]
pklen[0]
36
Preliminary Rev. 0.1
Si4030/31/32-B1
6.4. Data Whitening, Manchester Encoding, and CRC
Data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to achieve a
more uniform spectrum. When enabled, the payload data bits are XORed with a pseudorandom sequence output
from the built-in PN9 generator. The generator is initialized at the beginning of the payload. The receiver recovers
the original data by repeating this operation. Manchester encoding can be used to ensure a dc-free transmission
and good synchronization properties. When Manchester encoding is used, the effective datarate is unchanged but
the actual datarate (preamble length, etc.) is doubled due to the nature of the encoding. The effective datarate
when using Manchester encoding is limited to 128 kbps. The implementation of Manchester encoding is shown in
Figure 15. Data whitening and Manchester encoding can be selected with "Register 70h. Modulation Mode Control
1". The CRC is configured via "Register 30h. Data Access Control". Figure 14 demonstrates the portions of the
packet which have Manchester encoding, data whitening, and CRC applied. CRC can be applied to only the data
portion of the packet or to the data, packet length and header fields. Figure 15 provides an example of how the
Manchester encoding is done and also the use of the Manchester invert (enmaniv) function.
Manchester
Whitening
CRC
CRC
(Over data only)
Header/
Address
PK
Length
Preamble
Sync
CRC
Data
Figure 14. Operation of Data Whitening, Manchester Encoding, and CRC
Data before Manchester
1
1
1
1
1
1
1
1
0
0
0
1
0
Preamble = 0xFF
First 4bits of the synch. word = 0x2
Data after Machester ( manppol = 1, enmaninv = 0)
Data after Machester ( manppol = 1, enmaninv = 1)
Data before Manchester
0
0
0
0
0
0
0
0
0
0
0
1
0
Preamble = 0x00
First 4bits of the synch. word = 0x2
Data after Machester ( manppol = 0, enmaninv = 0)
Data after Machester ( manppol = 0, enmaninv = 1)
Figure 15. Manchester Coding Example
6.5. Synchronization Word Configuration
The synchronization word length can be configured in Reg 33h, synclen[1:0]. The expected or transmitted sync
word can be configured from 1 to 4 bytes as defined below:
synclen[1:0] = 00—Transmitted Synchronization Word (sync word) 3.
synclen[1:0] = 01—Transmitted Synchronization Word 3 first, followed by sync word 2.
synclen[1:0] = 10—Transmitted Synchronization Word 3 first, followed by sync word 2, followed by sync word 1.
synclen[1:0] = 1—Transmitted Synchronization Word 3 first, followed by sync word 2, followed by sync word 1,
followed by sync word 0.
The sync is transmitted in the following sequence: sync 3sync 2sync 1sync 0. The sync word values can be
programmed in Registers 36h–39h.
Preliminary Rev. 0.1
37
Si4030/31/32-B1
6.6. TX Retransmission and Auto TX
The Si4030/31/32 is capable of automatically retransmitting the last packet loaded in the TX FIFO. Automatic
retransmission is set by entering the TX state with the txon bit without reloading the TX FIFO. This feature is useful
for beacon transmission or when retransmission is required due to the absence of a valid acknowledgement. Only
packets that fit completely in the TX FIFO can be automatically retransmitted.
An automatic transmission function is available, allowing the radio to automatically start or stop a transmission
depending on the amount of data in the TX FIFO.
When autotx is set in “Register 08. Operating & Function Control 2," the transceiver will automatically enter the TX
state when the TX FIFO almost full threshold is exceeded. Packets will be transmitted according to the configured
packet length. To stop transmitting, clear the packet sent or TX FIFO almost empty interrupts must be cleared by
reading register.
38
Preliminary Rev. 0.1
Si4030/31/32-B1
7. Auxiliary Functions
7.1. Smart Reset
The Si4030/31/32 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both
a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce a
reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occur:
Initial power on, VDD starts from gnd: reset is active till V reaches V (see table);
DD
RR
When V decreases below V for any reason: reset is active till V reaches V ;
RR
DD
LD
DD
A software reset via “Register 08h. Operating Mode and Function Control 2,” on page 61: reset is active for time
T
SWRST
V
glitch when the supply voltage exceeds the following time functioned limit:
DD
VDD nom.
VDD(t)
reset limit:
0.4V+t*0.2V/ms
actual VDD(t)
showing glitch
0.4V
Reset
TP
t
t=0,
VDD starts to rise
reset:
Vglitch>=0.4+t*0.2V/ms
Figure 16. POR Glitch Parameters
Table 13. POR Parameters
Parameter
Symbol
VRR
Comment
Min
0.85
0.03
0.7
50
Typ
1.3
—
Max
1.75
300
1.3
470
—
Unit
V
Release Reset Voltage
Power-On VDD Slope
Low VDD Limit
SVDD
VLD
tested VDD slope region
VLD<VRR is guaranteed
V/ms
V
1
Software Reset Pulse
Threshold Voltage
TSWRST
VTSD
k
—
µs
—
0.4
0.2
15
V
Reference Slope
—
—
V/ms
ms
VDD Glitch Reset Pulse
TP
Also occurs after SDN, and
initial power on
5
40
The reset will initialize all registers to their default values. The reset signal is also available for output and use by
the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on
GPIO_1.
Preliminary Rev. 0.1
39
Si4030/31/32-B1
7.2. Microcontroller Clock
The 30 MHz crystal oscillator frequency is divided down internally and may be output to the microcontroller through
GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock
frequency is selectable from one of 8 options, as shown below. Except for the 32.768 kHz option, all other
frequencies are derived by dividing the crystal oscillator frequency. The 32.768 kHz clock signal is derived from an
internal RC oscillator or an external 32 kHz crystal. The default setting for GPIO2 is to output the microcontroller
clock signal with a frequency of 1 MHz.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/Description
0A R/W
Microcontroller Output Clock
clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0]
0Bh
mclk[2:0]
000
Clock Frequency
30 MHz
001
15 MHz
010
10 MHz
011
4 MHz
100
3 MHz
101
2 MHz
110
1 MHz
111
32.768 kHz
If the microcontroller clock option is being used there may be the need of a system clock for the microcontroller
while the Si4030/31/32 is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save
current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This
feature is called enable low frequency clock and is enabled by the enlfc bit in “Register 0Ah. Microcontroller Output
Clock." When enlfc = 1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided to the
microcontroller as the system clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz
will be provided through the GPIO output pin to the microcontroller as the system clock in all IDLE or TX states.
When the chip enters SLEEP mode, the system clock will automatically switch to 32.768 kHz from the RC oscillator
or 32.768 XTAL.
Another available feature for the microcontroller clock is the clock tail, clkt[1:0] in “Register 0Ah. Microcontroller
Output Clock." If the low frequency clock feature is not enabled (enlfc = 0), then the system clock to the
microcontroller is disabled in SLEEP mode. However, it may be useful to provide a few extra cycles for the
microcontroller to complete its operation prior to the shutdown of the system clock signal. Setting the clkt[1:0] field
will provide additional cycles of the system clock before it shuts off.
clkt[1:0]
Clock Tail
0 cycles
00
01
10
11
128 cycles
256 cycles
512 cycles
If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon
as the interrupt is read the state machine will then move to the selected mode. The minimum current consumption
will not be achieved until the interrupt is read. For instance, if the chip is commanded to SLEEP mode but an
interrupt has occurred the 30 MHz XTAL will not be disabled until the interrupt has been cleared.
40
Preliminary Rev. 0.1
Si4030/31/32-B1
7.3. General Purpose ADC
An 8-bit SAR ADC is integrated for general purpose use, as well as for digitizing the on-chip temperature sensor
reading. Registers 0Fh "ADC Configuration", 10h "Sensor Offset" and 4Fh "Amplifier Offset" can be used to
configure the ADC operation. Details of these registers are on pages 67 and 68, respectively.
Every time an ADC conversion is desired, bit 7 "adcstart/adcbusy" in “Register 1Fh. Clock Recovery Gearshift
Override” must be set to 1. This is a self clearing bit that will be reset to 0 at the end of the conversion cycle of the
ADC. The conversion time for the ADC is 350 µs. After this time or when the "adcstart/adcbusy" bit is cleared, then
the ADC value may be read out of “Register 11h. ADC Value."
The architecture of the ADC is shown in Figure 17. The signal and reference inputs of the ADC are selected by
adcsel[2:0] and adcref[1:0] in register 0Fh “ADC Configuration”, respectively. The default setting is to read out the
temperature sensor using the bandgap voltage (VBG) as reference. With the VBG reference the input range of the
ADC is from 0-1.02 V with an LSB resolution of 4 mV (1.02/255). Changing the ADC reference will change the LSB
resolution accordingly.
A differential multiplexer and amplifier are provided for interfacing external bridge sensors. The gain of the amplifier
is selectable by adcgain[1:0] in Register 0Fh. The majority of sensor bridges have supply voltage (VDD) dependent
gain and offset. The reference voltage of the ADC can be changed to either V /2 or V /3. A programmable V
DD
DD
DD
dependent offset voltage can be added using soffs[3:0] in register 10h.
See “AN448: General Purpose ADC Configuration” for more details on the usage of the general purpose ADC.
Diff. MUX
Diff. Amp.
Input MUX
aoffs [4:0]
soffs [3:0]
adcsel [2:0]
adcgain [1:0]
GPIO0
GPIO1
GPIO2
8-bit ADC
Temperature Sensor
Vin
adc [7:0]
adcsel [2:0]
Vref
0 -1020mV / 0-255
Ref MUX
VDD / 3
DD / 2
V
VBG (1.2V)
adcref [1:0]
Figure 17. General Purpose ADC Architecture
Add R/W
Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
0F
10
11
R/W
R/W
R
ADC Configuration
adcstart/adcbusy adcsel[2] adcsel[1] adcsel[0] adcref[1]
soffs[3]
adcref[0] adcgain[1] adcgain[0]
00h
Sensor Offset
ADC Value
soffs[2]
adc[2]
soffs[1]
adc[1]
soffs[0]
adc[0]
00h
—
adc[7]
adc[6]
adc[5]
adc[4]
adc[3]
Preliminary Rev. 0.1
41
Si4030/31/32-B1
7.4. Temperature Sensor
An integrated on-chip analog temperature sensor is available. The temperature sensor will be automatically
enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is
selected on the analog test bus. The temperature sensor value may be digitized using the general-purpose ADC
and read out over the SPI through "Register 10h. ADC Sensor Amplifier Offset." The range of the temperature
sensor is configurable. Table 14 lists the settings for the different temperature ranges and performance.
To use the Temp Sensor:
1. Set the input for ADC to the temperature sensor, "Register 0Fh. ADC Configuration"—adcsel[2:0] = 000
2. Set the reference for ADC, "Register 0Fh. ADC Configuration"—adcref[1:0] = 00
3. Set the temperature range for ADC, "Register 12h. Temperature Sensor Calibration"—tsrange[1:0]
4. Set entsoffs = 1, "Register 12h. Temperature Sensor Calibration"
5. Trigger ADC reading, "Register 0Fh. ADC Configuration"—adcstart = 1
6. Read temperature value—Read contents of "Register 11h. ADC Value"
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W Function/Description
tsrange[1]
tsrange[0] entsoffs entstrim
tstrim[3]
tstrim[2] vbgtrim[1] vbgtrim[0]
12 R/W
Temperature
20h
Sensor Control
tvoffs[7]
tvoffs[6]
tvoffs[5] tvoffs[4]
tvoffs[3]
tvoffs[2]
tvoffs[1]
tvoffs[0]
13 R/W Temperature Value Offset
00h
Table 14. Temperature Sensor Range
entoff
tsrange[1]
tsrange[0]
Temp. range Unit
Slope
ADC8 LSB
0.5 °C
1 °C
1
1
0
0
1
1
1
0
1
0
1
0
–64 … 64
–64 … 192
0 … 128
°C
°C
°C
°F
°K
8 mV/°C
4 mV/°C
8 mV/°C
4 mV/°F
3 mV/°K
1
0.5 °C
1 °F
1
–40 … 216
0 … 341
0*
1.333 °K
*Note: Absolute temperature mode, no temperature shift. This mode is only for test purposes. POR value of
EN_TOFF is 1.
The slope of the temperature sensor is very linear and monotonic. For absolute accuracy better than 10 °C
calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in “Register 12h.
Temperature Sensor Control” and setting the offset with the tvoffs[7:0] bits in “Register 13h. Temperature Value
Offset.” This method adds a positive offset digitally to the ADC value that is read in “Register 11h. ADC Value.” The
other method of calibration is to use the tstrim which compensates the analog circuit. This is done by setting
entstrim = 1 and using the tstrim[2:0] bits to offset the temperature in “Register 12h. Temperature Sensor Control.”
With this method of calibration, a negative offset may be achieved. With both methods of calibration better than
±3 °C absolute accuracy may be achieved.
The different ranges for the temperature sensor and ADC8 are demonstrated in Figure 18. The value of the ADC8
may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature in Temp Range.
For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64.
42
Preliminary Rev. 0.1
Si4030/31/32-B1
Temperature Measurement with ADC8
300
250
200
150
100
Sensor Range 0
Sensor Range 1
Sensor Range 2
Sensor Range 3
50
0
-40
-20
0
20
40
60
80
100
Temperature [Celsius]
Figure 18. Temperature Ranges using ADC8
Preliminary Rev. 0.1
43
Si4030/31/32-B1
7.5. Low Battery Detector
A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed
into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold." When the digitized battery voltage
reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller can
confirm source of the interrupt by reading "Register 03h. Interrupt/Status 1" and “Register 04h. Interrupt/Status 2,”
on page 56.
If the LBD is enabled while the chip is in SLEEP mode, it will automatically enable the RC oscillator which will
periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be read out
through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The low battery detect function
is enabled by setting enlbd=1 in "Register 07h. Operating Mode and Function Control 1".
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
14h
Ad R/W
Function/Description
1A R/W Low Battery Detector Threshold
lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0]
vbat[4] vbat[3] vbat[2] vbat[1] vbat[0]
1B
R
Battery Voltage Level
0
0
0
—
The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled, enlbd = 1 in "Register 07h.
Operating Mode and Function Control 1", the battery voltage may be read at anytime by reading "Register 1Bh.
Battery Voltage Level." A battery voltage threshold may be programmed in “Register 1Ah. Low Battery Detector
Threshold." When the battery voltage level drops below the battery voltage threshold an interrupt will be generated
on the nIRQ pin to the microcontroller if the LBD interrupt is enabled in “Register 06h. Interrupt Enable 2,” on page
59. The microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03
and 04h. The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in the table below. If the
LBD is enabled the LBD and ADC will automatically be enabled every 1 s for approximately 250 µs to measure the
voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated four consecutive
readings are required.
BatteryVoltage 1.7 50mV ADCValue
ADC Value
VDD Voltage [V]
< 1.7
0
1
1.7–1.75
1.75–1.8
…
2
…
29
30
31
3.1–3.15
3.15–3.2
> 3.2
44
Preliminary Rev. 0.1
Si4030/31/32-B1
7.6. Wake-Up Timer
The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode.
The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run
when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP
mode, the wake-up timer will count for a time specified defined in Registers 14–16h, "Wake Up Timer Period." At
the expiration of this period an interrupt will be generated on the nIRQ pin if this interrupt is enabled. The
microcontroller will then need to verify the interrupt by reading the Registers 03h–04h, "Interrupt Status 1 & 2". The
wake-up timer value may be read at any time by the wtv[15:0] read only registers 13h–14h.
The formula for calculating the Wake-Up Period is the following:
4 M 2R
32.768
WUT
ms
WUT Register
wtr[3:0]
Description
R Value in Formula
D Value in Formula
M Value in Formula
wtd[1:0]
wtm[15:0]
Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by using
the R value.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
00h
Add R/W Function/Description
14 R/W Wake-Up Timer Period 1
wtr[3]
wtr[2]
wtr[1]
wtr[0] wtd[1] wtd[0]
15 R/W Wake-Up Timer Period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8]
16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0]
00h
00h
17
18
R
R
Wake-Up Timer Value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8]
Wake-Up Timer Value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0]
—
—
There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled
in “Register 06h. Interrupt Enable 2,” on page 59. If the WUT interrupt is enabled then nIRQ pin will go low when
the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the microcontroller
clock output is available for the microcontroller to use to process the interrupt. The other method of use is to not
enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the chip will not change state
until commanded by the microcontroller. The different modes of operating the WUT and the current consumption
impacts are demonstrated in Figure 19.
A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in “Register 07h. Operating
& Function Control 1," GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to
this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be
connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set,
all internal functions such as WUT, microcontroller clock, and LDC mode will use the 32 kHz XTAL and not the
32 kHz RC oscillator.
Preliminary Rev. 0.1
45
Si4030/31/32-B1
Interrupt Enable enwut =1( Reg 06h)
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Ready
Sleep
Ready
1.5 mA
Sleep
1 uA
Ready
1.5 mA
Sleep
1.5 mA
Current
Consumption
1 uA
1 uA
Interrupt Enable enwut =0( Reg 06h)
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Current
Consumption
1 uA
Figure 19. WUT Interrupt and WUT Operation
46
Preliminary Rev. 0.1
Si4030/31/32-B1
7.7. GPIO Configuration
Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control,
Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode
all the GPIO pads are pulled low.
Note: The ADC should not be selected as an input to the GPIO in Standby or Sleep Modes and will cause excess current con-
sumption.
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
Add R/W
Function/
Description
0B R/W
0C R/W
0D R/W
0E R/W
GPIO0
Configuration
gpio0drv[1] gpio0drv[0] pup0
gpio1drv[1] gpio1drv[0] pup1
gpio2drv[1] gpio2drv[0] pup2
gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0]
gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0]
gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0]
00h
00h
00h
00h
GPIO1
Configuration
GPIO2
Configuration
I/O Port
extitst[2] extitst[1] extitst[0]
itsdo
dio2
dio1
dio0
Configuration
The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default
setting. The default settings for each GPIO are listed below:
GPIO
GPIO0
GPIO1
GPIO2
00000—Default Setting
POR
POR Inverted
Microcontroller Clock
For a complete list of the available GPIO's see “AN466: Si4430/31/32 Register Descriptions.”
The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase the drive
strength and current capability of the GPIO by changing the driver size. Special care should be taken in setting the
drive strength and loading on GPIO2 when the microcontroller clock is used. Excess loading or inadequate drive
may contribute to increased spurious emissions.
Preliminary Rev. 0.1
47
Si4030/31/32-B1
8. Reference Design
Reference designs are available at www.silabs.com for many common applications which include recommended
schematics, BOM, and layout. TX matching component values for the different frequency bands can be found in
the application notes “AN435: Si4032/4432 PA Matching” and “AN436: Si4030/4031/4430/4431 PA Matching.”
ꢘ ?
ꢘ ?
! ꢘ = ꢕ
ꢗ " ꢐ
ꢌ 8
ꢌ A
ꢌ B
ꢌ ꢚ
ꢏ ꢋ
ꢌ ꢋ
:
= ꢐ
ꢏ < ꢊ > ?
ꢚ
B
A
8
ꢓ 4 ꢔ ꢊ
ꢔ =
ꢕ " =
ꢌ < ꢊ > ?
ꢋ < ꢊ > ?
ꢑ = &
48
Preliminary Rev. 0.1
Si4030/31/32-B1
9. Application Notes and Reference Designs
A comprehensive set of application notes and reference designs are available to assist with the development of a
radio system. A partial list of applications notes is given below.
For the complete list of application notes, latest reference designs and demos visit the Silicon Labs website.
AN361: Wireless MBUS Implementation using EZRadioPRO Devices
AN379: Antenna Diversity with EZRadioPRO
AN414: EZRadioPRO Layout Design Guide
AN415: EZRadioPRO Programming Guide
AN417: Si4x3x Family Crystal Oscillators
AN419: ARIB STD-T67 Narrow-Band 426/429 MHz Measured on the Si4431-A0
AN427: EZRadioPRO Si433x and Si443x RX LNA Matching
AN429: Using the DC-DC Converter on the F9xx Series MCU for Single Battery Operation with the
EZRadioPRO RF Devices
AN432: RX BER Measurement on EZRadioPRO with a Looped PN Sequence
AN435: Si4032/4432 PA Matching
AN436: Si4030/4031/4430/4431 PA Matching
AN437: 915 MHz Measurement Results and FCC Compliance
AN439: EZRadioPRO Quick Start Guide
AN440: Si4430/31/32 Detailed Register Descriptions
AN445: Si4431 RF Performance and ETSI Compliance Test Results
AN448: General Purpose ADC Configuration
AN453: Using the EZRadioPRO Calculator and Advanced RX BW Calculations and Settings
AN459: 950 MHz Measurement Results and ARIB Compliance
AN460: 470 MHz Measurement Results for China
AN461:+24 dBm External PA Application Note and Reference Design
AN462: Extended battery life using the EZRadioPRO and a DC-DC Buck Converter
AN463: Support for Non-Standard Packet Structures and RAW Mode
AN466: Si4030/31/32 Register Descriptions
AN467: Si4330 Register Descriptions
10. Customer Support
Technical support for the complete family of Silicon Labs wireless products is available by accessing the wireless
section of the Silicon Labs' website at www.silabs.com\wireless. For answers to common questions please visit the
wireless knowledge base at www.silabs.com/support/knowledgebase.
Preliminary Rev. 0.1
49
Si4030/31/32-B1
11. Register Table and Descriptions
Table 15. Register Descriptions
Add R/W
Function/Desc
Data
D4
vc[4]
Reserved
Reserved
Reserved
Reserved
Reserved
x32ksel
POR
Default
D7
0
ffovfl
D6
0
ffunfl
itxffafull
Reserved
entxffafull
Reserved
enlbd
D5
0
D3
vc[3]
reserved
iext
D2
vc[2]
reserved
ipksent
ilbd
enpksent
enlbd
Reserved
enldm
xlc[2]
D1
vc[1]
cps[1]
Reserved
ichiprdy
Reserved
enchiprdy
pllon
D0
vc[0]
cps[0]
Reserved
ipor
Reserved
enpor
xton
01
02
03
04
05
06
07
08
09
R
R
R
R
R/W
R/W
Device Version
Device Status
Interrupt Status 1
Interrupt Status 2
Interrupt Enable 1
Interrupt Enable 2
06h
—
—
ifferr
itxffaem
Reserved
entxffaem
Reserved
enwt
Reserved
enfferr
Reserved
swres
Reserved
xtalshft
iwut
—
enext
enwut
txon
autotx
xlc[3]
00h
03h
01h
00h
7Fh
R/W Operating & Function Control 1
R/W Operating & Function Control 2
R/W
Reserved
xlc[6]
Reserved
xlc[5]
Reserved
xlc[4]
Reserved
xlc[1]
ffclrtx
xlc[0]
Crystal Oscillator Load
Capacitance
0A
0B
0C
0D
0E
0F
R/W
R/W
R/W
R/W
R/W
R/W
Microcontroller Output Clock
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
I/O Port Configuration
ADC Configuration
Reserved
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
Reserved
Reserved
gpio0drv[0]
gpio1drv[0]
gpio2drv[0]
extitst[2]
clkt[1]
pup0
pup1
pup2
extitst[1]
adcsel[1]
clkt[0]
gpio0[4]
gpio1[4]
gpio2[4]
extitst[0]
adcsel[0]
enlfc
gpio0[3]
gpio1[3]
gpio2[3]
itsdo
mclk[2]
gpio0[2]
gpio1[2]
gpio2[2]
dio2
mclk[1]
gpio0[1]
gpio1[1]
gpio2[1]
dio1
mclk[0]
gpio0[0]
gpio1[0]
gpio2[0]
dio0
06h
00h
00h
00h
00h
00h
adcstart/adc-
adcsel[2]
adcref[1]
adcref[0]
adcgain[1]
adcgain[0]
done
10
11
R/W
R
ADC Sensor Amplifier Offset
ADC Value
Reserved
adc[7]
Reserved
adc[6]
Reserved
adc[5]
Reserved
adc[4]
adcoffs[3]
adc[3]
adcoffs[2]
adc[2]
adcoffs[1]
adc[1]
adcoffs[0]
adc[0]
00h
—
12
13
14
15
16
17
18
19
1A
1B
1C-2F
30
31
32
33
34
36
37
38
39
3A
3B
3C
3D
3E
4F
60
62
6D
6E
6F
70
71
72
73
74
75
76
77
79
R/W
R/W
R/W
R/W
R/W
R
Temperature Sensor Control
Temperature Value Offset
Wake-Up Timer Period 1
Wake-Up Timer Period 2
Wake-Up Timer Period 3
Wake-Up Timer Value 1
Wake-Up Timer Value 2
tsrange[1]
tvoffs[7]
Reserved
wtm[15]
wtm[7]
tsrange[0]
tvoffs[6]
Reserved
wtm[14]
wtm[6]
entsoffs
tvoffs[5]
Reserved
wtm[13]
wtm[5]
wtv[13]
wtv[5]
Reserved
Reserved
0
Reserved
crcdonly
Reserved
entstrim
tvoffs[4]
wtr[4]
wtm[12]
wtm[4]
wtv[12]
wtv[4]
tstrim[3]
tvoffs[3]
wtr[3]
wtm[11]
wtm[3]
wtv[11]
wtv[3]
tstrim[2]
tvoffs[2]
wtr[2]
wtm[10]
wtm[2]
wtv[10]
wtv[2]
tstrim[1]
tvoffs[1]
wtr[1]
wtm[9]
wtm[1]
wtv[9]
tstrim[0]
tvoffs[0]
wtr[0]
wtm[8]
wtm[0]
wtv[8]
20h
00h
03h
00h
01h
—
wtv[15]
wtv[7]
wtv[14]
wtv[6]
R
wtv[1]
wtv[0]
—
R/W Low Battery Detector Threshold
R
Reserved
0
Reserved
0
lbdt[4]
vbat[4]
lbdt[3]
vbat[3]
lbdt[2]
vbat[2]
lbdt[1]
vbat[1]
lbdt[0]
vbat[0]
14h
—
Battery Voltage Level
R/W
R
Data Access Control
EzMAC status
Reserved
0
lsbfrst
Reserved
Reserved
Reserved
enpactx
Reserved
encrc
Reserved
crc[1]
pktx
crc[0]
pksent
8Dh
—
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Header Control 2
Preamble Length
Sync Word 3
Sync Word 2
Sync Word 1
Reserved
prealen[7]
sync[31]
sync[23]
sync[15]
sync[7]
txhd[31]
txhd[23]
txhd[15]
txhd[7]
hdlen[2]
prealen[6]
sync[30]
sync[22]
sync[14]
sync[6]
txhd[30]
txhd[22]
txhd[14]
txhd[6]
hdlen[1]
prealen[5]
sync[29]
sync[21]
sync[13]
sync[5]
txhd[29]
txhd[21]
txhd[13]
txhd[5]
hdlen[0]
prealen[4]
sync[28]
sync[20]
sync[12]
sync[4]
txhd[28]
txhd[20]
txhd[12]
txhd[4]
fixpklen
prealen[3]
sync[27]
sync[19]
sync[11]
sync[3]
txhd[27]
txhd[19]
txhd[11]
txhd[3]
synclen[1]
prealen[2]
sync[26]
sync[18]
sync[10]
sync[2]
txhd[26]
txhd[18]
txhd[10]
txhd[2]
synclen[0]
prealen[1]
sync[25]
sync[17]
sync[9]
prealen[8]
prealen[0]
sync[24]
sync[16]
sync[8]
22h
08h
2Dh
D4h
00h
00h
00h
00h
00h
00h
00h
10h
Sync Word 0
sync[1]
sync[0]
Transmit Header 3
Transmit Header 2
Transmit Header 1
Transmit Header 0
Transmit Packet Length
ADC8 Control
txhd[25]
txhd[17]
txhd[9]
txhd[1]
pklen[1]
adc8[1]
txhd[24]
txhd[16]
txhd[8]
txhd[0]
pklen[0]
adc8[0]
pklen[7]
Reserved
pklen[6]
Reserved
pklen[5]
adc8[5]
Reserved
pwst[0]
pklen[4]
adc8[4]
pklen[3]
adc8[3]
pklen[2]
adc8[2]
R/W Crystal Oscillator/Control Test
pwst[2]
papeakval
txdr[15]
txdr[7]
Reserved
trclk[1]
fd[7]
pwst[1]
papeaken
txdr[14]
txdr[6]
Reserved
trclk[0]
fd[6]
fo[6]
Reserved
sbsel
clkhyst
enbias2x
Ina_sw
txdr[11]
txdr[3]
manppol
eninv
fd[3]
fo[3]
Reserved
fb[3]
fc[11]
enamp2x
txpow[2]
txdr[10]
txdr[2]
enmaninv
fd[8]
fd[2]
fo[2]
Reserved
fb[2]
fc[10]
bufovr
txpow[1]
txdr[9]
txdr[1]
enmanch
modtyp[1]
fd[1]
fo[1]
fo[9]
fb[1]
fc[9]
enbuf
txpow[0]
txdr[8]
txdr[0]
enwhite
modtyp[0]
fd[0]
fo[0]
fo[8]
fb[0]
fc[8]
24h
18h
0Ah
3Dh
0Ch
00h
20h
00h
00h
75h
BBh
80h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TX Power
TX Data Rate 1
TX Data Rate 0
papeaklvl[1] papeaklvl[0]
txdr[13]
txdr[5]
txdtrtscale
dtmod[1]
fd[5]
fo[5]
Reserved
hbsel
txdr[12]
txdr[4]
enphpwdn
dtmod[0]
fd[4]
fo[4]
Reserved
fb[4]
Modulation Mode Control 1
Modulation Mode Control 2
Frequency Deviation
Frequency Offset 1
fo[7]
Frequency Offset 2
Reserved
Reserved
fc[15]
fc[7]
fhch[7]
Frequency Band Select
Nominal Carrier Frequency 1
Nominal Carrier Frequency 0
Frequency Hopping Channel
Select
fc[14]
fc[6]
fhch[6]
fc[13]
fc[5]
fhch[5]
fc[12]
fc[4]
fhch[4]
fc[3]
fhch[3]
fc[2]
fhch[2]
fc[1]
fhch[1]
fc[0]
fhch[0]
7A
7C
7D
7E
7F
R/W Frequency Hopping Step Size
fhs[7]
Reserved
Reserved
fhs[6]
Reserved
Reserved
fhs[5]
txafthr[5]
txaethr[5]
Reserved
fifod[5]
fhs[4]
txafthr[4]
txaethr[4]
fhs[3]
txafthr[3]
txaethr[3]
fhs[2]
txafthr[2]
txaethr[2]
fhs[1]
txafthr[1]
txaethr[1]
fhs[0]
txafthr[0]
txaethr[0]
00h
37h
04h
R/W
R/W
TX FIFO Control 1
TX FIFO Control 2
R/W
FIFO Access
fifod[7]
fifod[6]
fifod[4]
fifod[3]
fifod[2]
fifod[1]
fifod[0]
—
Note: Detailed register descriptions are available in “AN466: Si4030/31/32 Register Descriptions.”
50
Preliminary Rev. 0.1
Si4030/31/32-B1
12. Pin Descriptions: Si4030/31/32
20 19 18 17
VDD_RF
TX
1
16
2
15 SCLK
14 SDI
13 SDO
12 VDD_DIG
11 NC
NC
3
4
5
GND
PAD
NC
NC
6
7
8
9
10
Pin
Pin Name
I/O
Description
1
VDD_RF
VDD +1.8 to +3.6 V supply voltage input to all analog +1.7 V regulators. The recommended VDD supply voltage
is +3.3 V.
2
TX
O
Transmit output pin. The PA output is an open-drain connection so the L-C match must supply VDD
(+3.3 VDC nominal) to this pin.
3–6
NC
—
No Connect.
7
8
9
GPIO_0
GPIO_1
GPIO_2
I/O
I/O
I/O
General Purpose Digital I/O that may be configured through the registers to perform various functions
including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW,
AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for
more information.
10
11
VR_DIG
NC
O
Regulated Output Voltage of the Digital 1.7 V Regulator. A 1 µF decoupling capacitor is required.
—
Internally this pin is tied to the paddle of the package. This pin should be left unconnected or connected to
GND only.
12
VDD_DIG
VDD +1.8 to +3.6 V supply voltage input to the Digital +1.7 V Regulator. The recommended VDD supply voltage
is +3.3 V.
13
14
SDO
SDI
O
I
0–VDD V digital output that provides a serial readback function of the internal control registers.
Serial Data input. 0–VDD V digital input. This pin provides the serial data stream for the 4-line serial data
bus.
15
16
17
SCLK
nSEL
nIRQ
I
I
Serial Clock input. 0–VDD V digital input. This pin provides the serial data clock function for the 4-line
serial data bus. Data is clocked into the Si4030/31/32 on positive edge transitions.
Serial Interface Select input. 0– VDD V digital input. This pin provides the Select/Enable function for the 4-
line serial data bus. The signal is also used to signify burst read/write mode.
O
General Microcontroller Interrupt Status output. When the Si4030/31/32 exhibits anyone of the Interrupt
Events the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information
on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a cor-
responding SPI Interrupt Status Registers, Address 03h and 04h. No external resistor pull-up is required,
but it may be desirable if multiple interrupt lines are connected.
18
XOUT
O
Crystal Oscillator Output. Connect to an external 30 MHz crystal or to an external source. If using an
external source with no crystal then dc coupling with a nominal 0.8 VDC level is recommended with a min-
imum amplitude of 700 mVpp.
19
20
XIN
SDN
I
I
Crystal Oscillator Input. Connect to an external 30 MHz crystal or leave floating when driving with an
external source on XOUT.
Shutdown input pin. 0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode. When
SDN =1 the chip will be completely shutdown and the contents of the registers will be lost.
PKG
PADDLE_GND
GND The exposed metal paddle on the bottom of the Si4030/31/32 supplies the RF and circuit ground(s) for the
entire chip. It is very important that a good solder connection is made between this exposed metal paddle
and the ground plane of the PCB underlying the Si4030/31/32.
Preliminary Rev. 0.1
51
Si4030/31/32-B1
13. Ordering Information
Part
Number*
Description
Package
Type
Operating
Temperature
Si4030-B1-FM ISM EZRadioPRO Transmitter
Si4031-B1-FM ISM EZRadioPRO Transmitter
Si4032-B1-FM ISM EZRadioPRO Transmitter
QFN-20
Pb-free
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
QFN-20
Pb-free
QFN-20
Pb-free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
52
Preliminary Rev. 0.1
Si4030/31/32-B1
14. Package Markings (Top Marks)
14.1. Si4030/31/32 Top Mark
14.2. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
X = Part Number
0 = Si4030
1 = Si4031
2 = Si4032
Line 2 Marking:
Line 3 Marking:
R = Die Revision
B = Revision B1
TTTTT = Internal Code
Internal tracking code.
YY= Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and workweek of the mold date.
Preliminary Rev. 0.1
53
Si4030/31/32-B1
15. Package Outline: Si4030/31/32
Figure 21 illustrates the package details for the Si4030/31/32. Table 16 lists the values for the dimensions shown in
the illustration.
Figure 21. 20-Pin Quad Flat No-Lead (QFN)
Table 16. Package Dimensions
Symbol
Millimeters
Nom
0.85
Min
0.80
0.00
0.18
Max
0.90
0.05
0.30
A
A1
b
0.02
0.25
D
D2
e
E
E2
L
aaa
bbb
ccc
ddd
eee
4.00 BSC
2.60
0.50 BSC
4.00 BSC
2.60
2.55
2.65
2.50
0.30
—
—
—
2.70
0.50
0.10
0.10
0.08
0.10
0.10
0.40
—
—
—
—
—
—
—
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
Variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
54
Preliminary Rev. 0.1
Si4030/31/32-B1
16. PCB Land Pattern: Si4030/31/32
Figure 22 illustrates the PCB land pattern details for the Si4030/31/32. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 22. PCB Land Pattern
Preliminary Rev. 0.1
55
Si4030/31/32-B1
Table 17. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
3.90
3.90
Max
4.00
4.00
C1
C2
E
0.50 REF
X1
X2
Y1
Y2
0.20
2.65
0.65
2.65
0.30
2.75
0.75
2.75
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
Note: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the
perimeter pads.
4. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
used for the center ground pad.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for small body components.
56
Preliminary Rev. 0.1
Si4030/31/32-B1
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Corrected typo under Features/Low Power Consumption on page 1.
Preliminary Rev. 0.1
57
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