SI4112-D-GT [SILICON]
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS; 集成VCO用于无线通信的双频段RF合成器
| 型号： | SI4112-D-GT |
| 厂家： | 
SILICON |
| 描述： | DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS |
| 文件： | 总36页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4133
Si4123/22/13/12
DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS
FOR WIRELESS COMMUNICATIONS
FEATURES
Dual-band RF synthesizers
RF1: 900 MHz to 1.8 GHz
RF2: 750 MHz to 1.5 GHz
IF synthesizer
Low phase noise
Programmable powerdown modes
1 µA standby current
18 mA typical supply current
2.7 to 3.6 V operation
Packages: 24-pin TSSOP,
28-lead QFN
IF: 62.5 to 1000 MHz
Integrated VCOs, loop filters,
varactors, and resonators
Minimal (2) number of external
components required
Ordering Information:
Lead-free and RoHS compliant
See page 31.
Applications
Pin Assignments
Dual-band communications
Digital cellular telephones GSM 850, E-GSM 900, DCS 1800,
PCS 1900
Digital cordless phones
Analog cordless phones
Si4133-GT
SCLK
SDATA
GNDR
RFLD
1
2
24
23
22
21
20
19
18
17
16
15
14
13
SEN
VDDI
IFOUT
GNDI
3
Wireless local loop
4
Description
RFLC
5
IFLB
GNDR
6
IFLA
The Si4133 is a monolithic integrated circuit that performs both IF and dual-
band RF synthesis for wireless communications applications. The Si4133
includes three VCOs, loop filters, reference and VCO dividers, and phase
detectors. Divider and powerdown settings are programmable with a three-
wire serial interface.
7
RFLB
RFLA
GNDD
8
VDDD
GNDD
XIN
9
GNDR
GNDR
RFOUT
VDDR
10
11
12
PWDN
AUXOUT
Functional Block Diagram
Si4133-GM
Reference
Amplifier
XIN
RFLA
RFLB
R
R
R
Phase
Detector
RF1
RF2
IF
Powerdown
Control
PWDN
28 27 26 25 24 23
22
RFOUT
N
N
N
1
2
3
4
5
6
7
21
20 IFLB
19
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDI
SDATA
SCLK
RFLC
RFLD
Serial
Interface
Phase
Detector
IFLA
22-bit
Data
Register
GND
Pad
SEN
18 GNDD
17 VDDD
16
GNDD
Test
Mux
Phase
Detector
AUXOUT
IFDIV
IFOUT
15 XIN
8
9
10 11 12 13 14
IFLA
IFLB
Patents pending
Rev. 1.61 1/10
Copyright © 2010 by Silicon Laboratories
Si4133
Si4133
2
Rev. 1.61
Si4133
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2. Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3. Extended Frequency Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.4. Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.5. Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6. PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.7. RF and IF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.8. Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.9. Powerdown Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.10. Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5. Pin Descriptions: Si4133-GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Pin Descriptions: Si4133-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Si4133 Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Package Outline: Si4133-GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Package Outline: Si4133-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.61
3
Si4133
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Symbol
Test Condition
Min
–40
2.7
Typ
25
Max
85
Unit
°C
V
T
A
Supply Voltage
VDD
3.0
—
3.6
0.3
Supply Voltages Difference
V
(V
– V
– V
),
DDD
–0.3
V
DDR
(V
)
DDD
DDI
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
–0.5 to 4.0
±10
Unit
V
DC Supply Voltage
V
DD
3
IIN
VIN
mA
V
Input Current
3
–0.3 to V +0.3
Input Voltage
DD
o
Storage Temperature Range
TSTG
–55 to 150
C
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of
this device should only be done at ESD-protected workstations.
3. For signals SCLK, SDATA, SEN, PWDN and XIN.
4
Rev. 1.61
Si4133
Table 3. DC Characteristics
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
—
Typ
18
10
9
Max
27
Unit
mA
mA
mA
mA
µA
V
1
Total Supply Current
RF1 and IF operating
1
RF1 Mode Supply Current
—
16
1
RF2 Mode Supply Current
—
16
1
IF Mode Supply Current
—
8
13
Standby Current
PWDN = 0
—
1
—
2
High Level Input Voltage
VIH
VIL
IIH
0.7 VDD
—
—
—
—
—
2
Low Level Input Voltage
0.3 VDD
10
V
2
High Level Input Current
V
IH = 3.6 V,
–10
µA
V
DD = 3.6 V
2
Low Level Input Current
IIL
V
IL = 0 V,
–10
—
10
µA
V
DD= 3.6 V
3
High Level Output Voltage
VOH
VOL
IOH = –500 µA
IOH = 500 µA
VDD–0.4
—
—
—
—
V
V
3
Low Level Output Voltage
0.4
Notes:
1. RF1 = 1.6 GHz, RF2 = 1.1 GHz, IFOUT = 550 MHz, LPWR = 0.
2. For signals SCLK, SDATA, SEN, and PWDN.
3. For signal AUXOUT.
Rev. 1.61
5
Si4133
Table 4. Serial Interface Timing
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
1
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
SCLK Cycle Time
SCLK Rise Time
SCLK Fall Time
SCLK High Time
SCLK Low Time
tclk
tr
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
40
—
—
10
10
5
—
—
—
—
—
—
—
—
—
—
—
—
50
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tf
th
tl
2
SDATA Setup Time to SCLK
tsu
thold
ten1
ten2
ten3
tw
2
SDATA Hold Time from SCLK
0
2
SEN to SCLKDelay Time
10
12
12
10
2
SCLK to SENDelay Time
2
SEN to SCLKDelay Time
SEN Pulse Width
Notes:
1. All timing is referenced to the 50% level of the waveforms unless otherwise noted.
2. Timing is not referenced to 50% level of the waveform. See Figure 2.
tr
tf
80%
50%
20%
SCLK
th
tl
tclk
Figure 1. SCLK Timing Diagram
6
Rev. 1.61
Si4133
tsu
thold
SCLK
SDATA
SENB
D17
D16
D15
A1
A0
ten3
ten1
ten2
tw
Figure 2. Serial Interface Timing Diagram
First bit
clocked in
Last bit
clocked in
D
D
D
D
D
D
D
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
3
A
2
A
1
A
0
17 16 15 14 13 12 11 10
data
field
address
field
Figure 3. Serial Word Format
Rev. 1.61
7
Si4133
Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
1
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
XIN Input Frequency
Reference Amplifier Sensitivity
fREF
2
—
—
26
MHz
VREF
0.5
V
V
PP
DD
+0.3 V
Phase Detector Update Frequency
RF1 VCO Center Frequency Range
f
f = fREF/R
0.010
947
—
—
—
1.0
MHz
MHz
MHz
f
1720
2050
CEN
2
RF1 VCO Tuning Range
Extended frequency
operation
1850
RF2 VCO Center Frequency Range
f
f
789
–5
526
62.5
–5
—
—
—
1429
5
MHz
%
CEN
RF Tuning Range from f
Note: L
±10%
CEN
EXT
IF VCO Center Frequency Range
IFOUT Tuning Range
—
952
1000
5
MHz
MHz
%
CEN
with IFDIV
—
IFOUT Tuning Range from f
RF1 VCO Pushing
RF2 VCO Pushing
IF VCO Pushing
Note: L
±10%
—
CEN
EXT
Open loop
500
400
300
400
300
100
–132
0.9
—
kHz/V
kHz/V
kHz/V
—
—
—
—
RF1 VCO Pulling
VSWR = 2:1, all
phases, open loop
—
—
kHz
kHz
kHz
PP
PP
PP
RF2 VCO Pulling
—
—
IF VCO Pulling
—
—
RF1 Phase Noise
1 MHz offset
—
—
dBc/Hz
RF1 Integrated Phase Error
10 Hz to 100 kHz
—
—
degrees
rms
RF2 Phase Noise
1 MHz offset
—
—
–134
0.7
—
—
dBc/Hz
RF2 Integrated Phase Error
10 Hz to 100 kHz
degrees
rms
IF Phase Noise
100 kHz offset
—
—
–117
0.4
—
—
dBc/Hz
IF Integrated Phase Error
100 Hz to 100 kHz
degrees
rms
Notes:
1. f = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted.
2. Extended frequency operation only. VDD 3.0 V, QFN only, VCO Tuning Range fixed by directly shorting the RFLA and
RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation.
3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error).
4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current
equal to IPWDN
.
8
Rev. 1.61
Si4133
Table 5. RF and IF Synthesizer Characteristics (Continued)
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
1
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
RF1 Harmonic Suppression
RF2 Harmonic Suppression
IF Harmonic Suppression
RFOUT Power Level
Second Harmonic
—
—
–26
–26
–26
–3
–20
–20
–20
1
dBc
dBc
dBc
dBm
dBm
—
ZL = 50
–8
2
RFOUT Power Level
ZL = 50RF1 active,
Extended frequency
operation
–14
–7
1
IFOUT Power Level
Z = 50
–8
–4
0
dBm
L
RF1 Output Reference Spurs
Offset = 200 kHz
Offset = 400 kHz
Offset = 600 kHz
Offset = 200 kHz
Offset = 400 kHz
Offset = 600 kHz
Figures 4, 5
—
—
—
—
—
—
—
–65
–71
–75
–65
–71
–75
—
—
—
—
—
—
dBc
dBc
dBc
dBc
dBc
dBc
RF2 Output Reference Spurs
3
Powerup Request to Synthesizer Ready
Time
tpup
tpdn
40/f
50/f
4
Powerdown Request to Synthesizer Off
Time
Figures 4, 5
—
—
100
ns
Notes:
1. f = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted.
2. Extended frequency operation only. VDD 3.0 V, QFN only, VCO Tuning Range fixed by directly shorting the RFLA and
RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation.
3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error).
4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current
equal to IPWDN
.
Rev. 1.61
9
Si4133
RF and IF synthesizers settled to
within 0.1 ppm frequency error.
tpup
tpdn
IT
IPWDN
SEN
PDIB = 1
PDRB = 1
PDIB = 0
PDRB = 0
SDATA
Figure 4. Software Power Management Timing Diagram
RF and IF synthesizers settled to
within 0.1 ppm frequency error.
tpup
tpdn
IT
IPWDN
PWDN
Figure 5. Hardware Power Management Timing Diagram
10
Rev. 1.61
Si4133
TRACE A: Ch1 FM Main Time
A Marker
us
174.04471
711.00
Hz
1.424
kHz
Real
160
Hz
/div
176
Hz
Start: 0 s
Stop: 399.6003996 us
Figure 6. Typical Transient Response RF1 at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
Rev. 1.61
11
Si4133
−60
−70
−80
−90
−100
−110
−120
−130
−140
102
103
104
105
106
Offset Frequency (Hz)
Figure 7. Typical RF1 Phase Noise at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
Figure 8. Typical RF1 Spurious Response at 1.6 GHz
with 200 kHz Phase Detector Update Frequency
12
Rev. 1.61
Si4133
−60
−70
−80
−90
−100
−110
−120
−130
−140
102
103
104
105
106
Offset Frequency (Hz)
Figure 9. Typical RF2 Phase Noise at 1.2 GHz
with 200 kHz Phase Detector Update Frequency
Figure 10. Typical RF2 Spurious Response at 1.2 GHz
with 200 kHz Phase Detector Update Frequency
Rev. 1.61
13
Si4133
−70
−80
−90
−100
−110
−120
−130
−140
−150
102
103
104
105
106
Offset Frequency (Hz)
Figure 11. Typical IF Phase Noise at 550 MHz
with 200 kHz Phase Detector Update Frequency
Figure 12. IF Spurious Response at 550 MHz
with 200 kHz Phase Detector Update Frequency
14
Rev. 1.61
Si4133
2. Typical Application Circuits
VDD
Si4133-GT
From
30 *
0.022F
1
24
23
22
21
20
19
18
17
16
15
14
13
System
SEN
VDDI
IFOUT
GNDI
IFLB
SCLK
SDATA
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDR
RFOUT
VDDR
Controller
2
3
40 nH 560 pF
IFOUT
4
Printed Trace
Inductor or
Chip Inductor
5
6
Printed Trace
Inductors
IFLA
7
GNDD
VDDD
GNDD
XIN
0.022F
VDD
8
9
560 pF
10
11
12
External Clock
PWDN
560 pF 2 nH
RFOUT
PWDN
0.022F
VDD
AUXOUT
AUXOUT
* Add 30 series resistance if using IF output divide values 2, 4, or 8.
Figure 13. Si4133-GT
VDD
30 *
From
System
0.022F
40 nH 560 pF
Controller
IFOUT
28
27
26
25
24
23
22
Printed Trace
Inductor or
Chip Inductor
1
2
3
4
5
6
7
21
20
19
18
17
16
15
GNDR
GNDI
IFLB
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
IFLA
Printed Trace
Inductors
GNDD
VDDD
GNDD
XIN
VDD
Si4133-GM
0.022F
560 pF
External Clock
8
9
10
11
12
13
14
VDD
0.022F
AUXOUT
RFOUT
PWDN
2 nH
560 pF
* Add 30 series resistance if using IF output divide values 2, 4, or 8.
Figure 14. Si4133-GM
Rev. 1.61
15
Si4133
The unique PLL architecture used in the Si4133
produces settling (lock) times that are comparable in
3. Functional Description
The Si4133 is a monolithic integrated circuit that speed to fractional-N architectures without the high
performs IF and dual-band RF synthesis for wireless phase noise or spurious modulation effects often
communications applications. This integrated circuit associated with those designs.
(IC), with minimal external components, completes the
3.1. Serial Interface
frequency synthesis function necessary for RF
communications systems.
A timing diagram for the serial interface is shown in
Figure 2 on page 7. Figure 3 on page 7 shows the
format of the serial word.
The Si4133 has three complete phase-locked loops
(PLLs) with integrated voltage-controlled oscillators
(VCOs). The low phase noise of the VCOs makes the The Si4133 is programmed serially with 22-bit words
Si4133 suitable for demanding wireless comprised of 18-bit data fields and 4-bit address fields.
communications applications. Phase detectors, loop When the serial interface is enabled (i.e., when SEN is
filters, and reference and output frequency dividers are low) data and address bits on the SDATA pin are
integrated. The IC is programmed with a three-wire clocked into an internal shift register on the rising edge
serial interface.
of SCLK. Data in the shift register is then transferred on
the rising edge of SEN into the internal data register
addressed in the address field. The serial interface is
disabled when SEN is high.
Two PLLs are provided for dual-band RF synthesis.
These RF PLLs are multiplexed so that only one PLL is
active at a time, as determined by the setting of an
internal register. The active PLL is the last one to be Table 12 on page 21 summarizes the data register
written. The center frequency of the VCO in each PLL is functions and addresses. The internal shift register
set by the value of an external inductance. Inaccuracies ignores leading bits before the 22 required bits.
in these inductances are compensated for by the self-
3.2. Setting the VCO Center Frequencies
tuning algorithm. The algorithm is run after powerup or
after a change in the programmed output frequency.
The PLLs can adjust the IF and RF output frequencies
±5% of the center frequencies of their VCOs. Each
center frequency is established by the value of an
external inductance connected to the respective VCO.
Manufacturing tolerances of ±10% for the external
inductances are acceptable. The Si4133 compensates
for inaccuracies in each inductance by executing a self-
tuning algorithm after PLL powerup or after a change in
the programmed output frequency.
Each RF PLL, when active, can adjust the RF output
frequency by ±5% of its VCO’s center frequency.
Because the two VCOs can be set to have widely
separated center frequencies, the RF output can be
programmed to service two widely separated frequency
bands by programming the corresponding N-Divider.
One RF VCO is optimized to have its center frequency
set between 947 MHz and 1.72 GHz, while the second
RF VCO is optimized to have its center frequency set Because the total tank inductance is in the low nH
between 789 MHz and 1.429 GHz.
range, the inductance of the package must be
considered when determining the correct external
One PLL is provided for IF frequency synthesis. The
center frequency of this circuit’s VCO is set by the
connection of an external inductance. The PLL can
adjust the IF output frequency by ±5% of the VCO
center frequency. Inaccuracies in the value of the
external inductance are compensated for by the
Si4133’s proprietary self-tuning algorithm. This
algorithm is initiated each time the PLL is powered-up
(by either the PWDN pin or by software) and/or each
time a new output frequency is programmed.
inductance. The total inductance (L
) presented to
TOT
each VCO is the sum of the external inductance (L
)
EXT
and the package inductance (L
). Each VCO has a
PKG
nominal capacitance (C
) in parallel with the total
NOM
inductance, and the center frequency is as follows:
1
fCEN = -----------------------------------------------
2 LTOT CNOM
or
The IF VCO can have its center frequency set as low as
526 MHz and as high as 952 MHz. An IF output divider
divides down the IF output frequencies, if needed. The
divider is programmable and is capable of dividing by 1,
2, 4, or 8.
1
fCEN = ------------------------------------------------------------------------
2 LPKG + LEXT CNOM
Tables 6 and 7 summarize the characteristics of each
VCO.
16
Rev. 1.61
Si4133
the correct total inductance to the VCO. In
manufacturing, the external inductance can vary ±10%
of its nominal value and the Si4133 corrects for the
variation with the self-tuning algorithm.
Table 6. Si4133-GT VCO Characteristics
VCO f
Range C
L
L
Range
EXT
CEN
NOM
PKG
(MHz)
(pF) (nH)
(nH)
For more information on designing the external trace
inductors, refer to Application Note 31: Inductor Design
for the Si41xx Synthesizer Family.
Min Max
Min Max
RF1 947 1720 4.3
RF2 789 1429 4.8
2.0
2.3
2.1
0.0
0.3
2.2
4.6
6.2
3.3. Extended Frequency Operation
The Si4133 may operate at an extended frequency
range of 1850 MHz to 2050 MHz by connecting the
RFLA and RFLB pins directly. For information on
configuring the Si4133 for extended frequency
operation, refer to Application Note 41: Extended
Frequency Operation of Silicon Laboratories Frequency
Synthesizers.
IF
526 952
6.5
12.0
Table 7. Si4133-GM VCO Characteristics
VCO f
Range C
L
L
Range
EXT
CEN
NOM
PKG
(MHz)
(pF) (nH)
(nH)
3.4. Self-Tuning Algorithm
The self-tuning algorithm is initiated immediately after
powerup of a PLL or, if the PLL is already powered, after
a change in its programmed output frequency. This
algorithm attempts to tune the VCO so that its free-
running frequency is near the required output frequency.
In doing so, the algorithm compensates for
manufacturing tolerance errors in the value of the
external inductance connected to the VCO. It also
reduces the frequency error for which the PLL must
correct to get the precise required output frequency. The
self-tuning algorithm leaves the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output frequency.
Min Max
Min Max
RF1 947 1720 4.3
RF2 789 1429 4.8
1.5
1.5
1.6
0.5
1.1
2.7
5.1
7.0
IF
526 952
6.5
12.5
LPKG
2
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL completes frequency locking,
eliminating any remaining frequency error. From then
on, it maintains frequency-lock, compensating for
effects of temperature and supply voltage variations.
LEXT
LPKG
2
The Si4133’s self-tuning algorithm compensates for
component value errors at any temperature within the
specified temperature range. However, the ability of the
PLL to compensate for drift in component values that
occur after self-tuning is limited. For external
Figure 15. External Inductance Connection
As a design example, consider that the goal is to
synthesize frequencies in a 25 MHz band between
1120 and 1145 MHz using the Si4133-GT. The center
frequency should be defined as midway between the
two extremes, or 1132.5 MHz. The PLL can adjust the
VCO output frequency ±5% of the center frequency, or
±56.6 MHz of 1132.5 MHz (i.e., from approximately
inductances
with
temperature
coefficients
o
approximately ±150 ppm/ C, the PLL can maintain lock
for changes in temperature of approximately ±30 C.
o
Applications where the PLL is regularly powered down
or the frequency is periodically reprogrammed minimize
or eliminate the potential effects of temperature drift
because the VCO is re-tuned in either case. In
applications where the ambient temperature can drift
substantially after self-tuning, it might be necessary to
monitor the lock-detect bar (LDETB) signal on the
AUXOUT pin to determine whether a PLL is about to
run out of locking capability. See “3.10. Auxiliary Output
1076 to 1189 MHz). The RF2 VCO has a C
of
NOM
4.8 pF. A 4.1 nH inductance in parallel with this
capacitance yields the required center frequency. An
external inductance of 1.8 nH should be connected
between RFLC and RFLD as shown in Figure 15. This,
in addition to 2.3 nH of package inductance, presents
Rev. 1.61
17
Si4133
(AUXOUT)” for how to select LDETB. The LDETB setting the bits to 11. The values of the available gains,
signal is low after self-tuning is completed but rises relative to the highest gain, are as follows:
when the IF or RF PLL nears the limit of its
Table 8. Gain Values (Register 1)
compensation range. LDETB is also high when either
PLL is executing the self-tuning algorithm. The output
frequency is still locked when LDETB goes high, but the
PLL eventually loses lock if the temperature continues
to drift in the same direction. Therefore, if LDETB goes
high both the IF and RF PLLs should be re-tuned
promptly by initiating the self-tuning algorithm.
Relative P.D.
K Bits
P
Gain
00
01
10
11
1
1/2
1/4
1/8
3.5. Output Frequencies
The IF and RF output frequencies are set by
programming the R- and N-Divider registers. Each PLL
has R and N registers so that each can be programmed
independently. Programming either the R- or N-Divider
register for RF1 or RF2 automatically selects the
associated output.
The gain value bits is automatically set with the Auto K
P
bit (bit 2) in the Main Configuration register to 1. In
setting this bit, the gain values are optimized for a given
value of N. In general, a higher phase detector gain
decreases in-band phase noise and increase the speed
of the PLL transient until the point at which stability
begins to be compromised. The optimal gain depends
on N. Table 9 lists recommended settings for different
The reference frequency on the XIN pin is divided by R
and this signal is input to the PLL’s phase detector. The
other input to the phase detector is the PLL’s VCO
output frequency divided by N. The PLL acts to make
these frequencies equal.
values of N. These are the settings when the Auto K bit
P
is set.
Table 9. Optimal KP Settings
That is, after an initial transient:
RF1
<1:0>
RF2
K <3:2> K <5:4>
P2
IF
fOUT
fREF
N
K
----------- = -----------
P1
PI
N
R
2047
00
00
00
01
10
11
00
00
01
10
11
11
11
or
2048 to 4095
4096 to 8191
8192 to 16383
16384 to 32767
32768
00
01
10
11
11
N
R
---
fOUT
=
fREF
The R values are set by programming the RF1 R-
Divider register (Register 6), the RF2 R-Divider register
(Register 7) and the IF R-Divider register (Register 8).
The N values are set by programming the RF1 N-
Divider register (Register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
The VCO gain and loop filter characteristics are not
programmable.
Each N-Divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the control of these
sub-circuits is automatically handled. Only the
appropriate N value should be programmed.
The settling time for the PLL is directly proportional to its
phase detector update period T (T equals 1/f ). A
typical transient response is shown in Figure 6 on page
11. During the first 13 update periods the Si4133
executes the self-tuning algorithm. From then on the
PLL controls the output frequency. Because of the
unique architecture of the Si4133 PLLs, the time
required to settle the output frequency to 0.1 ppm error
is automatically 25 update periods. The total time after
powerup or a change in programmed frequency until the
synthesized frequency is settled—including time for
self-tuning—is approximately 40 update periods.
3.6. PLL Loop Dynamics
The transient response for each PLL is determined by
its phase detector update rate f (equal to f
/R) and
REF
the phase detector gain programmed for each RF1,
RF2, or IF synthesizer. See Register 1. Four different
settings for the phase detector gain are available for
each PLL. The highest gain is programmed by setting
the two phase detector gain bits to 00, and the lowest by
Note: The settling time analysis holds for RF1 f 500 kHz.
For RF1 f > 500 kHz, the settling time is larger.
18
Rev. 1.61
Si4133
For frequencies less than 500 MHz, the IF output buffer
can directly drive a 200 resistive load or higher. For
resistive loads greater than 500 (f < 500 MHz) the
LPWR bit can be set to reduce the power consumed by
the IF output buffer. See Figure 17.
3.7. RF and IF Outputs
The RFOUT and IFOUT pins are driven by amplifiers
that buffer the RF VCOs and IF VCO respectively. The
RF output amplifier receives its input from the RF1 or
RF2 VCO, depending on which R- or N-Divider register
is written last. For example, programming the N-Divider
register for RF1 automatically selects the RF1 VCO
output.
>500 pF
IFOUT
Figures 13 and 14 show application diagrams for the
Si4133. The RF output signal must be ac coupled to its
load through a capacitor. An external inductance
between the RFOUT pin and the ac coupling capacitor
is required as part of an output matching network to
maximize power delivered to the load. This 2 nH
inductance can be realized with a PC board trace. The
network is made to provide an adequate match to an
external 50 load for both the RF1 and RF2 frequency
bands. The matching network also filters the output
signal to reduce harmonic distortion.
>200
Figure 17. IF Frequencies < 500 MHz
3.8. Reference Frequency Amplifier
The Si4133 provides a reference frequency amplifier. If
the driving signal has CMOS levels it can be connected
directly to the XIN pin. Otherwise, the reference
frequency signal should be ac coupled to the XIN pin
through a 560 pF capacitor.
The IFOUT pin must also be ac coupled to its load
through a capacitor. The IF output level is dependent
upon the load. Figure 18 on page 20 displays the output
level versus load resistance for a variety of output
frequencies. For resistive loads greater than 500 the
output level saturates and the bias currents in the IF
output amplifier are higher than required. The LPWR bit
in the Main Configuration register (Register 0) can be
set to 1 to reduce the bias currents and therefore reduce
the power dissipated by the IF amplifier. For loads less
than 500 LPWR should be set to 0 to maximize the
output level.
3.9. Powerdown Modes
Table 11 summarizes the powerdown functionality. The
Si4133 can be powered down by taking the PWDN pin low
or by setting bits in the Powerdown register (Register 2).
When the PWDN pin is low, the Si4133 is powered down
regardless of the Powerdown register settings. When the
PWDN pin is high, power management is in control of the
Powerdown register bits.
The IF and RF sections of the Si4133 circuitry can be
individually powered down by setting the Powerdown
register bits PDIB and PDRB low, respectively. The
reference frequency amplifier is also powered up if the
PDRB and PDIB bits are high. Also, setting the AUTOPDB
bit to 1 in the Main Configuration register (Register 0) is
equivalent to setting both bits in the Powerdown register to
1.
For IF frequencies greater than 500 MHz, a matching
network is required to drive a 50 load. See Figure 16.
The value of L
can be determined from Table 10.
MATCH
Table 10. LMATCH Values
Frequency
L
MATCH
The serial interface remains available and can be written in
all powerdown modes.
500–600 MHz
600–800 MHz
800 MHz–1 GHz
40 nH
27 nH
18 nH
560 pF
IFOUT
LMATCH
50
Figure 16. IF Frequencies > 500 MHz
Rev. 1.61
19
Si4133
3.10. Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register
(Register 0).
The LDETB signal can be selected by setting the AUXSEL bits to 11. This signal can be used to indicate that the IF
or RF PLL is going to lose lock because of excessive ambient temperature drift and should be re-tuned. The
LDETB signal indicates a logical OR result if both IF and RF are simultaneously generating a signal.
Table 11. Powerdown Configuration
PWDN Pin
AUTOPDB
PDIB
PDRB IF Circuitry RF Circuitry
X
0
0
0
0
1
X
0
0
1
1
x
X
0
1
0
1
x
OFF
OFF
OFF
ON
OFF
OFF
ON
PWDN = 0
OFF
ON
PWDN = 1
ON
ON
ON
450
400
350
300
250
200
150
100
50
LPWR=1
LPWR=0
0
0
200
400
600
Load Resistance ()
800
1000
1200
Figure 18. Typical IF Output Voltage vs. Load Resistance at 550 MHz
20
Rev. 1.61
Si4133
4. Control Registers
Table 12. Register Summary
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
Register Name
Bit
4
Bit
3
Bit Bit
Bit
0
17 16 15 14 13 12 11 10
9
8
7
6
5
2
1
LPWR
AUTO AUTO
PDB
RF
PWR
AUXSEL
[1:0]
0
1
Main
Configura-
tion
0
0
0
0
0
0
0
0
0
0
0
0
IFDIV
[1:0]
0
0
0
0
0
0
K
P
Phase
Detector
Gain
0
0
0
0
0
0
0
0
0
0
0
0
0
0
K [1:0]
K
0
[1:0]
0
K [1:0]
P1
PI
P2
PDIB PDRB
2
3
Powerdown
0
0
0
0
RF1
N
[17:0]
RF1
N-Divider
4
RF2
0
N
[16:0]
RF2
N-Divider
5
6
IF N-Divider
0
0
0
0
N [15:0]
IF
RF1
R-Divider
0
0
0
0
0
0
0
0
0
R
[12:0]
[12:0]
RF1
7
RF2
R-Divider
0
0
0
0
R
RF2
8
9
IF R-Divider
Reserved
R [12:0]
IF
.
.
.
15
Reserved
Note: Registers 9–15 are reserved. Writes to these registers might result in unpredictable behavior. Registers not listed here
are reserved and should not be written.
Rev. 1.61
21
Si4133
Register 0. Main Configuration Address Field = A[3:0] = 0000
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D4 D3 D2 D1 D0
LPWR
AUTO AUTO
PDB
RF
PWR
Name
0
0
0
0
AUXSEL
[1:0]
IFDIV
[1:0]
0
0
0
0
0
0
K
P
Bit
Name
Function
17:14
13:12
Reserved
Program to zero.
AUXSEL[1:0]
Auxiliary Output Pin Definition.
00 = Reserved.
01 = Force output low.
10 = Reserved.
11 = Lock Detect—LDETB.
11:10
IFDIV[1:0]
IF Output Divider.
00 = IFOUT = IFVCO Frequency
01 = IFOUT = IFVCO Frequency/2
10 = IFOUT = IFVCO Frequency/4
11 = IFOUT = IFVCO Frequency/8
9:6
5
Reserved
LPWR
Program to zero.
Output Power-Level Settings for IF Synthesizer Circuit.
0 = R
1 = R
500 —normal power mode.
500 —low power mode.
LOAD
LOAD
4
3
Reserved
Program to zero.
AUTOPDB
Auto Powerdown.
0 = Software powerdown is controlled by Register 2.
1 = Equivalent to setting all bits in Register 2 = 1.
2
AUTOK
Auto K Setting.
P
P
0 = K s are controlled by Register 1.
P
1 = K s are set according to Table 9 on page 18.
P
1
0
RFPWR
Program to zero. (Used for extended frequency operation. See AN41 for
more information.)
Reserved
Program to zero.
22
Rev. 1.61
Si4133
Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
0
0
0
0
0
0
0
0
0
0
K [1:0]
K
[1:0]
K
[1:0]
P1
PI
P2
Bit
17:6
5:4
Name
Reserved
K [1:0]
Function
Program to zero.
IF Phase Detector Gain Constant.*
PI
N Value
K
PI
<2048
= 00
= 01
= 10
= 11
2048–4095
4096–8191
>8191
3:2
1:0
K
K
[1:0]
[1:0]
RF2 Phase Detector Gain Constant.*
P2
N Value
K
P2
<4096
= 00
= 01
= 10
= 11
4096–8191
8192–16383
>16383
RF1 Phase Detector Gain Constant.*
P1
N Value
K
P1
<8192
8192–16383
= 00
= 01
16384–32767 = 10
>32767 = 11
*Note: When AUTOKP = 1, these bits do not need to be programmed. When AUTOKP = 0, use these recommended values
for programming Phase Detector Gain.
Rev. 1.61
23
Si4133
Register 2. Powerdown Address Field (A[3:0]) = 0010
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
D2
D1
D0
PDIB PDRB
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
17:2
1
Name
Function
Reserved
PDIB
Program to zero.
Powerdown IF Synthesizer.
0 = IF synthesizer powered down.
1 = IF synthesizer on.
0
PDRB
Powerdown RF Synthesizer.
0 = RF synthesizer powered down.
1 = RF synthesizer on.
Note: Enabling any PLL with PDIB or PDRB automatically powers on the reference amplifier.
Register 3. RF1 N-Divider Address Field (A[3:0]) = 0011
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
[17:0]
Name
N
RF1
Bit
Name
[17:0]
Function
17:0
N
N-Divider for RF1 Synthesizer.
RF1
Register 4. RF2 N-Divider Address Field = A[3:0] = 0100
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
[16:0]
Name
0
N
RF2
Bit
17
Name
Function
Reserved
Program to zero.
N-Divider for RF2 Synthesizer.
16:0
N
[16:0]
RF2
24
Rev. 1.61
Si4133
Register 5. IF N-Divider Address Field (A[3:0]) = 0101
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
N [15:0]
Name
0
0
IF
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N-Divider for IF Synthesizer.
N [15:0]
IF
Register 6. RF1 R-Divider Address Field (A[3:0]) = 0110
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
0
0
0
R
[12:0]
RF1
Name
Function
17:13
12:0
Reserved
[12:0]
Program to zero.
R
R-Divider for RF1 Synthesizer.
RF1
R
can be any value from 7 to 8189 if K = 00
P1
RF1
8 to 8189 if K = 01
P1
10 to 8189 if K = 10
P1
14 to 8189 if K = 11
P1
Register 7. RF2 R-Divider Address Field (A[3:0]) = 0111
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
0
0
0
R
[12:0]
RF2
Bit
Name
Function
17:13
12:0
Reserved
[12:0]
Program to zero.
R
R-Divider for RF2 Synthesizer.
RF2
R
can be any value from 7 to 8189 if K = 00
P2
RF2
8 to 8189 if K = 01
P2
10 to 8189 if K = 10
P2
14 to 8189 if K = 11
P2
Rev. 1.61
25
Si4133
Register 8. IF R-Divider Address Field (A[3:0]) = 1000
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
0
0
0
R [12:0]
IF
Bit
Name
Function
17:13
12:0
Reserved
R [12:0]
Program to zero.
R-Divider for IF Synthesizer.
IF
R can be any value from 7 to 8189 if K = 00
IF
P1
8 to 8189 if K = 01
P1
10 to 8189 if K = 10
P1
14 to 8189 if K = 11
P1
26
Rev. 1.61
Si4133
5. Pin Descriptions: Si4133-GT
SCLK
SDATA
GNDR
RFLD
1
2
24
23
22
21
20
19
18
17
16
15
14
13
SEN
VDDI
IFOUT
GNDI
3
4
RFLC
5
IFLB
GNDR
6
IFLA
7
RFLB
RFLA
GNDD
VDDD
8
GNDR
GNDR
RFOUT
VDDR
9
GNDD
XIN
10
11
12
PWDN
AUXOUT
Pin Number
Name
Description
1
SCLK
SDATA
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDN
XIN
Serial clock input
Serial data input
2
3
Common ground for RF analog circuitry
Pins for inductor connection to RF2 VCO
Pins for inductor connection to RF2 VCO
Common ground for RF analog circuitry
Pins for inductor connection to RF1 VCO
Pins for inductor connection to RF1 VCO
Common ground for RF analog circuitry
Common ground for RF analog circuitry
Radio frequency (RF) output of the selected RF VCO
Supply voltage for the RF analog circuitry
Auxiliary output
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Powerdown input pin
Reference frequency amplifier input
Common ground for digital circuitry
Supply voltage for digital circuitry
GNDD
VDDD
GNDD
IFLA
Common ground for digital circuitry
Pins for inductor connection to IF VCO
Pins for inductor connection to IF VCO
Common ground for IF analog circuitry
Intermediate frequency (IF) output of the IF VCO
Supply voltage for IF analog circuitry
Enable serial port input
IFLB
GNDI
IFOUT
VDDI
SEN
Rev. 1.61
27
Si4133
Table 13. Pin Descriptions for Si4133 Derivatives—TSSOP
Pin Number
Si4133
SCLK
SDATA
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDN
XIN
Si4123
SCLK
SDATA
GNDR
GNDR
GNDR
GNDR
RFLB
RFLA
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDN
XIN
Si4122
SCLK
SDATA
GNDR
RFLD
RFLC
GNDR
GNDR
GNDR
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDN
XIN
Si4113
SCLK
Si4112
SCLK
SDATA
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
AUXOUT
PWDN
XIN
1
2
SDATA
GNDR
RFLD
3
4
5
RFLC
6
GNDR
RFLB
7
8
RFLA
9
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDN
XIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
SEN
GNDD
VDDD
GNDD
IFLA
IFLB
IFLB
IFLB
IFLB
GNDI
GNDI
GNDI
GNDI
IFOUT
VDDI
IFOUT
VDDI
IFOUT
VDDI
IFOUT
VDDI
SEN
SEN
SEN
SEN
28
Rev. 1.61
Si4133
6. Pin Descriptions: Si4133-GM
28 27 26 25 24 23
22
1
2
3
4
5
6
7
21
20 IFLB
19
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDI
IFLA
GND
Pad
18 GNDD
17 VDDD
16
GNDD
15 XIN
8
9
10 11 12 13 14
Pin Number
Name
Description
1
GNDR
RFLD
RFLC
GNDR
RFLB
RFLA
GNDR
GNDR
GNDR
RFOUT
VDDR
AUXOUT
PWDN
GNDD
XIN
Common ground for RF analog circuitry
Pins for inductor connection to RF2 VCO
Pins for inductor connection to RF2 VCO
Common ground for RF analog circuitry
Pins for inductor connection to RF1 VCO
Pins for inductor connection to RF1 VCO
Common ground for RF analog circuitry
Common ground for RF analog circuitry
Common ground for RF analog circuitry
Radio frequency (RF) output of the selected RF VCO
Supply voltage for the RF analog circuitry
Auxiliary output
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Powerdown input pin
Common ground for digital circuitry
Reference frequency amplifier input
Common ground for digital circuitry
Supply voltage for digital circuitry
Common ground for digital circuitry
Pins for inductor connection to IF VCO
Pins for inductor connection to IF VCO
Common ground for IF analog circuitry
Common ground for IF analog circuitry
Intermediate frequency (IF) output of the IF VCO
Supply voltage for IF analog circuitry
Enable serial port input
GNDD
VDDD
GNDD
IFLA
IFLB
GNDI
GNDI
IFOUT
VDDI
SEN
SCLK
SDATA
GNDR
Serial clock input
Serial data input
Common ground for RF analog circuitry
Rev. 1.61
29
Si4133
Table 14. Pin Descriptions for Si4133 Derivatives—QFN
Pin Number Si4133
Si4123
GNDR
GNDR
GNDR
GNDR
RFLB
Si4122
GNDR
RFLD
Si4113
GNDR
RFLD
Si4112
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
1
GNDR
RFLD
RFLC
GNDR
RFLB
2
3
RFLC
RFLC
4
GNDR
GNDR
GNDR
GNDR
GNDR
GNDR
RFOUT
VDDR
GNDR
RFLB
5
6
RFLA
RFLA
RFLA
7
GNDR
GNDR
GNDR
RFOUT
VDDR
GNDR
GNDR
GNDR
RFOUT
VDDR
GNDR
GNDR
GNDR
RFOUT
VDDR
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AUXOUT AUXOUT AUXOUT AUXOUT AUXOUT
PWDN
GNDD
XIN
PWDN
GNDD
XIN
PWDN
GNDD
XIN
PWDN
GNDD
XIN
PWDN
GNDD
XIN
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
IFLA
GNDD
VDDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
SEN
GNDD
VDDD
GNDD
IFLA
IFLB
IFLB
IFLB
IFLB
GNDI
GNDI
IFOUT
VDDI
SEN
GNDI
GNDI
IFOUT
VDDI
SEN
GNDI
GNDI
IFOUT
VDDI
SEN
GNDI
GNDI
IFOUT
VDDI
SEN
SCLK
SDATA
GNDR
SCLK
SDATA
GNDR
SCLK
SDATA
GNDR
SCLK
SDATA
GNDR
SCLK
SDATA
GNDD
30
Rev. 1.61
Si4133
7. Ordering Guide
Ordering Part
Number
Description
Operating Temperature
º
Si4133-D-GM
Si4133-D-GT
Si4123-D-GM
Si4123-D-GT
Si4122-D-GM
Si4122-D-GT
Si4113-D-GM
Si4113-D-GT
Si4113-D-ZT1
Si4112-D-GM
Si4112-D-GT
RF1/RF2/IF OUT, Lead Free, QFN
RF1/RF2/IF OUT, Lead Free, TSSOP
RF1/IF OUT, Lead Free, QFN
RF1/IF OUT, Lead Free, TSSOP
RF2/IF OUT, Lead Free, QFN
RF2/IF OUT, Lead Free, TSSOP
RF1/RF2 OUT, Lead Free, QFN
RF1/RF2 OUT, Lead Free, TSSOP
RF1/RF2 OUT, NiPd, TSSOP
IF OUT, Lead Free, QFN
–40 to 85 C
º
–40 to 85 C
º
–40 to 85 C
º
–40 to 85 C
º
–40 to 85 C
º
–40 to 85 C
º
–40 to 85 C
º
–40 to 85 C
º
–40 to 85 C
º
–40 to 85 C
º
IF OUT, Lead Free, TSSOP
–40 to 85 C
8. Si4133 Derivative Devices
The Si4133 performs both IF and dual-band RF frequency synthesis. The Si4112, Si4113, Si4122, and the Si4123
are derivatives of this device. Table 15 outlines which synthesizers each derivative device features and the pins
and registers that coincide with each synthesizer.
Table 15. Si4133 Derivatives
Name
Synthesizer
Pins
Registers
Si4112
IF
IFLA, IFLB
N , R , PDIB, IFDIV, LPWR, AUTOPDB = 0,
IF IF
PDRB = 0
Si4113
RF1, RF2
RFLA, RFLB, RFLC, RFLD
N
, N
, R
, R
, PDRB, AUTOPDB = 0,
RF1
RF2
RF1
RF2
PDIB = 0
Si4122
Si4123
Si4133
RF2, IF
RF1, IF
RFLC, RFLD, IFLA, IFLB
RFLA, RFLB, IFLA, IFLB
N
N
, R
, R
, PDRB, N , R , PDIB, IFDIV, LPWR
RF2
RF1
RF2
IF IF
, PDRB, N , R , PDIB, IFDIV, LPWR
RF1
IF IF
RF1, RF2, IF
RFLA, RFLB, RFLC, RFLD,
IFLA, IFLB
N
, N
, R
, R
, PDRB, N , R , PDIB,
RF1
RF2
RF1
RF2 IF IF
IFDIV, LPWR
Rev. 1.61
31
Si4133
9. Package Outline: Si4133-GT
Figure 19 illustrates the package details for the Si4133-GT. Table 16 lists the values for the dimensions shown in
the illustration.
24
B
E1
E
1
L
ddd
C B A
e
1
2
3
Detail G
A
D
c
A
b
C
bbb M C B A
A1
See Detail G
Figure 19. 24-Pin Thin Shrink Small Outline Package (TSSOP)
Table 16. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Nom
—
Max
1.20
0.15
0.30
0.20
7.90
A
A1
b
0.05
0.19
0.09
7.70
—
—
c
—
D
7.80
0.65 BSC
6.40 BSC
4.40
0.60
—
e
E
E1
L
4.30
0.45
0°
4.50
0.75
8°
1
bbb
ddd
0.10
0.20
32
Rev. 1.61
Si4133
10. Package Outline: Si4133-GM
Figure 20 illustrates the package details for the Si4133-GM. Table 17 lists the values for the dimensions shown in
the illustration.
Figure 20. 28-Pin Quad Flat No-Lead (QFN)
Table 17. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Min
0.50
—
Nom
0.60
—
Max
0.70
0.10
0.10
0.05
0.10
12
A
A1
L
0.01
aaa
bbb
ccc
ddd
b
0.23
—
—
D, E
e
5.00 BSC
0.50 BSC
2.70
—
—
—
—
D2, E2
2.55
2.85
—
—
Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. This package outline conforms to JEDEC MS-220, variant VHHD-1.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020B specification for Small Body
Components.
Rev. 1.61
33
Si4133
DOCUMENT CHANGE LIST
Revision 1.4 to Revision 1.5
"7.Ordering Guide" on page 31 updated.
Changed MLP to QFN (same package, generic
name)
Revision 1.5 to Revision 1.6
Updated "7.Ordering Guide" on page 31.
Revision 1.6 to Revision 1.61
Updated contact information.
34
Rev. 1.61
Si4133
NOTES:
Rev. 1.61
35
Si4133
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no war-
ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applica-
tions intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
36
Rev. 1.61
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