SI4134T-BM [SILICON]
RF and Baseband Circuit, CMOS, 5 X 5 MM, QFN-32;
| 型号： | SI4134T-BM |
| 厂家： | 
SILICON |
| 描述： | RF and Baseband Circuit, CMOS, 5 X 5 MM, QFN-32 电信 电信集成电路 |
| 文件： | 总48页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Aero+
AERO™+ TRANSCEIVER
FOR GSM AND GPRS WIRELESS COMMUNICATIONS
Features
Pin Assignments
Low-IF receiver:
Quad-band support:
(Top View)
Si4200-BM
z Dual or triple-band LNA
z Image-reject down-converter
Universal baseband interface:
z GSM 850 Class 4, small MS
z E-GSM 900 Class 4, small MS
z DCS 1800 Class 1
(Si4200DB-BM see page 39)
z PCS 1900 Class 1
z Digital IF to baseband converter
z Channel filter and gain control
z Analog or digital I/Q interface
Offset-PLL transmitter:
z Integrated TX VCO and loop filter
Dual RF synthesizer:
32 31 30 29 28 27 26 25
GPRS Class 12 compliant
ION
IOP
1
2
3
4
5
6
7
8
24 RFOD
CMOS process technology
23 VDD
CKN
22 RFIGN
21 RFIGP
20 RFIDN
19 RFIDP
18 RFIPN
17 RFIPP
Low profile packages:
z Si4200: 5 x 5 mm MLP32
z Si4201: 4 x 4 mm MLP20
z Si4134T: 5 x 5 mm MLP32
3-wire serial interface
CKP
GND
PAD
TXIP
TXIN
TXQP
TXQN
z Integrated RF and IF VCOs, loop
filters, varactors, and resonators
9
10 11 12 13 14 15 16
Integrated reference oscillator:
z 13 or 26 MHz operation
2.7 V to 3.0 V operation
Applications
Si4201-BM
Multi-band GSM/GPRS digital cellular handsets
Multi-band GPRS data modems and terminals
20 19 18 17 16
GND
1
15 SDO
Description
RXQP
RXQN
RXIP
2
3
4
5
14 PDN
13 XEN
12 ION
11 IOP
GND
PAD
The Aero™+ transceiver is a complete RF front end for multi-band GSM
and GPRS wireless communications. No external IF SAW filter or VCO
modules are required as all functions are completely implemented on-
chip, resulting in a dramatic reduction of board area and component
count. The Aero+ transceiver includes a digitally-controlled crystal
oscillator (DCXO) that completely integrates the reference oscillator and
varactor.
RXIN
6
7
8
9
10
Si4134T-BM
Functional Block Diagram
32 31 30 29 28 27 26 25
IFLB
1
2
3
4
5
6
7
8
24 GND
23 NC
Si4200
ADC
Si4201
DAC
GSM
DCS
PCS
LNA
LNA
LNA
IFLA
PDN
PGA
PGA
PGA
PGA
I
22 GND
21 RFLC
20 RFLD
19 GND
18 SDO
17 SDI
XDRVEN
XDRV
GND
GND
PAD
ADC
DAC
Q
XOUT
100 kHz
0 / 90
VDD
φ
DET
GSM
GND
PA
PA
I
9
10 11 12 13 14 15 16
DCS
PCS
Q
Si4134T
DCXO
Ordering Information:
See page 42.
RF
PLL
IF
PLL
AFC
Patents pending
Rev. 1.2 8/03
Copyright © 2003 by Silicon Laboratories
Aero+
Aero+
2
Rev. 1.2
Aero+
TABLE OF CONTENTS
Section
Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Typical Triple-Band Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Receive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
VCO Inductor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DCXO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
XDRV Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
XOUT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Pin Descriptions: Si4200-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Pin Descriptions: Si4200DB-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Pin Descriptions: Si4201-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Pin Descriptions: Si4134T-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Package Outline: Si4200-BM and Si4200DB-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Package Outline: Si4201-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Package Outline: Si4134T-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Rev. 1.2
3
Aero+
Electrical Specifications
Table 1. Recommended Operating Conditions1,2
Parameter
Symbol
TA
Test Condition
Min
–20
2.7
Typ
25
Max
85
Unit
°C
V
Ambient Temperature
Supply Voltage
Supply Voltages Difference
Notes:
VDD
2.85
—
3.0
0.3
V
–0.3
V
∆
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at 2.85 V and an operating temperature of 25 °C unless otherwise stated. Parameters are tested in
production unless otherwise stated.
2. Supply voltage difference specification applies to power supply pins per IC.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
VDD
Value
–0.5 to 3.3
±10
Unit
V
DC Supply Voltage
3
Input Current
IIN
mA
V
3
Input Voltage
VIN
–0.3 to (V + 0.3)
DD
Operating Temperature
Storage Temperature
TOP
–40 to 95
–55 to 150
10
°C
TSTG
°C
4
RF Input Level
dBm
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. The Si4200 and Si4134T devices are high-performance RF integrated circuits with an ESD rating of < 2 kV.
Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For signals SCLK, SDI, SEN, PDN, XIN, XEN, XTALEN, and XDRVEN.
4. At SAW filter output for all bands.
4
Rev. 1.2
Aero+
Table 3. DC Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
IRX0
Test Condition
Receive mode
Transmit mode
PDN = 0
Min
—
Typ
55
60
1
Max
Unit
mA
mA
µA
Si4200 Supply Current
80
80
50
12
50
ITX0
—
IPDN0
IRX1
—
1
Si4201 Supply Current
Receive mode
—
9
mA
µA
IPDN1
PDN = 0, XEN = 0,
XBUF = 0, XPD1 = 1
—
1
IXOUT1
IRX3
PDN = 0, XEN = 1
Receive mode
—
—
—
—
—
1
18
24
1
2
mA
mA
mA
µA
2
Si4134T Supply Current
22
30
50
3.5
ITX3
Transmit mode
IPDN3
PDN = 0, XTALEN = 0
IXTAL13 PDN = 0,XTALEN = 1,
= 13 MHz
2.5
mA
f
REF
IXTAL26 PDN = 0,XTALEN = 1,
= 26 MHz
—
3.0
4.0
mA
f
REF
Total Chipset Supply Current
IRX
ITX
VIH
VIL
IIH
Receive mode
Transmit mode
—
—
83
85
—
—
—
—
—
—
mA
mA
V
3
High Level Input Voltage
0.7 VDD
—
—
3
Low Level Input Voltage
0.3 VDD
10
V
3
High Level Input Current
VIH = VDD = 3.0 V
VIL = 0 V,
–10
–10
µA
µA
3
Low Level Input Current
IIL
10
V
DD = 3.0 V
4
High Level Output Voltage
VOH
VOL
VOH
VOL
IOH = –500 µA
IOL = 500 µA
IOH = –10 mA
IOL = 10 mA
VDD–0.4
—
—
—
—
—
—
0.4
—
V
V
V
V
4
Low Level Output Voltage
5
High Level Output Voltage
VDD–0.4
—
5
Low Level Output Voltage
0.4
Notes:
1. Measured with load on XOUT pin of 10 pF and fREF = 13 MHz. Limits with XEN = 1 guaranteed by characterization.
2. RF1 VCO is used for receive mode, RF2 and IF VCOs are used for transmit mode. Center frequencies for each VCO
are as follows: RF1 = 1.9 GHz, RF2 = 1.35 GHz, IF = 825 MHz, fREF = 13 MHz.
3. For pins SCLK, SDI, SEN, XEN, PDN, XDRVEN, and XTALEN.
4. For pins SDO and XOUT.
5. For pins DIAG1 and DIAG2.
Rev. 1.2
5
Aero+
Table 4. AC Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
tCLK
tR
Test Condition
Figure 1, Figure 3
Figure 1, Figure 3
Figure 1, Figure 3
Figure 1, Figure 3
Figure 1, Figure 3
Figure 2
Min
35
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
50
50
—
—
10
10
—
—
—
—
—
—
27
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
SCLK Cycle Time
SCLK Rise Time
SCLK Fall Time
tF
—
SCLK High Time
tHI
10
10
—
SCLK Low Time
tLO
PDN Rise Time
tPR
PDN Fall Time
tPF
Figure 2
—
SDI Setup Time to SCLK↑
SDI Hold Time from SCLK↑
SEN↓ to SCLK↑ Delay Time
SCLK↑ to SEN↑ Delay Time
SEN↑ to SCLK↑ Delay Time
SEN Pulse Width
tSU
Figure 3
15
10
10
12
12
10
—
tHOLD
tEN1
tEN2
tEN3
tW
Figure 3
Figure 3
Figure 3, Figure 4
Figure 3, Figure 4
Figure 3, Figure 4
Figure 4
SCLK↓ to SDO Time
tCA
1
Digital Input Pin Capacitance
—
2
Allowable Board Capacitance
—
1
Notes:
1. For pins SCLK, SDI, SEN, XEN, PDN, XDRVEN, and XTALEN.
2. For pins CKN, CKP, ION, and IOP.
tR
tF
80%
SCLK
50%
20%
tHI
tLO
tCLK
Figure 1. SCLK Timing Diagram
tPR
tPF
80%
20%
PDN
Figure 2. PDN Timing Diagram
6
Rev. 1.2
Aero+
80%
50%
20%
D17
D16
A0
SDI
SCLK
SEN
tSU
tHOLD
80%
50%
20%
tR
tLO
tHI
tF
tEN2
tEN3
tEN1
tCLK
80%
50%
20%
tW
Figure 3. Serial Interface Write Timing Diagram
80%
50%
20%
A0
SDI
SDO
80%
50%
20%
OD17
OD16
OD0
tCA
80%
50%
20%
SCLK
SEN
tEN2
tEN3
80%
50%
20%
tW
Figure 4. Serial Interface Read Timing Diagram
Rev. 1.2
7
Aero+
Table 5. Receiver Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM input
Min
869
925
1805
1930
—
Typ
—
Max
894
960
1880
1990
3.3
3.4
3.9
4.3
4.0
4.1
4.8
5.5
4.1
4.2
5.2
5.8
—
Unit
MHz
MHz
MHz
MHz
dB
1
GSM Input Frequency
F
IN
—
1
DCS or PCS Input Frequency
—
—
2,3
Noise Figure at 25 °C
NF
NF
NF
2.6
2.7
3.2
3.6
3.3
3.4
4.1
4.8
3.4
3.5
4.5
5.1
–21
–25
–16
–15
40
25
75
85
—
dB
—
dB
—
dB
2,3
Noise Figure at 75 °C
—
dB
—
dB
—
dB
—
dB
2,3
Noise Figure at 85 °C
—
dB
—
dB
—
dB
—
dB
2,3,4
3 MHz Input Desensitization
DES
–25
–28
–20
–19
29
dBm
dBm
dBm
dBm
dBm
3
DCS/PCS inputs
GSM input
—
2,3,4
20 MHz Input Desensitization
DES
—
20
DCS/PCS inputs
|f – f | ≥ 6 MHz,
—
2
Input IP2
IP2
IP3
IR
—
1,2
0
|f – f | = 100 kHz
2
1
2
Input IP3
|f – f | ≥ 800 kHz,
–18
–12
—
dBm
2
1
f = 2f – f
0
1
2
2,4
Image Rejection
GSM Input
28
28
35
40
—
—
dB
dB
DCS/PCS Inputs
GSM Input
2,5
1 dB Input Compression
CP
–28
–27
–23
–23
4.5
11.5
100
96
–23
–22
–18
–18
8.5
15.5
104
102
17
—
dBm
dBm
dBm
dBm
dB
MAX
DCS/PCS inputs
GSM Input
—
2,6
1 dB Input Compression
CP
—
MIN
DCS/PCS inputs
GSM input
—
2,6,7
Minimum Voltage Gain
G
12.5
19.5
108
106
—
MIN
DCS/PCS inputs
GSM input
dB
2,7
Maximum Voltage Gain
G
dB
MAX
DCS/PCS inputs
GSM input
dB
3,8
LNA Voltage Gain
G
—
dB
LNA
DCS/PCS inputs
—
15
—
dB
8
Rev. 1.2
Aero+
Table 5. Receiver Characteristics (Continued)
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
GSM input
Min
13
4
Typ
17
8
Max
Unit
dB
dB
dB
dB
dB
dB
LNA Gain Control Range
∆G
21
12
19
4.8
—
LNA
DCS/PCS inputs
Analog PGA Control Range
Analog PGA Step Size
∆G
13
3.2
—
16
4.0
63
1
APGA
Digital PGA Control Range
Digital PGA Step Size
∆G
DPGA
—
—
9
Maximum Differential Output Voltage
DACFS[1:0] = 00
DACFS[1:0] = 01
DACFS[1:0] = 10
DACCM[1:0] = 00
DACCM[1:0] = 01
DACCM[1:0] = 10
0.8
1.6
2.8
0.8
1.05
1.15
—
1.0
2.0
3.5
1.0
1.25
1.35
—
1.2
2.4
4.2
1.2
1.45
1.55
50
1
V
PPD
PPD
V
V
PPD
9
Output Common Mode Voltage
V
V
V
9,10
Differential Output Offset Voltage
mV
%
9,10
Baseband Gain Error
—
—
9,10
Baseband Phase Error
—
—
1
deg
kΩ
pF
µs
9
Output Load Resistance
R
Single-ended
Single-ended
CSEL = 0
10
—
—
—
L
9
Output Load Capacitance
C
—
10
22
16
1.5
1
L
11
Group Delay
—
—
CSEL = 1
—
—
µs
11
Differential Group Delay
CSEL = 0
—
—
µs
CSEL = 1
—
—
µs
3,12
Powerup Settling Time
From powerdown
—
200
220
µs
Notes:
1. GSM input pins RFIGP and RFIGN. DCS input pins RFIDP and RFIDN. PCS input pins RFIPP and RFIPN. On the Si4200DB, the PCS
input should be used for either PCS 1900 or DCS 1800 bands.
2. Measurement is performed with a 2:1 balun (50 Ω input, 200 Ω balanced output) and includes matching network and PCB losses.
Measured at max gain (AGAIN[2:0] =100b, LNAG[1:0] = 01b, LNAC[1:0] = 01b) unless otherwise noted. Noise figure measurements
are referred to 290 °K. Insertion loss of the balun is removed.
3. Specifications guaranteed by characterization.
4. Input signal at balun is –102 dBm. SNR at baseband output is 9 dB.
5. AGAIN[2:0]=000b, LNAG[1:0] = 01b, LNAC[1:0] = 01b.
6. AGAIN[2:0]=000b, LNAG[1:0] = 00b, LNAC[1:0] = 00b.
7. Voltage gain is defined as the differential rms voltage at the RXIP/RXIN pins or RXQP/RXQN pins divided by the rms voltage at the
balun input with DACFS[1:0] = 01 and CSEL = 1. Gain is 1.5 dB higher with CSEL = 0. Minimum and maximum values do not include
the variation in the Si4201 DAC full scale voltage (also see Maximum Differential Output Voltage specification).
8. Voltage gain is defined as the differential rms voltage at the LNA output divided by the rms voltage at the balun output.
9. Output pins RXIP, RXIN, RXQP, RXQN.
10. The baseband signal path is entirely digital. Gain, phase, and offset errors at the baseband outputs are because of the Si4201 D/A
converters. Offsets can be measured and calibrated out. See ZERODEL[2:0] in the register description.
11. Group delay is measured from antenna input to baseband outputs. Differential group delay is measured in-band.
12. Includes settling time of the Si4134T frequency synthesizer with 13 MHz DCXO output settled. Settling to 5 degrees phase error
measured at RXIP, RXIN, RXQP, and RXQN pins.
Rev. 1.2
9
Aero+
Receive Path Magnitude Response (CSEL = 0)
0
−20
−40
−60
−80
−100
−120
0
50
100
150
200
250
300
350
400
Frequency (KHz)
Figure 5. Receive Path Magnitude Response (CSEL = 0)
Receive Path Passband Magnitude Response (CSEL = 0)
2
0
−2
−4
−6
−8
−10
−12
−14
−16
0
10
20
30
40
50
60
70
80
90
100
Frequency (KHz)
Figure 6. Receive Path Passband Magnitude Response (CSEL = 0)
Receive Path Passband Group Delay (CSEL = 0)
25
24
23
22
21
20
19
18
17
16
15
0
10
20
30
40
50
60
70
80
90
100
Frequency (KHz)
Figure 7. Receive Path Passband Group Delay (CSEL = 0)
10
Rev. 1.2
Aero+
Receive Path Magnitude Response (CSEL = 1)
0
−20
−40
−60
−80
0
50
100
150
200
250
300
350
400
Frequency (KHz)
Figure 8. Receive Path Magnitude Response (CSEL = 1)
Receive Path Passband Magnitude Response (CSEL = 1)
2
0
−2
−4
−6
−8
−10
−12
−14
−16
0
10
20
30
40
50
60
70
80
90
100
Frequency (KHz)
Figure 9. Receive Path Passband Magnitude Response (CSEL = 1)
Receive Path Passband Group Delay (CSEL = 1)
20
19
18
17
16
15
14
13
12
11
10
0
10
20
30
40
50
60
70
80
90
100
Frequency (KHz)
Figure 10. Receive Path Passband Group Delay (CSEL = 1)
Rev. 1.2
11
Aero+
Table 6. Transmitter Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
Min
824
880
1710
1850
0.88
1.1
26
Typ
—
Max
849
915
1785
1910
2.2
1.4
35
Unit
MHz
MHz
MHz
MHz
1
RFOG Output Frequency
—
2
RFOD Output Frequency
—
—
3,4
I/Q Differential Input Swing
—
V
PPD
3
I/Q Input Common-Mode
—
V
3,4
I/Q Differential Input Resistance
BBG[1:0] = 11b
BBG[1:0] = 00b
BBG[1:0] = 01b
Powered down
30
kΩ
kΩ
22
25
29
17
20
23
kΩ
—
Hi-Z
—
—
kΩ
3,5
I/Q Input Capacitance
—
5
pF
3
I/Q Input Bias Current
13
16
19
µA
Sideband Suppression
Carrier Suppression
IM3 Suppression
67.7 kHz sinusoid
67.7 kHz sinusoid
67.7 kHz sinusoid
—
–46
–48
–57
1.9
5
–34
–33
–50
3.0
10
dBc
dBc
dBc
—
—
5
o
Phase Error
—
rms
o
—
PEAK
1,2
TXVCO Pushing
Open loop
—
100
200
—
kHz/V
1,2
TXVCO Pulling
VSWR 2:1, all phases
open loop
—
—
kHz
PP
1,6
RFOG Output Modulation Spectrum
400 kHz offset
1.8 MHz offset
400 kHz offset
1.8 MHz offset
10 MHz offset
20 MHz offset
20 MHz offset
—
—
—
—
—
—
—
7
–65
–70
–65
–70
–160
–166
–163
9
–63
–68
–63
–65
–155
–164
–157
11
dBc
dBc
dBc
2,6
RFOD Output Modulation Spectrum
dBc
1,5,7
RFOG Output Phase Noise
dBc/Hz
dBc/Hz
dBc/Hz
dBm
2,5,7
RFOD Output Phase Noise
1
RFOG Output Power Level
Z = 50 Ω
L
2
RFOD Output Power Level
Z = 50 Ω
6
8
10
dBm
L
12
Rev. 1.2
Aero+
Table 6. Transmitter Characteristics (Continued)
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
2nd harmonic
Min
—
Typ
—
Max
Unit
dBc
dBc
µs
1,2
RF Output Harmonic Suppression
–20
–10
150
3rd harmonic
—
—
5,8
Powerup Settling Time
From powerdown
—
—
Notes:
1. Measured at RFOG pin.
2. Measured at RFOD pin.
3. Input pins TXIP, TXIN, TXQP, and TXQN.
4. Differential Input Swing is programmable with the BBG[1:0] bits in Register 04h. Program these bits to the closest
appropriate value. The I/Q Input Resistance scales inversely with the BBG[1:0] setting.
5. Specifications are guaranteed by characterization.
6. Measured with pseudo-random pattern. Carrier power and noise power < 1.8 MHz measured with 30 kHz RBW. Noise
power ≥ 1.8 MHz measured with 100 kHz RBW.
7. Measured with all 1s pattern.
8. Including settling time of the Si4134T frequency synthesizer with 13 MHz DCXO output settled. Settling time measured
at the RFOD and RFOG pins to 0.1 ppm frequency error.
Rev. 1.2
13
Aero+
Table 7. Frequency Synthesizer Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1
f
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900
1737.8
1849.8
1804.9
1929.9
1272
1279
1327
1423
—
—
—
1787.8
1919.8
1879.9
1989.9
1297
1314
1402
1483
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
RF1 VCO Frequency
RF1
—
—
1
f
—
RF2 VCO Frequency
RF2
—
DCS 1800 band
PCS 1900 band
GSM 850 band
—
—
1
f
896
798
IF VCO Frequency
IF
E-GSM 900 band
880–895 MHz
900–915 MHz
—
—
E-GSM 900 band
895–900 MHz
—
790
—
MHz
DCS 1800 band
PCS 1900 band
—
—
—
766
854
200
—
—
—
MHz
MHz
kHz
f
GSM input,
RFUP = 0
RF1 PLL Phase Detector Update
Frequency
φ
DCS/PCS inputs,
RFUP = 1
—
—
100
200
—
—
kHz
kHz
f
IF and RF2 PLL Phase Detector
Update Frequency
φ
2,3
—
—
—
—
—
—
—
—
—
—
—
—
—
4.8
6.5
—
—
pF
pF
RF2 VCO Nominal Capacitance
C
L
NOM
PKG
2,3
IF VCO Nominal Capacitance
2,3
2.0
—
nH
RF2 VCO Package Inductance
2,3
1.6
—
nH
IF VCO Package Inductance
3
Open Loop
500
400
300
400
100
100
–144
–126
–128
—
kHz/V
kHz/V
kHz/V
RF1 VCO Pushing
3
—
RF2 VCO Pushing
3
—
IF VCO Pushing
3
VSWR = 2:1,
all phases, open loop
—
kHz
RF1 VCO Pulling
PP
3
—
kHz
RF2 VCO Pulling
PP
3
—
kHz
IF VCO Pulling
PP
3
3 MHz offset
400 kHz offset
400 kHz offset
–138
–121
–123
dBc/Hz
dBc/Hz
dBc/Hz
RF1 PLL Phase Noise
3
RF2 PLL Phase Noise
3
IF PLL Phase Noise
14
Rev. 1.2
Aero+
Table 7. Frequency Synthesizer Characteristics (Continued)
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
3 MHz offset
Min
—
Typ
–95
–80
–80
Max
Unit
dBc
dBc
dBc
3
3
–83
–75
–70
RF1 PLL Spurious
RF2 PLL Spurious
400 kHz offset
400 kHz offset
—
3
—
IF PLL Spurious
Notes:
1. For the GSM input, the RF1 VCO is divided by two on the Si4200. During transmit, the IF VCO is divided by two on the
Si4200. These tuning ranges are guaranteed provided the VCOs on the Si4134T are properly centered during the PC
board design phase. See “AN49: Aero Transceiver PCB Layout Guidelines” for more information.
2. See "VCO Inductor Design" on page 22.
3. Specifications are guaranteed by characterization.
Table 8. Reference Oscillator (DCXO) Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
—
Typ
—
Max
2
Unit
pF
XDRV Board Capacitance
XTAL1 Trace Capacitance
XTAL2 Trace Capacitance
C
XDRV
XTAL1
XTAL2
1
1
C
C
—
0.90
0.63
13
—
—
—
—
—
pF
—
pF
Crystal Oscillation Frequency
f
XSEL = 0, DIV2 = 0
XSEL = 1, DIV2 = 1
—
MHz
MHz
pF
REF
—
26
Crystal Load Capacitance
—
8
C
L
2
Crystal Sensitivity
—
22.5
—
—
10
10
ppm/pF
ppm
S
Initial Crystal Frequency Offset
∆f
–10
–10
T = 25 °C
OFF
TOL
A
3
Crystal Frequency Tolerance
∆f
—
ppm
4
CDAC Range
∆f
20
—
0
—
1.0
—
—
1.5
2.5
60
—
ppm
ppm
V
CDAC
4,5
CDAC Step Size
CVAR Input Voltage
V
XAFC
4
CVAR Range
∆f
V
= 0 to 2.5 V
CTL
20
—
30
1.0
ppm
ms
CVAR
DCXO
Powerup Settling Time
t
V
= 1.25 V
CTL
Notes:
1. See “AN49: Aero Transceiver PCB Layout Guidelines” for suggested layout.
2. Allowable manufacturing tolerance of ±10% from typical value.
3. Crystal accuracy over temperature range.
4. Specifications guaranteed when using a crystal that conforms to fREF = 13 MHz, CL = 8 pF, S = 22.5 ppm/pF,
∆fOFF = ±10 ppm, and ∆fTOL = ±10 ppm.
5. Average step size over CDAC codes 0 to 63.
Rev. 1.2
15
Aero+
Typical Triple-Band Application Schematic
PDN
SEN
SCLK
SDI
EGSM TX Output
DCS/PCS TX Output
SDO
VDD
C10
VDD
C14
VDD
C13
Z1
C1
EGSM RX Input
DCS RX Input
PCS RX Input
OUT-
In
Gnd
In
L1
L2
L3
1
2
3
4
5
15
14
13
12
11
GND
SDO
PDN
XOE
ION
RXQP
RXQN
RXIP
RXQP
RXQN
RXIP
RXIN
U2
SI4201
OUT+
VDD
1
2
3
4
5
6
7
8
24
ION
RFOD
C2
C3
23
22
21
20
19
18
17
RXIN
IOP
IOP
VDD
RFIGN
RFIGP
RFIDN
RFIDP
RFIPN
RFIPP
CKN
CKP
TXIP
TXIN
TXQP
TXQN
U1
SI4200
Z2
OUT-
OUT+
Gnd
In
VDD
C4
C5
C9
Z3
OUT-
TXIP
VDD
TXIN
TXQP
TXQN
OUT+
Gnd
C6
VDD
C12
VDD
C7
L4
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
IFLB
GND
NC
L5
PCB Trace
IFLA
PDN
GND
RFLC
RFLD
GND
SDO
SDI
XDRVEN
XDRV
GND
U3
SI4134T
VDD
VDD
GND
C11
X1
13/26MHz
XTAL_EN
XAFC
Notes:
1. Connect GND pad on bottom of U1–U3 to GND.
2. All VDD pins may be fed from a single supply or regulator.
3. For dual-band designs, the DCS LNA input pins (U1 pins 19–20) should be grounded. For a complete pinout, see "Pin
Descriptions: Si4200DB-BM" on page 39.
4. See “AN49: Aero Transceiver PCB Layout Guidelines” for details on the following:
z LNA matching network (C1–C6, L1–L3). Values should be custom tuned for a specific PCB layout and SAW filter to
optimize performance.
z Differential traces between the SAW filters (Z1–Z3) and transceiver (U1) pins 17–22.
z Detailed SAW filter (Z1–Z3) requirements.
z L4 and PCB inductor trace L5 for frequency synthesizer (U3) pins 1–2 and 20–21.
z CKP/CKN and IOP/ION differential traces between transceiver (U1) pins 1–4 and baseband interface (U2) pins 9–12.
z X1 connection to U3 pins 11–12.
5. XEN, XDRVEN, and XTALEN are recommended to be tied together and controlled simultaneously.
16
Rev. 1.2
Aero+
Bill of Materials
Component(s)
Value/Description
Supplier(s)
C1–C2
1.2 pF, ±0.1 pF, C0G
(GSM 850 and E-GSM 900)
Murata GRM36C0G series
Venkel C0402C0G500 series
C3–C4
C5–C6
1.0 pF, ±0.1 pF, C0G
(DCS 1800)
Murata GRM36C0G series
Venkel C0402C0G500 series
1.0 pF, ±0.1 pF, C0G
(PCS 1900)
Murata GRM36C0G series
Venkel C0402C0G500 series
C7
C9–C10, C13–C14
C11–C12
100pF, ±5%, C0G
22 nF, ±20%, Z5U
10 pF, ±20%, C0G
24 nH, ±5%
Venkel C0402C0G500 series
L1
Murata LQW18AN series (0603 size)
Murata LQW15A series (0402 size)
L2
L3
7.5 nH, ±0.5 nH
6.8 nH, ±0.2 nH
Murata LQW18AN series (0603 size)
Murata LQW15A series (0402 size)
Murata LQW18AN series (0603 size)
Murata LQW15A series (0402 size)
L4
L5
3.9 nH, ±5%
Inductor for RF2 VCO
100 Ω, ±5%
Multi-layer (0402 or 0603 size)
PCB Trace
R1
U1
U2
U3
GSM Transceiver
Silicon Laboratories Si4200-BM
Silicon Laboratories Si4201-BM
Silicon Laboratories Si4134T-BM
Universal Baseband Interface
RF Synthesizer
X1
13 or 26 MHz Crystal, C = 8.0 pF
KDS BR13000AA0E
L
KSS CX96FFFBQAJ13
Z1
GSM 850 RX SAW Filter
(150 or 200 Ω balanced output)
EPCOS B39881-B7719-C610 (6-pin, 2.0x2.5 mm)
EPCOS B39881-B9001-C710 (5-pin, 1.4x2.0 mm)
Murata SAFSD881MFL0T00R00 (6-pin, 2.0x2.5 mm)
Murata SAFEK881MFL0T00R00 (6-pin, 1.6x2.0 mm)
E-GSM 900 RX SAW Filter
(150 or 200 Ω balanced output)
EPCOS B39941-B7721-C910 (6-pin, 2.0x2.5 mm)
EPCOS B39941-B7820-C710 (5-pin, 1.4x2.0 mm)
Murata SAFSD942MFM0T00R00 (6-pin, 2.0x2.5 mm)
Murata SAFEK942MFM0T00R00 (6-pin, 1.6x2.0 mm)
Z2
Z3
DCS 1800 RX SAW Filter
(150 or 200 Ω balanced output)
EPCOS B39182-B7749-C910 (6-pin, 2.0x2.5 mm)
EPCOS B39182-B7821-C710 (5-pin, 1.4x2.0 mm)
Murata SAFSD1G84FA0T00R00 (6-pin, 2.0x2.5 mm)
Murata SAFEK1G84FA0T00R00 (6-pin, 1.6x2.0 mm)
PCS 1900 RX SAW Filter
(150 or 200 Ω balanced output)
EPCOS B39202-B7741-C910 (6-pin, 2.0x2.5 mm)
EPCOS B39202-B7825-C710 (5-pin, 1.4x2.0 mm)
Murata SAFSD1G96FB0T00R00 (6-pin, 2.0x2.5 mm)
Murata SAFEK1G96FA0T00R00 (6-pin, 1.6x2.0 mm)
Rev. 1.2
17
Aero+
Functional Description
Si4200
Si4201
GSM
LNA
PGA
PGA
ADC
PGA
PGA
DAC
I
DCS
PCS
LNA
LNA
ADC
DAC
Q
XOUT
100 kHz
0 / 90
φ
DET
GSM
PA
PA
I
DCS
PCS
Q
Si4134T
RF
PLL
IF
PLL
DCXO
AFC
Figure 11. Aero+ Transceiver Block Diagram
The Aero+ transceiver is the industry’s most integrated reduced complexity. The universal baseband interface
RF front end for multi-band GSM/GPRS digital cellular is compatible with any supplier’s baseband subsystem.
handsets and wireless data modems. The chipset
The transmit section is a complete up-conversion path
consists of the Si4200 GSM transceiver, Si4201
from the baseband subsystem to the power amplifier,
universal baseband interface, and Si4134T dual RF
and uses an offset phase-locked loop (PLL) with a fully
synthesizer with an integrated digitally-controlled crystal
integrated transmit VCO. The frequency synthesizer
oscillator (DCXO). The highly integrated solution
uses Silicon Laboratories’ proven technology that
eliminates the IF SAW filter, external low noise
includes integrated RF and IF VCOs, varactors, and
amplifiers (LNAs) for three bands, transmit and RF
loop filters.
voltage-controlled oscillator (VCO) modules, and more
The unique integer-N PLL architecture used in the
than 60 other discrete components found in
Si4134T produces a transient response superior in
conventional designs.
speed to fractional-N architectures without suffering the
The high level of integration combined with micro
high phase noise or spurious modulation effects often
leadframe package (MLP) technology and fine line
associated with those designs. This fast transient
CMOS process technology results in a solution with
response makes the Aero+ chipset well suited to GPRS
50% less area and 80% fewer components than
multi-slot applications where channel switching and
competing solutions. A triple-band GSM transceiver
settling times are critical.
using the Aero+ chipset can be implemented with 19
While conventional solutions use BiCMOS or other
bipolar process technologies, the Aero+ chipset is the
industry’s first cellular transceiver to be implemented in
a 100% CMOS process. This brings the cost savings
and extensive manufacturing capacity of CMOS to the
GSM market.
2
components in less than 2 cm of board area. This level
of integration is an enabling force in lowering the cost,
simplifying the design and manufacturing, and shrinking
the form factor in next-generation GSM/GPRS voice
and data terminals.
The receive section uses a digital low-IF architecture
that avoids the difficulties associated with direct
conversion while delivering lower solution cost and
18
Rev. 1.2
Aero+
Receive Section
Si4200
Si4201
LNA
LNA
LNA
GSM
DCS
PCS
PGA
ADC
PGA
DAC
I
PGA
ADC
PGA
DAC
Q
DGAIN[5:0]
DACCM[1:0]
DACFS[1:0]
AGAIN[2:0]
CSEL
RXBAND[1:0]
LNAC[1:0]
LNAG[1:0]
100 kHz
0 / 90
ZERODEL[2:0]
Si4134T
NRF1[15:0]
RF
PLL
RFUP
Figure 12. Receiver Block Diagram
The Aero+ transceiver uses
a
low-IF receiver GSM 900 modes. The mixer output is amplified with an
architecture that allows for the on-chip integration of the analog programmable gain amplifier (PGA), which is
channel selection filters, eliminating the external RF controlled with the AGAIN[2:0] bits in register 05h. The
image reject filters and the IF SAW filter required in quadrature IF signal is digitized with high resolution A/D
conventional superheterodyne architectures. Compared converters (ADCs).
to
a
direct-conversion architecture, the low-IF
The Si4201 downconverts the ADC output to baseband
with a digital 100 kHz quadrature LO signal. Digital
decimation and IIR filters perform channel selection to
remove blocking and reference interference signals.
The response of the IIR filter is programmable to a high
selectivity setting (CSEL = 0) or a low selectivity setting
(CSEL = 1). The low selectivity filter has a flatter group
architecture has a much greater degree of immunity to
dc offsets that can arise from RF local oscillator (RFLO)
self-mixing, 2nd-order distortion of blockers, and device
1/f noise. This relaxes the common-mode balance
requirements on the input SAW filters and simplifies PC
board design and manufacturing.
The Si4200 integrates three differential-input LNAs. The delay response that may be desirable where the final
GSM input supports the GSM 850 (869–894 MHz) or E- channelization filter is in the baseband chip. After
GSM 900 (925–960 MHz) bands. The DCS input channel selection, the digital output is scaled with a
supports the DCS 1800 (1805–1880 MHz) band. The digital PGA, which is controlled with the DGAIN[5:0] bits
PCS input supports the PCS 1900 (1930–1990 MHz) in register 05h.
band. For quad-band designs, SAW filters for the
The LNAG[1:0], LNAC[1:0], AGAIN[2:0] and DGAIN[5:0]
GSM 850 and E-GSM 900 bands should be connected
bits must be set to provide a constant amplitude signal
to a balanced combiner which drives the GSM input for
to the baseband receive inputs. See “AN51: Aero
both bands. For dual-band designs using the
Transceiver AGC Strategy” for more details.
Si4200DB-BM, the PCS input should be used for either
DACs drive a differential analog signal onto the RXIP,
DCS 1800 or PCS 1900 bands.
RXIN, RXQP, and RXQN pins to interface to standard
The LNA inputs are matched to the 200 Ω balanced-
output SAW filters through external LC matching
networks. See “AN49: Aero Transceiver PCB Layout
Guidelines” for details. The LNA gain is controlled with
the LNAG[1:0] and LNAC[1:0] bits in register 05h.
analog-input baseband ICs. No special processing is
required in the baseband for offset compensation or
extended dynamic range. The receive and transmit
baseband I/Q pins can be multiplexed together into a 4-
wire interface. The common mode level at the receive I
A quadrature image-reject mixer downconverts the RF and Q outputs is programmable with the DACCM[1:0]
signal to a 100 kHz intermediate frequency (IF) with the bits, and the full scale level is programmable with the
RFLO from the Si4134T frequency synthesizer. The DACFS[1:0] bits in register 12h.
RFLO frequency is between 1737.8 and 1989.9 MHz,
and is divided by two in the Si4200 for GSM 850 and E-
Rev. 1.2
19
Aero+
Transmit Section
Si4134T
IF
RF
PLL
NRF2[15:0]
PDRB
NIF [15:0]
PDIB
PLL
Si4200
BBG[1:0]
SWAP
REG
GSM
PA
FIF[3:0]
÷2
REG
I
φ
DET
PA
÷1, 2
DCS/PCS
Q
TXBAND[1:0]
Figure 13. Transmitter Block Diagram
The transmit (TX) section consists of an I/Q baseband RFLO, high-side injection is used for the GSM 850 and
upconverter, an offset phase-locked loop (OPLL), and E-GSM 900 bands, and low-side injection is used for
two output buffers that can drive external power the DCS 1800 and PCS 1900 bands. The I and Q
amplifiers (PA): one for the GSM 850 (824 to 849 MHz) signals are automatically swapped within the Si4200
and E-GSM 900 (880 to 915 MHz) bands and one for when switching bands. Additionally, the SWAP bit in
the DCS 1800 (1710 to 1785 MHz) and PCS 1900 register 03h can be used to manually exchange the I
(1850 to 1910 MHz) bands. The OPLL requires no and Q signals.
external filtering to attenuate transmitter noise or
Low-pass filters before the OPLL phase detector reduce
spurious signals in the receive band, saving both cost
the harmonic content of the quadrature modulator and
and power. Additionally, the output of the transmit VCO
feedback mixer outputs. The cutoff frequency of the
(TXVCO) is a constant-envelope signal that reduces the
filters is programmable with the FIF[3:0] bits in
problem of spectral spreading caused by non-linearity in
register 04h and should be set to the recommended
settings detailed in the register description.
the PA.
A quadrature mixer upconverts the differential in-phase
(TXIP, TXIN) and quadrature (TXQP, TXQN) signals
with the IFLO to generate a SSB IF signal that is filtered
and used as the reference input to the OPLL. The
Si4134T generates the IFLO frequency between 766
and 896 MHz. The IFLO is divided by two to generate
the quadrature LO signals for the quadrature modulator,
resulting in an IF between 383 and 448 MHz. For the E-
GSM 900 band, two different IFLO frequencies are
required for spur management. Therefore, the IF PLL
must be programmed per channel in the E-GSM 900
band. The IFLO frequencies are defined in Table 6 on
page 12.
The OPLL consists of a feedback mixer, a phase
detector, a loop filter, and a fully integrated TXVCO. The
TXVCO is centered between the DCS 1800 and
PCS 1900 bands, and its output is divided by two for the
GSM 850 and E-GSM 900 bands. The Si4134T
generates the RFLO frequency between 1272 and
1483 MHz. To allow a single VCO to be used for the
20
Rev. 1.2
Aero+
Frequency Synthesizer
RFLC
RFLD
Si4134T
XAFC
XTALEN
÷65,
RF1
÷1,2
RFLOP
RFLON
φ
DET
÷130
DCXO
XTAL1
XTAL2
RF2
DIV2
RFUP
NRF1[15:0]
Self
Tune
N
RF2[15:0]
CDAC[5:0]
RF PLL
IF PLL
÷N
XDRV
XDRVEN
÷N
Power
Control
PDIB
PDN
PDRB
Self
NIF [15:0]
Tune
SDI
SCLK
SEN
Serial
I/O
SDOSEL[3:0]
IFLOP
IFLON
φ
DET
SDO
IFLA
IFLB
Figure 14. Si4134T Frequency Synthesizer Block Diagram
The Si4134T dual frequency synthesizer is a monolithic should be set appropriately. The RF PLL phase detector
CMOS integrated circuit that performs IF and RF update rate (f ) can be programmed with the RFUP bit
φ
synthesis. An integrated digitally-controlled crystal in Register 31h to either f = 100 kHz or f = 200 kHz.
φ
φ
oscillator (DCXO) is provided to generate the reference Receive mode should use f = 100 kHz in DCS 1800
φ
clock. The DCXO allows the use of a standard crystal and PCS 1900 bands, and f = 200 kHz in the GSM 850
φ
resonator, avoiding the need for a crystal oscillator and E-GSM 900 bands. For transmit modes, the RF2
module.
and IF PLL phase detector update rates should always
be configured for f = 200 kHz.
φ
Two complete PLLs are integrated including VCOs,
varactors, resonators, loop filters, reference and VCO
dividers, and phase detectors. Differential outputs for
the IF and RF PLLs are provided for direct connection to
the Si4200 transceiver IC. The RF PLL uses two
multiplexed VCOs. The RF1 VCO is used for receive
mode, and the RF2 VCO is used for transmit mode. The
IF PLL is used only during transmit mode and uses a
single VCO.
The IF and RF output frequencies are set by
programming the N-Divider registers, N
, N
, and
RF1
RF2
N . Programming the N-Divider register for either RF1
IF
or RF2 automatically selects the proper VCO. The
output frequency of each PLL is as follows:
fOUT = N × fφ
A programmable divider in the input stage allows either
a 13 or 26 MHz reference frequency depending on the
choice of crystal. When configured for 26 MHz
operation using a TCXO, the DIV2 bit in Register 31h
Rev. 1.2
21
Aero+
VCO Inductor Design
Si4134T
LPKG/2
LEXT
CVAR
CTUNE
CFIX
AMP
LPKG/2
Self
Tune
PLL
IC PACKAGE BOARD
Figure 15. VCO Block Diagram
Table 9. VCO fCEN Values (MHz)
Determining L
EXT
The center frequencies for the RF2, and IF VCOs in the
Si4134T are set using an external inductance (L ). It
is very important that L
EXT
RF1* RF2 IF
be properly designed to
EXT
Supported Bands
VCO VCO VCO
1862 1341 782
1897 1381 810
ensure maximum manufacturing margin for the desired
VCO frequency tuning ranges. Because the total tank
inductance is in the low nH range, the inductance of the
European Dual-Band (900/1800)
Triple-Band (900/1800/1900)
package (L
) must be considered in determining the
PKG
correct external inductance.
Quad-Band (850/900/1800/1900) 1864 1378 831
or North American Dual Band
(850/1900)
Figure 15 shows the detailed configuration of the
integrated VCOs. The total inductance (L
VCO is the sum of the external inductance (L
) of each
TOT
) and
EXT
*Note: LEXT is set internally.
the package inductance (L
). The total capacitance
PKG
(C
) of each VCO is the sum of the self tuning
TOT
capacitance (C
), the PLL varactor capacitance
TUNE
Table 10. VCO LEXT Values (nH)
(C
), and the fixed capacitance (C ). The nominal
VAR
FIX
capacitance (C
) of each VCO is calculated with
NOM
RF2
IF
C
and C
at their center values. C
and L
TUNE
VAR
NOM PKG
Supported Bands
VCO VCO
0.91 4.77
0.75 4.34
0.76 4.04
values are defined in Table 7 on page 14.
The center frequency is calculated as follows:
European Dual-Band (900/1800)
Triple-Band (900/1800/1900)
1
------------------------------------------------------------------
=
fCEN
2π CNOM(LPKG + LEXT
)
Quad-Band (850/900/1800/1900) or
North American Dual Band (850/1900)
The value for the external inductor is determined by the
following:
For example, the RF2 VCO for a triple-band design
requires f = 1381 MHz. Table 7 on page 14 shows
1
-------------------------------------------
LEXT
=
– LPKG
CEN
(2πfCEN)2CNOM
C
= 4.8 pF and L
= 2.02 nH for the RF2 VCO.
NOM
PKG
The previous equation shows L
connected between the RFLC and RFLD pins.
= 0.75 nH should be
EXT
where f
= desired center frequency of VCO.
= nominal capacitance from Table 7.
= package inductance from Table 7.
= external inductance required.
CEN
C
NOM
PKG
EXT
See “AN49: Aero Transceiver PCB Layout Guidelines”
for details on how to implement and verify the proper
L
L
value of L
.
EXT
22
Rev. 1.2
Aero+
The CDAC[5:0] register (register 28) may be
programmed during powerup or after an initial
calibration. Periodic adjustments to compensate for
aging may also be performed over time to ensure
accuracy.
DCXO Overview
The Si4134T integrates the DCXO circuitry required to
generate a precise system reference clock using only
an external crystal resonator. (See Figure 16.) An
internal digitally programmable capacitor array (CDAC)
provides a coarse method of adjusting the reference
frequency in discrete steps. An integrated analog
varactor (CVAR) allows for a fine and continuous
adjustment of the reference frequency by an external
control voltage (XAFC). This control voltage is supplied
The baseband determines the appropriate frequency
adjustment based on the receipt of the FCCH burst. The
baseband then adjusts the XAFC voltage using the
baseband AFC DAC (12 or 13-bit), which controls the
varactor on the Si4134T.
by the AFC DAC on the baseband IC. The complete The baseband AFC DAC can adjust CVAR to correct for
DCXO solution effectively replaces the TCVCXO frequency variations caused by temperature drift. The
module typically required to provide a 13 or 26 MHz step size per bit depends on the resolution of the AFC
reference clock for the system. The Si4134T generates DAC and its output voltage range.
a single-ended 13 or 26 MHz output (XDRV) to drive the
DCXO Crystal Selection
Si4201, and the Si4201 then buffers a 13 or 26 MHz
The tuning range specifications listed in Table 8 on
reference clock (XOUT) to be sent to other system
page 15 for CDAC and CVAR assume that Aero+ is
components such as the baseband. The complete
used with a crystal that conforms to the crystal
circuit is shown in the "Typical Triple-Band Application
parameters listed in the same table. Other crystals may
Schematic" on page 16.
be used with Aero+ for cost and/or performance
reasons. For example, using a higher sensitivity crystal
DCXO Tuning
The DCXO uses the CDAC and the CVAR to correct for extends the CVAR and the CDAC frequency
both static and dynamic frequency errors, respectively. compensation range. However, care must be taken
To compensate for crystal systematic offset error, the when using a more sensitive crystal because other
CDAC ensures a minimum of ±10 ppm frequency system parameters are affected. Contact Silicon
adjustment capability. The CDAC is programmed using Laboratories' applications support for assistance in
register 28h.
specifying other crystals.
Si4201
Si4134T
To
XOUT
XIN
XDRV
PLLs
XTAL2
CVAR
AMP
Y1
XTAL1
XAFC
CDAC[5:0]
AFC
DAC
Figure 16. DCXO System Signal Routing Diagram
Rev. 1.2
23
Aero+
Serial Interface
XDRV Buffer
A three-wire serial interface is provided to allow an To supply a frequency adjusted reference clock to the
external system controller to write the control registers Si4201, the XDRVEN pin on the Si4134T must be high.
for dividers, receive path gain, powerdown settings, and When held low, the Si4134T is fully operational, but no
other controls. The serial control word is 24 bits in reference signal (either 13 or 26 MHz) is sourced from
length, comprised of an 18-bit data field and a 6-bit the XDRV pin.
address field as shown in Figure 17. A single logical
register space is shared among the three chips, which is
DCXO and must be enabled (XTALEN = 1) before the
summarized in Table 11 on page 25.
XDRV signal can be sourced.
The XTALEN signal controls the powerup state of the
Last bit
clocked in
XOUT Buffer
The Si4201 contains a reference clock buffer to drive
D
D
D
D
D
D
D
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
the baseband input. The clock signal from the Si4134T
is capacitively coupled to the XIN pin on the Si4201. To
achieve complete powerdown during sleep, the XEN pin
must be set low, the XBUF bit in Register 12 must be
set to 0, and the XPD1 bit in Register 11 must be set to
1. During normal operation, these bits should set to their
default values.
17 16 15 14 13 12 11 10
Data Field
Address Field
Figure 17. Serial Interface Format
The serial interface pins are intended to be connected in
parallel to both the Si4201 and the Si4134T. Serial
control is relayed from the Si4201 to the Si4200 over
the signal interface (IOP/ION and CKP/CKN pins). All
registers must be written when the PDN pin is asserted
(low), except for Register 22h. All serial interface pins
should be held at a constant level during receive and
transmit bursts to minimize spurious emissions. This
includes stopping the SCLK clock. A timing diagram for
the serial interface is shown in Figure 3 on page 7.
The XOUT buffer is a CMOS driver stage with
approximately 250 Ω of series resistance. This buffer is
enabled when the XEN hardware control (pin 13 on the
Si4201) is set high, independent of the PDN control pin.
When the serial interface is enabled (i.e., when SEN is
low), data and address bits on the SDI pin are clocked
into an internal shift register on the rising edge of SCLK.
Data in the shift register is then transferred on the rising
edge of SEN into the internal data register addressed in
the address field. The internal shift register ignores any
leading bits before the 24 required bits. The serial
interface is disabled when SEN is high.
Optionally, registers can be read as illustrated in
Figure 4 on page 7. The serial output data appears on
the SDO pin after writing the revision register with the
address to be read. SDO is enabled when PDN = 0 on
the Si4201 and when PDN = 1 on the Si4134T, allowing
the SDO pin to be shared. Writing to any of the registers
causes the function of SDO to revert to its previously
programmed function.
24
Rev. 1.2
Aero+
Control Registers
Table 11. Register Summary
Bit
Reg Name
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Si4200
Revision/Read
00h
0
0
0
0
0
0
0
0
0
0
REV0[7:0]
01h
02h
03h
04h
05h
Reset
Mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0
SWAP
0
AUTO
MODE[1:0]
Config
DIAG[1:0]
TXBAND[1:0] RXBAND[1:0]
FIF[3:0]
0
0
1
0
0
0
Transmit
Receive
0
0
0
BBG[1:0]
DGAIN[5:0]
0
AGAIN[2:0]
LNAC[1:0]
REV1[7:0]
LNAG[1:0]
Si4201
Revision/Read
10h
0
0
0
0
0
0
0
0
0
11h
12h
19h
20h
21h
22h
23h
24h
28h
30h
Config
0
0
0
0
0
0
0
0
0
0
0
0
DPDS[2:0]
XPD1
1
XBUF‘
0
XSEL
0
ZDBS
0
1
0
0
1
0
0
0
0
CSEL
DAC Config
Reserved
0
0
0
0
0
0
1
0
0
0
ZERODEL[2:0]
0
DACCM[1:0]
DACFS[1:0]
0
0
0
0
RX Master #1 RXBAND[1:0]
NRF1[15:0]
AGAIN[2:0]
RX Master #2
RX Master #3
0
0
DPDS[2:0]
0
LNAC[1:0]
LNAG[1:0]
0
0
DGAIN[5:0]
DGAIN[5:0]
0
0
0
0
0
0
0
0
0
TX Master #1 TXBAND[1:0]
N
RF2[15:0]
TX Master #2
CDAC
FIF[3:0]
NIF[13:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CDAC[5:0]
Si4134T
Revision/Read
REV3[7:0]
RFUP DIV2
31h
32h
Config
0
0
0
0
0
0
0
0
0
0
0
0
SDOSEL[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Powerdown
0
0
0
0
0
0
0
PDIB PDRB
33h RF1 N Divider
34h RF2 N Divider
N
N
RF1[15:0]
RF2[15:0]
35h
IF N Divider
NIF[15:0]
Notes:
1. Any register not listed here is reserved and should not be written. Writing to reserved registers may result in
unpredictable behavior.
2. Master registers 20h to 24h simplify programming the Aero+ transceiver to support initiation of receive (RX) and transmit
(TX) operations with only two register writes.
3. See “AN50: Aero Transceiver Programming Guide” for detailed instructions on register programming.
Rev. 1.2
25
Aero+
Register 00h. Revision/Read (Si4200)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
REV0[7:0]
Name
Bit
Name
Function
17:8
7:0
Reserved
REV0[7:0]
Read as zero.
Si4200 Revision (read only).
00h = Si4200 revision A
01h = Si4200 revision B
02h = Si4200 revision C
03h = Si4200 revision D
14h = Si4200DB revision E (dual-band)
05h = Si4200 revision F (triple-band)
Note: Registers on the Si4200 can be read by writing this register with the address of the register to be read.
Register 01h. Reset (Si4200/Si4201)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Name
Bit
Name
Function
17:1
0
Reserved
RESET
Program to zero.
Chip Reset.
0 = Normal operation (default).
1 = Reset all registers to default values.
Note: See “Control Registers” on page 25 for more details. This register must be
written to 0 twice after a reset operation. This bit does not reset Si4134T
registers 30h to 35h.
26
Rev. 1.2
Aero+
Register 02h. Mode Control (Si4200/Si4201)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AUTO
MODE[1:0]
Name
Bit
Name
Function
17:3
2
Reserved
AUTO
Program to zero.
Automatic Mode Select.
0 = Manual. Mode is controlled by MODE[1:0] bits (default).
1 = Automatic. Last register write to N implies RX mode; Last register
RF1
write to N
implies TX mode. MODE[1:0] bits are ignored.
RF2
1:0
MODE[1:0]
Transmit/Receive/Calibration Mode Select.
00 = Receive mode (default).
01 = Transmit mode.
10 = Calibration mode.
11 = Reserved.
Note: These bits are valid only when AUTO = 0.
Note: Calibration must be performed each time the power supply is applied. To initiate the calibration mode, set
MODE[1:0] = 10, and pulse the PDN pin high for at least 150 µs.
Rev. 1.2
27
Aero+
Register 03h. Configuration (Si4200)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DIAG[1:0]
SWAP
0
0
0
TXBAND[1:0]
RXBAND[1:0]
0
0
1
0
Name
Bit
Name
Function
17:14
13:12
Reserved
DIAG[1:0]
Program to zero.
DIAG1/DIAG2 Output Select.
DIAG1
LOW
LOW
HIGH
HIGH
DIAG2
LOW (default)
HIGH
LOW
HIGH
00 =
01 =
10 =
11 =
Note: These pins can be used to control antenna switch functions. These bits
must be programmed with the PDN pin is zero. The DIAG1/DIAG2 pins
are be held at the desired value regardless of the state of the PDN pin.
11
SWAP
Transmit I/Q Swap.
0 = Normal (default).
1 = Swap I and Q for TXIP, TXIN, TXQP, and TXQN pins.
10:8
7:6
Reserved
Program to zero.
TXBAND[1:0]
Transmit Band Select.
00 = GSM 850 or E-GSM 900 (default).
01 = DCS 1800.
10 = PCS 1900.
11 = Reserved.
5:4
RXBAND[1:0]
Receive Band Select.
00 = GSM input. (default),
01 = DCS input.
10 = PCS input.
11 = Reserved.
3:2
1
Reserved
Reserved
Reserved
Program to zero.
Program to one.
Program to zero.
0
28
Rev. 1.2
Aero+
Register 04h. Transmit Control (Si4200)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
1
BBG[1:0]
FIF[3:0]
0
0
0
0
Name
Bit
Name
Function
17:11
10
Reserved
Reserved
BBG[1:0]
Program to zero.
Program to one.
9:8
TX Baseband Input Full Scale Differential Input Voltage.
00 = 1.7 V
01 = 1.3 V
(default).
.
PPD
PPD
10 = Reserved.
11 = 2.0 V
.
PPD
Note: Refer to Table 6 for minimum and maximum values. Set this register to the
nearest value.
7:4
3:0
FIF[3:0]
TX IF Filter Cutoff Frequency.
0110 = Use for DCS 1800 band.
0111 = Use for GSM 850, E-GSM 900 and PCS 1900 bands.
Note: Use the recommended setting for each band. Other settings reserved.
Reserved
Program to zero.
Rev. 1.2
29
Aero+
Register 05h. Receive Gain (Si4200/Si4201)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DGAIN[5:0]
0
AGAIN[2:0]
LNAC[1:0]
LNAG[1:0]
Name
Bit
Name
Function
17:14
13:8
Reserved
Program to zero.
DGAIN[5:0]
Digital PGA Gain Control.
00h = 0 dB (default).
01h = 1 dB.
...
3Fh = 63 dB.
Note: See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
7
Reserved
Program to zero.
6:4
AGAIN[2:0]
Analog PGA Gain Control.
000 = 0 dB (default).
001 = 4 dB.
010 = 8 dB.
011 = 12 dB.
100 = 16 dB.
101 = Reserved.
110 = Reserved.
111 = Reserved.
Note: See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
3:2
1:0
LNAC[1:0]
LNAG[1:0]
LNA Bias Current Control.
00 = Minimum current (default).
01 = Maximum current.
10 = Reserved.
11 = Reserved.
Note: Program these bits to the same value as same as LNAG[1:0]
LNA Gain Control.
00 = Minimum gain (default).
01 = Maximum gain.
10 = Reserved.
11 = Reserved.
Notes:
1. Program these bits to the same value as same as LNAC[1:0]
2. See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
30
Rev. 1.2
Aero+
Register 10h. Revision/Read (Si4201)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
REV1[7:0]
Name
Bit
Name
Function
17:8
7:0
Reserved
REV1[7:0]
Read as zero.
Si4201 Revision (read only).
00h = Rev A.
01h = Rev B.
02h = Rev C (latest version).
Note: Registers on the Si4201 can be read by writing this register with the address of the register to be read.
Register 11h. Configuration (Si4201)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DPDS[2:0]
XPD1
1
XSEL
0
1
0
1
0
0
0
CSEL
Name
Bit
Name
Function
17:14
13:11
Reserved
Program to zero.
Data Path Delayed Start.
111= Use for GSM 850 and GSM 900 bands.
011= Use for DCS 1800 and PCS 1900 bands (default).
DPDS[2:0]
Note: Use the recommended setting for each band. Other settings reserved.
10
XPD1
Reference Buffer Powerdown.
0 = Reference buffer automatically enabled (default).
1 = Reference buffer disabled.
Note: This bit should be set to 0 during normal operation. To achieve lowest
Si4201 powerdown current (IPDN1), this bit should be set to 1. The XBUF
bit in Register 12h must also be set appropriately
9
8
Reserved
XSEL
Program to one.
Reference Frequency Select.
0 = No divider. XIN = 13 MHz (default).
1 = Divide XIN by 2. XIN = 26 MHz.
Note: The internal clock should always be 13 MHz.
7
6
Reserved
Reserved
Reserved
Reserved
Reserved
CSEL
Program to zero.
Program to one.
Program to zero.
Program to one.
Program to zero.
5
4
3:1
0
Digital IIR Coefficient Select.
0 = High selectivity filter (default).
1 = Low selectivity filter.
Rev. 1.2
31
Aero+
Register 12h. DAC Configuration (Si4201)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
1
XBUF
0
ZDBS
ZERODEL[2:0]
DACCM[1:0]
DACFS[1:0]
Name
Bit
Name
Function
17:11
10
Reserved
Reserved
XBUF
Program to zero.
Program to one.
9
Reference Buffer Power Control.
0 = Reference buffer disabled.
1 = Reference buffer automatically enabled (default).
Note: This bit should be set to 1 during normal operation. To achieve the lowest
Si4201 power down current (IPDN1), this bit should be set to 0. The XPD1
bit in Register 12h must also be set appropriately.
8
7
Reserved
ZDBS
Program to zero.
ZERODEL Band Select.
0 = Use ZERODEL[2:0] settings corresponding to DCS/PCS column
(default).
1 = Use RXBAND[1:0] to determine ZERODEL[2:0] delay setting (GSM
or DCS/PCS).
6:4
ZERODEL[2:0]
RX Output Zero Delay.
Code
000:
001:
010:
011:
100:
101:
110:
111:
GSM
90 µs
DCS/PCS
130 µs
150 µs
170 µs
180 µs
190 µs
200 µs
220 µs
(Default)
110 µs
130 µs
140 µs
150 µs
160 µs
180 µs
Reserved
Note: DAC input is forced to zero after PDN is deasserted. This feature can be
used for baseband ADC offset calibration. Offsets induced on channels
due to 13 MHz harmonics are not included in the calibrated value.
3:2
1:0
DACCM[1:0]
DACFS[1:0]
RX Output Common Mode Voltage.
00 = 1.0 V.
01 = 1.25 V (default).
10 = 1.35 V.
11 = Reserved.
RX Output Differential Full Scale Voltage.
00 = 1.0 V
01 = 2.0 V
10 = 3.5 V
.
PPD
PPD
PPD
(default).
.
11 = Reserved.
32
Rev. 1.2
Aero+
Register 19h. Reserved (Si4201)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Bit
17:0
Name
Function
Reserved
Program to zero.
Register 20h. RX Master #1
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RXBAND[1:0]
NRF1[15:0]
Name
Notes:
1. See registers 03h and 33h for bit definitions.
2. When this register is written, the PDIB bit automatically sets to 0, the PDRB bit is set to 1, and the RFUP bit is set as a
function of RXBAND[1:0].
Register 21h. RX Master #2
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
DPDS[2:0]
LNAC[1:0]
LNAG[1:0]
AGAIN[2:0]
0
DGAIN[5:0]
Name
Note: See registers 05h and 11h for bit definitions.
Register 22h. RX Master #3
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
DGAIN[5:0]
Name
Notes:
1. See register 05h for bit definitions.
2. The DGAIN[5:0] in Register 22h can be changed without powering down.
Register 23h. TX Master #1
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TXBAND[1:0]
NRF2[15:0]
Name
Notes:
1. See registers 03h and 34h for bit definitions.
2. When this register is written, the PDIB bit automatically sets to 1, and the PDRB bit is set to 1.
Rev. 1.2
33
Aero+
Register 24h. TX Master #2
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FIF[3:0]
NIF[13:0]
Name
Note: See registers 04h and 35h for bit definitions.
Register 28h. CDAC (Si4134T)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
Name
CDAC[5:0]
Bit
Name
Function
17:6
5:0
Reserved
Read as zero.
CDAC[5:0]
DCXO Coarse Frequency DAC Adjustment.
64 steps. See Table 8 on page 15 for step size. An increase in CDAC
results in a lower oscillating frequency. Likewise, a decrease in CDAC
results in a higher oscillating frequency.
000000 = Highest frequency
...
111111 = Lowest frequency
Register 30h. Revision/Read (Si4134T)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
REV3[7:0]
Name
Bit
Name
Function
17:8
7:0
Reserved
REV3[7:0]
Read as zero.
Si4134T Revision (read only).
C0h = Rev A (latest version).
Note: Registers on the Si4134T can be read by writing this register with the address of the register to be read.
34
Rev. 1.2
Aero+
Register 31h. Main Configuration (Si4134T)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
SDOSEL[3:0]
0
0
0
0
0
0
RFUP DIV2
0
0
0
Name
Bit
Name
Function
17:15
Reserved
Program to zero.
SDO Output Control Register.
The mux_output table is as follows:
14:11
SDOSEL[3:0]
0000 Connected to the Output Shift Register (default).
0001 Force the Output to Low.
0010 Reference Clock.
0011 Lock Detect (LDETB) Signal from Phase Detectors.
1111 High Impedance.
Notes:
1. SDO is high-impedance when PDN = 0.
2. SDO is Serial Data Output when in register read mode.
10:5
4
Reserved
RFUP
Program to zero.
RF PLL Update Rate (RF1 VCO only).
0 = 200 kHz update rate (Receive GSM modes).
1 = 100 kHz update rate (Receive DCS and PCS modes).
Note: This bit is set to 1 when Register 20h D[17:16] = 01b or 10b (DCS 1800 or
PCS 1900 receive modes) and is set to 0 when D[17:16] = 00b or 11b
(GSM 850 or GSM 900 modes).
3
DIV2
Input Clock Frequency.
0 = No divider. XIN = 13 MHz.
1 = Divide XIN by 2. XIN = 26 MHz.
2:0
Reserved
Program to zero.
Rev. 1.2
35
Aero+
Register 32h. Powerdown (Si4134T)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDIB PDRB
Name
Bit
17:2
1
Name
Reserved
PDIB
Function
Program to zero.
Powerdown IF PLL.
0 = IF synthesizer powered down.
1 = IF synthesizer powered up when the PDN pin is high.
Notes:
1. The IF PLL is only used in transmit mode. Powerdown for receive mode.
2. This bit is set to 0 when register 20h is written (receive mode).
3. This bit is set to 1 when register 23h is written (transmit mode).
0
PDRB
Powerdown RF PLL.
0 = RF synthesizer powered down.
1 = RF synthesizer powered up when the PDN pin is high.
Notes:
1. This bit is set to 1 when register 20h is written (receive mode).
2. This bit is set to 1 when register 23h is written (transmit mode).
Register 33h. RF1 N Divider (Si4134T)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N
[15:0]
RF1
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N
[15:0]
N Divider for RF PLL (RF1 VCO).
RF1
Used for Receive mode.
Register 34h. RF2 N Divider (Si4134T)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N
[15:0]
RF2
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N
[15:0]
N Divider for RF PLL (RF2 VCO).
RF2
Used for Transmit mode.
36
Rev. 1.2
Aero+
Register 35h. IF N Divider (Si4134T)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N [15:0]
IF
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N [15:0]
N Divider for IF Synthesizer.
Used for transmit mode.
IF
Rev. 1.2
37
Aero+
Pin Descriptions: Si4200-BM
32 31 30 29 28 27 26 25
ION
IOP
1
2
3
4
5
6
7
8
24 RFOD
23 VDD
CKN
CKP
22 RFIGN
21 RFIGP
20 RFIDN
19 RFIDP
18 RFIPN
17 RFIPP
GND
PAD
TXIP
TXIN
TXQP
TXQN
9
10 11 12 13 14 15 16
Top View
Pin Number(s) Name
Description
1, 2
3, 4
5, 6
7, 8
9, 10
ION, IOP
Data output to Si4201 (differential).
Clock input from Si4201 (differential).
Transmit I input (differential).
CKN, CKP
TXIP, TXIN
TXQP, TXQN
IFLOP, IFLON
GND
Transmit Q input (differential).
IFLO Input from Si4133T (differential).
Ground. Connect to ground plane on PCB.
11, 27, 30,
GND pad
12, 13
RFLOP, RFLON RFLO Input from Si4133T (differential).
14, 23, 26, 32
15, 16
V
Supply voltage.
DD
DIAG2, DIAG1
RFIPP, RFIPN
RFIDP, RFIDN
RFIGP, RFIGN
RFOD
Diagnostic output.
Can be used as digital outputs to control antenna switch functions.
17, 18
19, 20
21, 22
24
PCS LNA input (differential).
Use for PCS 1900 band.
DCS LNA input (differential).
Use for DCS 1800 band.
GSM LNA input (differential).
Used for GSM 850 or E-GSM 900 bands.
DCS and PCS transmit output to power amplifier.
Used for DCS 1800 and PCS 1900 bands.
25
RFOG
GSM transmit output to power amplifier.
Used for GSM 850 and E-GSM 900 bands.
28, 29
31
NC
These pins should be left disconnected.
Powerdown input (active low).
PDN
38
Rev. 1.2
Aero+
Pin Descriptions: Si4200DB-BM
32 31 30 29 28 27 26 25
ION
IOP
1
2
3
4
5
6
7
8
24 RFOD
23 VDD
CKN
CKP
22 RFIGN
21 RFIGP
20 RFIDN
19 RFIDP
18 RFIPN
17 RFIPP
GND
PAD
TXIP
TXIN
TXQP
TXQN
9
10 11 12 13 14 15 16
Top View
Pin Number(s) Name
Description
1, 2
ION, IOP
Data output to Si4201 (differential).
Clock input from Si4201 (differential).
Transmit I input (differential).
3, 4
CKN, CKP
5, 6
TXIP, TXIN
7, 8
TXQP, TXQN
IFLOP, IFLON
Transmit Q input (differential).
9, 10
IFLO Input from Si4134T (differential).
12, 13
14, 23, 26, 32
15, 16
RFLOP, RFLON RFLO Input from Si4134T (differential).
V
Supply voltage.
DD
DIAG2, DIAG1
RFIPP, RFIPN
RFIGP, RFIGN
RFOD
Diagnostic output.
Can be used as digital outputs to control antenna switch functions.
17, 18
21, 22
24
PCS LNA input (differential).
Use for DCS 1800 or PCS 1900 bands.
GSM LNA input (differential).
Used for GSM 850 or E-GSM 900 bands.
DCS and PCS transmit output to power amplifier.
Used for DCS 1800 and PCS 1900 bands.
25
RFOG
GSM transmit output to power amplifier.
Used for GSM 850 and E-GSM 900 bands.
28, 29
31
NC
These pins should be left disconnected.
Powerdown input (active low).
PDN
11, 19, 20, 27, 30, GND
GND pad
Ground. Connect to ground plane on PCB.
Rev. 1.2
39
Aero+
Pin Descriptions: Si4201-BM
20 19 18 17 16
GND
1
2
3
4
5
15 SDO
14 PDN
13 XEN
12 ION
11 IOP
RXQP
RXQN
RXIP
GND
PAD
RXIN
6
7
8
9
10
Top View
Pin Number(s) Name
Description
2, 3
4, 5
6, 20
7
RXQP, RXQN
RXIP, RXIN
Receive Q output (differential).
Receive I output (differential).
Supply voltage.
V
DD
XIN
Reference frequency input from crystal oscillator.
Clock output to Si4200 (differential).
Data input from Si4200 (differential).
XOUT pin enable
9, 10
11, 12
13
CKP, CKN
IOP, ION
XEN
14
PDN
Powerdown input (active low).
Serial data output.
15
SDO
16
SEN
Serial enable input (active low).
Serial clock input.
17
SCLK
SDI
18
Serial data input.
19
XOUT
GND
Clock output to baseband.
Ground. Connect to ground plane on PCB.
1, 8,
GND pad
40
Rev. 1.2
Aero+
Pin Descriptions: Si4134T-BM
32 31 30 29 28 27 26 25
IFLB
IFLA
1
2
3
4
5
6
7
8
24 GND
23 NC
PDN
22 GND
21 RFLC
20 RFLD
19 GND
18 SDO
17 SDI
XDRVEN
XDRV
GND
GND
PAD
VDD
GND
9
10 11 12 13 14 15 16
Top View
Pin Number(s) Name
Description
1, 2
IFLB, IFLA
Tuning inductor connection for IF VCO.
Power down input (active low).
XDRV enable.
3
PDN
4
XDRVEN
XDRV
5
Reference clock output to Si4201.
Supply voltage.
7, 28, 31
9, 10, 23
11
V
DD
NC
No connect.
XTAL1
XTAL2
XTALEN
XAFC
SEN
Crystal input.
12
Crystal output.
13
Crystal enable.
14
Baseband AFC signal input.
Serial enable input (active low).
Serial clock input.
15
16
SCLK
SDI
17
Serial data input.
18
SDO
Serial data output.
20, 21
26, 27
29, 30
RFLC, RFLD
Tuning inductor connection for RF2 VCO.
RFLON, RFLOP RF PLL output to Si4200 (differential).
IFLON, IFLOP
IF PLL output to Si4200 (differential).
6, 8, 19, 22, 24, GND
25, 32, GND pad
Ground. Connect to ground plane on PCB.
Rev. 1.2
41
Aero+
Ordering Guide
Part Number Description
Package Type
MLP*
Operating
Temperature
Si4200-BM
Si4200-GM
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
Tri-Band Transceiver
GSM 850 or E-GSM 900, DCS 1800, PCS 1900
MLP lead-free*
MLP*
Tri-Band Transceiver
GSM 850 or E-GSM 900, DCS 1800, PCS 1900
Si4200DB-BM
Si4200DB-GM
Dual-Band Aero Transceiver
GSM 850/PCS 1900 or E-GSM 900/DCS 1800
MLP lead-free*
Dual-Band Aero Transceiver
GSM 850/PCS 1900 or E-GSM 900/DCS 1800
Si4201-BM
Si4201-GM
Si4134T-BM
Si4134T-GM
MLP*
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
Universal Baseband Interface
Universal Baseband Interface
Dual RF Synthesizer with DCXO
Dual RF Synthesizer with DCXO
MLP lead-free*
MLP*
MLP lead-free*
*Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
42
Rev. 1.2
Aero+
Package Outline: Si4200-BM and Si4200DB-BM
Figure 18 illustrates the package details for the Si4200-BM and Si4200DB-BM. Table 12 lists the values for the
dimensions shown in the illustration.
D
A
A1
A3
D1
D2
A2
L
b
PIN1 ID
0.50 DIA.
PIN1 ID
0.20 R.
32
32
1
2
3
1
2
3
b
E1
E
E2
θ
e
e
Top View
Side View
Bottom View
Figure 18. 32-Pin Micro Leadframe Package (MLP)
Table 12. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
Min
Nom
4.75 BSC
3.30
Max
A
A1
—
0.85
0.90
D1, E1
3.15
3.45
0.00
—
0.01
0.65
0.05
0.70
D2, E2
A2
e
θ
L
0.50 BSC
—
A3
0.20 REF.
0.23
—
12°
b
0.18
0.30
0.30
0.40
0.50
D, E
Notes:
5.00 BSC
1. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
2. Package warpage MAX 0.05 mm.
3. “b” applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal TIP.
4. The package weight is approximately 68 mg.
5. The mold compound for this package has a flammability rating of UL94-V0 with an oxygen index of 28
minimum/54 typical.
6. The recommended reflow profile for this package is defined by the JEDEC-020B Small Body specification.
Rev. 1.2
43
Aero+
Package Outline: Si4201-BM
Figure 19 illustrates the package details for the Si4201-BM. Table 13 lists the values for the dimensions shown in
the illustration.
A
D
D1
A1
D2
A2
L
b
PIN1 ID
0.50 DIA.
A3
b
20
20
1
2
3
1
2
3
E1
E
E2
θ
e
e
Top View
Side View
Bottom View
Figure 19. 20-Pin Micro Leadframe Package (MLP)
Table 13. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
Min
Nom
Max
A
A1
—
0.85
0.90
D1, E1
3.75 BSC
0.00
—
0.01
0.65
0.05
0.70
D2, E2
1.95
2.10
0.50 BSC
—
2.25
A2
e
θ
L
A3
0.20 REF.
0.23
—
12°
0.50
0.60
0.75
b
0.18
0.30
D, E
Notes:
4.00 BSC
1. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
2. Package warpage MAX 0.05 mm.
3. “b” applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal TIP.
4. The package weight is approximately 42 mg.
5. The mold compound for this package has a flammability rating of UL94-V0 with an oxygen index of 28
minimum/54 typical.
6. The recommended reflow profile for this package is defined by the JEDEC-020B Small Body specification.
44
Rev. 1.2
Aero+
Package Outline: Si4134T-BM
Figure 18 illustrates the package details for the Si4134T-BM. Table 12 lists the values for the dimensions shown in
the illustration.
D
A
A1
A3
D1
D2
A2
L
b
PIN1 ID
0.50 DIA.
PIN1 ID
0.20 R.
32
32
1
2
3
1
2
3
b
E1
E
E2
θ
e
e
Top View
Side View
Bottom View
Figure 20. 32-Pin Micro Leadframe Package (MLP)
Table 14. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
Min
Nom
4.75 BSC
3.10
Max
A
A1
—
0.85
0.90
D1, E1
2.95
3.25
0.00
—
0.01
0.65
0.05
0.70
D2, E2
A2
e
θ
L
0.50 BSC
—
A3
0.20 REF.
0.23
—
12°
b
0.18
0.30
0.30
0.40
0.50
D, E
Notes:
5.00 BSC
1. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
2. Package warpage MAX 0.05 mm.
3. “b” applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal TIP.
4. The package weight is approximately 66 mg.
5. The mold compound for this package has a flammability rating of UL94-V0 with an oxygen index of 28
minimum/54 typical.
6. The recommended reflow profile for this package is defined by the JEDEC-020B Small Body specification.
Rev. 1.2
45
Aero+
Document Change List
Revision 1.0 to Revision 1.1
This document corresponds to the following:
z Si4200DB revision E (dual band LNA) or Si4200
revision F (triple band LNA)
z Si4201 revision C
z Si4134T revision A
"Bill of Materials" on page 17
z Updated L1–-L3 with 0402 sizes.
"Ordering Guide" on page 42 updated to include
lead-free ordering option.
"Package Outline: Si4200-BM and Si4200DB-BM"
on page 43 (documentation change only, no change
to part)
z Updated D2,E2 dimensions.
z Updated device weight.
z Added notes 5 and 6.
"Package Outline: Si4201-BM" on page 44
(documentation change only, no change to part)
z Updated L dimension.
z Updated device weight.
z Added notes 5 and 6.
"Package Outline: Si4134T-BM" on page 45
(documentation change only, no change to part)
z Updated L dimension.
z Updated device weight.
z Added notes 5 and 6.
Revision 1.1 to Revision 1.2
This document corresponds to the following:
z Si4200DB revision E (dual band LNA) or Si4200
revision F (triple band LNA)
z Si4201 revision C
z Si4134T revision A
"Package Outline: Si4134T-BM" on page 45
(documentation change only, no change to part)
z Updated L dimension
46
Rev. 1.2
Aero+
Notes:
Rev. 1.2
47
Aero+
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, Texas 78735
Tel:1+ (512) 416-8500
Fax:1+ (512) 416-9669
Toll Free:1+ (877) 444-3032
Email: Aeroinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no war-
ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applica-
tions intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a
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Silicon Laboratories, Silicon Labs, and Aero are trademarks of Silicon Laboratories Inc.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder
48
Rev. 1.2
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