SI4136-F-GMR [SILICON]
RF and Baseband Circuit, ROHS COMPLIANT, QFN-28;
| 型号： | SI4136-F-GMR |
| 厂家： | 
SILICON |
| 描述： | RF and Baseband Circuit, ROHS COMPLIANT, QFN-28 ISM频段 无线 通信 |
| 文件： | 总34页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4136/Si4126
ISM RF SYNTHESIZER WITH INTEGRATED VCOS
FOR WIRELESS COMMUNICATIONS
Features
Dual-band RF synthesizers
RF1: 2300 MHz to 2500 MHz
RF2: 2025 MHz to 2300 MHz
IF synthesizer
Minimal external components
required
Low phase noise
5 µA standby current
25.7 mA typical supply current
2.7 V to 3.6 V operation
Packages: 24-pin TSSOP,
28-lead QFN
62.5 MHz to 1000 MHz
Ordering Information:
Integrated VCOs, loop filters,
See page 29.
varactors, and resonators
Lead-free/RoHS-compliant options
available
Pin Assignments
Applications
Si4136-BT/GT
ISM and MMDS band
communications
Wireless LAN and WAN
Dual-band communications
SEN
SCLK
1
24
23
22
21
20
19
18
17
16
15
14
13
VDDI
IFOUT
GND
SDATA
GND
GND
NC
2
3
Description
4
IFLB
The Si4136 is a monolithic integrated circuit that performs both IF and RF
synthesis for wireless communications applications. The Si4136 includes
three VCOs, loop filters, reference and VCO dividers, and phase detectors.
Divider and powerdown settings are programmable through a three-wire
serial interface.
5
IFLA
GND
NC
6
GND
7
VDDD
GND
GND
GND
GND
RFOUT
VDDR
8
9
Functional Block Diagram
XIN
10
11
12
PWDN
AUXOUT
Reference
÷1/÷2
XIN
RRF1
RRF2
RIF
Phase
Detect
Amplifier
RF1
Power
Down
PWDN
Si4136-BM/GM
RFOUT
NRF1
NRF2
NIF
2
Control
SDATA
SCLK
Phase
Detect
Serial
Interface
RF2
28 27 26 25 24 23
22
22-bit
Data
SEN
GND
GND
NC
1
2
3
4
5
6
7
21 GND
20 IFLB
19 IFLA
18 GND
17 VDDD
16 GND
15 XIN
2
Register
Phase
Detect
Test
Mux
AUXOUT
IFDIV
IFOUT
GND
GND
NC
IF
IFLA
IFLB
GND
GND
8
9
10 11 12 13 14
Patents pending
Rev. 1.41 1/10
Copyright © 2010 by Silicon Laboratories
Si4136/Si4126
Si4136/Si4126
2
Rev. 1.41
Si4136/Si4126
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.2. Setting the IF VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.3. Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.4. Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.5. PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.6. RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.7. Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.8. Powerdown Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.9. Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4. Pin Descriptions: Si4136-BT/GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Pin Descriptions: Si4136-BM/GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7. Si4136 Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Package Outline: Si4136-BT/GT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Package Outline: Si4136-BM/GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Rev. 1.41
3
Si4136/Si4126
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Symbol
Test Condition
Min
–40
2.7
Typ
25
Max
85
Unit
°C
V
T
A
Supply Voltage
VDD
3.0
—
3.6
0.3
Supply Voltages Difference
V
(V
– V
– V
),
DDD
–0.3
V
DDR
(V
)
DDD
DDI
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
–0.5 to 4.0
±10
Unit
V
DC Supply Voltage
V
DD
3
IIN
VIN
mA
V
Input Current
3
–0.3 to V +0.3
Input Voltage
DD
o
Storage Temperature Range
TSTG
–55 to 150
C
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of
this device should only be done at ESD-protected workstations.
3. For signals SCLK, SDATA, SEN, PWDN, and XIN.
4
Rev. 1.41
Si4136/Si4126
Table 3. DC Characteristics
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
—
Typ
25.7
15.7
15
Max
31
Unit
mA
mA
mA
mA
µA
V
1
Total Supply Current
RF1 and IF operating
1
RF1 Mode Supply Current
—
19
1
RF2 Mode Supply Current
—
18
1
IF Mode Supply Current
—
10
12
Standby Current
PWDN = 0
—
1
—
2
High Level Input Voltage
VIH
VIL
IIH
0.7 VDD
—
—
—
2
Low Level Input Voltage
—
0.3 VDD
10
V
2
High Level Input Current
V
IH = 3.6 V,
–10
—
µA
V
DD = 3.6 V
2
Low Level Input Current
IIL
V
IL = 0 V,
–10
—
10
µA
V
DD= 3.6 V
3
High Level Output Voltage
VOH
VOL
IOH = –500 µA
IOH = 500 µA
VDD–0.4
—
—
—
—
V
V
3
Low Level Output Voltage
0.4
Notes:
1. RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0.
2. For signals SCLK, SDATA, SEN, and PWDN.
3. For signal AUXOUT.
Rev. 1.41
5
Si4136/Si4126
Table 4. Serial Interface Timing
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
1
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
SCLK Cycle Time
SCLK Rise Time
SCLK Fall Time
SCLK High Time
SCLK Low Time
tclk
tr
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
40
—
—
10
10
5
—
—
—
—
—
—
—
—
—
—
—
—
50
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tf
th
tl
2
SDATA Setup Time to SCLK
tsu
thold
ten1
ten2
ten3
tw
2
SDATA Hold Time from SCLK
0
2
SEN to SCLKDelay Time
10
12
12
10
2
SCLK to SENDelay Time
2
SEN to SCLKDelay Time
SEN Pulse Width
Notes:
1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.
2. Timing is not referenced to 50% level of the waveform. See Figure 2.
tr
tf
80%
50%
20%
SCLK
th
tl
tclk
Figure 1. SCLK Timing Diagram
6
Rev. 1.41
Si4136/Si4126
A
A
Figure 2. Serial Interface Timing Diagram
First bit
Last bit
clocked in
clocked in
D D D D D D D D D D D D D D D D D D A A A A
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0
data
field
address
field
Figure 3. Serial Word Format
Rev. 1.41
7
Si4136/Si4126
Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter1
Symbol
Test Condition
Min
Typ
Max
Unit
XIN Input Frequency
fREF
fREF
XINDIV2 = 0
XINDIV2 = 1
2
—
—
—
25
50
MHz
MHz
XIN Input Frequency
25
0.5
Reference Amplifier Sensitivity
VREF
V
V
PP
DD
+0.3 V
Phase Detector Update Frequency
f
f = f
/R for
0.010
—
1.0
MHz
REF
XINDIV2 = 0
f = f /2R for
REF
XINDIV2 = 1
2
RF1 VCO Tuning Range
2300
2025
526
62.5
–5
—
—
2500
2300
952
1000
5
MHz
MHz
2
RF2 VCO Tuning Range
IF VCO Center Frequency Range
f
—
MHz
CEN
IFOUT Tuning Range from f
with IFDIV
Note: L ±10%
Open loop
—
MHz
CEN
IFOUT VCO Tuning Range from f
RF1 VCO Pushing
RF2 VCO Pushing
IF VCO Pushing
—
%
CEN
—
0.75
0.65
0.10
0.250
0.100
0.025
–130
1.2
—
MHz/V
MHz/V
MHz/V
MHz p-p
MHz p-p
MHz p-p
dBc/Hz
—
—
—
—
RF1 VCO Pulling
VSWR = 2:1, all
phases, open loop
—
—
RF2 VCO Pulling
—
—
IF VCO Pulling
—
—
RF1 Phase Noise
1 MHz offset
—
—
RF1 Integrated Phase Error
100 Hz to 100 kHz
—
—
degrees
rms
RF2 Phase Noise
1 MHz offset
—
—
–131
1.0
—
—
dBc/Hz
RF2 Integrated Phase Error
100 Hz to 100 kHz
degrees
rms
IF Phase Noise at 800 MHz
IF Integrated Phase Error
100 kHz offset
—
—
–104
0.4
—
—
dBc/Hz
100 Hz to 100 kHz
degrees
rms
Notes:
1. f(RF) = 1 MHz, f(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters
unless otherwise noted.
2. RF VCO tuning range limits are fixed by inductance of internally bonded wires.
3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error).
4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current
equal to IPWDN
.
8
Rev. 1.41
Si4136/Si4126
Table 5. RF and IF Synthesizer Characteristics (Continued)
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter1
Symbol
Test Condition
Min
Typ
Max
Unit
RF1 Harmonic Suppression
RF2 Harmonic Suppression
IF Harmonic Suppression
RFOUT Power Level
RFOUT Power Level
IFOUT Power Level
Second Harmonic
—
—
—
–7
–7
–7
—
—
—
—
—
—
—
–28
–23
–26
–3.5
–3.5
–4
–20
–20
–20
–0.5
–0.5
0
dBc
dBc
dBc
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBc
s
Z = 50RF1 active
L
Z = 50RF2 active
L
Z = 50
L
RF1 Output Reference Spurs
Offset = 1 MHz
Offset = 2 MHz
Offset = 3 MHz
Offset = 1 MHz
Offset = 2 MHz
Offset = 3 MHz
Figures 4, 5
–63
–68
–70
–63
–68
–70
80
—
—
—
RF2 Output Reference Spurs
—
—
—
3
3
Powerup Request to Synthesizer Ready
Time
tpup
tpup
tpdn
100
f > 500 kHz
Powerup Request to Synthesizer Ready
Time
Figures 4, 5
—
—
40/f
—
50/f
f 500 kHz
4
Powerdown Request to Synthesizer Off
Time
Figures 4, 5
100
ns
Notes:
1. f(RF) = 1 MHz, f(IF) = 1 MHz, RF1 = 2.4 GHz, RF2 = 2.1 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters
unless otherwise noted.
2. RF VCO tuning range limits are fixed by inductance of internally bonded wires.
3. From powerup request (PWDN or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error).
4. From powerdown request (PWDN, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current
equal to IPWDN
.
Rev. 1.41
9
Si4136/Si4126
RF synthesizers settled to within
0.1 ppm frequency error.
RF synthesizers settled to within
0.1 ppm frequency error.
tpup
tpdn
IT
tpup
tpdn
IPWDN
IT
IPWDN
SEN
PWDN
PDIB = 1
PDRB = 1
PDIB = 0
PDRB = 0
SDATA
Figure 5. Hardware Power Management
Timing Diagram
Figure 4. Software Power Management
Timing Diagram
10
Rev. 1.41
Si4136/Si4126
Figure 6. Typical Transient Response RF1 at 2.4 GHz
with 1 MHz Phase Detector Update Frequency
Rev. 1.41
11
Si4136/Si4126
-60
-70
-80
-90
-100
-110
-120
-130
-140
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Offset Frequency (Hz)
Typical RF1 Phase Noise at 2.4 GHz
Figure 7. Typical RF1 Phase Noise at 2.4 GHz
with 1 MHz Phase Detector Update Frequency
Figure 8. Typical RF1 Spurious Response at 2.4 GHz
with 1 MHz Phase Detector Update Frequency
12
Rev. 1.41
Si4136/Si4126
s
-60
-70
-80
-90
-100
-110
-120
-130
-140
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Offset Frequency (Hz)
Typical RF2 Phase Noise at 2.1 GHz
Figure 9. Typical RF2 Phase Noise at 2.1 GHz
with 1 MHz Phase Detector Update Frequency
Figure 10. Typical RF2 Spurious Response at 2.1 GHz
with 1 MHz Phase Detector Update Frequency
Rev. 1.41
13
Si4136/Si4126
-60
-70
-80
-90
-100
-110
-120
-130
-140
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Offset Frequency (Hz)
Typical IF Phase Noise at 800 MHz
Figure 11. Typical IF Phase Noise at 800 MHz
with 1 MHz Phase Detector Update Frequency
Figure 12. IF Spurious Response at 800 MHz
with 1 MHz Phase Detector Update Frequency
14
Rev. 1.41
Si4136/Si4126
VDD
Si4136
From
System
30
0.022 F
1
2
24
23
22
21
20
19
18
17
16
15
14
13
SEN
VDDI
SCLK
SDATA
GND
GND
NC
Controller
560 pF
LMATCH
3
IFOUT
GND
IFOUT
4
Printed Trace
Inductor or
Chip Inductor
5
IFLB
6
IFLA
GND
NC
7
GND
VDD
0.022 F
8
VDDD
GND
GND
GND
GND
RFOUT
VDDR
9
560 pF
10
11
12
XIN
External Clock
PDWNB
560 pF
RFOUT
PWDN
AUXOUT
VDD
0.022 F
AUXOUT
*Add 30 series resistor if using IF output divide values 2, 4, or 8 and fCEN < 600 MHz.
Figure 13. Typical Application Circuit: Si4136-BT/GT
Rev. 1.41
15
Si4136/Si4126
frequencies greater than 25 MHz, the Si4136 includes a
programmable divide-by-2 option (XINDIV2 in
2. Functional Description
The Si4136 is a monolithic integrated circuit that Register 0, D6) on the XIN input. By enabling this
performs IF and dual-band RF synthesis for many option, the Si4136 can accept a range of TCXO
wireless communications applications. This integrated frequencies from 25 MHz to 50 MHz. This feature
circuit (IC), along with a minimum number of external makes the Si4136 ideal for W-LAN radio designs
components, is all that is necessary to implement the operating at an XIN of 44 MHz.
frequency synthesis function in applications like W-LAN
using the IEEE 802.11 standard.
The unique PLL architecture used in the Si4136
produces settling (lock) times that are comparable in
The Si4136 has three complete phase-locked loops speed to fractional-N architectures without suffering the
(PLLs), with integrated voltage-controlled oscillators high phase noise or spurious modulation effects often
(VCOs). The low phase noise of the VCOs makes the associated with those designs.
Si4136 suitable for use in demanding wireless
2.1. Serial Interface
communications applications. Also integrated are phase
detectors, loop filters, and reference and output A timing diagram for the serial interface is shown in
frequency dividers. The IC is programmed through a Figure 2 on page 7. Figure 3 on page 7 shows the
three-wire serial interface.
format of the serial word.
Two PLLs are provided for RF synthesis. These RF The Si4136 is programmed serially with 22-bit words
PLLs are multiplexed so that only one PLL is active at a comprised of 18-bit data fields and 4-bit address fields.
given time (as determined by the setting of an internal When the serial interface is enabled (i.e., when SEN is
register). The active PLL is the last one written. The low) data and address bits on the SDATA pin are
center frequency of the VCO in each PLL is set by the clocked into an internal shift register on the rising edge
internal bond wire inductance within the package. of SCLK. Data in the shift register is then transferred on
Inaccuracies in these inductances are compensated for the rising edge of SEN into the internal data register
by the self-tuning algorithm. The algorithm is run addressed in the address field. The serial interface is
following power-up or following a change in the disabled when SEN is high.
programmed output frequency.
Table 11 on page 21 summarizes the data register
The RF PLLs contain a divide-by-2 circuit before the N- functions and addresses. It is not necessary (although it
divider. As a result, the phase detector frequency (f) is is permissible) to clock into the internal shift register any
equal to half the desired channel spacing. For example, leading bits that are “don’t cares.”
for a 200 kHz channel spacing, f would equal 100 kHz.
2.2. Setting the IF VCO Center Frequencies
The IF PLL does not contain the divide-by-2 circuit
before the N-divider. In this case, f is equal to the The IF PLL can adjust its output frequency ±5% from
desired channel spacing. Each RF VCO is optimized for the center frequency as established by the value of an
a particular frequency range. The RF1 VCO is external inductance connected to the VCO. The RF1
optimized to operate from 2.3 GHz to 2.5 GHz, while the and RF2 PLLs have fixed operating ranges due to the
RF2 VCO is optimized to operate between 2.025 GHz inductance set by the internal bond wires. Each center
and 2.3 GHz.
frequency is established by the value of the total
inductance (internal and/or external) connected to the
respective VCO. Manufacturing tolerance of ±10% for
the external inductor is acceptable for the IF VCO. The
Si4136 will compensate for inaccuracies by executing a
self-tuning algorithm following PLL power-up or
One PLL is provided for IF synthesis. The center
frequency of this circuit’s VCO is set by an external
inductance. The PLL can adjust the IF output frequency
by ±5% of the VCO center frequency. Inaccuracies in
the value of the external inductance are compensated
for by the Si4136’s proprietary self-tuning algorithm.
This algorithm is initiated each time the PLL is powered-
following
a
change in the programmed output
frequency.
up (by either the PWDN pin or by software) and/or each Because the total tank inductance is in the low nH
time a new output frequency is programmed. The IF range, the inductance of the package needs to be
VCO can have its center frequency set as low as considered in determining the correct external
526 MHz and as high as 952 MHz. An IF output divider inductance. The total inductance (L
) presented to
TOT
is provided to divide down the IF output frequencies, if the IF VCO is the sum of the external inductance (L
)
EXT
needed. The divider is programmable, capable of and the package inductance (L
). The IF VCO has a
PKG
dividing by 1, 2, 4, or 8.
nominal capacitance (C
) in parallel with the total
NOM
inductance, and the center frequency is as follows:
In order to accommodate designs running at XIN
16
Rev. 1.41
Si4136/Si4126
2.3. Self-Tuning Algorithm
1
1
fCEN = --------------------------------------------- = ----------------------------------------------------------------------
2 LTOT CNOM 2 LPKG + LEXT CNOM
The self-tuning algorithm is initiated immediately
following power-up of a PLL or, if the PLL is already
powered, following a change in its programmed output
frequency. This algorithm attempts to tune the VCO so
that its free-running frequency is near the desired output
frequency. In so doing, the algorithm will compensate
for manufacturing tolerance errors in the value of the
external inductance connected to the IF VCO. It will also
reduce the frequency error for which the PLL must
correct to get the precise desired output frequency. The
self-tuning algorithm will leave the VCO oscillating at a
frequency in error by somewhat less than 1% of the
desired output frequency.
Table 6 summarizes the characteristics of the IF VCO.
Table 6. Si4136-BT/GT VCO Characteristics
VCO Fcen Range Cnom Lpkg
Lext Range
(nH)
(MHz)
(pF)
(nH)
Min Max
526 952
Min
Max
IF
6.5
2.1
2.2
12.0
After self-tuning, the PLL controls the VCO oscillation
frequency. The PLL will complete frequency locking,
eliminating any remaining frequency error. Thereafter, it
will maintain frequency-lock, compensating for effects
caused by temperature and supply voltage variations.
Si4136
IFLA
LEXT
LPKG
2
The Si4136’s self-tuning algorithm will compensate for
component value errors at any temperature within the
specified temperature range. However, the ability of the
PLL to compensate for drift in component values that
occur after self-tuning is limited. For external
inductances with temperature coefficients around ±150
ppm/°C, the PLL will be able to maintain lock for
changes in temperature of approximately ±30°C.
IFLB
LPKG
2
Figure 14. Example of IF External Inductor
design example, suppose synthesizing
As
a
Applications where the PLL is regularly powered-down
or the frequency is periodically reprogrammed minimize
or eliminate the potential effects of temperature drift
because the VCO is re-tuned in either case. In
applications where the ambient temperature can drift
substantially after self-tuning, it may be necessary to
monitor the lock-detect bar (LDETB) signal on the
AUXOUT pin to determine whether a PLL is about to
run out of locking capability. (See “2.9. Auxiliary Output
(AUXOUT)” for how to select LDETB.) The LDETB
signal will be low after self-tuning has completed but will
rise when either the IF or RF PLL nears the limit of its
compensation range. (LDETB will also be high when
either PLL is executing the self-tuning algorithm.) The
output frequency will still be locked when LDETB goes
high, but the PLL will eventually lose lock if the
temperature continues to drift in the same direction.
Therefore, if LDETB goes high both the IF and RF PLLs
should promptly be re-tuned by initiating the self-tuning
algorithm.
frequencies in a 30 MHz band between 735 MHz and
765 MHz is desired. The center frequency should be
defined as midway between the two extremes, or
750 MHz. The PLL will be able to adjust the VCO output
frequency ±5% of the center frequency, or ±37.5 MHz of
750 MHz (i.e., from approximately 713 MHz to
788 MHz). The IF VCO has a C
of 6.5 pF, and a
NOM
6.9 nH inductance (correct to two digits) in parallel with
this capacitance will yield the desired center frequency.
An external inductance of 4.8 nH should be connected
between IFLA and IFLB, as shown in Figure 14. This, in
addition to 2.1 nH of package inductance, will present
the correct total inductance to the VCO. In
manufacturing, the external inductance can vary ±10%
of its nominal value and the Si4136 will correct for the
variation with the self-tuning algorithm.
For more information on designing the external trace
inductor, please refer to Application Note 31.
2.4. Output Frequencies
The IF and RF output frequencies are set by
programming the R- and N-Divider registers. Each PLL
has its own R and N registers so that each can be
Rev. 1.41
17
Si4136/Si4126
programmed independently. Programming either the R- transient until the point at which stability begins to be
or N-Divider register for RF1 or RF2 automatically compromised. The optimal gain depends on N. Table 8
selects the associated output.
lists recommended settings for different values of N.
When XINDIV2 = 0, the reference frequency on the XIN
pin is divided by R and this signal is the input to the
PLL’s phase detector. The other input to the phase
detector is the PLL’s VCO output frequency divided by
2N for the RF PLLs or N for the IF PLL. After an initial
transient
Table 8. Optimal KP Settings
RF1
<1:0>
RF2
K <1:0> K <1:0>
P2
IF
N
K
P1
PI
2047
00
00
01
10
11
00
00
01
10
11
11
Equation 1. f
= (2N/R)
f
(for the RF PLLs)
OUT
OUT
REF
2048 to 4095
4096 to 8191
8192 to 16383
16384
01
10
11
11
Equation 2. f
= (N/R)
f
(for the IF PLL).
REF
The integers R are set by programming the RF1 R-
Divider register (Register 6), the RF2 R-Divider register
(Register 7) and the IF R-Divider register (Register 8).
The integers N are set by programming the RF1 N-
Divider register (register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
The VCO gain and loop filter characteristics are not
programmable.
If the optional divide-by-2 circuit on the XIN pin is
enabled (XINDIV2 = 1) then after an initial transient
The settling time for each PLL is directly proportional to
its phase detector update period T (T equals 1/f ).
f
f
= (N/R)
f
(for the RF PLLs)
OUT
OUT
REF
= (N/2R)
During the first 13 update periods the Si4136 executes
the self-tuning algorithm. Thereafter the PLL controls
the output frequency. Because of the unique
architecture of the Si4136 PLLs, the time required to
settle the output frequency to 0.1 ppm error is only
about 25 update periods. Thus, the total time after
power-up or a change in programmed frequency until
the synthesized frequency is well settled—including
time for self-tuning—is around 40 update periods.
f
(for the IF PLL).
REF
Each N-Divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the control of these
sub-circuits is handled automatically. Only the
appropriate N value should be programmed.
2.5. PLL Loop Dynamics
Note: This settling time analysis holds for f 500 kHz. For
f 500 kHz, the settling time can be a maximum of
100 s as specified in Table 5.
The transient response for each PLL is determined by
its phase detector update rate f (equal to f
/R) and
REF
the phase detector gain programmed for each RF1,
RF2, or IF synthesizer. (See Register 1.) Four different
settings for the phase detector gain are available for
each PLL. The highest gain is programmed by setting
the two phase detector gain bits to 00, and the lowest by
setting the bits to 11. The values of the available gains,
relative to the highest gain, are listed in Table 7.
2.6. RF and IF Outputs (RFOUT and IFOUT)
The RFOUT and IFOUT pins are driven by amplifiers
that buffer the RF VCOs and IF VCO, respectively. The
RF output amplifier receives its input from either the
RF1 or RF2 VCO, depending upon which R- or N-
Divider register was last written. For example,
programming the N-Divider register for RF1
automatically selects the RF1 VCO output.
Table 7. Gain Values (Register 1)
Relative P.D.
K Bits
P
Figure 13 on page 15 shows an application diagram for
the Si4136. The RF output signal must be AC coupled
to its load through a capacitor.
Gain
00
01
10
11
1
1/2
1/4
1/8
The IFOUT pin must also be AC coupled to its load
through a capacitor. The IF output level is dependent
upon the load. Figure 17 displays the output level
versus load resistance. For resistive loads greater than
500 the output level saturates and the bias currents in
the IF output amplifier are higher than they need to be.
The LPWR bit in the Main Configuration register
In general, a higher phase detector gain will decrease
in-band phase noise and increase the speed of the PLL
18
Rev. 1.41
Si4136/Si4126
(Register 0) can be set to 1 to reduce the bias currents
and therefore reduce the power dissipated by the IF
amplifier. For loads less than 500 LPWR should be
set to 0 to maximize the output level.
450
400
350
300
250
200
150
100
50
LPWR=1
LPWR=0
For IF frequencies greater than 500 MHz, a matching
network is required in order to drive a 50 load. See
Figure 15 below. The value of L
can be
MATCH
determined by Table 9.
Typical values range between 8 nH and 40 nH.
>500 pF
IFOUT
0
0
200
400
600
800
1000
1200
Load Resistance ()
LMATCH
Figure 17. Typical IF Output Voltage vs.
Load Resistance at 550 MHz
50
2.7. Reference Frequency Amplifier
The Si4136 provides a reference frequency amplifier. If
the driving signal has CMOS levels, it can be connected
directly to the XIN pin. Otherwise, the reference
frequency signal should be AC coupled to the XIN pin
through a 560 pF capacitor.
Figure 15. IF Frequencies > 500 MHz
Table 9. LMATCH Values
Frequency
L
MATCH
2.8. Powerdown Modes
500–600 MHz
600–800 MHz
800–1 GHz
40 nH
27 nH
18 nH
Table 10 summarizes the powerdown functionality. The
Si4136 can be powered down by taking the PWDN pin
low or by setting bits in the Powerdown register
(Register 2). When the PWDN pin is low, the Si4136 will
be powered down regardless of the Powerdown register
settings. When the PWDN pin is high, power
management is under control of the Powerdown register
bits.
For frequencies less than 500 MHz, the IF output buffer
can directly drive a 200 resistive load or higher. For
resistive loads greater than 500 (f < 500 MHz) the
LPWR bit can be set to reduce the power consumed by
the IF output buffer. See Figure 16 below.
The IF and RF sections of the Si4136 circuitry can be
individually powered down by setting the Powerdown
register bits PDIB and PDRB low. The reference
frequency amplifier will also be powered up if either the
PDRB and PDIB bits are high. Also, setting the
AUTOPDB bit to 1 in the Main Configuration register
(Register 0) is equivalent to setting both bits in the
Powerdown register to 1.
>500 pF
IFOUT
>200
The serial interface remains available and can be
written in all power-down modes.
Figure 16. IF Frequencies < 500 MHz
2.9. Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting
the AUXSEL bits in the Main Configuration register
(Register 0).
The LDETB signal can be selected by setting the
AUXSEL bits to 011. This signal can be used to indicate
that the IF or RF PLL is about to lose lock due to
excessive ambient temperature drift and should be re-
tuned.
Rev. 1.41
19
Si4136/Si4126
Table 10. Powerdown Configuration
RF
Circuitry
PWDN Pin
AUTOPDB
PDIB
PDRB IF Circuitry
PWDN = 0
x
0
0
0
0
1
x
0
0
1
1
x
x
0
1
0
1
x
OFF
OFF
OFF
ON
OFF
OFF
ON
PWDN = 1
OFF
ON
ON
ON
ON
Note: x = don’t care.
20
Rev. 1.41
Si4136/Si4126
3. Control Registers
Table 11. Register Summary
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
Register Name
Bit
5
Bit
4
Bit
3
Bit Bit
Bit
0
17 16 15 14 13 12 11 10
9
8
7
6
2
1
LPWR
AUTO
PDB
XIN
DIV2
Main
Configuration
AUXSEL
0
1
0
0
0
0
0
0
0
0
IFDIV
0
0
0
0
0
0
0
Phase
Detector
Gain
0
0
0
0
0
0
0
0
0
0
0
0
0
0
K
K
K
P1
PI
P2
PDIB PDRB
2
3
Powerdown
0
0
0
0
0
0
0
0
0
0
RF1 N
Divider
N
RF1
4
RF2 N
Divider
0
N
RF2
5
6
IF N Divider
0
0
0
0
N
IF
RF1 R
Divider
0
0
0
0
0
0
0
0
0
R
RF1
RF2
7
RF2 R
Divider
0
0
0
0
R
8
9
IF R Divider
Reserved
R
IF
.
.
.
15
Reserved
Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior.
Rev. 1.41
21
Si4136/Si4126
Register 0. Main Configuration Address Field = A[3:0] = 0000
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
D5
D4 D3 D2 D1 D0
LPWR
AUTO
PDB
Name
0
0
0
0
AUXSEL
IFDIV
0
0
0
XIN
DIV2
0
0
0
0
Bit
Name
Function
17:14
13:12
Reserved
AUXSEL
Program to zero.
Auxiliary Output Pin Definition.
00 = Reserved.
01 = Force output low.
11 = Lock Detect (LDETB).
11:10
IFDIV
IF Output Divider
00 = IFOUT = IFVCO Frequency
01 = IFOUT= IFVCO Frequency/2
10 = IFOUT = IFVCO Frequency/4
11 = IFOUT = IFVCO Frequency/8
9:7
6
Reserved
XINDIV2
Program to zero.
XIN Divide-By-2 Mode.
0 = XIN not divided by 2.
1 = XIN divided by 2.
5
LPWR
Output Power-Level Settings for IF Synthesizer Circuit.
0 = R
1 = R
500 —normal power mode.
500 —low power mode.
LOAD
LOAD
4
3
Reserved
Program to zero.
AUTOPDB
Auto Powerdown
0 = Software powerdown is controlled by Register 2.
1 = Equivalent to setting all bits in Register 2 = 1.
2:0
Reserved
Program to zero.
22
Rev. 1.41
Si4136/Si4126
Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
0
0
0
0
0
0
0
0
0
0
K
K
K
P1
PI
P2
Bit
17:6
5:4
Name
Reserved
Function
Program to zero.
K
IF Phase Detector Gain Constant.
PI
P2
P1
N Value
<2048
2048–4095
4096–8191
>8191
K
PI
= 00
= 01
= 10
= 11
3:2
1:0
K
K
RF2 Phase Detector Gain Constant.
N Value
<2048
2048–4095
4096–8191
>8191
K
P2
= 00
= 01
= 10
= 11
RF1 Phase Detector Gain Constant.
N Value
K
P1
<4096
= 00
= 01
= 10
= 11
4096–8191
8192–16383
>16383
Rev. 1.41
23
Si4136/Si4126
Register 2. Powerdown Address Field (A[3:0]) = 0010
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
D2
D1
D0
PDIB PDRB
Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
17:2
1
Name
Function
Reserved
PDIB
Program to zero.
Powerdown IF Synthesizer.
0 = IF synthesizer powered down.
1 = IF synthesizer on.
0
PDRB
Powerdown RF Synthesizer.
0 = RF synthesizer powered down.
1 = RF synthesizer on.
Register 3. RF1 N Divider Address Field (A[3:0]) = 0011
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
N
RF1
Bit
Name
Function
17:0
N
N Divider for RF1 Synthesizer.
992.
RF1
N
RF1
Register 4. RF2 N Divider Address Field = A[3:0] = 0100
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
N
RF2
Bit
17
Name
Function
Reserved
Program to zero.
16:0
N
N Divider for RF2 Synthesizer.
RF2
N
240.
RF2
24
Rev. 1.41
Si4136/Si4126
Register 5. IF N Divider Address Field (A[3:0]) = 0101
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
N
IF
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N Divider for IF Synthesizer.
56.
N
IF
N
IF
Register 6. RF1 R Divider Address Field (A[3:0]) = 0110
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
0
0
0
R
RF1
Name
Function
17:13
12:0
Reserved
Program to zero.
R
R Divider for RF1 Synthesizer.
RF1
R
can be any value from 7 to 8189 if K = 00
P1
RF1
8 to 8189 if K = 01
P1
10 to 8189 if K = 10
P1
14 to 8189 if K = 11
P1
Register 7. RF2 R Divider Address Field (A[3:0]) = 0111
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
0
0
0
R
RF2
Bit
Name
Function
17:13
12:0
Reserved
Program to zero.
R
R Divider for RF2 Synthesizer.
RF2
R
can be any value from 7 to 8189 if K = 00
P2
RF2
8 to 8189 if K = 01
P2
10 to 8189 if K = 10
P2
14 to 8189 if K = 11
P2
Rev. 1.41
25
Si4136/Si4126
Register 8. IF R Divider Address Field (A[3:0]) = 1000
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
0
0
0
0
0
R
IF
Bit
Name
Function
17:13
12:0
Reserved
Program to zero.
R
R Divider for IF Synthesizer.
IF
R can be any value from 7 to 8189 if K = 00
IF
P1
8 to 8189 if K = 01
P1
10 to 8189 if K = 10
P1
14 to 8189 if K = 11
P1
26
Rev. 1.41
Si4136/Si4126
4. Pin Descriptions: Si4136-BT/GT
SEN
SCLK
1
24
23
22
21
20
19
18
17
16
15
14
13
VDDI
IFOUT
GND
SDATA
2
GND
3
GND
4
IFLB
NC
5
IFLA
GND
6
GND
NC
7
VDDD
GND
GND
8
GND
9
XIN
GND
10
PWDN
AUXOUT
RFOUT
11
VDDR
12
Pin Number(s) Name
Description
1
2
SCLK
SDATA
GND
Serial clock input
Serial data input
Common ground
3, 4, 6, 8–10,
16, 18, 21
5, 7
11
NC
No connect
RFOUT
VDDR
AUXOUT
PWDN
XIN
Radio frequency (RF) output of the selected RF VCO
Supply voltage for the RF analog circuitry
Auxiliary output
12
13
14
Powerdown input pin
15
Reference frequency amplifier input
Supply voltage for digital circuitry
Pins for inductor connection to IF VCO
Intermediate frequency (IF) output of the IF VCO
Supply voltage for IF analog circuitry
Enable serial port input
17
VDDD
IFLA, IFLB
IFOUT
VDDI
19, 20
22
23
24
SEN
Rev. 1.41
27
Si4136/Si4126
5. Pin Descriptions: Si4136-BM/GM
28 27 26 25 24 23
22
GND
GND
NC
1
2
3
4
5
6
7
21 GND
20 IFLB
19 IFLA
18 GND
17 VDDD
16 GND
15 XIN
GND
GND
NC
GND
GND
8
9
10 11 12 13 14
Pin Number(s)
Name
Description
1, 2, 4, 6, 7–9, 14, GND
16, 18, 21, 22, 28
Common ground
3, 5
10
NC
No connect
RFOUT
VDDR
AUXOUT
PWDN
XIN
Radio frequency (RF) output of the selected RF VCO
Supply voltage for the RF analog circuitry
Auxiliary output
11
12
13
Powerdown input pin
15
Reference frequency amplifier input
Supply voltage for digital circuitry
Pins for inductor connection to IF VCO
Intermediate frequency (IF) output of the IF VCO
Supply voltage for IF analog circuitry
Enable serial port input
17
VDDD
IFLA, IFLB
IFOUT
VDDI
19, 20
23
24
25
SEN
26
SCLK
Serial clock input
27
SDATA
Serial data input
28
Rev. 1.41
Si4136/Si4126
6. Ordering Guide
Ordering Part
Number
Description
Lead-Free/
RoHS Compliant
Temperature
o
Si4136-F-BT
Si4136-F-GT
Si4136-F-BM
Si4136-F-GM
Si4126-F-BM
Si4126-F-GM
2.5 GHz/2.3 GHz/IF OUT
2.5 GHz/2.3 GHz/IF OUT/Lead Free
2.5 GHz/2.3 GHz/IF OUT
–40 to 85 C
o
–40 to 85 C
o
–40 to 85 C
o
2.5 GHz/2.3 GHz/IF OUT/Lead Free
2.3 GHz/IF OUT
–40 to 85 C
o
–40 to 85 C
o
2.3 GHz/IF OUT/Lead Free
–40 to 85 C
7. Si4136 Derivative Devices
The Si4136 performs both IF and dual-band RF frequency synthesis. The Si4126 is a derivative of this device. The
Si4126 features two synthesizers, RF2 and IF; it does not include RF1. The pinouts for the Si4126 and the Si4136
are the same. Unused registers related to RF1 should be programmed to zero.
Rev. 1.41
29
Si4136/Si4126
8. Package Outline: Si4136-BT/GT
Figure 18 illustrates the package details for the Si4136-BT/GT. Table 12 lists the values for the dimensions shown
in the illustration.
E/2
E1
E
L
C
2x
B A
ddd
e
ccc
A
D
C
aaa
C
A
Seating Plane
b
A1
C
24x
M
bbb
C B A
Figure 18. 24-Pin Thin Shrink Small Outline Package (TSSOP)
Table 12. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Nom
—
Max
1.20
0.15
0.30
0.20
7.90
A
A1
b
0.05
0.19
0.09
7.70
—
—
c
—
D
7.80
e
E
0.65 BSC
6.40 BSC
4.40
E1
L
4.30
0.45
0°
4.50
0.75
8°
0.60
—
aaa
bbb
ccc
ddd
0.10
0.10
0.05
0.20
30
Rev. 1.41
Si4136/Si4126
9. Package Outline: Si4136-BM/GM
Figure 19 illustrates the package details for the Si4136-BM/GM. Table 13 lists the values for the dimensions shown
in the illustration.
2x
0.10 C
A
A
D
D/2
0.05 C
A1
M
C A B
b
0.10
A
Pin 1 ID
0.20 R
D2
2x
N
N
0.10 C
B
1
2
3
1
2
3
E/2
E2
E
L
B
e
Seating
Plane
TOP VIEW
C
BOTTOM VIEW
SIDE VIEW
Figure 19. 28-Pin Quad Flat No-Lead (QFN)
Table 13. Package Dimensions
Controlling Dimension: mm
Symbol
Millimeters
Nom
Min
—
Max
0.90
0.05
0.30
A
0.85
A1
0.00
0.18
0.01
b
0.23
D, E
5.00 BSC
2.70
D2, E2
2.55
0.50
2.85
N
e
L
28
0.50 BSC
0.60
0.75
12°
Rev. 1.41
31
Si4136/Si4126
DOCUMENT CHANGE LIST
Revision 1.3 to Revision 1.4
Si4136-BT change to Si4136-BT/GT
Si4136-BM change to Si4136-BM/GM
Revision 1.4 to Revision 1.41
Updated contact information.
32
Rev. 1.41
Si4136/Si4126
NOTES:
Rev. 1.41
33
Si4136/Si4126
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
34
Rev. 1.41
相关型号：
SI4136DY-T1-GE3
Small Signal Field-Effect Transistor, 31A I(D), 20V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, HALOGEN FREE AND ROHS COMPLIANT, SOP-8
VISHAY
SI4160DY-T1-GE3
Small Signal Field-Effect Transistor, 16.8A I(D), 30V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, HALOGEN FREE AND ROHS COMPLIANT, SOP-8
VISHAY
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