SI4355_技术文档

Si4355

EASY-TO-USE, LOW-CURRENT OOK/(G)FSK SUB-GHZ RECEIVER

Features

 Frequency range =

 Max data rate = 500 kbps

 Power supply = 1.8 to 3.6 V

 64 byte FIFO

283–960 MHz

 Receive sensitivity

= –116 dBm

 Auto frequency control (AFC)

 Automatic gain control (AGC)

 Integrated battery voltage sensor

 Modulation

(G)FSK

OOK

 Packet handling including

preamble, sync word detection, and

CRC

 Low RX Current = 10 mA

 Low standby current = 50 nA

 Low BOM

 20-Pin 3x3 mm QFN package

Applications

Pin Assignments

 Remote control

 Remote keyless entry

 Home automation

 Industrial control

 Sensor networks

 Health monitors

 Home security and alarm

 Telemetry

GND

SDN

RXp

RXn

NC

1

20 19 18 17 16 nSEL

15 SDI

 Garage and gate openers

2

3

4

5

6

14 SDO

13 SCLK

Description

12 nIRQ

Silicon Laboratories’ Si4355 is an easy to use, low current, sub-GHz

GND

7

8

9

10 11 GPIO1

®

EZRadio receiver. Covering all major bands, it combines plug-and-play

simplicity with the flexibility needed to handle a wide variety of

applications. The compact 3x3 mm package size combined with a low

external BOM count makes the Si4355 both space efficient and cost

effective. Excellent sensitivity of 116 dBm allows for a longer operating

range, while the low current consumption of 10 mA active and 50 nA

standby, provides for superior battery life. By fully integrating all

components from the antenna to the GPIO or SPI interface to the MCU,

the Si4355 makes realizing this performance in an application easy.

Design simplicity is further exemplified in the Wireless Development Suite

(WDS) user interface module. This configuration module provides

simplified programming options for a broad range of applications in an

easy to use format that results in both a faster and lower risk

development. Like all Silicon Laboratories’ EZRadio devices, the Si4355

is fully compliant with all worldwide regulatory standards, such as FCC,

ETSI, and ARIB.

Patents pending

Rev 1.0 7/12

Si4355

Functional Block Diagram

GPIO3

GPIO2

XIN XOUT

Synthesizer

SDN

25-32MHz XO

Rx Chain

nSEL

SDI

RXp

RXn

PGA

LNA

ADC

Rx Modem

SDO

SCLK

nIRQ

Battery

Voltage

Sensor

Aux ADC

GPIO1

VDD

GPIO0

2

Rev 1.0

Si4355

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2. Typical Applications Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.2. Receiver Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.3. Receiver Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.4. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.6. Battery Voltage and Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4. Configuration Options and User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.1. EZConfig GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.2. Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.3. Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.2. Operating Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.3. Application Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5.4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.5. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6.1. RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6.2. Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

11.1. Si4355 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Rev 1.0

3

Si4355

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Ambient Temperature

Supply Voltage

T

–40

1.8

25

85

C

V

A

V

3.6

DD

I/O Drive Voltage

V

GPIO

1.8

3.6

Table 2. DC Characteristics¹

Parameter

Symbol

Conditions

Min Typ Max Units

Supply Voltage

Range

V

1.8 3.3

3.6

—

V

DD

Power Saving Modes

RC oscillator, main digital regulator, and low power

digital regulator OFF

I

—

30

50

nA

Shutdown

Register values maintained and

RC oscillator/WUT OFF

I

—

Standby

Crystal Oscillator and Main Digital Regulator ON,

all other blocks OFF

I

—

2

—

mA

Ready

I

SPI Active State

RX Tune

1.35

SPI Active

TUNE Mode Current

RX Mode Current

I

—

6.5

10

—

mA

Tune_RX

I

RX

Notes:

1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 9.

2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 9.

4

Rev 1.0

Si4355

Table 3. Synthesizer AC Electrical Characteristics¹

Parameter

Symbol

Conditions

Min

Typ

Max Units

Synthesizer Frequency

Range

F

SYN

283

—

350

525

960

MHz

425

850

—

Synthesizer Frequency

Resolution

F

—

114.4

57.2

38.1

—

Hz

RES-960

RES-525

RES-350

850–960 MHz

425–525 MHz

283–350 MHz

2

t

Measured from exiting Ready mode with

XOSC running to any frequency,

including VCO Calibration

Synthesizer Settling Time

LOCK

—

130

—

µs

Notes:

1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 9.

2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 9.

Table 4. Receiver AC Electrical Characteristics¹

Parameter

RX Frequency

Range

Symbol

Conditions

Min

283

425

850

—

Typ

—

Max Units

F

350

525

960

—

MHz

dBm

RX

—

RX Sensitivity

P

(BER < 0.1%)

–116

RX-_2

(2.4 kbps, GFSK, BT = 0.5,

2

f = 30 kHz) ,114 kHz Rx BW

P

(BER < 0.1%)

—

–108

–103

—

dBm

RX-_40

(40 kbps, GFSK, BT = 0.5,

2

f = 25 kHz) , 114 kHz Rx BW

P

(BER < 0.1%)

RX-_128

(128 kbps, GFSK, BT = 0.5,

2

f = 70 kHz) , 305 kHz Rx BW

P

BER < 0.1%, 1 kbps, 185 kHz Rx BW,

OOK, PN15 data

—

40

–113

–102

—

dBm

kHz

RX-_OOK

BER < 0.1%, 40 kbps, 185 kHz Rx BW,

OOK, PN15 data

2

RX Channel Bandwidth

BW

850

Notes:

1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 9.

2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 9.

Rev 1.0

5

Si4355

Table 4. Receiver AC Electrical Characteristics¹(Continued)

Parameter

Symbol

Conditions

Min

Typ

Max Units

BER Variation vs Power

Level

P

Up to +5 dBm Input Level

—

0

0.1

ppm

RX_RES

2

RSSI Resolution

RES

C/I

—

±0.5

–56

–59

—

dB

RSSI

2

1-Ch Offset Selectivity

2-Ch Offset Selectivity

Desired Ref Signal 3 dB above sensitiv-

ity, BER < 0.1%. Interferer is CW and

desired modulated with

1-CH

2-CH

2

C/I

1.2 kbps F = 5.2 kHz GFSK with

BT = 0.5,

Rx BW = 58 kHz,

channel spacing = 100 kHz

200K

1M

Desired Ref Signal 3 dB above sensitiv-

ity, BER < 0.1% Interferer is CW and

desired modulated with 1.2 kbps

F = 5.2 kHz GFSK with BT = 0.5,

RX BW = 58 kHz

—

–58

–61

–79

—

dB

Blocking 200 kHz–1 MHz

BLOCK

2

Blocking 1 MHz Offset

BLOCK

2

8M

Blocking 8 MHz Offset

2

Im

Rejection at the image frequency.

IF = 468 kHz

—

–40

—

dB

Image Rejection

REJ

2

P

Measured at RX pins

–54

dBm

Spurious Emissions

OB_RX1

Notes:

1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 9.

2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 9.

Table 5. Auxiliary Block Specifications¹

Parameter

Symbol

Conditions

Min

Typ

Max

Units

2

XTAL Range

XTAL-

25

—

32

MHz

RANGE

30 MHz XTAL Start-Up Time

t

Using XTAL and board layout in

reference design. Start-up time

will vary with XTAL type and

board layout

—

250

—

µs

30M

30 MHz XTAL Cap

Resolution

30M

—

70

—

5

fF

RES

3

POR Reset Time

t

ms

POR

Notes:

1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 9.

2. XTAL Range tested in production using an external clock source (similar to using a TCXO).

3. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 9.

6

Rev 1.0

Si4355

Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ)¹

Parameter

Symbol

Conditions

0.1 x V to 0.9 x V ,

DD

Min

Typ

Max

Units

Rise Time

Fall Time

T

—

2.3

—

ns

RISE

DD

C = 10 pF, DRV<1:0>=HH

L

T

0.9 x V to 0.1 x V

—

2

—

ns

FALL

DD

DD,

C = 10 pF, DRV<1:0>=HH

L

Input Capacitance

C

V

2

—

pF

V

IN

Logic High Level Input Voltage

Logic Low Level Input Voltage

Input Current

V

x 0.7

—

IH

DD

V

—

–10

1

—

V

x 0.3

DD

V

IL

I

0<V < V

DD

—

10

µA

mA

V

IN

Input Current If Pullup is Activated

Drive Strength for Output Low

I

V = 0 V

—

INP

IL

I

DRV<1:0> = LL

DRV<1:0> = LH

DRV<1:0> = HL

DRV<1:0> = HH

DRV<1:0> = LL

DRV<1:0> = LH

DRV<1:0> = HL

DRV<1:0> = HH

DRV<1:0> = LL

DRV<1:0> = LH

DRV<1:0> = HL

DRV<1:0> = HH

2.1

1.5

1.0

0.4

4.5

3.3

2.1

0.7

1.9

1.7

1.3

0.6

—

OLL

OLH

OHL

OHH

2

Level

I

Drive Strength for Output High

Level (GPIO1, GPIO2, GPIO3)

I

OLL

OLH

OHL

OHH

2

I

Drive Strength for Output High

Level (GPIO0)

I

OLL

OLH

OHL

OHH

2

I

Logic High Level Output Voltage

Logic Low Level Output Voltage

Notes:

V

I

= 500 µA

V x 0.8

DD

—

OH

OUT

V

I

—

V

x 0.2

DD

V

OL

1. All specifications guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test

Conditions" section in "1.1. Definition of Test Conditions" on page 9.

2. GPIO output current measured at 3.3 VDC VDD with V_OH= 2.7 VDC and V_OL= 0.66 VDC.

Rev 1.0

7

Si4355

Table 7. Thermal Characteristics

Parameter

Thermal Resistance Junction to Ambient

Junction Temperature

Symbol

Test Condition

Value

30

Unit

C/W

C



Still Air

JA

125

T

J

Table 8. Absolute Maximum Ratings

Parameter

Value

–0.3, +3.6

–0.3, V + 0.3

Unit

V

to GND

V

DD

Voltage on Digital Control Inputs

Voltage on Analog Inputs

RX Input Power

DD

–0.3, V + 0.3

V

DD

+10

dBm

C

Operating Ambient Temperature Range T

–40 to +85

–55 to +125

A

Storage Temperature Range T

STG

Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These

are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of

the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability. Caution: ESD sensitive device.

8

Rev 1.0

Si4355

1.1. Definition of Test Conditions

Production Test Conditions:

T = +25 °C

A

V

= +3.3 VDC

DD

Sensitivity measured at 434 MHz using a PN15 modulated input signal and with packet handler mode

enabled.

External reference signal (XIN) = 1.0 V at 30 MHz, centered around 0.8 VDC

PP

Production test schematic (unless noted otherwise)

All RF input and output levels referred to the pins of the Si4355 (not the RF module)

Qualification Test Conditions:

T = –40 to +85 °C (typical = 25 °C)

A

V

= +1.8 to +3.6 VDC (typical = 3.3 VDC)

DD

Using reference design or production test schematic

All RF input and output levels referred to the pins of the Si4355 (not the RF module)

Rev 1.0

9

Si4355

2. Typical Applications Circuit

30 MHz

SDN

GP1

C2

GP2

GP3

GP4

GP5

GND

SDI

1

2

3

15

14

13

SDN

SDO

SCLK

nIRQ

GPIO1

L2

C1

RXp

RXn

NC

L1

Si4355

4

5

12

11

VDD

C3

100 p

C4

C5

100 n

1u

Figure 1. Si4355 Applications Circuit

10

Rev 1.0

Si4355

3. Functional Description

GPIO3

GPIO2

XIN XOUT

Synthesizer

SDN

25-32MHz XO

Rx Chain

nSEL

SDI

RXp

LNA

RXn

PGA

ADC

Rx Modem

SDO

SCLK

nIRQ

Battery

Voltage

Sensor

Aux ADC

GPIO1

VDD

GPIO0

Figure 2. Si4355 Functional Block Diagram

3.1. Overview

The Si4355 is an easy-to-use, size efficient, low current wireless ISM receiver that covers the sub-GHz bands. The

wide operating voltage range of 1.8–3.6 V and low current consumption make the Si4355 an ideal solution for

battery powered applications. The Si4355 uses a single-conversion mixer to downconvert the FSK/GFSK or OOK

modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is

converted to the digital domain by a high performance  ADC allowing filtering, demodulation, slicing, and packet

handling to be performed in the built-in DSP, increasing the receiver’s performance and flexibility versus analog

based architectures. The demodulated signal is output to the system MCU through a programmable GPIO or via

the standard SPI bus by reading the 64-byte Rx FIFO.

A high precision local oscillator (LO) is used and is generated by an integrated VCO and  Fractional-N PLL

synthesizer. The Si4355 operates in the frequency bands of 283–350, 425–525, and 850–960 MHz.

Additional system features, such as 64 byte Rx FIFO, preamble detection, sync word detector and CRC, reduce

overall current consumption, and allow for the use of lower-cost system MCUs. Power-on-reset (POR), and GPIOs

further reduce overall system cost and size. The Si4355 is designed to work with an MCU, crystal, and a few

passives to create a very compact and low-cost system.

3.2. Receiver Chain

The internal low-noise amplifier (LNA) is designed to be a wide-band LNA that can be matched with three external

discrete components to cover any common range of frequencies in the sub-GHz band. The LNA has extremely low

noise to suppress the noise of the following stages and achieve optimal sensitivity; so, no external gain or front-end

modules are necessary. The LNA has gain control, which is controlled by the internal automatic gain control (AGC)

algorithm. The LNA is followed by an I-Q mixer, filter, programmable gain amplifier (PGA), and ADC. The I-Q

mixers downconvert the signal to an intermediate frequency. The PGA then boosts the gain to be within dynamic

range of the ADC. The ADC rejects out-of-band blockers and converts the signal to the digital domain where

filtering, demodulation, and processing is performed. Peak detectors are integrated at the output of the LNA and

PGA for use in the AGC algorithm.

Rev 1.0

11

Si4355

3.3. Receiver Modem

Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the

digital domain, which allows for flexibility in optimizing the device for particular applications. The digital modem

performs the following functions:

Channel selection filter

Preamble detection

Invalid preamble detection

RX demodulation

Automatic gain control (AGC)

Automatic frequency compensation (AFC)

Radio signal strength indicator (RSSI)

Cyclic redundancy check (CRC)

The digital channel filter and demodulator are optimized for ultra-low-power consumption and are highly

configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to

support bandwidths ranging from 850 kHz down to 40 kHz. A large variety of data rates are supported ranging from

500 kbps up to 500 kbps. The configurable preamble detector is used with the synchronous demodulator to

improve the reliability of the sync-word detection. Preamble detection can be skipped using only sync detection,

which is a valuable feature of the asynchronous demodulator when very short preambles are used. The received

signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The

resolution of the RSSI is 0.5 dB. This high-resolution RSSI enables accurate channel power measurements for

clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality. A wireless

communication channel can be corrupted by noise and interference, so it is important to know if the received data

is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet.

A CRC is computed and appended at the end of each transmitted packet and verified by the Si4355 receiver to

confirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system

microcontroller allowing for a simpler and cheaper microcontroller. The default bandwidth-time product (BT) is 0.5

for all programmed data rates.

3.3.1. Received Signal Strength Indicator

The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the

receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement of the

desired or undesired in-band signal power. The Si4355 uses a fast response register to read RSSI and so can

complete the read in 16 SPI clock cycles with no requirement to wait for CTS. The RSSI value is read using the

RSSI_READ command. The RSSI value reported by this API command can be converted to dBm using the

following equation:

RSSI_value

--------------------------------

– RSSI_cal

RSSI_dBm

=

2

RSSIcal in this formula is dependent on the matching network, modem settings, and external LNA gain (if present).

It can be obtained through lab measurements using a signal generator connected to the antenna input to provide a

known RSSI level. Without an external LNA, the RSSIcal will be approximately 130.

3.4. Synthesizer

The Si4355 includes an integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating over the

bands from 283–350, 425–525, and 850–960 MHz. The synthesizer has many advantages; it provides flexibility

in choosing data rate, deviation, channel frequency, and channel spacing. The frequency resolution is

19

18

(2/3)Freq_xo/(2 ) for 283–350 MHz, Freq_xo/(2 ) for 425–525 MHz, and Freq_xo/(2 ) for 850–960 MHz. The

nominal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz may be used. The

modem configuration calculator in WDS will automatically account for the XTAL frequency being used. The PLL

utilizes a differential LC VCO with integrated on-chip inductors. The output of the VCO is followed by a configurable

divider, which will divide the signal down to the desired output frequency band.

12

Rev 1.0

Si4355

3.4.1. Synthesizer Frequency Control

The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator will

automatically provide these settings, but the synthesizer equation is shown below for convenience. Initial

frequency settings are configured in the EZConfig setup and can also be modified using the API commands:

FREQ_CONTROL_INTE,

FREQ_CONTROL_FRAC0.

FREQ_CONTROL_FRAC2,

FREQ_CONTROL_FRAC1,

and

fc_frac

2¹⁹

4  freq_xo

------------------------------

Hz







------------------

RF_channel = fc_inte +





outdiv

Note: The fc_frac/2¹⁹value in the above formula must be a number between 1 and 2. The LSB of fc_frac must be "1".

Table 9. Output Divider (Outdiv) Values

Outdiv

Lower (MHz)

Upper (MHz)

12

8

284

425

850

350

525

960

4

3.4.1.1. EZ Frequency Programming

EZ frequency programming allows for easily changing radio frequency using a single API command. The base

frequency is first set using the EZConfig setup. This base frequency will correspond to channel 0. Next, a channel

step size is also programmed within the EZConfig setup. The resulting frequency will be:

RF Frequency = Base Frequency + Channel  Step Size

The second argument of the START_RX is CHANNEL, which sets the channel number for EZ frequency

programming. For example, if the channel step size is set to 1 MHz, the base frequency is set to 900 MHz, and a

CHANNEL number of 5 is programmed during the START_RX command, the resulting frequency will be 905 MHz.

If no CHANNEL argument is written as part of the START_RX command, it will default to the previous value. The

initial value of CHANNEL is 0 and so will be set to the base frequency if this argument is never used.

3.5. Crystal Oscillator

The Si4355 includes an integrated crystal oscillator with a fast start-up time of less than 250 µs. The design is

differential with the required crystal load capacitance integrated on-chip to minimize the number of external

components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is

designed to handle any XTAL from 25 to 32 MHz, set in the EZConfig setup. The crystal load capacitance can be

digitally programmed to accommodate crystals with various load capacitance requirements and to adjust the

frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the

GLOBAL_XO_TUNE API property. The total internal capacitance is 11 pF and is adjustable in 127 steps (70

fF/step). The crystal frequency adjustment can be used to compensate for crystal production tolerances. The

frequency offset characteristics of the capacitor bank are demonstrated in Figure 3.

Rev 1.0

13

Si4355

Figure 3. Capacitor Bank Frequency Offset Characteristics

3.6. Battery Voltage and Auxiliary ADC

The Si4355 contains an integrated auxiliary 11-bit ADC used for the internal battery voltage detector or an external

component via GPIO. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the

input voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first

sending the GET_ADC_READING command and enabling the desired inputs. When the conversion is finished and

all the data is ready, CTS will go high, and the data can be read out. Refer to application note, “AN691: EZRadio

API Guide”, for details on this command and the formulas needed to interpret the results.

14

Rev 1.0

Si4355

4. Configuration Options and User Interface

4.1. EZConfig GUI

The EZConfig Setup GUI is part of the Wireless Development Suite (WDS) program. This setup interface provides

an easy path for quickly selecting and loading the desired configuration for the device. The EZConfig Setup allows

for three different methods for device setup. One option is the configuration wizard, which easily identifies the

optimal setup based on a few questions about the application. Another option is the configuration table, which

provides a list of preloaded, common configurations. Lastly, EZConfig allows for custom configuration to be loaded

using the radio configuration application. After the desired configuration is selected, the EZConfig setup

automatically creates the configuration array that will be passed to the chip for setup. The program then gives the

option to load a sample project with the selected configuration onto the evaluation board, or launch IDE with the

new configuration array preloaded into the user program. For more complete information on EZConfig usage, refer

to the application note, “AN692: Si4x55 Programming Guide & Sample Codes”.

Open EZConfig

Setup in WDS

Input Method

Fast

Guided

Manual

Run

Configuration

Wizard

Select

Configuration

from Table

Create Custom

Configuration

Select Freq,

Power, and

Packet Handler

Features

Select Action

Write New Code

Lab Measurement

Run Sample Code

Add new

Open IDE with

configuration

array preloaded

Load

Configuration on

Device

configuration to

sample code and

load on board

Figure 4. Device Configuration Steps

Rev 1.0

15

Si4355

4.1.1. Configuration Wizard

The configuration wizard is available to easily identify the optimal device setup based on a few questions about the

desired application. Within this wizard, the user is able to define their system requirements and can see some

potential trade-offs for various settings. The wizard then provides a recommended configuration that is optimized

for the given application. This configuration can be further modified if needed to provide the desired setup.

4.1.2. Configuration Table

The configuration table is a list of predefined configurations that have been optimized for performance and

validated by Silicon Labs. These configurations are listed for many common application conditions and so most

users will be able to find the configuration they need in this table. These configurations are set to provide optimized

performance for a given application and can be implemented with low design risk. Once the list item is selected,

the specific frequency, and packet handler features can also be applied.

4.1.3. Radio Configuration Application

The Radio Configuration Application provides an intuitive interface for directly modifying the device configuration.

Using this control panel, the device parameters such as modulation type, data rate, and frequency deviation, can

be set. The EZConfig Setup then takes these parameters and automatically determines the appropriate device

register settings. This method allows the user to have complete flexibility in determining the configuration of the

device without the need to translate the system requirements into device specific properties. As with the other

EZConfig methods, the resulting configuration array is automatically generated and available for use in the user's

program.

4.2. Configuration Options

4.2.1. Frequency Band

The Si4355 can operate in the 283–350 MHz, 425–525 MHz, or 850–960 MHz bands. One of these three bands

will be selected during the configuration setup and then the specific receive frequency that will be used within this

band can be selected.

4.2.2. Modulation Type

The Si4355 can operate using On/Off Keying (OOK), Frequency Shift Keying (FSK), or Gaussian Frequency Shift

Keying (GFSK). OOK modulation is the most basic modulation type available. It is the most power efficient method

and does not require as high oscillator accuracy as FSK. FSK provides the best sensitivity and, therefore, range

performance but generally requires more precision from the oscillator used. GFSK is a version of FSK where the

signal is passed through a Gaussian filter, limiting its spectral width. As a result, the out of band components of the

signal are reduced.

The Si4355 also has an option for Manchester coding. This method provides a state transition at each bit and so

allows for more reliable clock recovery.

Clock

Data

1

0

1

0

1

Manchester

Figure 5. Manchester Code Example

16

Rev 1.0

Si4355

4.2.3. Frequency Deviation

If FSK or GFSK modulation is selected, then a frequency deviation will also need to be selected. The frequency

deviation is the maximum instantaneous difference between the FM modulated frequency and the nominal carrier

frequency. The Si4455 can operate across a wide range of data rates and frequency deviations. If a frequency

deviation needs to be selected, the following guideline might be helpful to build a robust link. A proper frequency

deviation is linked to the frequency error between transmitter and receiver. The frequency error can be calculated

using the crystal tolerance parameters and the RF operating frequency: (ppm_tx+ppm_rx)*Frf/1E-6. For frequency

errors below 50 kHz, the deviation can be about the same as the frequency error. For frequency errors exceeding

50 kHz the frequency deviation can be set to about 0.75 times the frequency error. It is advised to position the

modulation index (=2*freq_dev/data_rate) into a range between 1 and 100 for Packet Handling mode and 2 to 100

for direct mode (non-standard preamble). For example, when in Packet Handling mode and the frequency error is

smaller than data_rate/2, the frequency deviation is set to about data_rate/2. When the frequency error exceeds

100xdata_rate/2, the frequency deviation is preferred to be set to 100xdata_rate/2.

4.2.4. Data Rate

The Si4355 can be set to communicate at between 1 to 500 kbps in (G)FSK mode and between 0.5 to 120 kbps in

OOK mode. Higher data rates allow for faster data transfer while lower data rates result in improved sensitivity and

range performance.

4.2.5. Channel Bandwidth

The channel bandwidth sets the bandwidth for the receiver. Since the receiver bandwidth is directly proportional to

the noise allowed in the system, this will normally be set as low as possible. The specific channel bandwidth used

will usually be determined based upon the precision of the oscillator and the frequency deviation of the transmitted

signal. The EZConfig setup can provide the recommended channel bandwidth based upon these two parameters

to help optimize the system.

4.2.6. Preamble Length

A preamble is a defined simple bit sequence used to notify the receiver that a data transmission is imminent. The

length of this preamble will normally be set as short as possible to minimize power while still insuring that it will be

reliably detected given the receiver characteristics, such as duty cycling and packet error rate performance. The

Si4355 allows the preamble length to be set between 3 to 255 bytes in length with a default length of 4 bytes. The

preamble pattern for the Si4355 will always be 55h with a first bit of "0" if the packet handler capability is used.

4.2.7. Sync Word Length and Pattern

The sync word follows the preamble in the packet structure and is used to identify the start of the payload data and

to synchronize the receiver to the transmitted bit stream. The Si4355 allows for sync word lengths of 1 to 4 bytes

and the specific pattern can be set within the EZConfig program. The default is a 2 byte length 2d d4 pattern.

4.2.8. Cyclic Redundancy Check (CRC)

CRC is used to verify that no errors have occurred during transmission and the received packet has exactly the

same data as it did when transmitted. If this function is enabled in the Si4355, the last byte of transmitted data must

include the CRC generated by the transmitter. The Si4355 then performs a CRC calculation on the received packet

and compares that to the transmitted CRC. If these two values are the same, the Si4355 will set an interrupt

indicating a valid packet has been received and is waiting in the Rx FIFO. If these two CRC values differ, the

Si4355 will flag an interrupt indicating that a packet error occurred. The Si4355 uses CRC(16)-IBM: x16+x15+x2+1

with a seed of 0xFFFF.

Rev 1.0

17

Si4355

4.3. Configuration Commands

The EZConfig Setup provides all of the code needed for basic radio configuration. Once the setup is completed in

the GUI, the program outputs configuration array(s) that can be sent to the radio via the SPI interface. No

additional setup coding is needed. The configuration command process is shown in Figure 6. The

EZCONFIG_SETUP passes the configuration array to the device and the EZCONFIG_CHECK insures that all of

the configuration data was written correctly. For more information on the setup commands, refer to application

note, “AN691: EZRadio API Guide”.

EZCONFIG_SETUP

NOP

EZCONFIG_SETUP

EZCONFIG_CHECK

Figure 6. Configuration Command Flowchart

18

Rev 1.0

Si4355

5. Controller Interface

5.1. Serial Peripheral Interface (SPI)

The Si4355 communicates with the host MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI,

SDO, and nSEL. The SPI interface is designed to operate at a maximum of 10 MHz. The SPI timing parameters

are listed in Table 10. The host MCU writes data over the SDI pin and can read data from the device on the SDO

output pin. Figure 7 shows an SPI write command. The nSEL pin should go low to initiate the SPI command. The

first byte of SDI data will be one of the API commands followed by n bytes of parameter data, which will be variable

depending on the specific command. The rising edges of SCLK should be aligned with the center of the SDI data.

Table 10. Serial Interface Timing Parameters

Symbol

Parameter

Min (ns)

Diagram

Clock high time

t

40

20

CH

Clock low time

Data setup time

Data hold time

t

CL

DS

DH

DD

SCLK

t

t_SS

t_CL

t_CH

t_DSt_DH

t_DD

t_SH

t_DE

t

Output data delay

time

SDN

SDO

Output enable time

Output disable time

Select setup time

Select hold time

t

20

50

20

50

80

EN

DE

t_EN

t_SW

t

SS

SH

nSEL

t

Select high period

t

SW

nSEL

SDO

SDI

API Command

ParamByte 0

ParamByte n

SCLK

Figure 7. SPI Write Command

The Si4355 contains an internal MCU which controls all the internal functions of the radio. For SPI read

commands, a typical communication flow of checking clear-to-send (CTS) is used to make sure the internal MCU

has executed the command and prepared the data to be output over the SDO pin. Figure 8 demonstrates the

general flow of an SPI read command. Once the CTS value reads FFh, the read data is ready to be clocked out to

the host MCU. The typical time for a valid FFh CTS reading is 20 µs. Figure 9 demonstrates the remaining read

cycle after CTS is set to FFh. The internal MCU will clock out the SDO data on the negative edge so the host MCU

should process the SDO data on the rising edge of SCLK.

Rev 1.0

19

Si4355

0xFF

Retrieve

Response

Send Command

Read CTS

CTS Value

0x00

nSEL

SDO

SDI

CTS

ReadCmdBuff

SCLK

Figure 8. SPI Read Command—Check CTS Value

nSEL

SDO

SDI

Response Byte 0

Response Byte n

SCLK

Figure 9. SPI Read Command—Clock Out Read Data

20

Rev 1.0

Si4355

5.2. Operating Modes and Timing

The primary states of the Si4355 are shown in Figure 10. The shutdown state completely shuts down the radio,

minimizing current consumption and is controlled using the SDN (pin 2). All other states are controlled using the

API commands START_RX and CHANGE_STATE. Table 11 shows each of the operating modes with the time

required to reach either RX state as well as the current consumption of each state. The times in Table 11 are

measured from the rising edge of nSEL until the chip is in the desired state. This information is included for

reference only since an automatic sequencer moves the chip from one state to another and so it is not necessary

to manually step through each state. Most applications will utilize the standby mode since this provides the fastest

transition response time, maintains all register values, and results in nearly the same current consumption as

shutdown.

Standby

Shutdown

SPI Active

Config

Ready

Rx Tune

Rx

Figure 10. State Machine Diagram

Table 11. Operating State Response Time and Current Consumption

State / Mode

Shutdown

Standby

SPI Active

Ready

Response Time to Rx Current in State / Mode

30 ms

460 μs

330 μs

130 μs

75 μs

30 nA

50 nA

1.35 mA

1.8 mA

6.5 mA

10 mA

Rx Tune

Rx

150 μs

Rev 1.0

21

Si4355

5.2.1. Shutdown State

The shutdown state is the lowest current consumption state of the device and is entered by driving SDN (Pin 2)

high. In this state, all register contents are lost and there is no SPI access. To exit this mode, drive SDN low. The

device will then initiate a power on reset (POR) along with internal calibrations. Once this POR period is complete,

the POWER_UP command is required to initialize the radio and the configuration can then be loaded into the

device. The SDN pin must be held high for at least 10 µs before driving it low again to insure the POR can be

executed correctly. The shutdown state can be used to fully reset the part.

5.2.2. Standby State

The standby state has similar current consumption to the shutdown state but retains all register values, allowing for

a much faster response time. Because of these benefits, most applications will want to use standby mode rather

than shutdown. The standby state is entered by using the CHANGE_STATE API command. While in this state, the

SPI is accessible but any SPI event will automatically transition the chip to the SPI active state. After the SPI event,

the host will need to re-command the device to standby mode.

5.2.3. SPI Active State

The SPI active state enables the device to process any SPI events, such as API commands. In this state, the SPI

and boot up oscillator are enabled. The SPI active state is entered by using the CHANGE_STATE command or

automatically through an SPI event while in standby mode. If the SPI active state was entered automatically from

standby mode, a CHANGE_STATE command will be needed to return the device to standby mode.

5.2.4. Ready State

Ready state is designed to give a fast transition time to RX state with minimized current consumption. In this mode

the crystal oscillator remains enabled to minimize the transition time. Ready state can be entered using the

CHANGE_STATE command.

5.2.5. Power On Reset

A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this

process, VDD must ramp within 1ms and must remain applied to the device for at least 10ms. If VDD is removed,

then it must stay below 0.15V for at least 10ms before being applied again. Please see Figure x and Table x for

details.

Figure 11. POR Timing Diagram

22

Rev 1.0

Si4355

Table 12. POR Timing

Variable

Description

Min

Typ

Max Units

High time for VDD to fully settle POR circuit.

Low time for VDD to enable POR.

Voltage for successful POR.

t

10

ms

V

PORH

t

10

90%*Vdd

0

PORL

V

RRH

Starting Voltage for successful POR.

Slew rate of VDD for successful POR.

V

150

1

mV

ms

RRL

t

SR

5.2.6. RX State

The RX state is used whenever the device is required to receive data. It is entered using either the START_RX or

CHANGE_STATE commands. With the START_RX command, the next state can be defined to insure optimal

timing. When either command is sent to enter RX state, an internal sequencer automatically takes care of all

actions required to move between states with no additional user commands needed. The sequencer controlled

events can include enable the digital and analog LDOs, start up the crystal oscillator, enable PLL, calibrate VCO,

enable receiver circuits, and enable receive mode. The device will also automatically set up all receiver features

such as packet handling based upon the initial configuration of the device.

Rev 1.0

23

Si4355

5.3. Application Programming Interface

An Application Programming Interface (API) is embedded inside the device and is used for communications with

the host MCU. API commands are used to configure the device, control the chip during operation, and retrieve its

status. Available commands are shown in Table 13. The complete list of commands and their descriptions are

provided in application note, “AN691: EZRadio API Guide”.

Table 13. API Commands

#

Name

Description

NOP

No operation command

0x00

0x01

0x02

0x10

0x11

0x12

0x13

0x14

0x15

0x19

0x20

0x32

0x33

0x34

0x44

0x50

0x51

0x53

0x57

0x66

0x77

PART_INFO

POWER_UP

FUNC_INFO

Reports basic information about the device

Boot options and crystal frequency offset

Returns the function revision information of the device

Sets the value of a property

SET_PROPERTY

GET_PROPERTY

Retrieves the value of a property

GPIO_PIN_CFG

Configures the GPIO pins

GET_ADC_READING

FIFO_INFO

Performs and retrieves ADC conversion results

Provides access to the RX FIFO counts and reset

Validates the EZConfig array was written correctly

Returns the interrupt status byte

EZCONFIG_CHECK

GET_INT_STATUS

START_RX

Switches to RX state

REQUEST_DEVICE_STATE

CHANGE_STATE

Request current device state

Changes to a specified device state / mode

Used to read CTS and the command response

CHIP_STATUS_INT_PEND fast response register

MODEM_INT_PEND fast response register

PH_INT_PEND fast response register

RSSI fast response register

READ_CMD_BUFF

CHIP_STATUS_INT_PEND_READ

MODEM_INT_PEND_READ

PH_INT_PEND_READ

RSSI_READ

EZCONFIG_SETUP

READ_RX_FIFO

Configures device using EZConfig array

Reads the RX FIFO

24

Rev 1.0

Si4355

5.4. Interrupts

The Si4355 is capable of generating an interrupt signal when certain events occur. The chip notifies the

microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal

will be generated when any one (or more) of the interrupt events occur. The nIRQ pin will remain low until the

microcontroller reads the Interrupt Status Registers. The nIRQ output signal will then be reset until the next change

in status is detected.

The interrupt sources are grouped into three categories: packet handler, chip status, and modem. The individual

interrupts in these groups can be enabled/disabled in the interrupt property registers, 0x0101, 0x0102, and 0x0103.

An interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well

as the individual interrupts in API property 0x0100.

Once an interrupt event occurs and the nIRQ pin is low the interrupts are read and cleared using the

GET_INT_STATUS command. By default all interrupts will be cleared once read. The instantaneous status of a

specific function may be read if the specific interrupt is enabled or disabled. The status results are provided after

the interrupts and can be read with the same commands as the interrupts. The status bits will give the current state

of the function whether the interrupt is enabled or not.

5.5. GPIO

Four General Purpose IO (GPIO) pins are available for use in the application. The GPIOs are configured using the

GPIO_PIN_CFG command. GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins

2 and 3 have more susceptibility to generating spurious components in the synthesizer than pins 0 and 1. The drive

strength of the GPIOs can be adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command. By

default, the drive strength is set to the minimum. The default configuration and the state of the GPIO during

shutdown are shown in Table 14. For a complete list of the GPIO options, please refer to the API guide application

note, “AN691: EZRadio API Guide”.

Table 14. GPIOs

SDN State

POR Default

POR

GPIO0

GPIO1

GPIO2

GPIO3

nIRQ

0

CTS

POR

Resistive V pull-up

nIRQ

SDO

DD

SDO

Resistive V pull-up

DD

SDI

High Z

SDI

Rev 1.0

25

Si4355

6. Data Handling and Packet Handler

6.1. RX FIFO

A 64-byte RX FIFO is integrated into the chip. Reading from command register 77h reads data from this RX FIFO.

6.2. Packet Handler

The Si4355 includes integrated packet handler features such as preamble and sync word detection as well as CRC

calculation. This allows the chip to qualify and synchronize with legitimate transmissions independent of the

microcontroller. These features can be enabled using the EZConfig setup. In this setup, the preamble and sync

word length can be modified and the sync word pattern can be selected. The general packet structure is shown in

Figure 12.

There is also the option within the EZConfig setup to select a variable packet length. With this setting, the receiver

is not required to know the packet length ahead of time. The transmitter sends the length of the packet immediately

after the sync word. The packet structure for variable length packets is shown in Figure 13.

Preamble

Sync Word

1 – 4 Bytes

Data

CRC

0 – 255 Bytes

1 – 64 Bytes

2 Bytes

Figure 12. Packet Structure for Fixed Packet Length

Preamble

Sync Word

1 – 4 Bytes

Length

1 Byte

Data

CRC

0 – 255 Bytes

1 – 64 Bytes

2 Bytes

Figure 13. Packet Structure for Variable Packet Length

26

Rev 1.0

Si4355

7. Pin Descriptions

GND

1

2

3

4

5

6

20 19 18 17 16 nSEL

15 SDI

SDN

RXp

RXn

NC

14 SDO

13 SCLK

12 nIRQ

GND

7

8

9

10 11 GPIO1

Pin Name

I/O

Description

Ground

1

GND

I

Shutdown (0 – V V) – SDN = 1, part will be in shutdown mode and contents

of all registers are lost. SDN = 0, all other modes.

DD

2

SDN

Differential RF receiver input pin

3

4

RXp

RXn

NC

I

Differential RF receiver input pin

No Connect

5

—

Ground

6

GND

Supply voltage

7

V

DD

Supply voltage

8

Ground

9

GND

I/O

General Purpose Digital I/O

10

11

GPIO0

GPIO1

I/O

Interrupt Status Output – nIRQ = 0, interrupt event has occurred. Read interrupt

status for event details.

12

13

nIRQ

O

I

Serial Clock Input (0 – V V)—Provides serial data clock for 4-line serial data

DD

SCLK

bus.

Serial Data Output (0 – V V)— Provides serial data readback function of

internal control registers.

DD

14

15

SDO

SDI

O

I

Serial Data Input (0 – V V)—Serial data stream input for 4-line serial data bus

DD

Rev 1.0

27

Si4355

Pin Name

I/O

Description

Serial Interface Select Input (0 – V V) – Provides select/enable function for

4-line serial data bus

DD

16

nSEL

I

Crystal Oscillator Output

17

18

19

20

XOUT

XIN

O

I

Crystal Oscillator Input—No DC bias required, but if used, should be set to 7 V.

General Purpose Digital I/O

GPIO2

GPIO3

I/O

General Purpose Digital I/O

28

Rev 1.0

Si4355

8. Ordering Information

*

Description

Package Type

Operating

Temperature

Part Number

Si4355-B1A-FM

EZRadio Receiver

3x3 QFN-20

Pb-free

–40 to 85 °C

*Note: Add an “R” at the end of the device part number to denote tape and reel option.

Rev 1.0

29

Si4355

9. Package Outline

Figure 14. 20-pin QFN Package

30

Rev 1.0

Si4355

Table 15. Package Diagram Dimensions

Dimension

Min

0.80

0.00

Nom

0.85

Max

0.90

0.05

A

A1

A3

b

0.02

0.20 REF

0.25

0.18

0.25

0.30

0.35

c

0.30

D

3.00 BSC.

1.70

D2

e

1.55

1.85

0.50 BSC.

3.00 BSC.

1.70

E

E2

f

1.55

0.30

1.85

0.50

2.40 BSC.

0.40

L

aaa

bbb

ccc

ddd

eee

fff

0.15

0.10

0.05

0.08

0.10

Note: All dimensions shown are in millimeters (mm) unless otherwise noted.

Rev 1.0

31

Si4355

10. PCB Land Pattern

Figure 15. 20-pin QFN PCB Land Pattern

Table 16. PCB Land Pattern Dimensions

Dimension

C1

Min

Max

3.00

C2

E

0.50 REF

X1

X2

Y1

Y2

Y3

f

0.25

1.65

0.85

1.65

0.37

0.35

1.75

0.95

1.75

0.47

2.40 REF

c

0.25

0.35

Note: : All dimensions shown are in millimeters (mm) unless otherwise noted.

32

Rev 1.0

Si4355

11. Top Marking

11.1. Si4355 Top Marking

Figure 16. Si4355 Top Marking

11.2. Top Marking Explanation

Mark Method:

Laser

Line 1 Marking:

Part Number

4355A

Firmware Revision

Die Revision

Line 2 Marking:

Line 3 Marking:

Internal tracking number

TTTT = Trace Code

Circle = 0.5 mm Diameter

(Bottom-Left Justified)

Y = Year

WW = Workweek

Assigned by the Assembly House. Corresponds to the last

significant digit of the year and work week of the mold date.

Rev 1.0

33

Si4355

CONTACT INFORMATION

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Rev 1.0


型号：	SI4355
厂家：	SILICON
描述：	EASY-TO-USE, LOW-CURRENT OOK/(G)FSK SUB-GHZ RECEIVER 易于使用，低电流OOK / （ G） FSK的sub-GHz接收器
文件：	总34页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI4355 [SILICON]

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