SI4704 [SILICON]
Worldwide FM band support (64-108 MHz) integrated antenna support EN55020 compliant; 在全球FM频段支持（ 64-108 MHz）的集成天线的支持EN55020标准
| 型号： | SI4704 |
| 厂家： | 
SILICON |
| 描述： | Worldwide FM band support (64-108 MHz) integrated antenna support EN55020 compliant |
| 文件： | 总36页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4704/05-C40
BROADCAST FM RADIO RECEIVER FOR CONSUMER
ELECTRONICS
Features
Worldwide FM band support
(64–108 MHz)
Programmable reference clock
Volume control
Integrated antenna support
EN55020 compliant
Adjustable soft mute control
RDS/RBDS processor (Si4705)
Optional digital audio out (Si4705)
2-wire and 3-wire control interface
Integrated LDO regulator
Signal quality measurements
2.7 to 5.5 V supply voltage
3x3 mm 20-pin QFN package
RoHS compliant
Excellent real-world performance
Freq synthesizer with integrated VCO
Advanced FM seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Minimal BOM
Ordering Information:
See page 28.
Programmable de-emphasis
Pin Assignments
Applications
Si4704/05-GM (Top View)
Table and portable radios
Stereos
Mini/micro systems
CD/DVD players
Boom boxes
Modules
Clock radios
Mini HiFi
Entertainment systems
20 19 18 17
NC
FMI
1
16
2
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
Description
RFGND
LPI
3
4
5
GND
PAD
The Si4704/05 integrates all functions required for an advanced broadcast FM
radio receiver, from antenna input to stereo audio output.
RST
6
7
8
9
10
Functional Block Diagram
FM Antenna
Si4704/05
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both
foreign and domestic: 7,127,217;
ADC
ADC
DAC
FMI
LOUT
ROUT
LNA
AGC
PGA
DSP
RFGND
DAC
7,272,373;
7,355,476;
7,272,375;
7,426,376;
7,321,324;
7,471,940;
GPO
LPI
0/90
7,339,503; 7,339,504.
DCLK
DOUT
DFS
32.768 kHz
2.7–5.5 V
RDS
(Si4705)
RSSI
RCLK
VDD
AFC
REG
CONTROL
INTERFACE
XTAL
OSC
Rev. 1.0 12/09
Copyright © 2009 by Silicon Laboratories
Si4704/05-C40
Si4704/05-C40
2
Rev. 1.0
Si4704/05-C40
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2. Application Schematics and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.4. Digital Audio Interface (Si4705 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.6. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.7. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.9. RDS/RBDS Processor (Si4705 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.10. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.11. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.12. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.13. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.14. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.15. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.16. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Pin Descriptions: Si4704/05-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8.1. Si4704 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8.2. Si4705 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
9. Package Outline: Si4704/05-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
10. PCB Land Pattern: Si4704/05-C40-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.0
3
Si4704/05-C40
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Test Condition
Min
2.7
Typ
—
Max
5.5
3.6
—
Unit
V
V
DD
Interface Supply Voltage
V
1.85
10
—
V
IO
Digital Power Supply Powerup
Rise Time
V
—
µs
DRISE
Interface Power Supply Powerup
Rise Time
V
10
—
—
µs
IORISE
Ambient Temperature
T
–20
25
85
C
A
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD= 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
VDD
Interface Supply Voltage
V
V
IO
3
Input Current
I
mA
V
IN
3
Input Voltage
V
T
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
–40 to 95
–55 to 150
0.4
C
C
OP
T
STG
4
RF Input Level
V
PK
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended
operating conditions for extended periods may affect device reliability.
2. The Si4704/05 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should be done only at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pin, FMI.
4
Rev. 1.0
Si4704/05-C40
Table 3. DC Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Receiver to Line Output
1
Supply Current
I
I
I
—
—
—
19.2
19.9
19.2
22
23
23
mA
mA
mA
FM
FM
FM
2
Supply Current
Low SNR level
1
RDS Supply Current
Supplies and Interface
Interface Supply Current
I
—
—
320
10
1
600
20
µA
µA
µA
V
IO
V
V
Powerdown Current
Powerdown Current
I
DDPD
DD
IO
I
SCLK, RCLK inactive
—
10
IOPD
3
High Level Input Voltage
V
0.7 x V
–0.3
–10
—
—
—
—
V
+ 0.3
IO
IH
IO
3
Low Level Input Voltage
V
0.3 x V
10
V
IL
IO
3
High Level Input Current
I
V
= V = 3.6 V
µA
µA
IH
IN
IO
3
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V
= 3.6 V
IO
4
High Level Output Voltage
V
I
= 500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
OUT
IO
4
Low Level Output Voltage
V
I
= –500 µA
0.2 x V
OL
IO
Notes:
1. Guaranteed by characterization.
2. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4704/05-C40
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is high
impedance, then minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull
GPO1 high and GPO2 low.
tHRST
tSRST
70%
30%
RST
70%
30%
GPO1
70%
30%
GPO2/
INT
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.0
Si4704/05-C40
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold
0.6
—
—
µs
HD:STA
(START)
SDIO Input to SCLK Setup
t
t
100
0
—
—
—
—
900
—
ns
ns
µs
SU:DAT
4, 5
SDIO Input to SCLK Hold
HD:DAT
SU:STO
SCLK Input to SDIO Setup
t
0.6
(STOP)
STOP to START Time
SDIO Output Fall Time
t
1.3
—
—
—
µs
ns
BUF
t
250
f:OUT
Cb
----------
1pF
20 + 0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
r:IN
Cb
----------
1pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4704/05 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
Rev. 1.0
7
Si4704/05-C40
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
SCLK
30%
70%
SDIO
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO
A6-A0,
R/W
D7-D0
D7-D0
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
Si4704/05-C40
Table 6. 3-Wire Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
20
10
10
2
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLK Setup
SDIO Input to SCLK Hold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLK Hold
t
—
ns
HSEN
SCLK to SDIO Output Valid
SCLK to SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall Time
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
tS
SEN
30%
A6-A5,
R/W,
A4-A1
70%
A7
A0
D15
D14-D1
D0
SDIO
30%
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4704/05-C40
Table 7. SPI Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
15
10
5
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
SEN Input to SCLKHold
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
t
—
ns
S
t
—
ns
HSDIO
t
—
ns
HSEN
t
Read
Read
2
25
25
ns
CDV
t
2
ns
CDZ
t
t
R
—
—
10
ns
SCLK, SEN, SDIO, Rise/Fall time
F
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHIGH
tLOW
tHSDIO
tHSEN
70%
30%
tS
SEN
tS
70%
30%
C7
C6–C1
C0
D7
D6–D1
D0
SDIO
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
70%
30%
SCLK
tCDV
tS
tHSEN
tHSDIO
70%
30%
tS
SEN
tCDZ
70%
30%
SDIO
C7
C6–C1
C0
D7
D6–D1
D0
16 Data Bytes Out
(SDIO or GPO1)
Bus
Turnaround
Control Byte In
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.0
Si4704/05-C40
Table 8. Digital Audio Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
12
ns
PD:DOUT
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.0
11
Si4704/05-C40
Table 9. FM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
76
Typ
—
Max
108
3.5
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone
(S+N)/N = 26 dB
(S+N)/N = 26 dB
—
2.2
µV EMF
3,4,5
Network
3,4,5,6
Sensitivity with 50 Network
—
—
1.1
15
—
—
µV EMF
µV EMF
6
RDS Sensitivity
f = 2 kHz,
RDS BLER < 5%
6
LPI Sensitivity
—
3
3.5
4
—
5
µV EMF
6,7
LNA Input Resistance
k
6,7
LNA Input Capacitance
4
5
6
pF
6,8
Input IP3
100
40
35
60
35
72
—
—
15
32
55
—
—
—
105
50
50
70
—
80
—
—
—
42
63
58
32
38
—
—
—
—
—
90
1
dBµV EMF
3,4,6,7
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
6
Spurious Response Rejection
3,4,7
mV
Audio Output Voltage
RMS
3,7,9
dB
Hz
Audio Output L/R Imbalance
6
–3 dB
–3 dB
30
—
—
—
—
—
—
Audio Frequency Response Low
6
kHz
dB
Audio Frequency Response High
7,9
Audio Stereo Separation
3,4,5,7,10
dB
Audio Mono S/N
4,5,6,7,10,11
dB
Audio Stereo S/N
3,6,12,13
Blocking Sensitivity
f = ±400 kHz
f = ±4 MHz
dBµV
dBµV
Notes:
1. Additional testing information is available in application note, “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test
Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature 25°C.
12
Rev. 1.0
Si4704/05-C40
Table 9. FM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
f = ±400 kHz, ±800 kHz
f = ±4 MHz, ±8 MHz
Min
—
Typ
40
35
0.1
75
50
—
Max
—
Unit
dBµV
dBµV
%
3,6,12,13
Intermod Sensitivity
—
—
3,7,9
—
0.5
80
54
—
Audio THD
6
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
70
45
10
—
µs
µs
6,10
R
k
Audio Output Load Resistance
L
6,10
C
Single-ended
—
50
60
pF
Audio Output Load Capacitance
L
6
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
ms/channel
6
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
14
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in application note, “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test
Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature 25°C.
Rev. 1.0
13
Si4704/05-C40
Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
64
Typ
—
Max
75.9
—
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone
(S+N)/N = 26 dB
—
4.0
µV EMF
3,4,5
Network
7
LNA Input Resistance
3
4
4
5
5
6
k
7
LNA Input Capacitance
pF
dBµV EMF
dB
8
Input IP3
100
40
—
—
72
—
—
15
55
—
70
45
10
—
—
105
50
50
70
80
—
—
—
63
0.1
75
50
—
—
—
—
—
—
—
90
1
3,4,7
m = 0.3
±200 kHz
±400 kHz
AM Suppression
dB
Adjacent Channel Selectivity
Alternate Channel Selectivity
dB
3,4,7
mV
Audio Output Voltage
RMS
3,7,9
dB
Audio Output L/R Imbalance
–3 dB
–3 dB
30
—
—
0.5
80
54
—
50
60
Hz
Audio Frequency Response Low
Audio Frequency Response High
kHz
3,4,5,7,10
dB
Audio Mono S/N
3,7,9
%
Audio THD
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
k
10
R
Audio Output Load Resistance
L
L
10
C
Single-ended
pF
Audio Output Load Capacitance
Seek/Tune Time
RCLK tolerance
= 100 ppm
ms/channel
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
11
RSSI Offset
Input levels of 8 and
60 dBµV EMF
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. At temperature (25 °C).
14
Rev. 1.0
Si4704/05-C40
Table 11. Reference Clock and Crystal Characteristics
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
1
RCLK Supported Frequencies
31.130
–100
1
32.768
—
40,000
100
kHz
2
RCLK Frequency Tolerance
ppm
REFCLK_PRESCALE
REFCLK
—
4095
31.130
32.768
34.406
kHz
Crystal Oscillator
Crystal Oscillator Frequency
—
–100
—
32.768
—
—
kHz
ppm
pF
2
Crystal Frequency Tolerance
100
3.5
Board Capacitance
—
Notes:
1. The Si4704/05 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si47xx Programming Guide,” Table
6 for more details.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.
Rev. 1.0
15
Si4704/05-C40
2. Typical Application Schematic
GPO1
GPO2/INT
R1
R2
GPO3/DCLK
DFS
R3
15
DOUT
DOUT
Optional: Digital Audio Output
1
NC
2
FMI
FMI
LPI
14
13
12
11
LOUT
ROUT
LOUT
ROUT
GND
3
RFGND
U1
Si4704/05
4
5
LPI
VDD
RST
VBATTERY
2.7 to 5.5 V
C1
RST
SEN
X1
GPO3
RCLK
C3
SCLK
SDIO
RCLK
C2
Optional: for crystal oscillator option
VIO
1.85 to 3.6 V
Notes:
1. Place C1 close to V pin.
DD
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a headphone antenna. Pin 4 is for an integrated
antenna.
6. Place Si4704/05 as close as possible to antenna and keep the FMI and LPI traces as short as possible.
16
Rev. 1.0
Si4704/05-C40
3. Bill of Materials
Component(s)
Value/Description
Supplier
Murata
C1
U1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Si4704/05 FM Radio Receiver
Silicon Laboratories
Optional Components
C2, C3
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
X1
R1
R2
R3
32.768 kHz crystal (Optional: for crystal oscillator option)
Resistor, 2 k(Optional: for digital audio)
Epson
Venkel
Venkel
Venkel
Resistor, 2 k(Optional: for digital audio)
Resistor, 600 (Optional: for digital audio)
Rev. 1.0
17
Si4704/05-C40
4. Functional Description
4.1. Overview
FM Antenna
Si4704/05
ADC
ADC
DAC
FMI
LOUT
ROUT
LNA
AGC
PGA
DSP
RFGND
DAC
GPO
LPI
0/90
DCLK
DOUT
DFS
RDS
(Si4705)
32.768 kHz
RCLK
RSSI
AFC
REG
CONTROL
INTERFACE
2.7–5.5 V
VDD
XTAL
OSC
Figure 9. Functional Block Diagram
The Si4704/05 device leverages Silicon Laboratories’ The Si4704/05 performs much of the FM demodulation
highly successful and proven Si4700/01/02/03 FM digitally to achieve high fidelity, optimal performance
receiver, and offers unmatched integration and versus power consumption, and flexibility of design. The
performance. The Si4704/05 offers additional features, on-board DSP provides unmatched pilot rejection,
such as EN55020 compliance, embedded antenna selectivity, and optimum sound quality. The Si4704/05
support, and a digital audio interface. The Si4704/05 is offers both the manufacturer and the end-user
layout compatible with Silicon Laboratories’ Si4710/11 unmatched programmability and flexibility in the
FM Transmitter, Si4720/21 FM Transceiver, and listening experience.
Si4730/31 AM/FM Receiver. The Si4704/05 is the first
FM radio receiver integrated circuit to support a short
for the European Radio Data System (RDS) and the US
PCB trace or wire antenna, which can be integrated into
The Si4705 incorporates on-board processing capability
Radio Broadcast Data System (RBDS) including all the
symbol encoding/decoding, block synchronization, error
the enclosure or PCB.
The Si4704/05’s digital integration reduces the required detection, and error correction functions. RDS allows
external components of traditional offerings, resulting in digital information sent from the broadcaster to be
a solution requiring only an external inductor and displayed, such as station ID, song name, and music
bypass capacitor, and occupying board space of category. In Europe, alternate frequency (AF)
2
approximately 15 mm . Other advantages of the information is also provided to automatically change
Si4704/05 include highly reliable device manufacturing, stations in areas where broadcasters use multiple
excellent quality, and ease of use to design-in and frequencies.
program.
The Si4704/05 has two separate RF inputs. FMI is the
The Si4704/05 includes line outputs from the on-chip input for use with a traditional FM antenna. The LPI
digital-to-analog converters (DAC), digital audio mixers, input is for use with a short PCB trace or wire antenna
a
programmable reference clock input, and
a
that may be integrated into the system enclosure. There
configurable digital audio interface with the Si4705. The is a clocking mode to choose to clock the Si4704/05
2
chip supports an I C-compliant 2-wire interface, an from a reference clock or crystal. On the Si4705, there
Si4700/01/02/03 backwards compatible 3-wire control is an audio output mode to choose between an analog
interface, and an SPI control interface.
and/or digital audio output.
18
Rev. 1.0
Si4704/05-C40
In the analog audio output mode, pin 13 is ROUT, pin 14 The quadrature mixer output is amplified, filtered, and
is LOUT, and pin 17 is GPO3. In the digital audio mode, digitized with high resolution analog-to-digital
pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK. converters (ADCs). This advanced architecture allows
Concurrent analog/digital audio output mode requires the Si4704/05 to perform channel selection, FM
pins 13, 14, 15, 16, and 17.
demodulation, and stereo audio processing to achieve
superior performance compared to traditional analog
architectures.
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
2
including I S and left-justified modes. The interface has
4.4. Digital Audio Interface (Si4705 Only)
three pins: digital data input (DIN), digital frame
synchronization input (DFS), and
The digital audio interface operates in slave mode and
supports three different audio data formats:
a
digital bit
synchronization input clock (DCLK). The Si4704/05
supports a number of industry-standard sampling rates
including 32, 40, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
2
I S
Left-Justified
DSP Mode
4.4.1. Audio Data Formats
2
In I S mode, by default the MSB is captured on the
The Si4704/05 is reset by applying a logic low on RST
signal. This causes all register values to be reset to their
default values. The digital output interface supply (V )
provides voltage to the RST, SEN, SDIO, RCLK, DOUT,
DFS, and DCLK pins and can be connected to the audio
baseband processor's supply voltage to save power and
remove the need for voltage level translators. RCLK is
not required for register operation.
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
IO
In Left-Justified mode, by default the MSB is captured
on the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
The Si4704/05 reference clock is programmable,
supporting many RCLK inputs as shown in Table 11.
4.2. Application Schematics and Operating
Modes
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
The application schematic for the Si4704/05 is shown in
Section "2. Typical Application Schematic" on page 16.
The Si4704/05 supports selectable analog, digital, or
concurrent analog and digital audio output modes. In
the analog output mode, pin 13 is ROUT, pin 14 is
LOUT, and pin 17 is GPO3. In the digital output mode,
pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK.
Concurrent analog and digital audio output mode
requires pins 13, 14, 15, 16, and 17. In addition to
output mode, there is a clocking mode to clock the
Si4704/05 from a reference clock or crystal oscillator.
The user sets the operating modes with commands as
described in Section "5. Commands and Properties" on
page 25.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
4.3. FM Receiver
4.4.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
The Si4704/05 FM receiver is based on the proven
Si4700/01 FM tuner. The receiver uses a digital low-IF
architecture allowing the elimination of external
components and factory adjustments. The Si4704/05
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (64 to 108 MHz). An
AGC circuit controls the gain of the LNA to optimize
sensitivity and rejection of strong interferers. An image-
reject mixer downconverts the RF signal to low-IF.
Rev. 1.0
19
Si4704/05-C40
INVERTED
(OFALL = 1)
DCLK
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I2S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 10. I2S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 11. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 12. DSP Digital Audio Format
20
Rev. 1.0
Si4704/05-C40
4.5. Stereo Audio Processing
4.6. De-emphasis
The output of the FM demodulator is a stereo Pre-emphasis and de-emphasis is a technique used by
multiplexed (MPX) signal. The MPX standard was FM broadcasters to improve the signal-to-noise ratio of
developed in 1961, and is used worldwide. Today's FM receivers by reducing the effects of high-frequency
MPX signal format consists of left + right (L+R) audio, interference and noise. When the FM signal is
left – right (L–R) audio, a 19 kHz pilot tone, and transmitted,
a
pre-emphasis filter is applied to
RDS/RBDS data as shown in Figure 13 below.
accentuate the high audio frequencies. The Si4704/05
incorporates a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The de-
emphasis time constant is programmable to 50 or 75 µs
and is set by the FM_DEEMPHASIS property.
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
4.7. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted. Volume is
adjusted digitally with the RX_VOLUME property.
0
15 19 23
38
53 57
Frequency (kHz)
4.8. Soft Mute
Figure 13. MPX Signal Spectrum
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The softmute attenuation level is adjustable
using the FM_SOFT_MUTE_MAX_ATTENUATION
property.
4.5.1. Stereo Decoder
The Si4704/05's
integrated
stereo
decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4705 uses frequency information from the 19 kHz
stereo pilot to recover the 57 kHz RDS/RBDS signal.
4.9. RDS/RBDS Processor (Si4705 Only)
The Si4705 implements an RDS/RBDS* processor for
symbol decoding, block synchronization, error
detection, and error correction.
The Si4705 device is user configurable and provides an
optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
4.5.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Stereo/mono status can be
monitored with the FM_RSQ_STATUS command. Mono
The Si4705 reports RDS decoder synchronization
status and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors or that the block checkword
contains errors.
operation
can
be
forced
with
the
FM_BLEND_MONO_THRESHOLD property.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
Rev. 1.0
21
Si4704/05-C40
4.10. Tuning
4.13. Control Interface
The tuning frequency can be directly programmed using A serial port slave interface is provided, which allows an
the FM_TUNE_FREQ command. The Si4704/05 external controller to send commands to the Si4704/05
supports channel spacing steps of 10 kHz in FM mode. and receive responses from the device. The serial port
can operate in three bus modes: 2-wire mode, 3-wire
mode, or SPI mode. The Si4704/05 selects the bus
4.11. Seek
Seek tuning will search up or down for a valid channel.
Valid channels are found when the receive signal
strength indicator (RSSI) and the signal-to-noise ratio
(SNR) values exceed the set threshold. Using the SNR
qualifier rather than solely relying on the more
traditional RSSI qualifier can reduce false stops and
increase the number of valid stations detected. Seek is
initiated using the FM_SEEK_START command. The
RSSI and SNR threshold settings are adjustable using
properties (see Table 14).
mode by sampling the state of the GPO1 and GPO2
pins on the rising edge of RST. The GPO1 pin includes
an internal pull-up resistor, which is connected while
RST is low, and the GPO2 pin includes an internal pull-
down resistor, which is connected while RST is low.
Therefore, it is only necessary for the user to actively
drive pins which differ from these states. See Table 12.
Table 12. Bus Mode Select on Rising Edge of
RST
4.12. Reference Clock
Bus Mode
2-Wire
SPI
GPO1
GPO2
The Si4704/05 reference clock is programmable,
supporting RCLK frequencies in Table 11. Refer to
Table 3, “DC Characteristics,” on page 5 for switching
1
0
1
1 (must drive)
0
3-Wire
0 (must drive)
voltage
levels
and
Table 9,
“FM
Receiver
Characteristics,” on page 12 for frequency tolerance
information.
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins as
described in Section “4.14. GPO Outputs”. In any bus
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 16. This mode is enabled using the
POWER_UP command. Refer to Table 13, “Selected
Si4704/05 Commands,” on page 25.
mode, commands may only be sent after V and V
IO
DD
supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
The Si4704/05 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4704/05 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
4.13.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4704/05 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4704/05 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
22
Rev. 1.0
Si4704/05-C40
Although the Si4704/05 will respond to only a single A transaction ends when the user sets SEN high, then
device address, this address can be changed with the pulses SCLK high and low one final time. SCLK may
SEN pin (note that the SEN pin is not used for signaling either stop or continue to toggle while SEN is high.
in 2-wire mode). When SEN = 0, the 7-bit device
address is 0010001b. When SEN = 1, the address is
argument to register(s) 0xA1–0xA3, then writing the
1100011b.
In 3-wire mode, commands are sent by first writing each
command word to register 0xA0. A response is
For write operations, the user then sends an 8-bit data retrieved by reading registers 0xA8–0xAF.
byte on SDIO, which is captured by the device on rising
For details on timing specifications and diagrams, refer
edges of SCLK. The Si4704/05 acknowledges each
to Table 6, “3-Wire Control Interface Characteristics,” on
data byte by driving SDIO low for one cycle, on the next
page 9; Figure 4, “3-Wire Control Interface Write Timing
falling edge of SCLK. The user may write up to 8 data
Parameters,” on page 9, and Figure 5, “3-Wire Control
bytes in a single 2-wire transaction. The first byte is a
Interface Read Timing Parameters,” on page 9.
command, and the next seven bytes are arguments.
4.13.3. SPI Control Interface Mode
For read operations, after the Si4704/05 has
When selecting SPI mode, the user must ensure that a
acknowledged the control byte, it will drive an 8-bit data
rising edge of SCLK does not occur within 300 ns
byte on SDIO, changing the state of SDIO on the falling
before the rising edge of RST.
edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling SPI bus mode uses the SCLK, SDIO, and SEN pins for
edge of SCLK. If a data byte is not acknowledged, the read/write operations. The system controller can
transaction will end. The user may read up to 16 data choose to receive read data from the device on either
bytes in a single 2-wire transaction. These bytes contain SDIO or GPO1. A transaction begins when the system
the response data from the Si4704/05.
controller drives SEN = 0. The system controller then
pulses SCLK eight times, while driving an 8-bit control
byte serially on SDIO. The device captures the data on
rising edges of SCLK. The control byte must have one
of five values:
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high. For
details on timing specifications and diagrams, refer to
Table 5, “2-Wire Control Interface Characteristics” on
page 7; Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8, and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 8.
0x48 = write a command (controller drives 8
additional bytes on SDIO).
0x80 = read a response (device drives one
additional byte on SDIO).
4.13.2. 3-Wire Control Interface Mode
0xC0 = read a response (device drives 16 additional
bytes on SDIO).
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
0xA0 = read a response (device drives one
additional byte on GPO1).
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 3-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
0xE0 = read a response (device drives 16 additional
bytes on GPO1).
For write operations, the system controller must drive
exactly eight data bytes (a command and seven
arguments) on SDIO after the control byte. The data is
captured by the device on the rising edge of SCLK.
For read operations, the controller must read exactly 1
byte (STATUS) after the control byte or exactly 16 data
bytes (STATUS and RESP1–RESP15) after the control
byte. The device changes the state of SDIO (or GPO1, if
specified) on the falling edge of SCLK. Data must be
captured by the system controller on the rising edge of
SCLK.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4704/05 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
Rev. 1.0
23
Si4704/05-C40
Keep SEN low until all bytes have transferred. A
transaction may be aborted at any time by setting SEN
high and toggling SCLK high and then low. Commands
will be ignored by the device if the transaction is
aborted.
4.16. Programming with Commands
To ease development time and offer maximum
customization, the Si4704/05 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
For details on timing specifications and diagrams, refer properties, and responses.
to Figure 6 and Figure 7 on page 10.
To perform an action, the user writes a command byte
and associated arguments, causing the chip to execute
the given command. Commands control an action such
as powerup the device, shut down the device, or tune to
a station. Arguments are specific to a given command
and are used to modify the command. A partial list of
commands is available in Table 13, “Selected Si4704/05
Commands,” on page 25.
4.14. GPO Outputs
The Si4704/05 provides three general-purpose output
pins. The GPO pins can be configured to output a
constant low, constant high, or high-impedance. The
GPO pins can be reconfigured as specialized functions.
GPO2/INT can be configured to provide interrupts and
GPO3 can be configured to provide external crystal
support or as DCLK in digital audio output mode.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. A partial list of
properties is available in Table 14, “Selected Si4704/05
Properties,” on page 26.
4.15. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. All commands provide a one-byte status update
indicating interrupt and clear-to-send status information.
For a detailed description of the commands and
properties for the Si4704/05, see “AN332: Universal
Programming Guide.”
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry
while keeping the bus active.
24
Rev. 1.0
Si4704/05-C40
5. Commands and Properties
Table 13. Selected Si4704/05 Commands
Cmd
Name
Description
Powerup device and mode selection. Modes include analog or digital output
and reference clock or crystal support.
0x01
POWER_UP
0x10
0x11
0x12
0x13
0x20
0x21
GET_REV
Returns revision information on the device.
Powerdown device.
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
FM_TUNE_FREQ
FM_SEEK_START
Sets the value of a property.
Retrieves a property’s value.
Selects the FM tuning frequency.
Begins searching for a valid frequency.
Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START
command.
0x22
0x23
0x24
FM_TUNE_STATUS
FM_RSQ_STATUS
FM_RDS_STATUS
Queries the status of the Received Signal Quality (RSQ) of the current
channel (Si4705 only).
Returns RDS information for current channel and reads an entry from the
RDS FIFO (Si4705 only).
Rev. 1.0
25
Si4704/05-C40
Table 14. Selected Si4704/05 Properties
Prop
Name
Description
Default
0x1100
FM_DEEMPHASIS
Sets deemphasis time constant. Default is 75 us.
0x0002
Sets RSSI threshold for stereo blend (Full stereo above
threshold, blend below threshold). To force stereo set this to 0. 0x0031
To force mono set this to 127. Default value is 49 dBuV.
FM_BLEND_STEREO_
THRESHOLD
0x1105
0x1106
Sets RSSI threshold for mono blend (Full mono below
threshold, blend above threshold). To force stereo set this to 0. 0x001E
To force mono set this to 127. Default value is 30 dBuV.
FM_BLEND_MONO_
THRESHOLD
FM_RSQ_INT_
SOURCE
0x1200
0x1302
Configures interrupt related to Received Signal Quality metrics. 0x0000
FM_SOFT_MUTE_
MAX_ATTENUATION
Sets maximum attenuation during soft mute (dB). Set to 0 to
0x0010
disable soft mute. Default is 16 dB.
FM_SEEK_BAND_
BOTTOM
0x1400
0x1401
0x1402
Sets the bottom of the FM band for seek. Default is 8750.
Sets the top of the FM band for seek. Default is 10790.
Selects frequency spacing for FM seek.
0x222E
0x2A26
0x000A
FM_SEEK_BAND_TOP
FM_SEEK_FREQ_
SPACING
FM_SEEK_TUNE_
SNR_THRESHOLD
Sets the SNR threshold for a valid FM Seek/Tune. Default value
is 3 dB.
0x1403
0x0003
FM_SEEK_TUNE_
RSSI_TRESHOLD
Sets the RSSI threshold for a valid FM Seek/Tune. Default
value is 20 dBuV.
0x1404
0x1500
0x1501
0x0014
0x0000
0x0000
RDS_INT_SOURCE
Configures RDS interrupt behavior.
Sets the minimum number of RDS groups stored in the receive
RDS FIFO required before RDS RECV is set.
RDS_INT_FIFO_COUNT
0x1502
0x4000
RDS_CONFIG
RX_VOLUME
Configures RDS setting.
Sets the output volume.
0x0000
0x003F
Mutes the audio output. L and R audio outputs may be muted
independently in FM mode.
0x4001
RX_HARD_MUTE
0x0000
26
Rev. 1.0
Si4704/05-C40
6. Pin Descriptions: Si4704/05-GM
20 19 18 17
NC 1
FMI 2
RFGND 3
LPI 4
16
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
GND
PAD
RST 5
6
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
No connect. Leave floating.
FM RF input.
2
FMI
3
RFGND
LPI
RF ground. Connect to ground plane on PCB.
Loop antenna RF input.
4
5
RST
Device reset input (active low).
Serial enable input (active low).
Serial clock input.
6
SEN
7
SCLK
SDIO
RCLK
8
Serial data input/output.
9
External reference or crystal oscillator input.
I/O supply voltage.
10
V
IO
11
V
Supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
Right audio analog line output.
DD
12, GND PAD
GND
ROUT
LOUT
DOUT
DFS
13
14
15
16
17
Left audio analog line output.
Digital audio output data.
Digital frame synchronization.
GPO3/DCLK General purpose output/digital bit synchronous clock or crystal oscillator
input.
18
19
General purpose output/interrupt.
General purpose output.
GPO2/INT
GPO1
Rev. 1.0
27
Si4704/05-C40
7. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4704-C40-GM FM Broadcast Radio Receiver
QFN
–20 to 85 °C
Pb-free
Si4705-C40-GM FM Broadcast Radio Receiver with RDS/RBDS
QFN
–20 to 85 °C
Pb-free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
28
Rev. 1.0
Si4704/05-C40
8. Package Markings (Top Marks)
8.1. Si4704 Top Mark
0440
CTTT
YWW
Figure 14. Si4704 Top Mark
8.2. Si4705 Top Mark
0540
CTTT
YWW
Figure 15. Si4705 Top Mark
8.3. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
04 = Si4704
05 = Si4705
Firmware Revision
R = Die Revision
40 = Firmware Revision 4.0
C = Revision C Die.
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier.
(Bottom-Left Justified)
Y = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and workweek of the mold date.
Rev. 1.0
29
Si4704/05-C40
9. Package Outline: Si4704/05-GM
Figure 16 illustrates the package details for the Si4704/05. Table 15 lists the values for the dimensions shown in
the illustration.
Figure 16. 20-Pin Quad Flat No-Lead (QFN)
Table 15. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
30
Rev. 1.0
Si4704/05-C40
10. PCB Land Pattern: Si4704/05-C40-GM
Figure 17 illustrates the PCB land pattern details for the Si4704/05-GM. Table 16 lists the values for the dimensions
shown in the illustration.
Figure 17. PCB Land Pattern
Rev. 1.0
31
Si4704/05-C40
Table 16. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
32
Rev. 1.0
Si4704/05-C40
11. Additional Reference Resources
Contact your local sales representatives for more information or to obtain copies of the following references:
EN55020 Compliance Test Certificate
AN332: Si47xx Programming Guide
AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
Rev. 1.0
33
Si4704/05-C40
DOCUMENT CHANGE LIST
Revision 0.7 to Revision 0.71
V
minimum changed from 1.5 V to 1.85 V.
IO
Revision 0.71 to Revision 1.0
Updated patent information on page 1.
Updated Table 3 on page 5.
34
Rev. 1.0
Si4704/05-C40
NOTES:
Rev. 1.0
35
Si4704/05-C40
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: FMinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
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quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
36
Rev. 1.0
相关型号：
SI4704-C40
Worldwide FM band support (64-108 MHz) integrated antenna support EN55020 compliant
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