SI4710-B31-GM [SILICON]
SI4710 BROADCAST FM RADIO TRANSMITTER;
| 型号： | SI4710-B31-GM |
| 厂家： | 
SILICON |
| 描述： | SI4710 BROADCAST FM RADIO TRANSMITTER 电信 电信集成电路 |
| 文件： | 总40页 (文件大小：1661K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4710/11-B30
Si4710/11-B30 FM RADIO TRANSMITTER
Features
Integrated receive power
measurement
Worldwide FM band support
(76–108 MHz)
Requires only two external
components
RDS/RBDS encoder (Si4711 only)
PCB loop and stub antenna
support with self-calibrated
capacitor tuning
Programmable transmit level
Audio dynamic range control
Advanced modulation control
2.7 to 5.5 V supply voltage
Integrated LDO regulator
3 x 3 x 0.55 mm 20-pin QFN
Pb-free and RoHS Compliant
Designed for compatibility with
cellular operation
Frequency synthesizer with
integrated VCO
Digital stereo modulator
Programmable pre-emphasis
Analog/digital audio interface
Audio silence detector
Programmable reference clock
Ordering Information:
See page 32.
Pin Assignments
Applications
Si4710/11
Cellular handsets/hands-free
MP3 players
Portable media players
Wireless speakers/microphone
Satellite digital audio radios
Personal computers/notebooks
(Top View)
Description
20 19 18 17
NC
NC
1
16
The Si4710/11 integrates the complete transmit functions for standards-
compliant unlicensed FM broadcast stereo transmission. Users must
comply with local regulations on radio frequency (RF) transmission.
2
15 RIN
14 DFS
13 DIN
12 GND
11 VDD
RFGND
TXO
3
4
5
GND
PAD
Functional Block Diagram
RST
DIGITAL
AUDIO
DFS
DIN
6
Si4710/11
7
8
9
10
LIN
RIN
ADC
ADC
DAC
DAC
Tx
Ant
TXO
DSP
Patents pending
L1
120 nH
RFGND
Note: To ensure proper operation and
performance, follow the guide-
lines in “AN383: Universal
Antenna Selection and Layout
Guidelines.” Silicon Laboratories
will evaluate schematics and lay-
outs for qualified customers.
2.7–5.5 V
VDD
GPO
RDS Si4711
CONTROL
INTERFACE
LDO
AFC
C1 GND
(
)
22 nF
Rev. 1.1 2/08
Copyright © 2008 by Silicon Laboratories
Si4710/11
Si4710/11-B30
2
Rev. 1.1
Si4710/11-B30
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Test Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.2. Test Circuit Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Analog Audio Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Digital Audio Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3. Typical Application Schematic Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Universal AM/FM RX/FM TX Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1. Universal AM/FM RX/FM TX Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2. FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4. Line Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.5. Audio Dynamic Range Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.6. Audio Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.7. Pre-Emphasis and De-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.8. RDS/RBDS Processor (Si4711 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.9. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.10. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.11. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.12. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.13. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.14. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Pin Descriptions: Si4710/11-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.1. Si4710 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.2. Si4711 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10. Package Outline: Si4710/11-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11. PCB Land Pattern: Si4710/11-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
12. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.1
3
Si4710/11-B30
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Test Condition
Min
2.7
1.5
10
Typ
—
Max
5.5
3.6
—
Unit
V
V
DD
Interface Supply Voltage
V
—
V
IO
DDRISE
Power Supply Powerup Rise Time
V
—
µs
µs
Interface Supply Powerup Rise
Time
V
10
—
—
IORISE
Ambient Temperature
T
–20
25
85
C
A
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
DD
Interface Supply Voltage
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
T
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
–40 to 95
–55 to 150
0.4
C
C
OP
T
STG
4
RF Input Level
V
PK
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended
operating conditions for extended periods may affect device reliability.
2. The Si4710/11 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, DIN, GPO1, GPO2/INT, and GPO3.
4. At RF input pin, TXO.
4
Rev. 1.1
Si4710/11-B30
Table 3. DC Characteristics
Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Transmitter from Line Input
TX Supply Current
I
—
—
18.8
320
22.8
600
mA
µA
TX
TX Interface Supply Current
I
IO
FM Transmitter from Digital Audio Input
TX Supply Current
I
DCLK = 3.072 MHz
DCLK = 3.072 MHz
—
—
18.3
320
—
—
mA
µA
DTX
TX Interface Supply Current
Supplies and Interface
I
DIO
V
V
Powerdown Current
I
Powerdown mode
—
—
10
3
20
10
µA
µA
DD
DD
Interface Powerdown Current
I
SCLK, RCLK inactive
Powerdown mode
IO
IO
1
High Level Input Voltage
V
0.7 x VIO
–0.3
—
—
—
—
—
—
VIO + 0.3
0.3 x VIO
10
V
V
IH
1
Low Level Input Voltage
V
IL
1
High Level Input Current
I
V
= VIO = 3.6 V
IN
–10
µA
µA
V
IH
1
Low Level Input Current
I
V
= 0 V, V = 3.6 V
–10
10
IL
IN
IO
2
High Level Output Voltage
V
I
= 500 µA
0.8 x VIO
—
—
OH
OUT
OUT
2
Low Level Output Voltage
V
I
= –500 µA
0.2 x VIO
V
OL
Notes:
1. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, DIN, GPO1, GPO2/INT, and GPO3.
2. For output pins SDIO, GPO1, GPO2/INT, and GPO3.
Rev. 1.1
5
Si4710/11-B30
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tHRST
tSRST
70%
30%
RST
70%
30%
GPO1
70%
30%
GPO2/
INT
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.1
Si4710/11-B30
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold (START)
SDIO Input to SCLK Setup
0.6
100
0
—
—
—
—
—
—
—
—
µs
ns
ns
µs
µs
ns
HD:STA
SU:DAT
t
t
4,5
SDIO Input to SCLK Hold
900
—
HD:DAT
SU:STO
SCLK input to SDIO Setup (STOP)
STOP to START Time
t
0.6
1.3
t
—
BUF
SDIO Output Fall Time
t
250
f:OUT
Cb
-----------
20 + 0.1
1 pF
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
r:IN
Cb
-----------
1 pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VIO = 0 V, SCLK and SDIO are low-impedance. 2-wire control interface is I2C compatible.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4710/11 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum t
5. HD:DAT specification.
6. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
Rev. 1.1
7
Si4710/11-B30
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
SCLK
30%
70%
SDIO
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO
A6-A0,
R/W
D7-D0
D7-D0
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.1
Si4710/11-B30
Table 6. 3-Wire Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
f
CLK
SCLK High Time
t
25
25
20
10
10
2
HIGH
SCLK Low Time
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
SEN Input to SCLKHold
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
t
—
ns
S
t
—
ns
HSDIO
t
—
ns
HSEN
t
Read
Read
25
25
ns
CDV
t
2
ns
CDZ
t
t
R
SCLK, SEN, SDIO, Rise/Fall time
—
—
10
ns
F
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.1
9
Si4710/11-B30
Table 7. SPI Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
f
CLK
SCLK High Time
t
25
25
15
10
5
HIGH
SCLK Low Time
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
SEN Input to SCLKHold
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
—
ns
S
t
—
ns
HSDIO
t
—
ns
HSEN
t
Read
Read
2
25
25
10
ns
CDV
t
2
ns
CDZ
t
t
—
ns
R, F
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHIGH
tLOW
tHSDIO
tHSEN
70%
30%
tS
SEN
tS
70%
30%
C7
C6–C1
C0
D7
D6–D1
D0
SDIO
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
70%
30%
SCLK
tCDV
tS
tHSEN
tHSDIO
70%
30%
tS
SEN
tCDZ
70%
30%
SDIO
C7
C6–C1
C0
D7
D6–D1
D0
16 Data Bytes Out
(SDIO or GPO1)
Bus
Turnaround
Control Byte In
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.1
Si4710/11-B30
Table 8. Digital Audio Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
DCLK pulse width high
Symbol Test Condition
Min
10
10
5
Typ
—
Max
—
Unit
ns
t
DCH
DCLK pulse width low
t
—
—
ns
DCL
DFS set-up time to DCLK rising edge
DFS hold time from DCLK rising edge
DIN set-up time from DCLK rising edge
DIN hold time from DCLK rising edge
t
t
—
—
ns
SU:DFS
HD:DFS
5
—
—
ns
t
5
—
—
ns
SU:DIN
t
5
—
—
ns
HD:DIN
t
t
R
—
—
—
10
ns
DCLK, DFS, DIN, Rise/Fall time
F
1,2
1.0
40.0
MHz
DCLK Tx Frequency
Notes:
1. Guaranteed by characterization.
2. The DCLK frequency may be set below the minimum specification if DIGITAL_INPUT_SAMPLE_RATE is first set to 0
(disable).
DCLK
tR
tF
tHD:DFS
tSU:DFS
DFS
DIN
tSU:DIN
tHD:DIN
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.1
11
Si4710/11-B30
Table 9. FM Transmitter Characteristics1
(Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 µs pre-emphasis,
unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
Parameters are tested in production unless otherwise specified.)
Parameter
Symbol
Test Condition
Min
76
Typ
—
Max
108
3.5
Unit
MHz
kHz
2
Transmit Frequency Range
f
RF
Transmit Frequency Accuracy and
–3.5
—
2,3
Stability
2
Transmit Voltage Accuracy
V
V
= 103–117 dBµV
= 102, 118 dBµV
–2.5
–2.5
—
—
—
2.5
2.5
dB
dB
RF
RF
Transmit Voltage Accuracy
Transmit Voltage Temperature Coef-
–0.075
–0.025
dB/ºC
2
ficient
Transmit Channel Edge Power
Transmit Adjacent Channel Power
Transmit Alternate Channel Power
Transmit Emissions
> ±100 kHz,
pre-emphasis off
—
—
—
—
–20
–26
–26
dBc
dBc
dBc
> ±200 kHz,
pre-emphasis off
–30
–30
> ±400 kHz,
pre-emphasis off
In-band (76–108 MHz)
—
—
—
70
45
58
—
53
5
–30
—
dBc
pF
pF
µs
2
Output Capacitance Max
C
C
tune
tune
2
Output Capacitance Min
—
2
Pre-emphasis Time Constant
TX_PREMPHASIS = 75 µs
TX_PREMPHASIS = 50 µs
75
50
63
80
54
—
µs
2
Audio SNR Mono
f = 22.5 kHz, Mono,
dB
limiter off
Audio SNR Stereo
Audio THD Mono
f = 22.5 kHz,
fpilot = 6.75 kHz, Stereo,
limiter off
53
58
—
dB
f = 75 kHz, Mono,
—
—
0.1
0.1
0.5
0.5
%
%
limiter off
2
Audio THD Stereo
f = 22.5 kHz,
fpilot = 6.75 kHz, Stereo,
limiter off
2
Audio Stereo Separation
left channel only
30
35
—
dB
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in “AN383:
Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q > 30) shown in Figure 9 on page 14.
2. Guaranteed by characterization.
3. No measurable fRF/VDD at VDD of 500 mVpk-pk at 100 Hz to 10 kHz.
12
Rev. 1.1
Si4710/11-B30
Table 9. FM Transmitter Characteristics1 (Continued)
(Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 µs pre-emphasis,
unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
Parameters are tested in production unless otherwise specified.)
Parameter
Symbol
Test Condition
Min
40
—
Typ
50
—
Max
—
Unit
dB
Sub Carrier Rejection Ratio
SCR
2
Powerup Settling Time
110
ms
2
Input Signal Level
V
—
—
0.636
15 k
V
PK
AI
2
Frequency Flatness
Mono, ±1.5 dB,
f = 75 kHz, 0, 50, 75 µs
pre-emphasis, limiter off
30
—
Hz
Hz
Hz
2
High Pass Corner Frequency
Mono, –3 dB, f = 75 kHz,
0, 50, 75 µs pre-emphasis,
limiter off
5
—
—
30
2
Low Pass Corner Frequency
Audio Imbalance
Mono, –3 dB, f = 75 kHz,
0, 50, 75 µs pre-emphasis,
limiter off
15 k
16 k
Mono
–1
—
—
1
dB
%
2
Pilot Modulation Rate Accuracy
f = 68.25 kHz,
–10
10
fpilot = 6.75 kHz, Stereo
2
Audio Modulation Rate Accuracy
f = 68.25 kHz,
–10
—
10
%
fpilot = 6.75 kHz, Stereo
2
Input Resistance
LIATTEN[1:0] = 11
50
—
60
10
—
—
k
2
Input Capacitance
pF
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in “AN383:
Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q > 30) shown in Figure 9 on page 14.
2. Guaranteed by characterization.
3. No measurable fRF/VDD at VDD of 500 mVpk-pk at 100 Hz to 10 kHz.
Table 10. Reference Clock Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz)
Supported Parameter
Symbol
Test Condition
Min
31.130 32.768 40,000
–50 50
Typ
Max
Unit
kHz
ppm
1,2
RCLK Frequency Range
1
Frequency Tolerance
—
Notes:
1. Guaranteed by characterization.
2. The RCLK frequency divided by an integer number (the prescaler value) must fall in the range of 31,130 to 34,406 Hz.
Therefore, the range of RCLK frequencies is not continuous below frequencies of 311.3 kHz.
Rev. 1.1
13
Si4710/11-B30
2. Test Circuit
2.1. Test Circuit Schematic
C2
VIO
0.47 µF
LIN
RIN
C3
0.47 µF
1
2
3
4
5
15
14
13
12
11
NC
RIN
DFS
DIN
NC
U1
Si4710/11
RFGND
TXO
RST
GND
VDD
C4
2 pF
L1
VBATTERY
2.7 to 5.5 V
120 nH
VTXOUT
C1
22 nF
50
R1
RST
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
Notes:
1. Si4710/11 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the
guidelines in “AN383: 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. LIN, RIN line inputs must be ac-coupled.
Figure 9. Test Circuit Schematic
2.2. Test Circuit Bill of Materials
Table 11. Si4710/11 Test Circuit Bill of Materials
Component(s)
Value/Description
Supply bypass capacitor, 22 nF, 20%, Z5U/X7R
AC Coupling Capacitor, 0.47 µF
2 pF, ±.05 pF, 06035JZR0AB
120 nH inductor, Qmin = 30
Supplier(s)
Murata
C1
C2, C3
C4
Murata
AVX
L1
Murata
R1
49.9 , 5%
Murata
U1
Si4710/11 FM Radio Transmitter
Silicon Laboratories
14
Rev. 1.1
Si4710/11-B30
3. Typical Application Schematics
3.1. Analog Audio Inputs
C2
VIO
0.47 µF
LIN
RIN
C3
0.47 µF
1
15
14
13
12
11
NC
RIN
DFS
DIN
2
NC
U1
Si4710/11
3
RFGND
TX Antenna
4
TXO
GND
VDD
5
RST
L1
120 nH
VBATTERY
2.7 to 5.5 V
C1
22 nF
RST
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
Notes:
1. Si4710/11 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the
guidelines in “AN383: 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. LIN, RIN line inputs must be ac-coupled.
Figure 10. Analog Audio Inputs (LIN, RIN)
Rev. 1.1
15
Si4710/11-B30
3.2. Digital Audio Inputs
VIO
R1
R2
DCLK
DFS
DIN
1
2
3
4
5
15
14
13
12
11
NC
RIN
DFS
DIN
R3
NC
U1
Si4710/11
RFGND
TXO
RST
TX Antenna
GND
VDD
L1
VBATTERY
2.7 to 5.5 V
C1
22 nF
120 nH
RST
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
Notes:
1. Si4710/11 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the
guidelines in “AN383: Si47xx 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
Figure 11. Digital Audio Inputs (DIN, DFS, DCLK)
3.3. Typical Application Schematic Bill of Materials
Table 12. Si4710/11 Bill of Materials
Component(s)
Value/Description
Supply bypass capacitor, 22 nF, 20%, Z5U/X7R
AC Coupling Capacitor, 0.47 µF
120 nH inductor, Qmin = 30
2 k Resistor
Supplier(s)
Murata
C1
C2, C3
L1
Murata
Murata
R1, R2
R3
Any
600 Resistor
Any
U1
Si4710/11 FM Radio Transmitter
Silicon Laboratories
16
Rev. 1.1
Si4710/11-B30
4. Universal AM/FM RX/FM TX Application Schematic
Figure 12 shows an application schematic that supports the Si47xx family of 3 mm x 3 mm QFN products,
including the Si4702/3/4/5 FM receivers, Si471x FM transmitters, Si472x FM transceivers, and Si473x AM/FM
receivers.
FB1
2.5 k @ 100 MHz
R 2
T 5
S 1
Right
Audio
U2
Headphone Amplifier
Left
Audio
FB2
2.5 k @ 100 MHz
Si4702/03: Populate R12, R13, R21, C14, and C15
Si4704/05/1x/2x/3x Analog: Populate C7, C8, C14
and C15 as shown
Si4704/05/1x/2x/3x Digital: Populate R16, R17,
R18, R19, and R20 as shown
J1 HP Jack
R16
2 k
VBATTERY
2.7 to 5.5 V
System Component
GPIO3
GPIO2
GPIO1
C4
1 nF
LHEADPHONE
270 nH
R13
0
C7/R17
0.39 uF/ 2 k
LIN
System Component
FM Embedded RX/TX Antenna
RIN
R12
0
C8/R18
0.39 uF/ 600
R14
L1
D3
0
10 nH
C14/R19
0.39 uF/ 0
C17/R21
3.3pF/0
D4
1
2
3
4
5
15
14
13
12
11
LSHORT
NC
GND/RIN/DOUT
120 nH
FMI
LOUT/DFS
ROUT/DIN
GND
U1
Si47xx
RFGND
TXO/AMI
RST
System Component
C15/R20
System Component
0.39 uF/ 0
AM Ferrite Antenna
VDD
VBATTERY
2.7 to 5.5 V
System Components
C1
22 nF
LFERRITE
180–
600 uH
C16
470 nF
D5
RST
SEN
SCLK
SDIO
RCLK
VIO
Figure 12. Universal AM/FM RX/FM TX Application Schematic
Following the schematic and layout recommendations detailed in “AN383: Universal Antenna Selection and Layout
Guidelines” will result in optimal performance with the minimal application schematic shown in Figure 12. “Universal
AM/FM RX/FM TX Application Schematic”. System components are those that are likely to be present for any tuner
or transmitter design.
Rev. 1.1
17
Si4710/11-B30
4.1. Universal AM/FM RX/FM TX Bill of Materials
The bill of materials for the expanded application schematic shown in Figure 12 is provided in Table 13. Refer to
the individual device layout guides and antenna interface guides for a discussion of the purpose of each
component.
Table 13. Bill of Materials
Designator
Description
Note
C1
U1
Supply bypass capacitor, 22 nF, 10%, Z5U/X7R, 0402
Silicon Laboratories Si47xx, 3 mm x 3 mm, 20 pin, QFN
R12, R13, R19, 0 jumper, 0402
R12, R13, and R21 for
Si4702/03 Only
R20, R21
C16
AM antenna ac coupling capacitor, 470 nF, 20%, Z5U/X7R
AM Ferrite Antenna
AM Ferrite Antenna
LFERRITE AM Ferrite loop stick, 180–600 µH
FB1,FB2
Ferrite bead, 2.5 k @ 100 MHZ, 0603, Murata BLM18BD252SN1D Headphone Antenna
LHEADPHONE Headphone antenna matching inductor, 270 nH, 0603, Q>15, Murata Headphone Antenna
LQW18ANR27J00D
LSHORT
Embedded antenna matching inductor, 120 nH, 0603, Q>30, Murata Embedded Antenna
LQW18ANR12J00D
R14
C2
Embedded antenna jumper, 2.2 , 0402
Optional
Optional
Optional
Supply bypass capacitor, 22 nF, 10%, Z5U/X7R, 0402
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R, 0402
C3
C5, C6
R7-R11
C12, C13
X1
Headphone amp output shunt capacitor, 100 pF, 10%, Z5U/X7R, 0402 Optional
Current limiting resistor, 20 –2 k, 0402
Optional
Crystal load capacitor, 22 pF, 5%, COG
Optional
Crystal, Epson FC-135
Optional
C7, C8
D1-D5
C11
Si47xx input ac coupling capacitor, 0.39 µF, X7R/X5R, 0402
ESD Diode, SOT23-3, California Micro Devices CM1214-01ST
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R, 0402
System Component
System Component
Headphone Amplifier
C4
Headphone antenna ac coupling capacitor, 1 nF, 10%, Z5U/X7R, 0402 Headphone Antenna
Headphone amp output ac coupling capacitor, 125 uF, X7R, 0805 Headphone Amplifier
Headphone amp input ac coupling capacitor, 0.39 µF, X7R/X5R, 0402 Headphone Amplifier
C9, C10
C14, C15
R1,R2,R3,R4 Headphone amp feedback/gain resistor, 20 k, 0402
Headphone Amplifier
Headphone Amplifier
Headphone Amplifier
System Component
System Component
R5, R6
U2
Headphone amp bleed resistor, 100 k, 0402
Headphone amplifier, National Semiconductor, LM4910MA
Current limiting resistor, 2 k0402
R16, R17
R18
Current limiting resistor, 600 , 0402
L1
VCO filter inductor, 10 nH, 0603, Q30, Murata, LQW18ANR01J00D Optional
C17
VCO filter capacitor, 3.3 pF, 0402, COG, Venkel,
C0402COG2503R3JN
Optional
18
Rev. 1.1
Si4710/11-B30
5. Functional Description
5.1. Overview
Si4710/11
DIN
DIGITAL
AUDIO
DFS
DSP
Tx
Ant
ADC
ADC
LIN
DAC
DAC
TXO
L1
120 nH
RIN
VDD
RFGND
2.7–5.5 V
CONTROL
INTERFACE
GPO
RDS (Si4711)
LDO
AFC
GND C1
22 nF
Figure 13. Functional Block Diagram
The Si4710/11 is the first 100% CMOS FM radio synchronization, and error correction functions. Using
transmitter with integrated receive functionality to this feature, the Si4711 enables data such as artist
measure received signal strength. The device leverages name and song title to be transmitted to an RDS/RBDS
Silicon Labs’ highly successful and proven Si4700/01 receiver.
FM receiver patent family and offers unmatched
The transmit output (TXO) connects directly to the
integration and performance, allowing FM transmit to be
transmit antenna with only one external inductor to
added to any portable device with a single chip. The
provide harmonic filtering. The output is programmable
Si4710/11 offers industry-leading size, performance, low
over a 10 dB voltage range in 1 dB steps. The TXO
output pin can also be configured for loop antenna
power consumption, flexibility, and ease of use.
The Si4710/11’s digital integration reduces the required support. Users are responsible for complying with local
external components of traditional offerings, resulting in regulations on RF transmission (FCC, ETSI, ARIB,
a solution requiring only an external inductor and etc.).
bypass capacitor, and PCB space of approximately
15 mm . This increases the device reliability and
supports a variety of MSB-first audio data formats
simplifies the design and manufacturing for companies
The digital audio interface operates in slave mode and
2
2
including I S and left-justified modes. The interface has
adopting this technology.
three pins: digital data input (DIN), digital frame
The Si4710/11 performs FM modulation in the digital synchronization input (DFS), and
a
digital bit
domain to achieve high fidelity, optimal performance synchronization input clock (DCLK). The Si4710/11
versus power consumption, and flexibility of design. The supports a number of industry-standard sampling rates
onboard DSP provides modulation adjustment and including 32, 40, 44.1, and 48 kHz. The digital audio
audio dynamic range control for optimum sound quality. interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
The Si4711 supports the European Radio Data System
(RDS) and the US Radio Broadcast Data System
(RBDS) including all the symbol encoding, block The Si4710/11 includes a low-noise stereo line input
Rev. 1.1
19
Si4710/11-B30
(LIN/RIN) with programmable attenuation. To ensure
optimal audio performance, the Si4710/11 has a
transmit line input property that allows the user to
specify the peak amplitude of the analog input required
to reach maximum deviation level. The deviation levels
of the audio, pilot, and RDS/RBDS signals can be
independently programmed to customize FM transmitter
designs. The Si4710/11 has a programmable low audio
level and high audio level indicators that allows the user
to selectively enable and disable the carrier based on
the presence of audio content. In addition, the device
provides an overmodulation indicator to allow the user
to dynamically set the maximum deviation level. The
Si4710/11 has a programmable audio dynamic range
control that can be used to reduce the dynamic range of
the audio input signal and increase the volume at the
receiver. These features can dramatically improve the
end user’s listening experience.
5.2. FM Transmitter
The transmitter (TX) integrates a stereo audio ADC to
convert analog audio signals to high fidelity digital
signals. Alternatively, digital audio signals can be
applied to the Si4710/11 directly to reduce power
consumption by eliminating the need to convert audio
baseband signals to analog and back again to digital.
Digital signal processing is used to perform the stereo
MPX encoding and FM modulation to a low digital IF.
Transmit baseband filters suppress out-of-channel
noise and images from the digital low-IF signal. A
quadrature single-sideband mixer up-converts the
digital IF signal to RF, and internal RF filters suppress
noise and harmonics to support the harmonic emission
requirements of cellular phones, GPS, WLAN, and other
wireless standards.
The TXO output has over 10 dB of output level control,
programmable in approximately 1 dB steps. This large
output range enables a variety of antennas to be used
for transmit, such as a monopole stub antenna or a loop
antenna. The 1 dB step size provides fine adjustment of
the output voltage.
The Si4710/11 is reset by applying a logic low on the
RST pin. This causes all register values to be reset to
their default values. The digital input/output interface
supply (V ) provides voltage to the RST, SEN, SDIO,
IO
RCLK, DIN, DFS, and DCLK pins and can be connected
to the audio baseband processor's supply voltage to
save power and remove the need for voltage level
translators. RCLK is not required for register operation.
The TXO output requires only one external 120 nH
inductor. The inductor is used to resonate the antenna
and is automatically calibrated within the integrated
circuit to provide the optimum output level and
frequency response for supported transmit frequencies.
Users are responsible for adjusting their system’s
radiated power levels to comply with local regulations
on RF transmission (FCC, ETSI, ARIB, etc.).
The Si4710/11 reference clock is programmable,
supporting many RCLK inputs as shown in Table 9.
The Si4710/11 are part of a family of broadcast audio
solutions offered in standard, 3 x 3 mm 20-pin QFN
packages. All solutions are layout compatible, allowing
a single PCB to accommodate various feature offerings.
The Si4710/11 includes line inputs to the on-chip
analog-to-digital converters (ADC), a programmable
reference clock input, and a configurable digital audio
2
interface. The chip supports I C-compliant 2-wire, 8-bit
SPI, and a 3-wire control interface.
20
Rev. 1.1
Si4710/11-B30
5.3.2. Audio Sample Rates
5.3. Digital Audio Interface
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs and ADCs on
the audio baseband processor. The sampling rate is
selected using the DIGITAL_INPUT_SAMPLE_RATE
property.
The digital audio interface operates in slave mode and
supports 3 different audio data formats:
2
1. I S
2. Left-Justified
3. DSP Mode
5.3.1. Audio Data Formats
2
The device supports DCLK frequencies above 1 MHz.
After powerup the DIGITAL_INPUT_SAMPLE_RATE
property defaults to 0 (disabled). After DCLK is
In I S mode, the MSB is captured on the second rising
edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is low, and the Right Channel is transferred when the
DFS is high.
supplied,
property should be set to the desired audio sample rate
such as 32, 40, 44.1, or 48 kHz. The
the
DIGITAL_INPUT_SAMPLE_RATE
DIGITAL_INPUT_SAMPLE_RATE property must be set
to 0 before DCLK is removed or the DCLK frequency
drops below 1 MHz. A device reset is required if this
requirement is not followed.
In Left-Justified mode, the MSB is captured on the first
rising edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is high, and the Right Channel is transferred when the
DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1 DCLK period. The Left Channel is transferred first,
followed right away by the Right Channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
Rev. 1.1
21
Si4710/11-B30
INVERTED
(IFALL = 1)
DCLK
(IFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
I2S
(IMODE = 0000)
1 DCLK
1 DCLK
n-2
DIN/DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 14. I2S Digital Audio Format
INVERTED
DCLK
(IFALL = 1)
(IFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(IMODE = 0110)
DIN/DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 15. Left-Justified Digital Audio Format
(IFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DIN/DOUT
1
2
3
2
n-1
n
(IMODE = 1100)
(IMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DIN/DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 16. DSP Digital Audio Format
22
Rev. 1.1
Si4710/11-B30
The maximum analog input level is 636 mVpK. If the
analog input level from the audio baseband processor
exceeds this voltage, series resistors must be inserted
in front of the LIN and RIN pins to attenuate the voltage
such that it is within the allowable operating range. For
example, if the audio baseband's expected peak
5.4. Line Input
The Si4710/11 provides left and right channel line inputs
(LIN and RIN). The inputs are high-impedance and low-
capacitance, suited to receiving line level signals from
external audio baseband processors. Both line inputs
are low-noise inputs with programmable attenuation.
Passive and active anti-aliasing filters are incorporated
to prevent high frequencies from aliasing into the audio
band and degrading performance.
amplitude is 900 mV and the V supply voltage is 1.8 V,
IO
the designer can use 30 k series resistors in front of
the LIN and RIN pins and select LIATTEN[1:0] = 11. The
resulting expected peak input voltage at the LIN/RIN
pins is 600 mV, since this is just a voltage divider
between the LIN/RIN input resistance (see Table 14,
60 k for this example) and the external resistor. Note
that the Peak Input Voltage corresponding to the chosen
LIATTEN[1:0] code still needs to satisfy the condition of
being just greater than the attenuated voltage. In this
example, a line attenuation code of LIATTEN[1:0] = 11
has a Peak Input Voltage of 636 mV, which is just
greater than the expected peak attenuated voltage of
600 mV. Also, the expected peak attenuated voltage is
entered into the LILEVEL[9:0] parameter. Again, in this
example, 600 mV is entered into LILVEVEL[9:0]. This
example shows one possible solution, but many other
solutions exist. The optimal solution is to apply the
largest possible voltage to the LIN and RIN pins for
signal-to-noise considerations; however, practical
resistor values may limit the choices.
To ensure optimal audio performance, the Si4710/11
has a TX_LINE_INPUT_LEVEL property that allows the
user to specify the peak amplitude of the analog input
(LILEVEL[9:0]) required to reach the maximum
deviation level programmed in the audio deviation
property, TX_AUDIO_DEVIATION. A corresponding line
input attenuation code, LIATTEN[1:0], is also selected
by the expected peak amplitude level. Table 14 shows
the line attenuation codes.
Table 14. Line Attenuation Codes
LIATTEN[1:0]
Peak Input
Voltage [mV] Resistance [k]
RIN/LIN Input
00
01
10
11
190
301
416
636
396
100
74
Note that the TX_LINE_INPUT_LEVEL parameter will
affect the high-pass filter characteristics of the ac-
coupling capacitors and the resistance of the audio
inputs.
60
The line attenuation code is chosen by picking the
lowest Peak Input Voltage in Table 14 that is just above
the expected peak input voltage coming from the audio
baseband processor. For example, if the expected peak
input voltage from the audio baseband processor is
400 mV, the user chooses LIATTEN[1:0] = 10 since the
Peak Input Voltage of 416 mV associated with
LIATTEN[1:0] = 10 is just greater than the expected
peak input voltage of 400 mV. The user also enters
400 mV into the LILEVEL[9:0] to associate this input
level to the maximum frequency deviation level
programmed into the audio deviation property. Note that
selecting a particular value of LIATTEN[1:0] changes
the input resistance of the LIN and RIN pins. This
feature is used for cases where the expected peak input
level exceeds the maximum input level of the LIN and
RIN pins.
The Si4710/11 has a programmable low audio level and
high audio level indicators that allows the user to
selectively enable and disable the carrier based on the
presence of audio content. The TX_ASQ_LEVEL_LOW
and TX_ASQ_LEVEL_HIGH parameters set the low
level and high level thresholds in dBFS, respectively.
The time required for the audio level to be below the low
threshold is set with the TX_ASQ_DURATION_LOW
parameter, and similarly, the time required for the audio
level to be above the high threshold is set with the
TX_ASQ_DURATION_HIGH parameter.
Rev. 1.1
23
Si4710/11-B30
Figure 18 shows the time domain characteristics of the
audio dynamic range controller. The attack rate sets the
speed with which the audio dynamic range controller
responds to changes in the input level, and the release
rate sets the speed with which the audio dynamic range
controller returns to no compression once the audio
input level drops below the threshold.
5.5. Audio Dynamic Range Control
The Si4710/11 includes digital audio dynamic range
control with programmable gain, threshold, attack rate,
and release rate. The total dynamic range reduction is
set by the gain value and the audio output compression
above
the
threshold
is
equal
to
Threshold/(Gain + Threshold) in dB. The gain specified
cannot be larger than the absolute value of the
threshold. This feature can also be disabled if audio
compression is not desired.
Threshold
Audio
Input
The audio dynamic range control can be used to reduce
the dynamic range of the audio signal, which improves
the listening experience on the FM receiver. Audio
dynamic range reduction increases the transmit volume
by decreasing the peak amplitudes of audio signals and
increasing the root mean square content of the audio
signal. In other words, it amplifies signals below a
threshold by a fixed gain and compresses audio signals
Audio
Output
above
a
threshold
by
the
ratio
of
Threshold/(Gain + Threshold). Figure 17 shows an
example transfer function of an audio dynamic range
controller with the threshold set at –40 dBFS and a
Gain = 20 dB relative to an uncompressed transfer
function.
Attack
time
Release
time
Figure 18. Time Domain Characteristics of the
Audio Dynamic Range Controller
Input [dBFS]
–90
–80
–70
–60
–50 –40
–30
–20
–10
0
5.6. Audio Limiter
Compression
2:1 dB
The Si4710/11 also includes a digital audio limiter. The
audio limiter prevents over-modulation of the FM
transmit output by dynamically attenuating peaks in the
audio input signal that exceed a programmable
threshold. The limiter threshold is set to the
programmed audio deviation + ten percent. The
threshold ensures that the output signal audio deviation
does not exceed the programmed levels, avoiding
audible artifacts or distortion in the target FM receiver,
and complying with FCC or ETSI regulatory standards.
–10
–20
–30
–40
–50
–60
–70
–80
–90
Threshold
= –40 dB
No
Compression
M = 1
M = 1
Gain
= 20 dB
The limiter performs as a peak detector with an attack
rate set to one audio sample, resulting in an almost
immediate attenuation of the input peak. The recover
rate is programmable to the customer’s preference, and
is set by default to 5 ms. This is the recommended
setting to avoid audible pumping or popping. Please
refer to “AN332: Universal Programming Guide.”
Figure 17. Audio Dynamic Range Transfer
Function
For input signals below the threshold of –40 dBFS, the
output signal is amplified or gained up by 20 dB relative
to an uncompressed signal. Audio inputs above the
threshold are compressed by a 2 to 1 dB ratio, meaning
that every 2 dB increase in audio input level above the
threshold results in an audio output increase of 1 dB. In
this example, the input dynamic range of 90 dB is
reduced to an output dynamic range of 70 dB.
24
Rev. 1.1
Si4710/11-B30
5.7. Pre-Emphasis and De-Emphasis
5.9. Tuning
Pre-emphasis and de-emphasis is a technique used by The frequency synthesizer uses Silicon Laboratories’
FM broadcasters to improve the signal-to-noise ratio of proven technology including a completely integrated
FM receivers by reducing the effects of high-frequency VCO. The frequency synthesizer generates the
interference and noise. When the FM signal is quadrature local oscillator signal used to upconvert the
transmitted,
a
pre-emphasis filter is applied to low intermediate frequency to RF. The VCO frequency
accentuate the high audio frequencies. All FM receivers is locked to the reference clock and adjusted with an
incorporate a de-emphasis filter that attenuates high automatic frequency control (AFC) servo loop during
frequencies to restore a flat frequency response. Two transmission.
time constants are used in various regions. The pre-
emphasis time constant is programmable to 50 or 75 µs
commands. For example, to tune to 98.1 MHz, the user
and is set by using the TX_PREEMPHASIS property.
The tuning frequency can be directly programmed with
writes the TX_TUNE_FREQ command with an
argument = 9810.
5.8. RDS/RBDS Processor (Si4711 Only)
The Si4710/11 supports channel spacing of 50, 100, or
The Si4711 implements an RDS/RBDS* processor for
200 kHz.
symbol encoding, block synchronization, and error
correction. Digital data can be transmitted with the
Si4711 RDS/RBDS encoding feature.
5.10. Reference Clock
The Si4710/11 reference clock is programmable,
RDS transmission is supported with three different
supporting RCLK frequencies from 31.130 kHz to
modes. The first mode is the simplest mode and
40 MHz. The RCLK frequency divided by an integer
requires no additional user support except for pre-
number (the prescaler value) must fall in the range of
loading the desired RDS PI and PTY codes and up to
31,130 to 34,406 Hz. Therefore, the range of RCLK
12 8-byte PS character strings. The Si4711 will transmit
frequencies is not continuous below frequencies of
the PI code and rotate through the transmission of the
311.3 kHz. The default RCLK frequency is 32.768 kHz.
PS character strings with no further control required
Please refer to “AN332: Universal Programming Guide”
from outside the device. The second mode allows for
for using other RCLK frequencies.
more complicated transmissions. The PI and PTY
codes are written to the device as in mode 1. The 5.11. Control Interface
remaining blocks (B, C, and D) are written to a 252 byte
A serial port slave interface is provided; this allows an
buffer. This buffer can hold 42 sets of BCD blocks. The
external controller to send commands to the Si4710/11
Si4711 creates RDS groups by creating block A from
and receive responses from the device. The serial port
the PI code, concatenating blocks BCD from the buffer,
can operate in three bus modes: 2-wire mode, SPI
and rotating through the buffer. The BCD buffer is
mode, or 3-wire mode. The Si4710/11 selects the bus
circular; so, the pattern is repeated until the buffer is
mode by sampling the state of the GPO1 and
changed. Finally, the third mode allows the outside
GPO2/INT pins on the rising edge of RST. The GPO1
controller to burst data into the BCD buffer, which
pin includes an internal pull-up resistor that is
emulates a FIFO. The data does not repeat, but, when
connected while RST is low, and the GPO2/INT pin
the buffer is nearly empty, the Si4711 signals the
includes an internal pull-down resistor that is connected
outside device to initiate another data burst. This mode
while RST is low. Therefore, it is only necessary for the
permits the outside device to use any RDS functionality
user to actively drive pins that differ from these states.
(including open data applications) that it wants.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
Rev. 1.1
25
Si4710/11-B30
from the Si4710/11.
Table 15. Bus Mode Select on Rising Edge of
RST
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
Bus Mode
2-Wire
SPI
GPO1
GPO2/INT
to
Table 5,
“2-Wire
Control
Interface
1
0
1,2,3
Characteristics
,” on page 7, Figure 2, “2-Wire
1
1 (must drive)
0
Control Interface Read and Write Timing Parameters,”
on page 8, and Figure 3, “2-Wire Control Interface Read
and Write Timing Diagram,” on page 8.
3-Wire
0 (must drive)
After the rising edge of RST, the pins, GPO1 and 5.11.2. SPI Control Interface Mode
GPO2/INT, are used as general-purpose output (O) pins
as described in Section “5.12. GPO Outputs”. In any
When selecting SPI mode, the user must ensure that a
rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
bus mode, commands may only be sent after V and
IO
V
supplies are applied.
DD
SPI bus mode uses the SCLK, SDIO, and SEN pins for
read/write operations. For reads, the user can choose to
receive data from the device on either SDIO or GPO1. A
transaction begins when the user drives SEN low. The
user then pulses SCLK eight times while driving an 8-bit
control byte (MSB first) serially on SDIO. The device
captures the data on rising edges of SCLK. The control
byte must have one of these values:
5.11.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
2-wire bus mode uses only the SCLK and SDIO pins for
signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a seven bit
device address followed by a read/write bit (read = 1,
write = 0). The Si4710/11 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
0x48 = write eight command/argument bytes (user
drives write data on SDIO)
0x80 = read status byte (device drives read data on
SDIO)
0xA0 = read status byte (device drives read data on
GPO1)
0xC0 = read 16 response bytes (device drives read data
on SDIO)
0xE0 = read 16 response bytes (device drives read data
on GPO1)
Although the Si4710/11 responds to only a single device
address, this address can be changed with the SEN pin
(note that the SEN pin is not used for signaling in 2-wire
mode). When SEN = 0, the seven-bit device address is
0010001. When SEN = 1, the address is 1100011.
When writing a command, after the control byte has
been written, the user must drive exactly eight data
bytes (a command byte and seven argument bytes) on
SDIO. The data will be captured by the device on the
rising edges of SCLK. After all eight data bytes have
been written, the user raises SEN after the last falling
edge of SCLK to end the transaction.
For write operations, the user then sends an eight bit
data byte on SDIO, which is captured by the device on
rising edges of SCLK. The Si4710/11 acknowledges
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to
eight data bytes in a single two-wire transaction. The
first byte is a command, and the next seven bytes are
arguments.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high). In SPI
mode, this is done by sending control byte 0x80 or
0xA0, followed by reading a single byte on SDIO or
GPO1. The Si4710/11 changes the state of SDIO or
GPO1 after the falling edges of SCLK. Data should be
captured by the user on the rising edges of SCLK. After
the status byte has been read, the user raises SEN after
the last falling edge of SCLK to end the transaction.
For read operations, after the Si4710/11 has
acknowledged the control byte, it drives an eight-bit
data byte on SDIO, changing the state of SDIO on the
falling edge of SCLK. The user acknowledges each data
byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. If
a
data byte is not
When reading a response, the user must read exactly
16 data bytes after sending the control byte. It is
recommended that the user keep SEN low until all bytes
acknowledged, the transaction ends. The user may
read up to 16 data bytes in a single two-wire
transaction. These bytes contain the response data
26
Rev. 1.1
Si4710/11-B30
have transferred. However, it will not disrupt the
protocol if SEN temporarily goes high at any time, as
long as the user does not change the state of SCLK
while SEN is high. After 16 bytes have been read, the
user raises SEN after the last falling edge of SCLK to
end the transaction.
5.12. GPO Outputs
The Si4710/11 provides three general-purpose output
pins. The GPO pins can be configured to output a
constant low, constant high, or high-Z. The GPO pins
are multiplexed with the bus mode pins or DCLK
depending on the application schematic of the
transmitter. GPO2/INT can be configured to provide
interrupts.
At the end of any SPI transaction, the user must drive
SEN high after the final falling edge of SCLK. At any
time during a transaction, if SEN is sampled high by the
device on a rising edge of SCLK, the transaction will be
aborted. When SEN is high, SCLK may toggle without
affecting the device.
5.13. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
For details on timing specifications and diagrams, refer disable the bus. Setting the RST pin high will bring the
to Figure 6 and Figure 7 on page 10.
device out of reset and place it in powerdown mode.
5.11.3. 3-Wire Control Interface Mode
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry
and keep the bus active. For more information
concerning Reset, Powerup, Powerdown, and
Initialization, refer to “AN332: Universal Programming
Guide”.
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
3-wire bus mode uses the SCLK, SDIO and SEN pins.
A transaction begins when the system controller drives
SEN low. Next, the system controller drives a 9-bit
control word on SDIO, which is captured by the device
on rising edges of SCLK. The control word is comprised
of a three bit chip address (A7:A5 = 101b), a read/write
bit (write = 0, read = 1), the chip address (A4 = 0), and a
four bit register address (A3:A0).
5.14. Programming with Commands
To ease development time and offer maximum
customization, the Si4710/11 provides a simple yet
powerful software interface to program the transmitter.
The device is programmed using commands,
arguments, properties, and responses.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
To perform an action, the user writes a command byte
and associated arguments causing the chip to execute
the given command. Commands control actions, such
as powering up the device, shutting down the device, or
tuning to a station. Arguments are specific to a given
command and are used to modify the command. For
example, after the TX_TUNE_FREQ command,
arguments are required to set the tune frequency. A
complete list of commands is available in Table 16,
“Si471x Command Summary,” on page 28.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turnaround. Next,
the Si4710/11 drives the 16-bit read data word serially
on SDIO, changing the state of SDIO on each rising
edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
properties
are
TX_PREEMPHASIS
and
GPO_CONFIGURE. A complete list of properties is
available in Table 17, “Si471x Property Summary,” on
page 29.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 9, Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. At a minimum, all commands provide a one-byte
status update indicating interrupt and clear-to-send
status information. For a detailed description of using
the commands and properties of the Si4710/11, see
“AN332: Universal Programming Guide.”
Rev. 1.1
27
Si4710/11-B30
6. Commands and Properties
Table 16. Si471x Command Summary
Cmd
Name
Description
Power up device and mode selection. Modes include FM transmit
and analog/digital audio interface configuration.
0x01
POWER_UP
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x30
0x31
GET_REV
Returns revision information on the device.
Power down device.
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
GET_INT_STATUS
PATCH_ARGS
Sets the value of a property.
Retrieves a property’s value.
Read interrupt status bits.
Reserved command used for patch file downloads.
Reserved command used for patch file downloads.
Tunes to given transmit frequency.
PATCH_DATA
TX_TUNE_FREQ
TX_TUNE_POWER
Sets the output power level and tunes the antenna capacitor
Queries the status of a previously sent TX Tune Freq, TX Tune
Power, or TX Tune Measure command.
0x33
0x34
0x35
TX_TUNE_STATUS
TX_ASQ_STATUS
TX_RDS_BUFF
Queries the TX status and input audio signal metrics.
Si4711 Only. Queries the status of the RDS Group Buffer and loads
new data into buffer.
0x36
0x80
0x81
TX_RDS_PS
GPO_CTL
GPO_SET
Si4711 Only. Set up default PS strings.
Configures GPO3 as output or Hi-Z.
Sets GPO3 output level (low or high).
28
Rev. 1.1
Si4710/11-B30
Table 17. Si471x Property Summary
Prop
Name
Description
Default
0x0001
0x0101
GPO_IEN
Enables interrupt sources.
0x0000
0x0000
DIGITAL_INPUT _FORMAT
Configures the digital input format.
Configures the digital input sample rate in 10 Hz steps.
Default is 0.
0x0103 DIGITAL_INPUT _SAMPLE_RATE
0x0000
Sets frequency of the reference clock in Hz. The range is
31130 to 34406 Hz, or 0 to disable the AFC. Default is
32768 Hz.
0x0201
REFCLK_FREQ
0x8000
0x0202
0x2100
REFCLK_PRESCALE
Sets the prescaler value for the reference clock.
0x0001
0x0003
Enable transmit multiplex signal components.
Default has pilot and L-R enabled.
TX_COMPONENT_ENABLE
Configures audio frequency deviation level. Units are in
10 Hz increments. Default is 6285 (68.25 kHz).
0x2101
0x2102
TX_AUDIO_DEVIATION
TX_PILOT_DEVIATION
0x1AA9
0x02A3
Configures pilot tone frequency deviation level. Units are
in 10 Hz increments. Default is 675 (6.75 kHz)
Si4711 Only. Configures the RDS/RBDS frequency
0x2103
0x2104
TX_RDS_DEVIATION
deviation level. Units are in 10 Hz increments. Default is 0x00C8
2 kHz.
Configures maximum analog line input level to the
LIN/RIN pins to reach the maximum deviation level pro-
grammed into the audio deviation property TX Audio
TX_LINE_INPUT_LEVEL
0x327C
Deviation. Default is 636 mV
.
PK
Sets line input mute. L and R inputs may be indepen-
dently muted. Default is not muted.
0x2105
0x2106
0x2107
0x2200
0x2201
0x2202
0x2203
TX_LINE_INPUT_MUTE
TX_PREEMPHASIS
0x0000
0x0000
0x4A38
0x0002
0xFFD8
0x0000
0x0004
Configures pre-emphasis time constant.
Default is 0 (75 µS).
Configures the frequency of the stereo pilot. Default is
19000 Hz.
TX_PILOT_FREQUENCY
TX_ACOMP_ENABLE
Enables audio dynamic range control.
Default is 0 (disabled).
Sets the threshold level for audio dynamic range control.
Default is –40 dB.
TX_ACOMP_THRESHOLD
TX_ACOMP_ATTACK_TIME
TX_ACOMP_RELEASE_TIME
Sets the attack time for audio dynamic range control.
Default is 0 (0.5 ms).
Sets the release time for audio dynamic range control.
Default is 4 (1000 ms).
Sets the gain for audio dynamic range control.
Default is 15 dB.
0x2204
0x2205
TX_ACOMP_GAIN
0x000F
0x0066
0x0000
TX_LIMITER_RELEASE_TIME
Sets the limiter release time. Default is 102 (5.01 ms)
Configures measurements related to signal quality met-
rics. Default is none selected.
0x2300 TX_ASQ_INTERRUPT_SOURCE
Configures low audio input level detection threshold.
This threshold can be used to detect silence on the
incoming audio.
0x2301
TX_ASQ_LEVEL_LOW
0x0000
Rev. 1.1
29
Si4710/11-B30
Table 17. Si471x Property Summary (Continued)
Prop
Name
Description
Default
Configures the duration which the input audio level must
0x2302
TX_ASQ_DURATION_LOW
be below the low threshold in order to detect a low audio 0x0000
condition.
Configures high audio input level detection threshold.
0x2303
0x2304
TX_ASQ_LEVEL_HIGH
This threshold can be used to detect activity on the
incoming audio.
0x0000
0x0000
Configures the duration which the input audio level must
be above the high threshold in order to detect a high
audio condition.
TX_ASQ_DURATION_HIGH
Si4711 Only. Configure RDS interrupt sources. Default
is none selected.
0x2C00 TX_RDS_INTERRUPT_SOURCE
0x0000
0x40A7
0x0003
0x2C01
0x2C02
TX_RDS_PI
Si4711 Only. Sets transmit RDS program identifier.
Si4711 Only. Configures mix of RDS PS Group with
RDS Group Buffer.
TX_RDS_PS_MIX
Si4711 Only. Miscellaneous bits to transmit along with
RDS_PS Groups.
0x2C03
TX_RDS_PS_MISC
0x1008
Si4711 Only. Number of times to repeat transmission of
0x2C04 TX_RDS_PS_REPEAT_COUNT a PS message before transmitting the next PS mes-
sage.
0x0003
0x0001
0x2C05 TX_RDS_PS_MESSAGE_COUNT Si4711 Only. Number of PS messages in use.
Si4711 Only. RDS Program Service Alternate Fre-
quency. This provides the ability to inform the receiver of
a single alternate frequency using AF Method A coding
and is transmitted along with the RDS_PS Groups.
0x2C06
0x2C07
TX_RDS_PS_AF
0xE0E0
0x0000
Si4711 Only. Number of blocks reserved for the FIFO.
Note that the value written must be one larger than the
desired FIFO size.
TX_RDS_FIFO_SIZE
30
Rev. 1.1
Si4710/11-B30
7. Pin Descriptions: Si4710/11-GM
20 19 18 17
NC 1
NC 2
16
15 RIN
14 DFS
13 DIN
12 GND
11 VDD
RFGND 3
TXO 4
RST 5
6
GND
PAD
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 2, 20
No connect. Leave floating.
RF ground. Connect to ground plane on PCB.
3
RFGND
TXO
4
FM transmit output connection to transmit antenna.
Device reset (active low) input.
Serial enable input (active low).
Serial clock input.
5
RST
6
SEN
7
SCLK
SDIO
RCLK
8
Serial data input/output.
9
External reference oscillator input.
I/O supply voltage.
10
V
IO
11
V
Supply voltage. May be connected directly to battery.
Digital input data.
DD
13
DIN
DFS
RIN
LIN
14
Digital frame synchronization input.
Right audio line input.
15
16
Left audio line input.
17
GPO3/DCLK General purpose output/digital bit synchronous clock input.
18
19
General purpose output/interrupt request.
General purpose output.
GPO2/INT
GPO1
12, GND PAD
GND
Ground. Connect to ground plane on PCB.
Rev. 1.1
31
Si4710/11-B30
8. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4710-B30-GM Portable broadcast FM transmitter
QFN
–20 to 85 °C
Pb-free
Si4711-B30-GM Portable broadcast FM transmitter with RDS/RBDS
encoder
QFN
Pb-free
–20 to 85 °C
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
32
Rev. 1.1
Si4710/11-B30
9. Package Markings (Top Marks)
9.1. Si4710 Top Mark
Figure 19. Si4710 Top Mark
9.2. Si4711 Top Mark
Figure 20. Si4711 Top Mark
9.3. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
10 = Si4710
11 = Si4711
Firmware Revision
R = Die Revision
30 = Firmware Revision 30
B = Revision B Die
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the last sig-
nificant digit of the year and workweek of the mold date.
Rev. 1.1
33
Si4710/11-B30
10. Package Outline: Si4710/11-GM
Figure 21 illustrates the package details for the Si4710/11. Table 18 lists the values for the dimensions shown in
the illustration.
Figure 21. 20-Pin Quad Flat No-Lead (QFN)
Table 18. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
34
Rev. 1.1
Si4710/11-B30
11. PCB Land Pattern: Si4710/11-GM
Figure 22 illustrates the PCB land pattern details for the Si4710/11-GM. Table 19 lists the values for the dimensions
shown in the illustration.
Figure 22. PCB Land Pattern
Rev. 1.1
35
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Table 19. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification.
3. This land pattern design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a fabrication allowance of 0.05 mm.
Note: Solder Mask Design
1. All metal pads are to be non-solder-mask-defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 mm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component standoff.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for small body components.
36
Rev. 1.1
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12. Additional Reference Resources
Si47xx-Evaluation Board User’s Guide
AN309: Si4710/11/12/13 Evaluation Board Quick-Start Guide
AN332: Universal Programming Guide
AN383: Universal Antenna Selection and Layout Guidelines
AN388: Universal Evaluation Board Test Procedure
Si4710/11/12/13 Customer Support Site: http://www.mysilabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, send mysilabs user name and request for access to
fminfo@silabs.com.
Rev. 1.1
37
Si4710/11-B30
NOTES:
38
Rev. 1.1
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DOCUMENT CHANGE LIST
Revision 0.5 to Revision 1.1
Updated Table 9 on pages 12 and 13
Corrected typo in Section 5.3.2 on page 21.
Updated references to new application notes
throughout document.
Updated Table 3 on page 5.
Updated production test condition in Table 9 on
page 12.
Rev. 1.1
39
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