SI4738-C40 [SILICON]
BROADCAST AM/FM RADIO RECEIVER;
| 型号： | SI4738-C40 |
| 厂家： | 
SILICON |
| 描述： | BROADCAST AM/FM RADIO RECEIVER |
| 文件： | 总42页 (文件大小：1513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4736/37/38/39-C40
BROADCAST AM/FM RADIO RECEIVER
Features
NOAA weather band support
(162.4–162.55 MHz)
Worldwide FM band support
(64–108 MHz)
AM/FM/WB digital tuning
No manual alignment necessary
Programmable reference clock
Volume control
Worldwide AM band support
(520–1710 kHz) (Si4736/37)
1050 Hz alert tone detection
Excellent real-world performance
Freq synthesizer with integrated VCO
Advanced AM/FM seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Programmable AVC max gain
Programmable de-emphasis
Adjustable soft mute control
RDS/RBDS processor (Si4737/39)
Optional digital audio out (Si4737/39)
2-wire and 3-wire control interface
Integrated LDO regulator
2.0 to 5.5 V supply voltage (SSOP)
2.7 to 5.5 V supply voltage (QFN)
Wide range of ferrite loop sticks and
air loop antennas supported
Ordering Information:
See page 32.
Pin Assignments
Si4736/37/38/39 (QFN)
QFN and SSOP packages
RoHS compliant
Applications
20 19 18 17
NC
FMI
1
16
2
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
Emergency radios
Table and portable radios
Stereos
Boom boxes
Modules
Clock radios
Mini HiFi
RFGND
AMI
3
4
5
GND
PAD
Mini/micro systems
RST
6
7
8
9
10
Description
The Si4736/37/38/39 is the first digital CMOS AM/FM radio receiver IC that
integrates the complete tuner function from antenna input to audio output.
Si4736/37 (SSOP)
DOUT
1
2
24
23
22
21
20
19
18
17
16
15
14
13
LOUT
ROUT
Functional Block Diagram
DFS
GPO3/DCLK
GPO2/INT
GPO1
NC
3
DBYP
VDD
VIO
4
5
Si473x
RCLK
SDIO
SCLK
SEN
6
AMI
RDS
(Si4737/
39)
DIGITAL
AUDIO
(Si4737/
39)
DOUT
NC
7
AM
LNA
AGC
ANT
RFGND
FMI
8
DFS
RFGND
NC
9
GPO/DCLK
LOW-IF
RST
10
11
12
NC
GND
GND
FM/
WB
ANT
ADC
ADC
DAC
DAC
ROUT
LOUT
AMI
LNA
AGC
DSP
FMI
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both foreign
and domestic: 7,127,217; 7,272,373;
2.7– 5.5 V (QFN)
2.0– 5.5 V (SSOP)
VDD
GND
CONTROL
INTERFACE
LDO
AFC
VIO
1.85–3.6 V
7,272,375;
7,426,376;
7,339,504.
7,321,324;
7,471,940;
7,355,476;
7,339,503;
Rev. 1.0 12/09
Copyright © 2009 by Silicon Laboratories
Si4736/37/38/39-C40
Si4736/37/38/39-C40
2
Rev. 1.0
Si4736/37/38/39-C40
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Typical Application Schematic (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Bill of Materials (QFN/SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.5. Weather Band Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.6. Digital Audio Interface (Si4737/39 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.7. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.8. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.9. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.10. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.11. RDS/RBDS Processor (Si4737/39 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.12. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.13. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.14. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.15. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.16. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.17. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.18. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.19. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7. Pin Descriptions: Si4736/37/38/39-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Pin Descriptions: Si4736/37-GU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.1. Si4736/37/38/39 Top Mark (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.2. Top Mark Explanation (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.3. Si4736/37 Top Mark (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
10.4. Top Mark Explanation (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11. Package Outline: Si4736/37/38/39 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
12. PCB Land Pattern: Si4736/37/38/39 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
13. Package Outline: Si4736/37 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14. PCB Land Pattern: Si4736/37 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
15. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Rev. 1.0
3
Si4736/37/38/39-C40
1. Electrical Specifications
Table 1. Recommended Operating Conditions1
Parameter
Symbol Test Condition
Min
2.7
1.85
10
Typ
—
Max
5.5
3.6
—
Unit
V
2
Supply Voltage
V
DD
Interface Supply Voltage
V
—
V
IO
DDRISE
Power Supply Powerup Rise Time
Interface Power Supply Powerup Rise Time
V
—
µs
µs
C
V
10
—
—
IORISE
Ambient Temperature
T
–20
25
85
A
Note:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
VDD = 3.3 V and 25 C unless otherwise stated.
2. SSOP devices operate down to VDD = 2 V at 25 °C.
Table 2. Absolute Maximum Ratings1,2
Parameter
Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
DD
Interface Supply Voltage
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
T
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
–40 to 95
–55 to 150
0.4
C
C
OP
T
STG
4
RF Input Level
V
PK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4736/37/38/39 devices are high-performance RF integrated circuits with certain pins having an ESD rating of <
2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, and DCLK.
4. At RF input pins, FMI and AMI.
4
Rev. 1.0
Si4736/37/38/39-C40
Table 3. DC Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Mode
1
Supply Current
Supply Current
I
I
I
—
—
—
19.2
19.9
19.2
22
23
23
mA
mA
mA
FM
FM
FM
2
Low SNR level
1
RDS Supply Current
WB Mode
1
Supply Current
I
I
—
—
19.2
19.8
22
23
mA
mA
FM
Supply Current
Low SNR level
FM
AM Mode
1
Supply Current
I
Analog Output Mode
—
15.4
20.5
mA
AM
Supplies and Interface
Interface Supply Current
I
—
—
320
10
1
600
20
µA
µA
µA
V
IO
V
V
Powerdown Current
I
DDPD
DD
Powerdown Current
I
SCLK, RCLK inactive
—
10
IO
IOPD
3
High Level Input Voltage
V
0.7 x V
–0.3
–10
—
—
—
—
V
+ 0.3
IO
IH
IO
3
Low Level Input Voltage
V
0.3 x V
10
V
IL
IO
3
High Level Input Current
I
V
= V = 3.6 V
µA
µA
IH
IN
IO
3
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V
= 3.6 V
IO
4
High Level Output Voltage
V
I
= 500 µA
= –500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
IO
4
Low Level Output Voltage
V
I
0.2 x V
OL
OUT
IO
Notes:
1. Specifications are guaranteed by characterization.
2. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, and DCLK.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4736/37/38/39-C40
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tHRST
tSRST
70%
30%
RST
70%
30%
GPO1
70%
30%
GPO2/
INT
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.0
Si4736/37/38/39-C40
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.85 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold
0.6
—
—
µs
HD:STA
(START)
SDIO Input to SCLK Setup
t
t
100
0
—
—
—
—
900
—
ns
ns
µs
SU:DAT
4,5
SDIO Input to SCLK Hold
HD:DAT
SU:STO
SCLK input to SDIO Setup
t
0.6
(STOP)
STOP to START Time
SDIO Output Fall Time
t
1.3
—
—
—
µs
ns
BUF
t
250
f:OUT
Cb
----------
1pF
20 + 0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
r:IN
Cb
----------
1pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4736/37/38/39 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the
minimum tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
Rev. 1.0
7
Si4736/37/38/39-C40
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
SCLK
SDIO
70%
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
D7-D0
D7-D0
SDIO
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
Si4736/37/38/39-C40
Table 6. 3-Wire Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
20
10
10
2
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLKHold
t
—
ns
HSEN
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4736/37/38/39-C40
Table 7. SPI Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
15
10
5
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLKHold
t
—
ns
HSEN
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
Read
Read
2
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHIGH
tLOW
tHSDIO
tHSEN
70%
30%
tS
SEN
tS
70%
30%
C7
C6–C1
C0
D7
D6–D1
D0
SDIO
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
70%
30%
SCLK
tCDV
tS
tHSEN
tHSDIO
70%
30%
tS
SEN
tCDZ
70%
30%
SDIO
C7
C6–C1
C0
D7
D6–D1
D0
16 Data Bytes Out
(SDIO or GPO1)
Bus
Turnaround
Control Byte In
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.0
Si4736/37/38/39-C40
Table 8. Digital Audio Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
12
ns
PD:DOUT
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.0
11
Si4736/37/38/39-C40
Table 9. FM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
76
Typ
—
Max
108
3.5
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone Net-
(S+N)/N = 26 dB
(S+N)/N = 26 dB
—
2.2
µV EMF
3,4,5
work
3,4,5,6
Sensitivity with 50 Network
—
—
1.1
15
—
—
µV EMF
µV EMF
6
RDS Sensitivity
f = 2 kHz,
RDS BLER < 5%
6,7
LNA Input Resistance
3
4
4
5
5
6
k
6,7
LNA Input Capacitance
pF
6,8
Input IP3
100
40
35
60
35
72
—
—
15
32
55
—
—
70
45
105
50
50
70
—
—
—
—
—
—
90
1
dBµV EMF
3,4,6,7
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
6
3,4,7
80
—
mV
Audio Output Voltage
RMS
3,7,9
dB
Hz
kHz
dB
dB
dB
%
Audio Output L/R Imbalance
Audio Frequency Response Low
6
–3 dB
–3 dB
—
30
—
—
—
—
0.5
80
54
6
—
Audio Frequency Response High
7,9
42
63
58
0.1
75
50
Audio Stereo Separation
3,4,5,7,10
Audio Mono S/N
4,5,6,7,10,11
Audio Stereo S/N
3,7,9
Audio THD
6
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
µs
µs
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).
12
Rev. 1.0
Si4736/37/38/39-C40
Table 9. FM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
f = ±400 kHz
Min
—
Typ
32
38
40
35
—
Max
—
Unit
dBµV
dBµV
dBµV
dBµV
k
3,4,5,6,12,13
Blocking Sensitivity
f = ±4 MHz
—
—
3,4,5,6,12,13
Intermode Sensitivity
f = ±400 kHz, ±800 kHz
f = ±4 MHz, ±8 MHz
Single-ended
—
—
—
—
6,10
R
10
—
—
Audio Output Load Resistance
L
6,10
C
Single-ended
—
50
60
pF
Audio Output Load Capacitance
L
6
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
ms/channel
6
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
14
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).
Rev. 1.0
13
Si4736/37/38/39-C40
Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
64
Typ
—
Max
75.9
—
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone Net-
(S+N)/N = 26 dB
—
4.0
µV EMF
3,4,5
work
7
LNA Input Resistance
3
4
4
5
5
6
k
7
LNA Input Capacitance
pF
dBµV EMF
dB
8
Input IP3
100
40
—
—
72
—
—
15
55
—
70
45
10
—
—
105
50
50
70
80
—
—
—
63
0.1
75
50
—
—
—
—
—
—
—
90
1
3,4,7
m = 0.3
±200 kHz
±400 kHz
AM Suppression
dB
Adjacent Channel Selectivity
Alternate Channel Selectivity
dB
3,4,7
mV
Audio Output Voltage
RMS
3,7,9
dB
Audio Output L/R Imbalance
–3 dB
–3 dB
30
—
—
0.5
80
54
—
50
60
Hz
Audio Frequency Response Low
Audio Frequency Response High
kHz
3,4,5,7,10
dB
Audio Mono S/N
3,7,9
%
Audio THD
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
k
10
R
Audio Output Load Resistance
L
L
10
C
Single-ended
pF
Audio Output Load Capacitance
Seek/Tune Time
RCLK tolerance
= 100 ppm
ms/channel
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
11
RSSI Offset
Input levels of 8 and
60 dBµV EMF
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. At temperature (25 °C).
14
Rev. 1.0
Si4736/37/38/39-C40
Table 11. WB Receiver Characteristics1
(V = 2.7 to 5.5 V, VIO = 1.85 to 3.6V, T = 25 °C)
DD
A
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
f
162.4
—
162.55
MHz
R
Input Frequency
2,3
SINAD = 12 dB
±25 kHz
Mono
—
—
—
—
3
0.9
52
45
—
—
—
µV EMF
dB
Sensitivity
Adjacent Channel Selectivity
2,3,4,5
—
dB
Audio S/N
6
–3 dB
300
—
Hz
Audio Frequency Response Low
6
–3 dB
—
kHz
Audio Frequency Response High
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. F
= 1 kHz.
MOD
3. f = 3 kHz.
4. V = 1 mV.
EMF
5. A-weighted.
6. Guaranteed by characterization
Table 12. AM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
520
—
Typ
—
Max
1710
35
Unit
kHz
Input Frequency
f
RF
3,4,5,6
Sensitivity
(S+N)/N = 26 dB
THD < 8%
25
µV EMF
Large Signal Voltage Han-
—
300
—
mV
RMS
4,,6,7
dling
6
Power Supply Rejection Ratio
∆V = 100 mVRMS, 100 Hz
—
54
50
—
40
60
56
0.1
—
67
—
dB
DD
3,4,8
Audio Output Voltage
mV
RMS
3,4,5,8
Audio S/N
dB
3,4,8
Audio THD
0.5
%
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 520 kHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter.
4. Analog audio output mode.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method.
8. V = 5 mVrms.
IN
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
Rev. 1.0
15
Si4736/37/38/39-C40
Table 12. AM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
6,9
Antenna Inductance
180
—
—
—
450
110
µH
ms
6
Powerup Time
From powerdown
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 520 kHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter.
4. Analog audio output mode.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method.
8. V = 5 mVrms.
IN
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
Table 13. Reference Clock and Crystal Characteristics
(V = 2.7 to 5.5 V, V = 1.85 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
1
RCLK Supported Frequencies
31.130
–50
1
32.768
—
40,000
50
kHz
2
RCLK Frequency Tolerance
ppm
REFCLK_PRESCALE
—
4095
REFCLK
31.130
32.768
34.406
kHz
Crystal Oscillator
Crystal Oscillator Frequency
—
–50
—
32.768
—
—
50
kHz
ppm
pF
2
Crystal Frequency Tolerance
Board Capacitance
—
3.5
Notes:
1. The Si4736/37/38/39 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx
Programming Guide”.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing and WB tune.
16
Rev. 1.0
Si4736/37/38/39-C40
2. Typical Application Schematic (QFN)
GPO1
GPO2/INT
R1
GPO3/DCLK
R2
DFS
R3
15
DOUT
DOUT
Optional: Digital Audio Output
1
NC
2
FMI
FMIP
L1
14
13
12
11
LOUT
ROUT
LOUT/DFS
ROUT/DOUT
GND
3
RFGND
U1
Si4736/37/38/39-GM
4
5
AMI
AM antenna
Si4736/37 only
VDD
C5
RST
VBATTERY
2.7 to 5.5 V
C1
RST
SEN
X1
GPO3
RCLK
C3
SCLK
SDIO
RCLK
VIO
C2
Optional: for crystal oscillator option
1.85 to 3.6 V
L2
RFGND
AMI
T1
C5
Optional: AM air loop antenna
Notes:
1. Place C1 close to V pin.
DD
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. Place Si4736/37/38/39 as close as possible to antenna and keep the FMI and AMI traces as short as possible.
Rev. 1.0
17
Si4736/37/38/39-C40
3. Typical Application Schematic (SSOP)
Optional: Digital Audio Output
R3
DOUT
DFS
1
24
23
22
21
20
19
18
17
16
15
14
13
LOUT
ROUT
C4
R2
R1
2
DBYP
VDD
VIO
3
GPO3/DCLK
C1
2.0 to 5.5 V
4
GPO2/INT
GPO1
1.85 to 3.6 V
5
NC
6
RCLK
SDIO
NC
7
8
SCLK
SEN
RST
FMI
RFGND
NC
9
10
11
12
L1
AM antenna
NC
GND
AMI
Si4736/37 only
C5
X1
F2
GPIO3
RCLK
RFGND
AMI
C2
C3
T1
C5
Optional: for crystal oscillator option
Optional: AM air loop antenna
Notes:
1. Place C1 close to V and DBYP pins.
DD
2. All grounds connect directly to GND plane on PCB.
3. Pins 6 and 7 are no connects, leave floating.
4. Pins 10 and 11 are unused. Tie these pins to GND.
5. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
6. Pin 8 connects to the FM antenna interface, and pin 12 connects to the AM antenna interface.
7. Place Si4736/37/38/39 as close as possible to antenna and keep the FMI and AMI traces as short as possible.
18
Rev. 1.0
Si4736/37/38/39-C40
4. Bill of Materials (QFN/SSOP)
Component(s)
Value/Description
Supplier
Murata
C1
C5
L1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R
Ferrite loop stick, 180–450 µH
Murata
Jiaxin
U1
Si4736/37/38/39 AM/FM Radio Tuner
Optional Components
Silicon Laboratories
T1
L2
Transformer, 1–5 turns ratio
Jiaxin, UMEC
Various
Air loop antenna, 10–20 µH
C2, C3
Crystal load capacitors, 22 pF, ±5%, COG
(Optional for crystal oscillator option)
Venkel
C4
X1
R1
R2
R3
Noise mitigating capacitor, 2~5 pF(Optional for digital audio)
32.768 kHz crystal (Optional for crystal oscillator option)
Resistor, 2 k(Optional for digital audio)
Murata
Epson
Venkel
Venkel
Venkel
Resistor, 2 k(Optional for digital audio)
Resistor, 600 (Optional for digital audio)
Rev. 1.0
19
Si4736/37/38/39-C40
5. Functional Description
5.1. Overview
Si473x
AMI
RDS
(Si4737/
39)
DIGITAL
AUDIO
(Si4737/
39)
DOUT
AM
LNA
ANT
RFGND
DFS
GPO/DCLK
AGC
LOW-IF
FM/
WB
ANT
ADC
ADC
DAC
DAC
ROUT
LOUT
LNA
AGC
DSP
FMI
2.7– 5.5 V (QFN)
2.0– 5.5 V (SSOP)
VDD
GND
CONTROL
INTERFACE
LDO
AFC
VIO
1.85–3.6 V
Figure 9. Functional Block Diagram
The Si4736/37 and Si4738/39 are the industry's first offers both the manufacturer and the end-user
fully integrated, 100% CMOS AM/FM/WB and FM/WB extensive programmability and flexibility in listening
radio receiver ICs. Offering unmatched integration and experience.
PCB space savings, the Si4736/37/38/39 requires only
The Si4737/39 incorporates a digital processor for the
2
two external components and less than 15 mm of
European Radio Data System (RDS) and the North
board area, excluding the antenna inputs. The
American Radio Broadcast Data System (RBDS), and
Si4736/37/38/39 AM/FM/WB radio provides the space
includes all required symbol decoding, block
savings and low power consumption necessary for
synchronization, error detection, and error correction
portable devices while delivering the high performance
functions. Using this feature, the Si4737/39 enables
and design simplicity desired for all AM/FM/WB
broadcast data such as station identification and song
name to be displayed to the user.
solutions.
Leveraging Silicon Laboratories' proven and patented
Si4700/01 FM tuner's digital low intermediate frequency
5.2. Operating Modes
(low-IF) receiver architecture, the Si4736/37/38/39 The Si4736/37/38/39 operates in an FM receive, an AM
delivers superior RF performance and interference receive, or a weather band receive mode. In FM mode
rejection in both AM and FM bands. The high integration and WB mode, radio signals are received on FMI and
and complete system production test simplifies design- processed by the FM front-end circuitry. In AM mode,
in, increases system quality, and improves radio signals are received on AMI and processed by the
manufacturability.
AM front-end circuitry. In addition to the receiver mode,
there is a clocking mode to choose to clock the
Si4736/37/38/39 from a reference clock or crystal. On
the Si4731, there is an audio output mode to choose
between an analog and/or digital audio output. In the
analog audio output mode, ROUT and LOUT are used
for the audio output pins. In the digital audio mode,
DOUT, DFS, and DCLK pins are used. Concurrent
analog/digital audio output mode is also available
requiring all five pins. The receiver mode and the audio
output mode are set by the POWER_UP command
listed in Table 15, “Selected Si473x Commands,” on
page 27.
The Si4736/37/38/39 is a feature-rich solution including
1050 Hz tone detection, advanced seek algorithms, soft
mute, auto-calibrated digital tuning, and FM stereo
processing. In addition, the Si4736/37/38/39 provides
analog and digital audio outputs and a programmable
reference clock. The device supports I C-compatible, 2-
wire control interface, SPI, and a Si4700/01 backwards-
compatible, 3-wire control interface.
2
The Si4736/37/38/39 utilizes digital processing to
achieve high fidelity, optimal performance, and design
flexibility. The chip provides excellent pilot rejection,
selectivity, and unmatched audio performance, and
20
Rev. 1.0
Si4736/37/38/39-C40
The AFC locks on to the strongest signal within a
narrow, adjustable frequency range to compensate for
any potential frequency errors such as crystal tolerance
or transmit frequency errors. The AFC ensures the
channel filter is always centered on the desired channel
providing optimal reception. The dynamic channel
bandwidth feature utilizes a wide filter in strong signal
conditions to provide best sound quality and a narrower
filter in weak conditions to provide best sensitivity.
5.3. FM Receiver
The Si4736/37/38/39 FM receiver is based on the
proven Si4700/01 FM tuner. The receiver uses a digital
low-IF architecture allowing the elimination of external
components
and
factory
adjustments.
The
Si4736/37/38/39 integrates a low noise amplifier (LNA)
supporting the worldwide FM broadcast band (64 to 108
MHz). An AGC circuit controls the gain of the LNA to
optimize sensitivity and rejection of strong interferers.
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified,
filtered, and digitized with high resolution analog-to-
digital converters (ADCs). This advanced architecture
allows the Si4736/37/38/39 to perform channel
selection, FM demodulation, and stereo audio
processing to achieve superior performance compared
to traditional analog architectures.
5.6. Digital Audio Interface
(Si4737/39 Only)
The digital audio interface operates in slave mode and
supports three different audio data formats:
2
I S
Left-Justified
DSP Mode
5.4. AM Receiver
5.6.1. Audio Data Formats
2
In I S mode, by default the MSB is captured on the
The highly-integrated Si4736/37/38/39 supports
worldwide AM band reception from 520 to 1710 kHz
using a digital low-IF architecture with a minimum
number of external components and no manual
alignment required. This digital low-IF architecture
allows for high-precision filtering offering excellent
selectivity and SNR with minimum variation across the
AM band. The DSP also provides adjustable channel
step sizes in 1 kHz increments, AM demodulation, soft
mute, seven different channel bandwidth filters, and
additional features, such as a programmable automatic
volume control (AVC) maximum gain allowing users to
adjust the level of background noise. Similar to the FM
receiver, the integrated LNA and AGC optimize
sensitivity and rejection of strong interferers allowing
better reception of weak stations.
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In Left-Justified mode, by default the MSB is captured
on the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
The Si4736/37/38/39 provides highly-accurate digital
AM tuning without factory adjustments. To offer
maximum flexibility, the receiver supports a wide range
of ferrite loop sticks from 180–450 µH. An air loop
antenna is supported by using a transformer to increase
the effective inductance from the air loop. Using a 1:5
turn ratio inductor, the inductance is increased by 25
times and easily supports all typical AM air loop
antennas which generally vary between 10 and 20 µH.
In all audio formats, depending on the word size, DCLK
frequency and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
5.5. Weather Band Receiver
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
The Si4736/37/38/39 supports weather band reception
from 162.4 to 162.55 MHz. The highly integrated
Si4736/37/38/39 meets NOAA specification, receives all
seven NOAA specified frequencies, implements narrow-
band FM de-emphasis, and supports 1050 Hz alert tone
detection. In addition, the Si4736/37/38/39 provides
advanced features not available on conventional radios,
such as an AFC and a dynamic channel bandwidth filter.
5.6.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
Rev. 1.0
21
Si4736/37/38/39-C40
INVERTED
(OFALL = 1)
DCLK
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I2S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 10. I2S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 11. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 12. DSP Digital Audio Format
22
Rev. 1.0
Si4736/37/38/39-C40
5.7. Stereo Audio Processing
5.9. Stereo DAC
The output of the FM demodulator is a stereo High-fidelity stereo digital-to-analog converters (DACs)
multiplexed (MPX) signal. The MPX standard was drive analog audio signals onto the LOUT and ROUT
developed in 1961, and is used worldwide. Today's pins. The audio output may be muted. Volume is
MPX signal format consists of left + right (L+R) audio, adjusted digitally with the RX_VOLUME property.
left – right (L–R) audio, a 19 kHz pilot tone, and
5.10. Soft Mute
RDS/RBDS data as shown in Figure 13 below.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The softmute attenuation level is adjustable
using the FM_SOFT_MUTE_MAX_ATTENUATION and
Mono Audio
AM_SOFT_MUTE_MAX_ATTENUATION properties.
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
5.11. RDS/RBDS Processor
(Si4737/39 Only)
The Si4737/39 implements an RDS/RBDS* processor
for symbol decoding, block synchronization, error
detection, and error correction.
0
15 19 23
38
53 57
Frequency (kHz)
Figure 13. MPX Signal Spectrum
The Si4737/39 device is user configurable and provides
an optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
5.7.1. Stereo Decoder
The Si4736/37/38/39's integrated stereo decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4731 uses frequency information from the 19 kHz
stereo pilot to recover the 57 kHz RDS/RBDS signal.
The Si4737/39 reports RDS decoder synchronization
status and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors or that the block checkword
contains errors.
*Note: RDS/RBDS is referred to only as RDS throughout the
5.7.2. Stereo-Mono Blending
remainder of this document.
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Stereo/mono status can be
monitored with the FM_RSQ_STATUS command. Mono
5.12. Tuning
The tuning frequency is directly programmed using the
FM_TUNE_FREQ, WB_TUNE_FREQ, and
AM_TUNE_FREQ commands. The Si4736/37/38/39
supports channel spacing steps of 10 kHz in FM mode,
25 kHz in WB mode, and 1 kHz in AM mode.
operation
can
be
forced
with
the
FM_BLEND_MONO_THRESHOLD property.
5.8. De-emphasis
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
transmitted,
accentuate the high audio frequencies. The
Si4736/37/38/39 incorporates de-emphasis filter
a
pre-emphasis filter is applied to
a
which attenuates high frequencies to restore a flat
frequency response. Two time constants are used in
various regions. The de-emphasis time constant is
programmable to 50 or 75 µs and is set by the
FM_DEEMPHASIS property.
Rev. 1.0
23
Si4736/37/38/39-C40
RST. The GPO1 pin includes an internal pull-up resistor,
which is connected while RST is low, and the GPO2 pin
includes an internal pull-down resistor, which is
connected while RST is low. Therefore, it is only
necessary for the user to actively drive pins which differ
from these states. See Table 14.
5.13. Seek
Seek tuning will search up or down for a valid channel.
Valid channels are found when the receive signal
strength indicator (RSSI) and the signal-to-noise ratio
(SNR) values exceed the set threshold. Using the SNR
qualifier rather than solely relying on the more
traditional RSSI qualifier can reduce false stops and
increase the number of valid stations detected. Seek is
Table 14. Bus Mode Select on Rising Edge of
RST
initiated
using
the
FM_SEEK_START
and
Bus Mode
2-Wire
SPI
GPO1
GPO2
AM_SEEK_START commands. The RSSI and SNR
threshold settings are adjustable using properties (see
Table 16).
1
1
0
1 (must drive)
0
3-Wire
0 (must drive)
5.14. Reference Clock
The Si4736/37/38/39 reference clock is programmable, After the rising edge of RST, the pins GPO1 and GPO2
supporting RCLK frequencies in Table 13. Refer to are used as general purpose output (O) pins, as
Table 3, “DC Characteristics,” on page 5 for switching described in Section “5.16. GPO Outputs”. In any bus
voltage
levels
and
Table 9,
“FM
Receiver mode, commands may only be sent after V and V
IO DD
Characteristics,” on page 12 for frequency tolerance supplies are applied.
information.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic (QFN)" on page 17. This mode is enabled
using the POWER_UP command. Refer to Table 15,
“Selected Si473x Commands,” on page 27.
5.15.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
The Si4736/37/38/39 performance may be affected by
data activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4736/37/38/39 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4736/37/38/39 acknowledges the
control word by driving SDIO low on the next falling
edge of SCLK.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4736/37/38/39 seek and tune operations. This
is achieved by keeping the bus quiet for all other
devices on the bus, and delaying tuner polling until the
tune or seek operation is complete. The seek/tune
complete (STC) interrupt should be used instead of
polling to determine when a seek/tune operation is
complete.
Although the Si4736/37/38/39 will respond to only a
single device address, this address can be changed
with the SEN pin (note that the SEN pin is not used for
signaling in 2-wire mode). When SEN = 0, the 7-bit
device address is 0010001b. When SEN = 1, the
address is 1100011b.
5.15. Control Interface
For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the device on rising
edges of SCLK. The Si4736/37/38/39 acknowledges
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to 8
data bytes in a single 2-wire transaction. The first byte is
a command, and the next seven bytes are arguments.
A serial port slave interface is provided, which allows an
external controller to send commands to the
Si4736/37/38/39 and receive responses from the
device. The serial port can operate in three bus modes:
2-wire mode, 3-wire mode, or SPI mode. The
Si4736/37/38/39 selects the bus mode by sampling the
state of the GPO1 and GPO2 pins on the rising edge of
24
Rev. 1.0
Si4736/37/38/39-C40
For read operations, after the Si4736/37/38/39 has 5.15.3. SPI Control Interface Mode
acknowledged the control byte, it will drive an 8-bit data
byte on SDIO, changing the state of SDIO on the falling
edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling
edge of SCLK. If a data byte is not acknowledged, the
transaction will end. The user may read up to 16 data
bytes in a single 2-wire transaction. These bytes contain
the response data from the Si4736/37/38/39.
When selecting SPI mode, the user must ensure that a
rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
SPI bus mode uses the SCLK, SDIO, and SEN pins for
read/write operations. The system controller can
choose to receive read data from the device on either
SDIO or GPO1. A transaction begins when the system
controller drives SEN = 0. The system controller then
pulses SCLK eight times, while driving an 8-bit control
byte serially on SDIO. The device captures the data on
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer rising edges of SCLK. The control byte must have one
to Table 5, “2-Wire Control Interface Characteristics” on of five values:
page 7; Figure 2, “2-Wire Control Interface Read and
0x48 = write a command (controller drives 8
additional bytes on SDIO).
Write Timing Parameters,” on page 8, and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 8.
0x80 = read a response (device drives 1additional
byte on SDIO).
5.15.2. 3-Wire Control Interface Mode
0xC0 = read a response (device drives 16 additional
bytes on SDIO).
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
0xA0 = read a response (device drives 1 additional
byte on GPO1).
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 9-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
0xE0 = read a response (device drives 16 additional
bytes on GPO1).
For write operations, the system controller must drive
exactly 8 data bytes (a command and seven arguments)
on SDIO after the control byte. The data is captured by
the device on the rising edge of SCLK.
For read operations, the controller must read exactly 1
byte (STATUS) after the control byte or exactly 16 data
bytes (STATUS and RESP1–RESP15) after the control
byte. The device changes the state of SDIO (or GPO1, if
specified) on the falling edge of SCLK. Data must be
captured by the system controller on the rising edge of
SCLK.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4736/37/38/39 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
Keep SEN low until all bytes have transferred. A
transaction may be aborted at any time by setting SEN
high and toggling SCLK high and then low. Commands
will be ignored by the device if the transaction is
aborted.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
For details on timing specifications and diagrams, refer
to Figure 6 and Figure 7 on page 10.
5.16. GPO Outputs
The Si4736/37/38/39 provides three general-purpose
output pins. The GPO pins can be configured to output
a constant low, constant high, or high-impedance. The
GPO pins can be reconfigured as specialized functions.
GPO2/INT can be configured to provide interrupts and
GPO3 can be configured to provide external crystal
support or as DCLK in digital audio output mode.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 9; Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
Rev. 1.0
25
Si4736/37/38/39-C40
5.17. Firmware Upgrades
5.19. Programming with Commands
The Si4736/37/38/39 contains on-chip program RAM to To ease development time and offer maximum
accommodate minor changes to the firmware. This customization, the Si4736/37/38/39 provides a simple
allows Silicon Labs to provide future firmware updates yet powerful software interface to program the receiver.
to optimize the characteristics of new radio designs and The device is programmed using commands,
those already deployed in the field.
arguments, properties, and responses.
To perform an action, the user writes a command byte
and associated arguments, causing the chip to execute
the given command. Commands control an action such
as powerup the device, shut down the device, or tune to
a station. Arguments are specific to a given command
and are used to modify the command. A partial list of
5.18. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset.
A powerdown mode is available to reduce power commands is available in Table 15, “Selected Si473x
consumption when the part is idle. Putting the device in Commands,” on page 27.
powerdown mode will disable analog and digital circuitry
while keeping the bus active.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. A partial list of
properties is available in Table 16, “Selected Si473x
Properties,” on page 28.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. All commands provide a 1-byte status update,
indicating interrupt and clear-to-send status information.
For a detailed description of the commands and
properties for the Si4736/37/38/39, see “AN332: Si47xx
Programming Guide.”
26
Rev. 1.0
Si4736/37/38/39-C40
6. Commands and Properties
Table 15. Selected Si473x Commands
Cmd
Name
Description
Powerup device and mode selection. Modes include AM or FM receive,
analog or digital output, and reference clock or crystal support.
0x01
POWER_UP
0x10
0x11
0x12
0x13
0x20
0x21
GET_REV
Returns revision information on the device.
Powerdown device.
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
FM_TUNE_FREQ
FM_SEEK_START
Sets the value of a property.
Retrieves a property’s value.
Selects the FM tuning frequency.
Begins searching for a valid frequency.
Queries the status of the Received Signal Quality (RSQ) of the current
channel.
0x23
0x24
FM_RSQ_STATUS
FM_RDS_STATUS
Returns RDS information for current channel and reads an entry from the
RDS FIFO (Si4731 only).
0x40
0x41
0x43
0x50
0x53
AM_TUNE_FREQ
AM_SEEK_START
AM_RSQ_STATUS
WB_TUNE_FREQ
WB_RSQ_STATUS
Selects the AM tuning frequency.
Begins searching for a valid frequency.
Queries the status of the RSQ of the current channel.
Selects the WB tuning frequency.
Queries the status of the RSQ of the current channel.
Rev. 1.0
27
Si4736/37/38/39-C40
Table 16. Selected Si473x Properties
Prop
Name
Description
Default
0x1100
FM_DEEMPHASIS
Sets de-emphasis time constant. Default is 75 µs.
0x0002
Sets RSSI threshold for stereo blend (full stereo above
threshold, blend below threshold). To force stereo set this to 0. 0x0031
To force mono set this to 127. Default value is 49 dBµV.
FM_BLEND_STEREO_
THRESHOLD
0x1105
0x1106
Sets RSSI threshold for mono blend (full mono below threshold,
blend above threshold). To force stereo, set this to 0. To force
mono, set this to 127. Default value is 30 dBµV.
FM_BLEND_MONO_
THRESHOLD
0x001E
FM_RSQ_INT_
SOURCE
0x1200
0x1300
0x1302
0x1303
Configures interrupt related to RSQ metrics.
0x0000
0x0040
0x0010
0x0004
Sets the attack and decay rates when entering and leaving soft
mute.
FM_SOFT_MUTE_RATE
FM_SOFT_MUTE_
MAX_ATTENUATION
Sets maximum attenuation during soft mute (dB). Set to 0 to
disable soft mute. Default is 16 dB.
FM_SOFT_MUTE_
SNR_THRESHOLD
Sets SNR threshold to engage soft mute. Default is 4 dB.
FM_SEEK_BAND_
BOTTOM
0x1400
0x1401
0x1402
Sets the bottom of the FM band for seek. Default is 8750.
Sets the top of the FM band for seek. Default is 10790.
Selects frequency spacing for FM seek.
0x222E
0x2A26
0x000A
FM_SEEK_BAND_TOP
FM_SEEK_FREQ_
SPACING
FM_SEEK_TUNE_
SNR_THRESHOLD
Sets the SNR threshold for a valid FM Seek/Tune. Default value
is 3 dB.
0x1403
0x0003
FM_SEEK_TUNE_
RSSI_TRESHOLD
Sets the RSSI threshold for a valid FM Seek/Tune. Default
value is 20 dBuV.
0x1404
0x1500
0x1501
0x1502
0x3100
0x0014
0x0000
0x0000
0x0000
0x0000
RDS_INT_SOURCE
RDS_INT_FIFO_COUNT
RDS_CONFIG
Configures RDS interrupt behavior.
Sets the minimum number of RDS groups stored in the receive
RDS FIFO required before RDS RECV is set.
Configures RDS setting.
Sets de-emphasis time constant. Can be set to 50 us. De-
emphasis is disabled by default.
AM_DEEMPHASIS
Selects the bandwidth of the channel filter for AM reception. The
choices are 6, 4, 3, 2.5, 2, 1.8, or 1 kHz. In addition, a power
line rejection filter can be applied. The default is the 2 kHz band-
width filter without power line rejection.
0x3102
AM_CHANNEL_FILTER
0x0003
AM_AUTOMATIC_VOLUME_
CONTROL_MAX_GAIN
0x3103
0x3200
Selects the maximum gain for automatic volume control.
0x1543
0x0000
0x0040
0x0008
0x0008
0x0208
Configures interrupt related to RSQ metrics. All interrupts are
disabled by default.
AM_RSQ_INTERRUPTS
Sets the rate of attack when entering or leaving soft mute. The
default is 278 dB/s.
0x3300 AM_SOFT_MUTE_RATE
AM_SOFT_MUTE_MAX_
0x3302
Sets maximum attenuation during soft mute (dB).
ATTENUATION
AM_SOFT_MUTE_SNR_ Sets SNR threshold to engage soft mute. Default is 0 dB, which
0x3303
0x3400
THRESHOLD
disables soft mute.
AM_SEEK_BAND_
BOTTOM
Sets the bottom of the AM band for seek. Default is 520.
28
Rev. 1.0
Si4736/37/38/39-C40
Table 16. Selected Si473x Properties (Continued)
Prop
Name
Description
Default
0x3401
AM_SEEK_BAND_TOP
Sets the top of the AM band for seek.
0x06AE
AM_SEEK_FREQ_
SPACING
Selects frequency spacing for AM seek. Default is 10 kHz
spacing.
0x3402
0x000A
Sets the SNR threshold for a valid AM Seek/Tune. If the value is
zero, then SNR threshold is not considered when doing a seek. 0x0005
Default value is 5 dB.
AM_SEEK_SNR_
THRESHOLD
0x3403
Sets the RSSI threshold for a valid AM Seek/Tune. If the value
is zero, then RSSI threshold is not considered when doing a
seek. Default value is 25 dBuV.
AM_SEEK_RSSI_
THRESHOLD
0x3404
0x0019
0x4000
0x4001
RX_VOLUME
Sets the output volume.
0x003F
0x0000
Mutes the audio output. L and R audio outputs may be muted
independently in FM mode.
RX_HARD_MUTE
Maximum change in frequencies from the WB_TUNE_FREQ to
which the AFC will lock.
0x5108 WB_MAX_TUNE_ERROR
0x000F
0x0000
0x0000
WB_RSQ_INTERRUPT_
Configures interrupts related to RSQ metrics. All interrupts are
disabled by default.
0x5200
SOURCE
WB_ASQ_INTERRUPT_
Configures 1050 Hz alert tone interrupts. All interrupts are dis-
abled by default.
0x5600
SOURCE
Rev. 1.0
29
Si4736/37/38/39-C40
7. Pin Descriptions: Si4736/37/38/39-GM
20 19 18 17
NC
1
16
FMI 2
RFGND 3
AMI 4
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
GND
PAD
RST 5
6
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
No connect. Leave floating.
2
FMI
FM/WB RF inputs. FMI should be connected to the antenna trace.
RF ground. Connect to ground plane on PCB.
AM RF input. AMI should be connected to the AM antenna.
Device reset (active low) input.
3
RFGND
AMI
4
5
RST
6
SEN
Serial enable input (active low).
7
SCLK
SDIO
RCLK
Serial clock input.
8
Serial data input/output.
9
External reference oscillator input.
10
V
I/O supply voltage.
IO
11
V
Supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
Right audio line output in analog output mode.
Left audio line output in analog output mode.
Digital output data in digital output mode.
Digital frame synchronization input in digital output mode.
DD
12, GND PAD
GND
ROUT
LOUT
DOUT
DFS
13
14
15
16
17
GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
18
19
GPO2/INT
GPO1
General purpose output or interrupt pin.
General purpose output.
30
Rev. 1.0
Si4736/37/38/39-C40
8. Pin Descriptions: Si4736/37-GU
DOUT
DFS
LOUT
ROUT
1
2
24
23
22
21
20
19
18
17
16
15
14
13
GPO3/DCLK
GPO2/INT
GPO1
DBYP
VDD
VIO
3
4
5
NC
RCLK
SDIO
SCLK
SEN
6
NC
7
FMI
8
RFGND
9
NC
NC
RST
10
11
12
GND
GND
AMI
Pin Number(s)
Name
DOUT
DFS
Description
1
2
3
Digital output data in digital output mode.
Digital frame synchronization input in digital output mode.
GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
4
5
GPO2/INT
GPO1
NC
General purpose output or interrupt pin.
General purpose output.
6,7
8
No connect. Leave floating.
FMI
FM/WB RF inputs. FMI should be connected to the antenna trace.
RF ground. Connect to ground plane on PCB.
Unused. Tie these pins to GND.
9
RFGND
NC
10,11
12
AMI
AM RF input. AMI should be connected to the AM antenna.
Ground. Connect to ground plane on PCB.
13,14
GND
15
RST
Device reset (active low) input.
16
17
18
19
20
21
22
23
24
SEN
SCLK
SDIO
RCLK
Serial enable input (active low).
Serial clock input.
Serial data input/output.
External reference oscillator input.
I/O supply voltage.
V
IO
V
Supply voltage. May be connected directly to battery.
DD
DBYP
ROUT
LOUT
Dedicated bypass for V and V .
DD IO
Right audio line output in analog output mode.
Left audio line output in analog output mode.
Rev. 1.0
31
Si4736/37/38/39-C40
9. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature/Voltage
Si4736-C40-GM AM/FM/WB Broadcast Radio Receiver
Si4736-C40-GU AM/FM/WB Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
SSOP
Pb-free
–20 to 85 °C
2.0 to 5.5 V
Si4737-C40-GM AM/FM/WB Broadcast Radio Receiver with
RDS/RBDS
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
Si4737-C40-GU AM/FM/WB Broadcast Radio Receiver with
RDS/RBDS
SSOP
Pb-free
–20 to 85 °C
2.0 to 5.5 V
Si4738-C40-GM FM/WB Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
Si4739-C40-GM FM/WB Broadcast Radio Receiver with
RDS/RBDS
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. SSOP
devices operate down to V = 2 V at 25 °C.
DD
32
Rev. 1.0
Si4736/37/38/39-C40
10. Package Markings (Top Marks)
10.1. Si4736/37/38/39 Top Mark (QFN)
3640 3740 3840 3940
CTTT CTTT CTTT CTTT
YWW
YWW
YWW
YWW
10.2. Top Mark Explanation (QFN)
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
36 = Si4736, 37 = Si4737, 38 = Si4738, 39 = Si4739
40 = Firmware Revision 4.0
C = Revision C Die
Firmware Revision
Die Revision
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
Assigned by the Assembly House. Corresponds to the last sig-
nificant digit of the year and workweek of the mold date.
WW = Workweek
Rev. 1.0
33
Si4736/37/38/39-C40
10.3. Si4736/37 Top Mark (SSOP)
4736C40GU
YYWWTTTTTT
10.4. Top Mark Explanation (SSOP)
Mark Method:
YAG Laser
Part Number
Die Revision
Firmware Revision
4736 = Si4736; 4737 = Si4737.
C = Revision C die.
Line 1 Marking:
40 = Firmware Revision 4.0.
YY = Year
Line 2 Marking:
WW = Work week
TTTTTT = Manufacturing code
Assigned by the Assembly House.
34
Rev. 1.0
Si4736/37/38/39-C40
11. Package Outline: Si4736/37/38/39 QFN
Figure 14 illustrates the package details for the Si4736/37/38/39. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 14. 20-Pin Quad Flat No-Lead (QFN)
Table 17. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
Rev. 1.0
35
Si4736/37/38/39-C40
12. PCB Land Pattern: Si4736/37/38/39 QFN
Figure 15 illustrates the PCB land pattern details for the Si4736/37/38/39-C40-GM QFN. Table 18 lists the values
for the dimensions shown in the illustration.
Figure 15. PCB Land Pattern
36
Rev. 1.0
Si4736/37/38/39-C40
Table 18. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.0
37
Si4736/37/38/39-C40
13. Package Outline: Si4736/37 SSOP
Figure 16 illustrates the package details for the Si4736/37. Table 19 lists the values for the dimensions shown in
the illustration.
Figure 16. 24-Pin SSOP
Table 19. Package Dimensions
Dimension
Min
—
Nom
—
Max
1.75
0.25
0.30
0.25
A
A1
b
0.10
0.20
0.10
—
—
c
—
D
8.65 BSC
6.00 BSC
3.90 BSC
0.635 BSC
—
E
E1
e
L
0.40
0°
1.27
8°
L2
θ
0.25 BSC
—
aaa
bbb
ccc
ddd
0.20
0.18
0.10
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
38
Rev. 1.0
Si4736/37/38/39-C40
14. PCB Land Pattern: Si4736/37 SSOP
Figure 17 illustrates the PCB land pattern details for the Si4736/37-C40-GU SSOP. Table 20 lists the values for the
dimensions shown in the illustration.
Figure 17. PCB Land Pattern
Table 20. PCB Land Pattern Dimensions
Dimension
Min
Max
C
E
5.20
5.40
0.65 BSC
X1
Y1
0.35
1.55
0.45
1.75
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the
pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.0
39
Si4736/37/38/39-C40
15. Additional Reference Resources
Contact your local sales representatives for more information or to obtain copies of the following references:
AN332: Si47xx Programming Guide
AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
40
Rev. 1.0
Si4736/37/38/39-C40
DOCUMENT CHANGE LIST
Revision 0.71 to Revision 1.0
Updated patent information on page 1.
Pin 22 changed from “GND” to “DBYP.”
Updated Table 1 on page 4.
Updated Table 3 on page 5.
Updated Table 12 on page 15.
Updated "3. Typical Application Schematic (SSOP)"
on page 18.
Updated "4. Bill of Materials (QFN/SSOP)" on page
19.
Updated "8. Pin Descriptions: Si4736/37-GU" on
page 31.
Updated "9. Ordering Guide" on page 32.
Rev. 1.0
41
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