SI5017-X-GM [SILICON]
OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER; OC- 48 / STM - 16 SONET / SDH CDR IC限幅放大器
| 型号： | SI5017-X-GM |
| 厂家： | 
SILICON |
| 描述： | OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER |
| 文件： | 总26页 (文件大小：398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5017
OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
Features
High-speed clock and data recovery device with integrated limiting amplifier:
ꢀ Supports OC-48/STM-16 and ꢀ Loss-of-signal level alarm
2.7 Gbps FEC
ꢀ Data slicing level control
ꢀ DSPLL® technology
ꢀ Jitter generation 3.0 mUI
ꢀ 10 mV differential sensitivity
PP
(typ)
rms
ꢀ 3.3 V supply
ꢀ Small footprint: 5 x 5 mm
ꢀ Reference and reference-less
Ordering Information:
operation supported
See page 22.
Applications
ꢀ SONET/SDH/ATM routers
ꢀ Add/drop multiplexers
ꢀ Digital cross connects
ꢀ Board level serial links
ꢀ SONET/SDH test equipment
ꢀ Optical transceiver modules
ꢀ SONET/SDH regenerators
Pin Assignments
Si5017
Description
28 27 26 25 24 23 22
VDD
VDD
VDD
21
1
2
3
4
5
6
7
The Si5017 is a fully-integrated, high-performance limiting amplifier (LA)
and clock and data recovery (CDR) IC for high-speed serial
communication systems. It derives timing information and data from a
serial input at OC-48 and STM-16 rates. Support for 2.7 Gbps data
streams is also provided for OC-48/STM-16 applications that employ
forward error correction (FEC). Use of an external reference clock is
optional. Silicon Laboratories DSPLL® technology eliminates sensitive
noise entry points, thus making the PLL less susceptible to board-level
interaction and helping to ensure optimal jitter performance.
20 REXT
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
19 RESET/CAL
GND
Pad
18
17
16
15
VDD
DOUT+
DOUT–
TDI
8
9
10 11 12 13 14
The Si5017 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
LOS_LVL
Signal
Detect
DSQLCH
LOS
2
DOUT+
DOUT–
Retimer
BUF
BUF
2
DIN+
DIN–
Limiting
Amp
DSPLL
BER
Monitor
2
CLKOUT+
CLKOUT–
CLK_DSBL
REFCLK+
REFCLK–
(Optional)
2
Lock
Detection
Reset/
Calibration
Bias Gen.
BER_ALM
REXT
RESET/CAL
BER_LVL
SLICE_LVL
LOL
LTR
Rev. 1.4 10/05
Copyright © 2005 by Silicon Laboratories
Si5017
Si5017
2
Rev. 1.4
Si5017
TABLE OF CONTENTS
Section
Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
®
4.2. DSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.3. Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.4. Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.5. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.6. Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.7. Loss-of-Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.8. Bit-Error-Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.9. Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.10. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.11. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.12. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.13. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.14. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.15. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.16. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.17. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.18. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. Pin Descriptions: Si5017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3
Rev. 1.4
Si5017
1. Detailed Block Diagram
LTR
LOS
BER_LVL
BER_ALM
DSQLCH
BER
Monitor
Signal
Detect
LOS_LVL
DOUT+
DOUT–
Retime
DIN+
DIN+
CLKOUT+
CLKOUT–
Limiting
Amp
Phase
Detector
CLK
Dividers
A/D
DSP
VCO
n
CLKDSBL
Slicing
Control
SLICE_LVL
Lock
Detection
REFCLK±
(optional)
LOL
Bias
Generation
REXT
Calibration
RESET/CAL
4
Rev. 1.4
Si5017
2. Electrical Specifications
Table 1. Recommended Operating Conditions
1
1
Parameter
Symbol
Test Condition
Typ
Unit
Min
Max
85
Ambient Temperature
Si5017 Supply Voltage
Notes:
T
–40
25
°C
V
A
2
V
3.135
3.3
3.465
DD
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5017 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of the "Typical Application Schematic" on page 11.
V
SIGNAL+
SIGNAL–
VIS
t
A. Operation with Single-Ended Inputs
V
SIGNAL+
SIGNAL–
0.5 VID
(SIGNAL+) – (SIGNAL–)
VID
t
B. Operation with Differential Inputs and Outputs
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
tCf-D
tCr-D
DOUT
CLKOUT
Figure 2. Clock to Data Timing
Rev. 1.4
5
Si5017
80%
20%
DOUT,
CLKOUT
tF
tR
Figure 3. DOUT and CLKOUT Rise/Fall Times
taq
RESET/Cal
LOL
DATAIN
LOL
taq
Figure 4. PLL Acquisition Time
DATAIN
LOS
LOS Threshold
Level
tLOS
Figure 5. LOS Response Time
6
Rev. 1.4
Si5017
Table 2. DC Characteristics
(VDD = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Supply Current1
FEC (2.7 Gbps)
OC-48
IDD
—
—
173
170
184
180
mA
Power Dissipation
FEC (2.7 Gbps)
OC-48
PD
—
—
571
561
637
623
mW
Common Mode Input Voltage (DIN)2
Common Mode Input Voltage (REFCLK)2
DIN Single-ended Input Voltage Swing2
DIN Differential Input Voltage Swing2
REFCLK Single-ended Input Voltage Swing2
REFCLK Differential Input Voltage Swing2
Input Impedance (DIN)
VICM
VICM
VIS
See Figure 11
See Figure 10
See Figure 1A
See Figure 1B
See Figure 1A
See Figure 1B
Line-to-Line
1.30
1.90
10
1.50
2.10
—
1.62
2.30
500
V
V
mV
mV
mV
mV
Ω
VID
10
—
1000
750
VIS
200
200
84
—
VID
—
1500
116
RIN
100
800
Differential Output Voltage Swing
(DOUT)
VOD
100 Ω Load
Line-to-Line
700
1000
mVPP
Differential Output Voltage Swing
(CLKOUT)
VOD
100 Ω Load
Line-to-Line
700
1.6
1.6
800
1.95
1.80
1100
2.35
2.35
mVPP
Output Common Mode Voltage (DOUT)
VOCM
VOCM
100 Ω Load
Line-to-Line
V
V
Output Common Mode Voltage (CLKOUT)
100 Ω Load
Line-to-Line
Output Impedance (DOUT,CLKOUT)
Input Voltage Low (LVTTL Inputs)
Input Voltage High (LVTTL Inputs)
Input Low Current (LVTTL Inputs)
Input High Current (LVTTL Inputs)
Input Impedance (LVTTL Inputs)
ROUT
VIL
VIH
IIL
Single-ended
84
—
2.0
—
—
9
100
—
116
.8
Ω
V
—
—
V
—
10
10
—
µA
µA
kΩ
kΩ
IIH
—
RIN
RIN
—
LOS_LVL, BER_LVL, SLICE_LVL
Input Impedance
50
100
125
Output Voltage Low (LVTTL Outputs)
Output Voltage High (LVTTL Outputs)
VOL
VOH
IO = 2 mA
IO = 2 mA
—
—
—
0.4
—
V
V
2.0
Notes:
1. No load on LVTTL outputs.
2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac
coupled to ground.
7
Rev. 1.4
Si5017
Table 3. AC Characteristics (Clock and Data)
(VDD = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
fCLK
tR
Test Condition
Min
2.4
—
Typ
—
Max
2.7
90
Unit
GHz
ps
Output Clock Rate
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Figure 3
Figure 3
70
70
50
tF
—
90
ps
48
52
% of
UI
Output Data Rise Time
Output Data Fall Time
tR
tF
Figure 3
Figure 3
Figure 2
—
—
80
80
110
110
ps
ps
Clock to Data Delay
FEC (2.7 Gbps)
OC-48
tCr-D
190
190
230
230
265
265
ps
ps
Clock to Data Delay
FEC (2.7 Gbps)
OC-48
tCf-D
Figure 2
–70
–60
–40
–30
–10
0
Input Return Loss
100 kHz–1.5 GHz
1.5 GHz–4.0 GHz
–15
–10
—
—
—
—
dB
dB
See Figure 8 on page 14.
Slicing Level Offset
(relative to the internally set input
common mode voltage)
VSLICE
SLICE_LVL = 750 mV to
2.25 V
Loss-of-Signal Range*
(peak-to-peak differential)
VLOS
tLOS
LOS_LVL = 1.50 to 2.50 V
Figure 5
0
8
—
40
25
mV
µs
Loss-of-Signal Response Time
20
*Note: Adjustment voltage is calculated as follows: VLOS = (LOS_LVL – 1.50)/25.
8
Rev. 1.4
Si5017
Table 4. AC Characteristics (PLL Characteristics)
(VDD =3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
f = 600 Hz
Min
40
4
Typ
—
Max
—
Unit
UIPP
UIPP
UIPP
Jitter Tolerance
(OC-48)*
JTOL(PP)
f = 6000 Hz
f = 100 kHz
f = 1 MHz
—
—
3
—
—
0.3
—
—
—
—
—
—
3.0
25
—
5.0
55
UIPP
mUI
mUI
MHz
dB
RMS Jitter Generation*
JGEN(rms) with no jitter on serial data
JGEN(PP) with no jitter on serial data
Peak-to-Peak Jitter Generation*
Jitter Transfer Bandwidth*
Jitter Transfer Peaking*
JBW
JP
OC-48
—
2.0
0.1
2.2
0.03
1.6
Acquisition Time
(Reference clock applied)
TAQ
After falling edge of
RESET/CAL
ms
From the return of valid
data
20
—
100
2.0
2.5
500
5.5
5.5
µs
ms
ms
Acquisition Time
TAQ
After falling edge of
RESET/CAL
(Reference-less operation)
From the return of valid
data
1.5
Reference Clock Range
See Table 7 on page 13.
f
CLK / 16
—
—
—
155.52
77.76
19.44
—
—
—
fCLK / 32
fCLK / 128
MHz
Input Reference Clock Frequency
Tolerance
CTOL
–500
—
+500
ppm
ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
—
±650
—
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 – 1 data pattern.
9
Rev. 1.4
Si5017
Table 5. Absolute Maximum Ratings
Parameter
Symbol
VDD
Value
–0.5 to 3.5
–0.3 to 3.6
–0.3 to (VDD+ 0.3)
±50
Unit
V
DC Supply Voltage
LVTTL Input Voltage
VDIG
V
Differential Input Voltages
Maximum Current any output PIN
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pf, 1.5 kΩ)
VDIF
V
mA
°C
°C
kV
TJCT
TSTG
–55 to 150
–55 to 150
1
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
ϕ
Still Air
38
°C/W
JA
10
Rev. 1.4
Si5017
3. Typical Application Schematic
BER Alarm
Indicator
LVTTL
Control Inputs
Loss-of-Signal
Indicator
Loss-of-Lock
Indicator
DIN+
DOUT+
DOUT–
High-Speed
Serial Input
Recovered
Data
DIN–
System
Reference
Clock
Si5017
REFCLK+
REFCLK–
CLKOUT+
CLKOUT–
Recovered
Clock
(Optional)
100 pF x 4
10 kΩ
VDD
(1%)
0.1 µF
Loss-of-Signal Data Slice
Level Set
Level Set
Bit Error Rate
Level Set
Rev. 1.4
11
Si5017
traditional methods, and it eliminates performance
degradation caused by external component aging. In
4. Functional Description
The Si5017 integrates a high-speed limiting amplifier addition, because external loop filter components are
with a CDR unit that operates between 2.4 and not required, sensitive noise entry points are eliminated,
2.7 Gbps. No external reference clock is required for thus making the DSPLL less susceptible to board-level
clock and data recovery. The limiting amplifier magnifies noise sources and making SONET/SDH jitter
very low-level input data signals so accurate clock and compliance easier to attain in the application.
data recovery can be performed. The CDR uses Silicon
4.3. Operation Without an External Refer-
®
Laboratories DSPLL technology to recover a clock
ence
synchronous to the input data stream. The recovered
clock retimes the incoming data, and both are output
synchronously via current-mode logic (CML) drivers.
Silicon Laboratories’ DSPLL technology ensures
superior jitter performance while eliminating the need
for external loop filter components found in traditional
phase-locked loop (PLL) implementations.
The Si5017 can perform clock and data recovery
without an external reference clock. Tying the
REFCLK+ input to VDD and the REFCLK– input to
GND configures the device to operate without an
external reference clock. Clock recovery is achieved by
monitoring the timing quality of the incoming data
relative to the VCO frequency. Lock is maintained by
continuously monitoring the incoming data timing quality
and adjusting the VCO accordingly. Details of the lock
detection and the lock-to-reference functions while in
this mode are described in their respective sections
below.
The limiting amplifier includes a control input for
adjusting the data slicing level and provides a loss-of-
signal level alarm output. The CDR includes a bit-error-
rate performance monitor which signals a high bit-error-
rate condition (associated with excessive incoming
jitter) relative to an externally adjustable bit-error-rate
threshold.
Note: Without an external reference the acquisition of data is
dependent solely on the data itself and typically
requires more time to acquire lock than when a refer-
ence is applied.
The optional reference clock minimizes the CDR
acquisition time and provides a stable reference for
maintaining the output clock when locking to reference
is desired.
4.4. Operation With an External Reference
The Si5017 can also perform clock and data recovery
with an external reference. The device’s optional
external reference clock centers the DSPLL, minimizes
the acquisition time, and maintains a stable output clock
(CLKOUT) when lock-to-reference (LTR) is asserted.
4.1. Limiting Amplifier
The limiting amplifier accepts the low-level signal output
from a transimpedance amplifier (TIA). The low-level
signal is amplified to a usable level for the CDR unit.
The minimum input swing requirement is specified in
Table 2. Larger input amplitudes (up to the maximum
input swing specified in Table 2) are accommodated
without degradation of performance. The limiting
amplifier ensures optimal data slicing by using a digital
dc offset cancellation technique to remove any dc bias
introduced by the amplification stage.
When the reference clock is present, the Si5017 uses
the reference clock to center the VCO output frequency
so that clock and data are recovered from the input data
stream. The device self configures for operation with
one of three reference clock frequencies. This
eliminates the need to externally configure the device to
operate with a particular reference clock.
®
4.2. DSPLL
The reference clock centers the VCO for a nominal
output between 2.5 and 2.7 GHz. The VCO frequency is
centered at 16, 32, or 128 times the reference clock
frequency. Detection circuitry continuously monitors the
reference clock input to determine whether the device
should be configured for a reference clock that is 1/16,
1/32, or 1/128 the nominal VCO output. Approximate
reference clock frequencies for some target applications
are given in Table 7.
The Si5017 PLL structure (shown in the "Detailed Block
Diagram" on page 4) utilizes Silicon Laboratories'
DSPLL technology to maintain superior jitter
performance while eliminating the need for external loop
filter
components
found
in
traditional
PLL
implementations. This is achieved using a digital signal
processing (DSP) algorithm to replace the loop filter
commonly found in analog PLL designs. This algorithm
processes the phase detector error term and generates
a digital control value to adjust the frequency of the
voltage-controlled oscillator (VCO). This technology
enables CDR with far less jitter than is generated using
12
Rev. 1.4
Si5017
of LTR forces the DSPLL to lock CLKOUT to the
provided reference. If no external reference clock is
used, LTR forces the DSPLL to hold the digital
frequency control input to the VCO at the last value.
This produces a stable output clock as long as supply
and temperature are constant.
Table 7. Typical REFCLK Frequencies
OC-48 with Ratio of VCO
15/14 FEC to REFCLK
SONET/SDH
19.44 MHz 20.83 MHz
77.76 MHz 83.31 MHz
155.52 MHz 166.63 MHz
128
32
4.7. Loss-of-Signal (LOS)
The Si5017 indicates a loss-of-signal condition on the
LOS output pin when the input peak-to-peak signal level
on DIN falls below an externally controlled threshold.
The LOS threshold range is specified in Table 3 and is
16
4.5. Lock Detect
The Si5017 provides lock-detect circuitry that indicates set by applying a voltage on the LOS_LVL pin. The
whether the PLL has achieved frequency lock with the graph in Figure 6 illustrates the LOS_LVL mapping to
incoming data. The operation of the lock-detector the LOS threshold. The LOS output is asserted when
depends on the reference clock option used.
the input signal drops below the programmed peak-to-
peak value. If desired, the LOS function may be
disabled by grounding LOS_LVL or by adjusting
LOS_LVL to be less than 1 V.
When an external reference clock is provided, the circuit
compares the frequency of a divided-down version of
the recovered clock with the frequency of the applied
reference clock (REFCLK). If the recovered clock
frequency deviates from that of the reference clock by
the amount specified in Table 4 on page 9, the PLL is
declared out of lock, and the loss-of-lock (LOL) pin is
asserted. In this state, the PLL will periodically try to
reacquire lock with the incoming data stream. During
reacquisition, the recovered clock frequency (CLKOUT)
drifts over a ±600 ppm range relative to the applied
reference clock and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
low noise and stability of the DSPLL, there is the
possibility that the PLL will not drift enough to render an
out-of-lock condition, even if the data is removed from
inputs.
Note: The LOS circuit is designed to only work with pseudo-
random, dc-balanced data.
40 mV
30 mV
15 mV
40mV/V
LOS Limited by Device Noise
0 mV
0 V
1.00 V
1.50 V
1.875 V
2.25 V
2.50 V
In applications requiring a more stable output clock
during out-of-lock conditions, the lock-to-reference
(LTR) input can be used to force the PLL to lock to the
externally supplied reference.
LOS_LVL (V)
Figure 6. LOS_LVL Mapping
In the absence of an external reference, the lock detect
circuitry uses a data quality measure to determine when
frequency lock has been lost with the incoming data
stream. During reacquisition, CLKOUT may vary by
approximately ±10% from the nominal data rate.
R1
3
LOS_LVL
Set LOS
Level
Si5017
CDR
R2
10k
4.6. Lock-to-Reference
The LTR input is used to force a stable output clock
when an alarm condition, like LOS, exists. In typical
applications, the LOS output is tied to the LTR input to
force a stable output clock when the input data signal is
lost. When LTR is asserted, the DSPLL is prevented
from acquiring the data signal present on DIN. The
operation of the LTR control input depends on which
reference clocking mode is used.
9
LOS
LOS Alarm
Figure 7. LOS Signal Hysteresis
When an external reference clock is present, assertion
13
Rev. 1.4
Si5017
In many applications it is desirable to produce a fixed of the expected event window are counted as bit errors.
amount of signal hysteresis for an alarm indicator such The BER threshold is programmed by applying a
as LOS, since a marginal data input signal could cause voltage to the BER_LVL pin between 500 mV and
intermittent toggling, leading to false alarm status. 2.25 V corresponding to a BER of approximately 10–10
When it is anticipated that very low-level DIN signals will and 10–6, respectively. The voltage present on
be encountered, the introduction of an adequate BER_LVL maps to the BER as follows: log10(BER) = (4
amount of LOS hysteresis is recommended to minimize x BER_LVL) – 13. (BER_LVL is in volts; BER is in bits
any undesirable LOS signal toggling. Figure 7 illustrates per second.).
a simple circuit that may be used to set a fixed level of
LOS signal hysteresis for the Si5017 CDR. The value of
4.9. Data Slicing Level
R1 may be chosen to provide a range of hysteresis from The Si5017 provides the ability to externally adjust the
3 to 8 dB where a nominal value of 800 Ω adjusts the slicing level for applications that require bit-error-rate
hysteresis level to approximately 6 dB. Use a value of (BER) optimization. Adjustments in slicing level of
500 Ω or 1000 Ω for R1 to provide 3 dB or 8 dB of ±25 mV (typical, relative to the internally set input
hysteresis, respectively.
common mode voltage) are supported. The slicing level
is set by applying a voltage between 0.75 and 2.25 V to
the SLICE_LVL input. See Figure 8 for the operation
levels of the slice circuit.
Hysteresis is defined as the ratio of the LOS deassert
level (LOSD) and the LOS assert level (LOSA). The
hysteresis in decibels is calculated as 20log(LOSD/
LOSA).
When SLICE_LVL is driven below 500 mV, the slicing
level adjustment is disabled, and the slicing level is set
to the cross-point of the differential input signal.
4.8. Bit-Error-Rate (BER) Detection
The Si5017 uses a proprietary Silicon Laboratories
algorithm to generate a bit-error-rate (BER) alarm on
the BER_ALM pin if the observed BER is greater than a
user programmable threshold. Bit error detection relies
on the input data edge timing; edges occurring outside
Note: The slice circuit is designed to only work with pseudo-
random, dc-balanced data.
40
30
20
10
0
10 mV
-10
-20
-30
-40
10 mV
Note: SLICE is a continuous curve. This chart shows
the range of results from part-to-part.
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
Figure 8. Si5017 OC-48 Slice Specification
14
Rev. 1.4
Si5017
the DSPLL on powerup. Calibration may also be
initiated by a high-to-low transition on the RESET/CAL
pin. The RESET/CAL pin must be held high for at least
1 µs. When RESET/CAL is released (set to low) the
digital logic resets to a known initial condition,
recalibrates the DSPLL, and begins to lock to the
incoming data stream. For a valid reset to occur when
4.10. PLL Performance
The PLL implementation used in the Si5017 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 3, September 2000 and ITU-T G.958.
4.10.1. Jitter Tolerance
The Si5017’s tolerance to input jitter exceeds that of the using Reference mode, a proper, external reference
Bellcore/ITU mask shown in Figure 8. This mask clock frequency must be applied as specified in Table 7.
defines the level of peak-to-peak sinusoid jitter that
4.12. Clock Disable
must be tolerated when applied to the differential data
input of the device.
The Si5017 provides a clock disable pin (CLK_DSBL)
that is used to disable the recovered clock output
(CLKOUT). When the CLK_DSBL pin is asserted, the
positive and negative terminals of CLKOUT are tied to
VDD through 100 Ω on-chip resistors.
4.10.2. Jitter Transfer
The Si5017 exceeds all relevant Bellcore/ITU
specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency.
These measurements are made with an input test signal
that is degraded with sinusoidal jitter whose magnitude
is defined by the mask in Figure 9.
4.13. Data Squelch
The Si5017 provides a data squelching pin (DSQLCH)
that is used to set the recovered data output (DOUT) to
binary zero. When the DSQLCH pin is asserted, the
DOUT+ signal is held low and the DOUT– signal is held
high. This pin can be is used to squelch corrupt data
during LOS and LOL situations. Care must be taken
when ac coupling these outputs; a long string of zeros
or ones will not be held through ac coupling capacitors.
Jitter
Transfer
0.1 dB
20 dB/Decade
Slope
4.14. Device Grounding
The Si5017 uses the GND pad on the bottom of the 28-
pin micro leaded package (QFN) for device ground. This
pad should be connected directly to the analog supply
ground. See Figure 15 on page 19 and Figure 16 on
page 23 for the ground (GND) pad location.
Acceptable
Range
Fc
4.15. Bias Generation Circuitry
Frequency
The Si5017 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
SONET
Data Rate
OC-48
Fc
(kHz)
2000
Figure 9. Jitter Transfer Specification
4.10.3. Jitter Generation
4.16. Voltage Regulator
The Si5017 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
The Si5017 operates from a 3.3 V external supply
voltage. Internally the device operates from a 2.5 V
supply. The Si5017 regulates 2.5 V internally down from
the external 3.3 V supply.
Si5017 typically generates less than 3.0 mUI
when presented with jitter-free input data.
of jitter
rms
In addition to supporting 3.3 V systems, the on-chip
linear regulator offers better power supply noise
rejection versus a direct 2.5 V supply.
4.11. RESET/DSPLL Calibration
The Si5017 achieves optimal jitter performance by
automatically calibrating the loop gain parameters within
15
Rev. 1.4
Si5017
4.17. Differential Input Circuitry
The Si5017 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is shown in Figures 10 and 11, respectively. In applications where
direct dc coupling is possible, the 0.1 µF capacitors may be omitted. (LOS operation is only guaranteed when ac
coupled.) The data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as
–12
specified in Table 2 on page 7 to ensure a BER of at least 10 . The REFCLK input differential peak-to-peak
voltage requirement is also specified in Table 2.
Si5017
Clock source
2.5 V (±5%)
2.5 kΩ
0.1 µF
Zo = 50 Ω
RFCLK +
RFCLK –
10 kΩ
2.5 kΩ
100 Ω
Zo = 50 Ω
0.1 µF
10 kΩ
GND
Figure 10. Input Termination for REFCLK (ac coupled)
Si5017
TIA
2.5 V (±5%)
0.1 µF
Zo = 50 Ω
DIN+
50 Ω
50 Ω
5 kΩ
7.5 kΩ
0.1 µF
Zo = 50 Ω
DIN–
GND
Figure 11. Input Termination for DIN (ac coupled)
16
Rev. 1.4
Si5017
Si5017
2.5 V (±5%)
Clock
source
2.5 kΩ
0.1 µF
Zo = 50 Ω
RFCLK +
RFCLK –
10 kΩ
2.5 kΩ
50 Ω
10 kΩ
0.1 µF
GND
Figure 12. Single-Ended Input Termination for REFCLK (ac coupled)
Si5017
(±5%)
2.5 V
Signal
source
0.1 µF
Zo = 50 Ω
DIN+
50 Ω
50 Ω
5 kΩ
100Ω
7.5 kΩ
DIN–
0.1 µF
GND
Figure 13. Single-Ended Input Termination for DIN (ac coupled)
17
Rev. 1.4
Si5017
4.18. Differential Output Circuitry
The Si5017 utilizes a CML architecture to output both the recovered clock (CLKOUT) and data (DOUT). An
example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is
possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML
architecture is specified in Table 2 on page 7.
Si5017
VDD
50 Ω
2.5 V (±5%)
100 Ω
DOUT+,
CLKOUT+
0.1 µF
0.1 µF
Zo = 50 Ω
Zo = 50 Ω
DOUT–,
CLKOUT–
100 Ω
2.5 V (±5%)
50 Ω
VDD
Figure 14. Output Termination for DOUT and CLKOUT (ac coupled)
18
Rev. 1.4
Si5017
5. Pin Descriptions: Si5017
28 27 26 25 24 23 22
VDD
VDD
VDD
21
1
2
3
4
5
6
7
20 REXT
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
19 RESET/CAL
GND
Pad
18
17
16
15
VDD
DOUT+
DOUT–
TDI
8
9
10 11 12 13 14
Figure 15. Si5017 Pin Configuration
Table 8. Si5017 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1,2,11,14,18,
21,25
VDD
3.3 V
Supply Voltage.
Nominally 3.3 V.
3
LOS_LVL
I
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 13 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
4
SLICE_LVL
I
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
5
6
REFCLK+
REFCLK–
I
See Table 2 Differential Reference Clock (Optional).
When present, the reference clock sets the center
operating frequency of the DSPLL for clock and
data recovery. Tie REFCLK+ to VDD and REFCLK–
to GND to operate without an external reference
clock.
See Table 7 on page 13 for typical reference clock
frequencies.
Rev. 1.4
19
Si5017
Table 8. Si5017 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
7
O
LVTTL
Loss-of-Lock.
LOL
This output is driven low when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 9. If no exter-
nal reference is supplied, this signal will be active
when the internal PLL is no longer locked to the
incoming data.
8
I
LVTTL
Lock-to-Reference.
LTR
When this pin is low, the DSPLL disregards the data
inputs. If an external reference is supplied, the out-
put clock locks to the supplied reference. If no
external reference is used, the DSPLL locks the
control loop until LTR is released.
Note: This input has a weak internal pullup.
9
O
LVTTL
LVTTL
Loss-of-Signal.
LOS
This output pin is driven low when the input signal is
below the threshold set via LOS_LVL. (LOS opera-
tion is guaranteed only when ac coupling is used on
the DIN inputs.)
10
DSQLCH
Data Squelch.
When driven high, this pin forces the data present
on DOUT+ to zero and DOUT– to one. For normal
operation, this pin should be low. DSQLCH may be
used during LOS/LOL conditions to prevent random
data from being presented to the system.
Note: This input has a weak internal pulldown.
12
13
DIN+
DIN–
I
See Table 2 Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins. AC coupling is
recommended.
15
GND
GND
CML
Production Test Input.
This pin is used during production testing and must
be tied to GND for normal operation.
16
17
DOUT–
DOUT+
O
I
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN.
19
RESET/CAL
LVTTL
Reset/Calibrate.
Driving this input high for at least 1 µs will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low.
Note: This input has a weak internal pulldown.
20
REXT
External Bias Resistor.
This resistor is used to establish internal bias cur-
rents within the device. This pin must be connected
to GND through a 10 kΩ (1%) resistor.
20
Rev. 1.4
Si5017
Table 8. Si5017 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Differential Clock Output.
22
23
CLKOUT–
CLKOUT+
O
CML
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
24
26
27
CLKDSBL
BER_LVL
BER_ALM
I
I
LVTTL
Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note: This input has a weak internal pulldown.
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. When the BER exceeds the pro-
grammed threshold, BER_ALM is driven low. If this
pin is tied to GND, BER_ALM is disabled.
O
LVTTL
GND
Bit Error Rate Alarm.
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded.
There is no hysteresis.
28
NC
No Connect.
Leave this pin disconnected.
GND Pad
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 28-lead QFN (see Figure 16 on page 23)
must be connected directly to supply ground.
Minimize the ground path inductance for optimal
performance.
Rev. 1.4
21
Si5017
6. Ordering Guide
Part Number
Package
Voltage
Lead-Free
Temperature
Si5017-X-GM
28-Lead QFN
3.3
Yes
–40 to 85 °C
1. “X” denotes product revision.
2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
22
Rev. 1.4
Si5017
7. Package Outline
Figure 16 illustrates the package details for the Si5017. Table 9 lists the values for the dimensions shown in the
illustration.
2X
0.10 C
A
A
D
D/2
0.05 C
A
b
M
D1
0.10
N
C
A
B
A1
D1/2
D2
2X
N
C
B
0.10
1
2
3
1
2
3
E1/2
E1
E/2
E
B
(Ne–1) Xe
REF.
E2
L
θ
C
SEATING
PLANE
e
TOP VIEW
(Nd–1) Xe
REF.
C
C
C
L
b
A1
BOTTOM VIEW
SECTION "C–C"
e
SCALE: NONE
Approximate device weight is 62.2 mg.
Figure 16. 28-Lead Quad Flat No-Lead (QFN)
Table 9. Package Diagram Dimensions
Controlling Dimension: mm
Symbol
Millimeters
Nom
Min
—
Max
0.90
0.05
0.30
A
A1
b
0.85
0.00
0.18
0.01
0.23
D
5.00 BSC
4.75 BSC
3.10
D1
D2
E
2.95
2.95
3.25
3.25
5.00 BSC
4.75 BSC
3.10
E1
E2
N
28
Nd
Ne
e
7
7
0.50 BSC
0.60
L
0.50
0.75
12°
θ
Rev. 1.4
23
Si5017
ꢀ Updated Figure 16, “28-Lead Quad Flat No-Lead
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
(QFN),” on page 23.
ꢀ Updated Table 9, “Package Diagram Dimensions,”
on page 23.
ꢀ Added Figure 4, “PLL Acquisition Time,” on page 6.
ꢀ Table 2 on page 7
ꢁ Changed dimension A.
ꢁ Changed dimension E2.
ꢁ Added FEC (2.7 GHz) Supply Current
ꢁ Updated values: Supply Current
ꢁ Added FEC (2.7 GHz) Power Dissipation
ꢁ Updated values: Power Dissipation
ꢁ Updated values: Common Mode Input Voltage
(REFCLK)
Revision 1.2 to Revision 1.3
ꢀ Table 2 on page 7.
ꢁ Updated power consumption.
ꢁ Updated R .
IN
ꢀ Table 3 on page 8.
ꢁ Updated values: Output Common Mode Voltage
ꢁ Updated clock to data delay.
ꢁ Updated slicing level accuracy.
ꢀ Table 4 on page 9.
ꢁ Updated tolerance.
ꢁ Updated acquisition time.
ꢁ Updated reference clock information.
ꢀ Updated "Ordering Guide" on page 22.
ꢁ Added “X” to part number.
ꢀ Table 3 on page 8
ꢁ Added separate Output Clock Rise Time
ꢁ Added separate Output Clock Fall Time
ꢁ Updated values: Output Clock Rise Time
ꢁ Updated values: Output Clock Fall Time
ꢀ Table 4 on page 9
ꢁ Updated values: Jitter Tolerance (OC-48) for f = 1 MHz
ꢁ Updated values: Acquisition Time
(reference clock applied)
ꢁ Updated values: Acquisition Time
(reference-less operation)
Revision 1.3 to Revision 1.4
ꢀ Updated Table 2 on page 7.
ꢁ Added limits for V
.
ꢁ Updated values: Freq Difference at which Receive PLL
goes out of Lock
ICM
ꢁ Updated V
.
OD
ꢁ Updated values: Freq Difference at which Receive PLL
goes into Lock
ꢀ Updated Table 3 on page 8.
ꢁ Updated T
ꢁ Updated T
.
Cr-D
ꢀ Removed “Hysteresis Dependency” Figure.
.
Cf-D
ꢀ Added Figure 7, “LOS Signal Hysteresis,” on page
ꢁ Revised SLICE specification.
ꢀ Updated Table 4 on page 9.
13.
ꢀ Corrected error: Table 8 on page 19—changed
description for LOS_LVL from “LOS is disabled when
the voltage applied is less than 500 mV” to “LOS is
disabled when the voltage applied is less than
1.0 V.”
ꢁ T min/max values updated.
AQ
ꢀ Updated "Loss-of-Signal (LOS)" on page 13.
ꢁ Added note describing valid signal.
ꢁ Updated Figure 6, “LOS_LVL Mapping,” on page 13.
ꢀ Updated "Data Slicing Level" on page 14.
ꢁ Added Figure 8 on page 14.
Revision 1.0 to Revision 1.1
ꢁ Revised text.
ꢀ Corrected “Revision 0.1 to Revision 1.0” Change
List.
Revision 1.1 to Revision 1.2
ꢀ Added Figure 5, “LOS Response Time,” on page 6.
ꢀ Updated Table 2 on page 7
ꢁ Added “Output Common Mode Voltage (DOUT)” with
updated values.
ꢁ Added “Output Common Mode Voltage (CLKOUT)” with
updated values.
ꢀ Table 3 on page 8.
ꢁ Added “Output Clock Duty Cycle”
ꢁ Added “Loss-of-Signal Response Time”
ꢀ Updated Table 8 on page 19
ꢁ Changed “clock input” to “DIN inputs” for Loss-of-Signal.
24
Rev. 1.4
Si5017
NOTES:
Rev. 1.4
25
Si5017
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: HighSpeed@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
26
Rev. 1.4
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