SI5315A-C-GM [SILICON]
Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet; 提供SONET / PDH和Ethemet之间的抖动衰减和频率转换
| 型号： | SI5315A-C-GM |
| 厂家： | 
SILICON |
| 描述： | Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet |
| 文件： | 总54页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5315
SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING
CLOCK MULTIPLIER
Features
Provides jitter attenuation and frequency Selectable loop bandwidth for jitter
translation between SONET/PDH and
Ethernet
attenuation: 60 to 8.4 kHz
Automatic/Manual hitless switching
and holdover during loss of inputs
clock
Programmable output clock signal
format: LVPECL, LVDS, CML or
CMOS
Supports ITU-T G.8262 Synchronous
Ethernet equipment slave clock (EEC
option 1 and 2) requirements with
optional Stratum 3 compliant timing card
clock source
Two clock inputs/two clock outputs
Input frequency range: 8 kHz–644 MHz
Output frequency range: 8 kHz–644 MHz On-chip voltage regulator with high
40 MHz crystal or XO reference
Single supply: 1.8, 2.5, or 3.3 V
Ultra low jitter:
PSRR
0.23 ps RMS (1.875–20 MHz)
0.47 ps RMS (12 kHz–20 MHz)
Simple pin control interface
Loss of lock and loss of signal alarms
Small size: 6 x 6 mm, 36-QFN
Wide temperature range: –40 to
+85 ºC
Ordering Information:
See page 48.
Applications
Pin Assignments
Synchronous Ethernet line cards
SONET OC-3/12/48 line cards
PON OLT/ONU
Carrier Ethernet switches routers
MSAN / DSLAM
T1/E1/DS3/E3 line cards
Description
36 35 34 33 32 31 30 29 28
RST
1
2
3
4
5
6
7
8
9
27 FRQSEL3
26
The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous
Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE
EEC options 1 and 2 when paired with a timing card that implements the required
wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to
644.53 MHz. The input clock frequency and clock multiplication ratio are selectable
from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon
FRQTBL
LOS1
LOS2
VDD
FRQSEL2
25 FRQSEL1
24
23
FRQSEL0
BWSEL1
GND
Pad
XA
22 BWSEL0
XB
21
20
19
CS_CA
GND
GND
GND
AUTOSEL
®
10 11 12 13 14 15 16 17 18
Laboratories' third-generation DSPLL technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop bandwidth is
user programmable, providing jitter performance optimization at the application level.
Functional Block Diagram
XTAL/Clock
Si5315
Clock Out 1
Clock In 1
®
Output Signal Format[1:0]
Clock Out 2
DSPLL
Clock In 2
Clock 2 Disable/PLL Bypass
Loss of Lock
Loss of Signal 1
Loss of Signal 2
Status/Control
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency Select[3:0]
Manual/Auto Clock Selection
Frequency Table Select
Clock Switch/Clock Active Indicator
XTAL/Clock
Loop Bandwidth Select[1:0]
Rev. 1.0 4/12
Copyright © 2012 by Silicon Laboratories
Si5315
Si5315
2
Rev. 1.0
Si5315
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . .11
1.2. Three-Level (3L) Input Pins (With External Resistors) . . . . . . . . . . . . . . . . . . . . . . .12
2. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. System Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1. Frequency Multiplication Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.3. Input Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.4. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.5. Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.6. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
6. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.1. Input Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.2. Output Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
7.1. Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
8. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
9. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
9.1. 10G LAN SyncE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
10. Pin Descriptions: Si5315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
11. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
12. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
13. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
14.1. Si5315 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Rev. 1.0
3
Si5315
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
–40
Typ
25
Max
85
Unit
ºC
V
Temperature Range
Supply Voltage
T
A
V
3.3 V nominal
2.5 V nominal
1.8 V nominal
2.97
2.25
1.71
3.3
2.5
1.8
3.63
2.75
1.89
DD
V
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Current (Supply
current is independent of
I
LVPECL Format
644.53125 MHz Out
All CKOUTs Enabled
—
251
279
mA
DD
1
V
)
DD
LVPECL Format
644.53125 MHz Out
Only 1 CKOUT Enabled
—
—
—
217
204
194
243
234
220
mA
mA
mA
1
CMOS Format
25.00 MHz Out
All CKOUTs Enabled
2
CMOS Format
25.00 MHz Out
Only CKOUT1 Enabled
2
CKINn Input Pins
Input Common Mode Voltage
(Input Threshold Voltage)
V
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Single-ended
0.9
1.0
1.1
20
0
—
—
—
40
—
1.4
1.7
1.95
60
V
V
ICM
V
Input Resistance
Input Voltage Level Limits
Notes:
CKN
CKN
k
V
RIN
V
VIN
DD
1. Refers to Si5315A speed grade.
2. Refers to Si5315B speed grade.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
4
Rev. 1.0
Si5315
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
< 212.5 MHz
Min
Typ
Max
Units
Single-ended Input Voltage
Swing
V
f
f
f
f
0.2
—
—
—
—
—
V
V
V
V
ISE
CKIN
PP
PP
PP
PP
See Figure 2.
> 212.5 MHz
0.25
0.2
—
—
—
CKIN
See Figure 2.
< 212.5 MHz
CKIN
Differential Input
Voltage Swing
V
ID
See Figure 2.
> 212.5 MHz
0.25
CKIN
See Figure 2.
CKOUTn Output Clocks
Common Mode
V
LVPECL 100 load
V
1.42
–
—
—
V
1.25
–
V
OCM
DD
DD
line-to-line
Differential Output Swing
Single Ended Output Swing
Differential Output Voltage
V
LVPECL 100 load
1.1
1.9
V
OD
PP
PP
line-to-line
V
LVPECL 100 load
0.5
—
0.93
500
—
V
SE
line-to-line
CKO
CML 100 load
350
—
425
mV
PP
VD
line-to-line
Common Mode
Output Voltage
CKO
CML 100 load
V
–
V
VCM
DD
0.36
line-to-line
Differential
Output Voltage
CKO
LVDS 100 load
500
350
1.125
—
700
425
1.2
900
500
1.275
—
mV
VD
PP
line-to-line
Low swing LVDS 100 load
mV
PP
line-to-line
Common Mode
Output Voltage
CKO
LVDS 100 load
V
VCM
line-to-line
Differential Output Resistance
CKO
CML, LVPECL, LVDS,
Disable
200
RD
Output Voltage Low
Output Voltage High
CKO
CKO
CMOS
—
—
—
0.4
—
V
V
VOLLH
V
= 1.71 V
0.8 x V
DD
VOHLH
DD
CMOS
Notes:
1. Refers to Si5315A speed grade.
2. Refers to Si5315B speed grade.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
Rev. 1.0
5
Si5315
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
CKO
Test Condition
Min
Typ
Max
Units
Output Drive Current
CMOS
IO
Driving into CKO
for out-
VOL
put low or CKO
for out-
VOH
put high. CKOUT+ and
CKOUT– shorted externally.
V
V
= 1.71 V
= 2.97 V
7.5
32
—
—
—
—
mA
mA
DD
DD
2-Level LVCMOS Input Pins
Input Voltage Low
V
V
V
V
V
V
V
= 1.71 V
= 2.25 V
= 2.97 V
= 1.89 V
= 2.25 V
= 3.63 V
—
—
—
—
—
—
—
—
—
—
75
0.5
0.7
0.8
—
V
V
IL
DD
DD
DD
DD
DD
DD
—
V
Input Voltage High
V
1.4
1.8
2.5
—
V
IH
—
V
—
V
Input Low Current
Input High Current
I
50
50
—
µA
µA
k
IL
I
—
IH
Weak Internal Input Pull-up
Resistor
R
—
PUP
Weak Internal Input
Pull-down Resistor
R
—
75
—
k
PDN
3-Level Input Pins
Input Voltage Low
Input Voltage Mid
Input Voltage High
Input Low Current
Input Mid Current
Input High Current
0.15 x VDD
V
—
0.45 x VDD
0.85 x VDD
–20
—
—
—
—
—
—
V
V
ILL
0.55 x VDD
V
IMM
V
—
—
2
V
IHH
ILL
I
See note 3.
See note 3.
See note 3.
µA
µA
µA
I
–2
IMM
I
—
20
IHH
Notes:
1. Refers to Si5315A speed grade.
2. Refers to Si5315B speed grade.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
6
Rev. 1.0
Si5315
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVCMOS Output Pins
Output Voltage Low
V
I = 2 mA
—
—
—
—
—
—
—
0.4
0.4
—
V
V
OL
OH
OZ
O
V
V
= 1.62 V
DD
I = 2 mA
O
= 2.97 V
DD
Output Voltage High
V
I = –2 mA
V
V
– 0.4
V
O
DD
DD
V
= 1.62 V
DD
I = –2 mA
– 0.4
—
V
O
V
= 2.97 V
DD
Disabled Leakage Current
I
RST = 0
–100
100
µA
Single-Ended Reference Clock Input Pin XA (XB with Cap to Gnd)
Input Resistance
XA
XA
XTAL/CLOCK = M
XTAL/CLOCK = M
—
0
12
—
—
—
k
RIN
VIN
Input Voltage Level Limits
Input Voltage Swing
1.2
1.2
V
XA
0.5
V
PP
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Resistance
XA/XB
—
0
12
—
—
k
RIN
VIN
Differential Input Voltage
Level Limits
XA/XB
1.2
V
Input Voltage Swing
XA
/XB
0.5
—
2.4
V
PP
VPP
VPP
Notes:
1. Refers to Si5315A speed grade.
2. Refers to Si5315B speed grade.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
Rev. 1.0
7
Si5315
Table 3. AC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Input Frequency
CKINn Input Pins
CKN
0.008
—
644.53 MHz
F
Input Duty Cycle (Minimum
Pulse Width)
40
2
—
—
—
—
60
—
3
%
ns
pF
ns
1
CKN
Whichever is smaller
DC
Input Capacitance
CKN
—
—
CIN
Input Rise/Fall Time
CKN
20–80%
11
TRF
See Figure 2
CKOUTn Output Pins
Output Frequency (Output not
configured for CMOS or disable)
Note 2
Note 3
0.008
0.008
—
—
—
—
644.53 MHz
125 MHz
161.13 MHz
CK
OF
Maximum Output Frequency in CKO
CMOS Format
FMC
Output Rise/Fall (20–80%) at
644.5313 MHz
CKO
Output not configured for CMOS
or disabled, see Figure 2
—
—
230
—
350
8
ps
ns
TRF
Single Ended Output Rise/Fall
(20–80%)
CMOS Output
V
= 1.62
DD
Cload = 5 pF
CKO
TRF
CMOS Output
—
—
—
—
2
ns
ps
V
= 2.97
DD
Cload = 5 pF
Output Duty Cycle Differential
Uncertainty
CKO
100 Load
Line to Line
±40
DC
Measured at 50% Point
(not for CMOS)
LVCMOS Pins
Input Capacitance
Notes:
C
—
—
3
pF
in
1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 µs.
2. Refers to Si5315A speed grade.
3. Refers to Si5315B speed grade.
8
Rev. 1.0
Si5315
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVCMOS Output Pins
Rise/Fall Times
t
CLOAD = 20 pf
See Figure 2
—
—
—
25
—
10
—
750
—
ns
µs
RF
LOSn Trigger Window
From last CKINn to
internal detection of LOSn
LOS
t
TRIG
Time to Clear LOL after LOS
Cleared
LOS to LOL
Assume Fold=Fnew,
Stable XA-XB reference
ms
CLRLOL
PLL Performance
Output Clock Skew
t
of CKOUTn to CKOUTn
—
—
—
100
500
ps
ps
SKEW
Phase Change Due to
Temperature Variation
t
Maximum phase change from
–40 to +85 °C
300
TEMP
Lock Time
t
RST with valid CKIN to LOL;
—
—
1200
0.05
—
ms
dB
LOCKHW
BW = 100 Hz
Closed Loop Jitter Peaking
Jitter Tolerance
J
0.1
PK
See 4.2.3. "Jitter Toler- ns pk-
J
TOL
ance" on page 18.
pk
µs
ps
Minimum Reset Pulse Width
Output Clock Initial Phase Step
t
1
—
—
RSTMIN
P_STEP
During clock switch CKIN > 19.44
MHz
—
—
—
—
100
200
t
Holdover Frequency Historical
Averaging Time
6.7
26.2
–75
—
sec
ms
t
t
HISTAVG
HISTDEL
Holdover Frequency Historical
Delay Time
—
Spurious Noise
Max spur @ n x f3
(n > 1, n x f3 < 100 MHz)
—
dBc
SP
SPUR
Notes:
1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 µs.
2. Refers to Si5315A speed grade.
3. Refers to Si5315B speed grade.
Rev. 1.0
9
Si5315
Table 4. Jitter Generation
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
1,2,3,4
Parameter
Symbol
Min
Typ
Max
GR-253 Spec
Unit
Test Condition
1
Measuremen
DSPLL BW
t Filter (MHz)
0.02–80
4–80
5
167 Hz
—
—
—
0.483 0.628
0.302 0.392
0.467 0.607
N/A
N/A
ps
ps
ps
rms
rms
rms
5
167 Hz
Jitter Gen OC-192
Jitter Gen OC-48
J
GEN
5
0.05–80
167 Hz
1.0 ps
rms
(0.01 UI
rms
5
167 Hz
—
—
—
0.470 0.611
0.565 0.734
0.232 0.301
4.02 ps
(0.01 UI
4.02 ps
(0.01 UI
ps
ps
ps
rms
rms
rms
rms
)
rms
J
J
0.012–20
1.875–20
GEN
6
111 Hz
rms
rms
)
IEEE 802.3 GbE
RMS Jitter
6
83 Hz
GEN
Notes:
1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 20.
2. 40 MHz fundamental mode crystal used as XA/XB input.
3. VDD = 2.5 V
4. TA = 85 °C
5. Si5315A test condition: fIN = 19.44 MHz, fOUT = 156.25 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
(20–80%), LVPECL clock output.
6. Si5315B test condition: fIN =19.44 MHz, fOUT = 125 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20-
80%), LVPECL clock output.
V
SIGNAL +
Single-Ended
Peak-to-Peak Voltage
Differential I/Os
V
ICM , V
VISE,VOSE
SIGNAL – OCM
(SIGNAL +) – (SIGNAL –)
ICM, VOCM
Differential
Peak-to-Peak Voltage
V ,VOD
ID
V
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
Figure 1. CKIN Voltage Characteristics
80%
20%
DOUT, CLOUT
tF
tR
Figure 2. Rise/Fall Time Characteristics
10
Rev. 1.0
Si5315
1.1. Three-Level (3L) Input Pins (No External Resistors)
VDD
Si5315
75 k
Iimm
75 k
External Driver
Figure 3. Three-Level Input Pins
Table 5. Three-Level Input Pins (No External Resistors)
Parameter
Symbol
Vill
Min
—
Max
0.15 x V
0.55 x V
—
Input Voltage Low
Input Voltage Mid
Input Voltage High
Input Low Current
Input Mid Current
Input High Current
DD
DD
Vimm
Vihh
Iill
0.45 x V
0.85 x V
–6 µA
–2 µA
—
DD
DD
—
Iimm
Iihh
2 µA
6 µA
Note: The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver.
Rev. 1.0
11
Si5315
1.2. Three-Level (3L) Input Pins (With External Resistors)
VDD
18 k
VDD
Si5315
75 k
Iimm
18 k
75 k
External Driver
One of eight resistors from a Panasonic EXB-D10C183J
(or similar) resistor pack
Figure 4. Three Level Input Pins
Table 6. Three-Level Input Pins (With External Resistors)
Parameter
Symbol
Iill
Min
–30 µA
–11 µA
—
Max
—
Input Low Current
Input Mid Current
Input High Current
Iimm
Iihh
–11 µA
–30 µA
Note: The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver.
Any resistor pack may be used.
The Panasonic EXB-D10C183J is an example.
PCB layout is not critical.
Resistor packs are only needed if the leakage current of the external driver exceeds the listed currents.
If a pin is tied to ground or V , no resistors are needed.
DD
If a pin is left open (no connect), no resistors are needed.
12
Rev. 1.0
Si5315
Table 7. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Thermal Resistance
Junction to Ambient
Still Air
—
32
—
ºC/W
JA
Thermal Resistance
Junction to Case
Still Air
—
14
—
ºC/W
JC
Table 8. Absolute Maximum Limits
Parameter
Symbol
Value
Unit
DC Supply Voltage
V
–0.5 to 3.8
V
V
DD
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
DD
DIG
CKINn Voltage Level Limits
XA/XB Voltage Level Limits
Operating Junction Temperature
Storage Temperature Range
CKN
0 to V
V
VIN
DD
XA
0 to 1.2
–55 to 150
–55 to 150
2
V
VIN
T
C
C
kV
JCT
T
STG
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except
CKIN+/CKIN–
ESD MM Tolerance; All pins except CKIN+/CKIN–
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
ESD MM Tolerance; CKIN+/CKIN–
150
V
V
V
750
100
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Rev. 1.0
13
Si5315
2. Typical Application Circuit
C4
C3
1 µF
System
Power
Supply
0.1 µF
Ferrite
Bead
C2
C1
0.1 µF
0.1 µF
VDD = 3.3 V
130
82
130
82
0.1 µF
CKOUT1+
CKOUT1–
CKIN1+
CKIN1–
+
–
100
0.1 µF
0.1 µF
Clock Outputs to
Ethernet PHYs
CKOUT2+
CKOUT2–
+
–
Backplane or Line
Recovered Clock
Inputs
100
VDD = 3.3 V
0.1 µF
130
82
130
82
CKIN2+
CKIN2–
LOS1
LOS2
LOL
CKIN1 Loss of Signal Indicator
CKIN2 Loss of Signal Indicator
PLL Loss of Lock Indicator
XA
XB
Option 1:
40 MHz Crystal
0.1 µF
Si5315
Option 2:
Ext. Refclk+
Ext. Refclk–
XA
XB
0.1 µF
VDD
15 k
XTAL/Clock2
AUTOSEL2
CS3
Crystal/Ref Clk
VDD
VDD
VDD
VDD
15 k
Manual/Automatic Clock 15 k
Selection (L)15 k
VDD
15 k
Input Clock Select
15 k
15 k
FRQTBL2
Frequency Table Select
VDD
15 k
15 k
FRQSEL[3:0]2
BWSEL[1:0]2
Frequency Select
15 k
15 k
Bandwidth Select
VDD
15 k
15 k
Signal Format Select
SFOUT[1:0]2
DBL2_BY2
RST
15 k
Clock Output 2 Disable/ 15 k
Bypass Mode Control 15 k
Reset
Notes:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. Assumes manual input clock selection.
Figure 5. Si5315 Typical Application Circuit
14
Rev. 1.0
Si5315
3. System Level Overview
The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous
Ethernet* line card timing applications.
*Note: The Si5315 supports SyncE EEC options 1 and 2 when paired with a timing card that implements the required wander
filtering and Stratum 3 compliant reference clock. For detailed information, refer to “AN420: SyncE and IEEE 1588: Sync
Distribution for a Unified Network”.
The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous
Ethernet line card timing applications. The device accepts two clock inputs ranging from 8 kHz to 644.53 MHz and
generates two equal frequency, low jitter clock outputs ranging from 8 kHz to 644.53 MHz. For ease of use, the
Si5315 is pin controlled to enable simple device configuration of frequency plans, PLL loop bandwidth, and input
clock selection. The DSPLL locks to one of two input reference clocks and provides over 200 frequency
translations to synchronize output clocks for Ethernet, SONET/SDH, and PDH line cards. The Si5315 implements
internal state machines to control hitless switching between input clocks and holdover. Status alarms, loss of signal
(LOS) and loss of lock (LOL) are provided on output pins to indicate a change in device status.
This device is designed for systems with line cards that are synchronized to a redundant, centralized telecom or
Ethernet backplane. The Si5315 synchronizes to backplane clocks and generates a multiplied, jitter attenuated
Ethernet/SONET/SDH clock or PDH clock. A typical system application is shown in Figure 6. The Si5315
translates a 19.44 MHz clock from the telecom backplane to an Ethernet or SONET/SDH clock frequency to the
PHY and filters the jitter to ensure compliance with related ITU-T and Telcordia standards.
Telecom
or
Ethernet
Redundant
Timing Cards
10G LAN / WAN
SyncE Line Card
Backplane
Wander Filtering
Hitless Switching
Holdover
Tx Timing Path
Hitless Switching
Jitter Filtering
Frequency Translation
10GbE
PHY
A
B
BITS A
BITS B
Network
Synchronization
155.52 MHz
156.25 MHz
161.1328125 MHz
A
B
Si5315
8 kHz
19.44 MHz
25 MHz
10GbE
PHY
Rx Timing Path
Line
Recovered
Clocks
8 kHz
19.44 MHz
25 MHz
Multi-Port
SONET / SDH / PDH Line Card
Tx Timing Path
Hitless Switching
Jitter Filtering
Frequency Translation
OC-3 / 12
77.76 / 155.52 MHz
1.544 / 2.048 MHz
A
B
Si5315
T1 / E1
Rx Timing Path
Line
Recovered
Clocks
8 kHz
19.44 MHz
25 MHz
Figure 6. Typical Si5315 Application
Rev. 1.0
15
Si5315
4. Functional Description
Crystal or
Reference Clock
Xtal/Clock
XB
XA
PLL Bypass
0
1
2
CKOUT1+
CKOUT1–
2
CKIN1+
CKIN1–
0
1
f3
fOSC
DSPLL®
2
SFOUT[1:0]
CKIN2+
CKIN2–
0
1
2
CKOUT2+
CKOUT2–
LOS1
LOS2
DBL2_BY
Signal Detect
Control
LOL
AUTOSEL
CS/CA
RST
Bandwidth
Control
BWSEL[1:0]
VDD (1.8, 2.5, or 3.3 V)
GND
FRQSEL[3:0]
FRQTBL
Frequency
Control
Figure 7. Detailed Block Diagram
4.1. Overview
The Si5315 is a jitter-attenuating precision clock multiplier for Synchronous Ethernet, SONET/SDH, and PDH
(T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two
frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The two input clocks are at the same
frequency and the two output clocks are at the same frequency. The input clock frequency and clock multiplication
ratio are selectable from a look up table of popular SyncE and T1/E1 rates.
®
The Si5315 is based on Silicon Laboratories' 3rd-generation DSPLL technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The Si5315 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a
range from 60 to 8.4 kHz.
The Si5315 supports hitless switching between the two input clocks in compliance with ITU-T G.8262 and Telcordia
GR-253-CORE and GR-1244-CORE. This feature greatly minimizes the propagation of phase transients to the
clock outputs during an input clock transition (<200 ps typ). Manual and automatic revertive and non-revertive input
clock switching options are available via the AUTOSEL input pin. The Si5315 monitors both input clocks for loss-of-
signal and provides a LOS alarm when it detects missing pulses on either input clock. The device monitors the lock
status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock. The Si5315 provides a holdover capability that allows the device to
continue generation of a stable output clock when the selected input reference is lost.
The Si5315 has two differential clock outputs. The signal format of the clock outputs is programmable to support
LVPECL, LVDS, CML, or CMOS loads. The second clock output can be powered down to minimize power
consumption. For system-level debugging, a bypass mode is available which drives the output clock directly from
the input clock, bypassing the internal DSPLL. The device operates from a single 1.8, 2.5, or 3.3 V supply.
16
Rev. 1.0
Si5315
4.2. PLL Performance
The Si5315 provides extremely low jitter generation, a well-controlled jitter transfer function, and high jitter
tolerance due to the high level of integration.
4.2.1. Jitter Generation
Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock.
Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of
the PLL bandwidth setting. Higher loop bandwidth settings may result in lower jitter generation, but may result in
less attenuation of jitter that might be present on the input clock signal.
4.2.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5315 provides tightly controlled jitter transfer curves because the PLL gain parameters
are determined largely by digital circuits which do not vary over supply voltage, process, and temperature. In a
system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board
and provides more consistent system level jitter performance.
The jitter transfer characteristic is a function of the loop bandwidth setting. Lower bandwidth settings result in more
jitter attenuation of the incoming clock, but may result in higher jitter generation. Figure 8 shows the jitter transfer
curve mask.
Jitter
Transfer
Jitter Out
Jitter In
0 dB
Peaking
–20 dB/dec.
fJitter
BW
Figure 8. PLL Jitter Transfer Mask/Template
Rev. 1.0
17
Si5315
4.2.3. Jitter Tolerance
Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock
before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for
lower input jitter frequency.
The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 9 shows the general shape of
the jitter tolerance curve versus input jitter frequency. For jitter frequencies above the loop bandwidth, the tolerance
is a constant value A . Beginning at the PLL bandwidth, the tolerance increases at a rate of 20 dB/decade for
j0
lower input jitter frequencies.
Input
Jitter
–20 dB/dec.
Amplitude
Excessive Input Jitter Range
Aj0
BW
BW/100 BW/10
fJitter In
Figure 9. Jitter Tolerance Mask/Template
The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth
(i.e., BW):
5000
BW
------------
ns pk-pk
Aj0
=
For example, the jitter tolerance when f = 19.44 MHz, f = 161.13 MHz and the loop bandwidth (BW) is 113 Hz:
in
out
5000
113
------------
Aj0
=
= 44.24 ns pk-pk
4.2.4. Jitter Attenuation Performance
The Internal VCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins
support either a crystal input or an input buffer single-ended or differential clock input, such that an external
oscillator can become the reference source. In either case, the device accepts a wide margin in absolute frequency
of the reference input. (See 5.5. "Holdover Mode" on page 32.) In holdover, the Si5315's output clock stability
matches the reference supplied on the XA/XB pins. The external crystal or reference clock must be selected based
on the stability requirements of the application if holdover is a key requirement.
However, care must be exercised in certain areas for optimum performance. For examples of connections to the
XA/XB pins, refer to 7. "Crystal/Reference Clock Input" on page 38.
18
Rev. 1.0
Si5315
5. Frequency Plan Tables
For ease of use, the Si5315 is pin controlled to enable simple device configuration of the frequency plan and PLL
loop bandwidth via a predefined look up table. The DSPLL has been optimized for each frequency multiplication
and PLL loop bandwidth provided in Table 9 on page 20.
Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels
determined by the supply voltage: V and Ground. If the input pin is left floating, it is driven to nominally half of
DD
V
. Effectively, this creates three logic levels for these controls. See 1.2. "Three-Level (3L) Input Pins (With
DD
External Resistors)" on page 12 and 8. "Power Supply Filtering" on page 41 for additional information.
5.1. Frequency Multiplication Plan
The input to output clock multiplication is set by the 3-level FRQSEL[3:0] pins. The device provides a wide range of
commonly used SyncE, SONET/SDH, and PDH frequency translations. The CKIN1 and CKIN2 inputs must be the
same frequency as specified in Table 9. Both CKOUT1 and CKOUT2 outputs are at the same frequency.
5.1.1. PLL Loop Bandwidth Plan
The Si5315's loop bandwidth ranges from 60 Hz to 8.4 kHz. For each frequency multiplication, its corresponding
loop bandwidth is provided in a simple look up table. (See Table 9 on page 20.) The loop bandwidth (BW) is
digitally programmable using the 3-level BWSEL [1:0] and FRQTBL input pins.
Rev. 1.0
19
Si5315
20
Rev. 1.0
Si5315
Rev. 1.0
21
Si5315
22
Rev. 1.0
Si5315
Rev. 1.0
23
Si5315
24
Rev. 1.0
Si5315
Rev. 1.0
25
Si5315
26
Rev. 1.0
Si5315
Rev. 1.0
27
Si5315
28
Rev. 1.0
Si5315
5.2. PLL Self-Calibration
An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter
performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the self-
calibration state machine. The LOL alarm will be active during ICAL. The self-calibration time t
Table 3, “AC Characteristics”.
is given in
LOCKHW
Any of the following events will trigger a self-calibration:
Power-on-reset (POR)
Release of the external reset pin RST (transition of RST from 0 to 1)
Change in FRQSEL, FRQTBL, BWSEL, or XTAL/CLOCK pins
Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL
In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm)
and is selected as the active clock at that time. The external crystal or reference clock must also be present for the
self-calibration to begin. If valid clocks are not present, the self-calibration state machine will wait until they appear,
at which time the calibration will start. An output clock will be active while waiting for a valid input clock. The output
clock frequency is based on the VCO range determine by FRQSEL and FRQTBL settings. This output clock will
vary by ±20%. If no output clock is desired prior to an ICAL, then the SFOUT pins should be kept at LM for
1.2 seconds until the output clock is stable.
After a successful self-calibration has been performed with a valid input clock, no subsequent self calibrations are
performed unless one of the above conditions are met. If the input clock is lost following self-calibration, the device
enters holdover mode. When the input clock returns, the device relocks to the input clock without performing a self-
calibration.
5.2.1. Input Clock Stability during Internal Self-Calibration
An exit from reset must occur when the selected CKINn clock is stable in frequency with a frequency value that is
within the device operating range. The other CKINs must also either be stable in frequency or squelched during a
reset.
5.2.2. Self-Calibration caused by Changes in Input Frequency
If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a
self-calibration.
5.2.3. Device Reset
Upon powerup, the device internally executes a power-on-reset (POR) which resets the internal device logic. The
pin RST can also be used to initiate a reset. The device stays in this state until a valid CKINn is present, when it
then performs a PLL Self-Calibration (See 5.2. "PLL Self-Calibration”).
5.2.4. Recommended Reset Guidelines
Follow the recommended RESET guidelines in Table 10 when reset should be applied to a device.
Table 10. Si5315 Pins and Reset
Pin #
2
Si5315 Pin Name
FRQTBL
Must Reset after Changing
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
11
XTAL/CLOCK
BWSEL0
22
23
24
25
26
27
BWSEL1
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
Rev. 1.0
29
Si5315
5.2.5. Hitless Switching with Phase Build-Out
Silicon Laboratories switching technology performs "phase build-out" to minimize the propagation of phase
transients to the clock outputs during input clock switching. All switching between input clocks occurs within the
input multiplexor and phase detector circuitry. The phase detector circuitry continually monitors the phase
difference between each input clock and the DSPLL output clock, f
. The phase detector circuitry can lock to a
OSC
clock signal at a specified phase offset relative to f
so that the phase offset is maintained by the PLL circuitry.
OSC
At the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for
the original input clock and for the new input clock. The phase detector circuitry locks to the new input clock at the
new clock's phase offset so that the phase of the output clock is not disturbed. The phase difference between the
two input clocks is absorbed in the phase detector's offset value, rather than being propagated to the clock output.
The switching technology virtually eliminates the output clock phase transients traditionally associated with clock
rearrangement (input clock switching). The Maximum Time Interval Error (MTIE) and maximum slope for clock
output phase transients during clock switching are given in (Table 3, “AC Characteristics”). These values fall
significantly below the limits specified in the ITU-T G.8262, Telcordia GR-1244-CORE, and GR-253-CORE
requirements.
5.3. Input Clock Control
This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless
switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two
clocks differ in frequency by more than 100 ppm.
5.3.1. Manual Clock Selection
Manual control of input clock selection is chosen via the CS_CA pin according to Table 11 and Table 12.
Table 11. Automatic/Manual Clock Selection
AUTOSEL
Clock Selection Mode
Manual
L
M
H
Automatic non-revertive
Automatic revertive
Table 12. Manual Input Clock Selection, AUTOSEL = L
CS_CA
Si5315
AUTOSEL = L
0
1
CKIN1
CKIN2
5.3.2. Automatic Clock Selection
The AUTOSEL input pin sets the input clock selection mode as shown in Table 11. Automatic switching is either
revertive or non-revertive. Setting AUTOSEL to M or H, changes the CS_CA pin to an output pin that indicates the
state of the automatic clock selection.
Table 13. Clock Active Indicators, AUTOSEL = M or H
CS_CA
Active Clock
CKIN1
0
1
CKIN2
30
Rev. 1.0
Si5315
The prioritization of clock inputs for automatic switching is shown in Table 14. This priority is hardwired in the
devices.
Table 14. Input Clock Priority for Auto Switching
Priority
Input Clocks
CKIN1
1
2
3
CKIN2
Holdover
At power-on or reset, the valid CKINn with the highest priority (1 being the highest priority) is automatically
selected. If no valid CKINn is available, the device suppresses the output clocks and waits for a valid CKINn signal.
If the currently selected CKINn goes into an alarm state, the next valid CKINn in priority order is selected. If no valid
CKINn is available, the device enters holdover.
Operation in revertive and non- revertive is different when a signal becomes valid:
Revertive (AUTOSEL = H):
The device constantly monitors all CKINn. If a CKINn with a higher priority than
the current active CKINn becomes valid, the active CKINn is changed to the
CKINn with the highest priority.
Non-revertive (AUTOSEL = M): The active clock does not change until there is an alarm on the active clock. The
device will then select the highest priority CKINn that is valid. Once in holdover,
the device will switch to the first CKINn that becomes valid.
5.4. Alarms
Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all the
alarm conditions for that alarm output are cleared.
5.4.1. Loss-of-Signal
The device has loss-of-signal circuitry that continuously monitors CKINn for missing pulses. The LOS circuitry
generates an internal LOSn_INT output signal that is processed with other alarms to generate LOS1 and LOS2.
An LOS condition on CKIN1 causes the internal LOS1_INT alarm to become active. Similarly, an LOS condition on
CKINn causes the LOSn_INT alarm to become active. Once a LOSn_INT alarm is asserted on one of the input
clocks, it remains asserted until that input clock is validated over a designated time period. The time to clear
LOSn_INT after a valid input clock appears is listed in Table 3, “AC Characteristics”. If another error condition on
the same input clock is detected during the validation time then the alarm remains asserted and the validation time
starts over.
5.4.1.1. LOS Algorithm
The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. The LOS circuitry over
samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input
clock transitions. If the LOS monitor detects twice the normal number of samples without a clock edge, a
LOSn_INT alarm is declared. Table 3, “AC Characteristics” gives the minimum and maximum amount of time for
the LOS monitor to trigger.
5.4.1.2. Lock Detect
The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time
between two consecutive phase cycle slips is greater than the retrigger time, the PLL is in lock. The LOL output
has a guaranteed minimum pulse width as shown in (Table 3, “AC Characteristics”). The LOL pin is also held in the
active state during an internal PLL calibration. The retrigger time is automatically set based on the PLL closed loop
bandwidth (See Table 15).
Rev. 1.0
31
Si5315
Table 15. Lock Detect Retrigger Time
PLL Bandwidth Setting (BW)
60–120 Hz
Retrigger Time (ms)
53
120–240 Hz
240–480 Hz
26.5
13.3
6.6
480–960 Hz
960–1920 Hz
1920–3840 Hz
3840–7680 Hz
3.3
1.66
0.833
5.5. Holdover Mode
If an LOS condition exists on the selected input clock, the device enters holdover. In this mode, the device provides
a stable output frequency until the input clock returns and is validated. When the device enters holdover, the
internal oscillator is initially held to its last frequency value. Next, the internal oscillator slowly transitions to a
historical average frequency value that was taken over a time window of 6,711 ms in size that ended 26 ms before
the device entered holdover. This frequency value is taken from an internal memory location that keeps a record of
previous DSPLL frequency values. By using a historical average frequency, input clock phase and frequency
transients that may occur immediately preceding loss of clock or any event causing holdover do not affect the
holdover frequency. Also, noise related to input clock jitter or internal PLL jitter is minimized.
If a highly stable reference, such as an oven-controlled crystal oscillator, is supplied at XA/XB, an extremely stable
holdover can be achieved. If a crystal is supplied at the XA/XB port, the holdover stability will be limited by the
stability of the crystal; Table 3, “AC Characteristics” gives the specifications related to the holdover function.
5.5.1. Recovery from Holdover
When the input clock signal returns, the device transitions from holdover to the selected input clock. The device
performs hitless recovery from holdover. The clock transition from holdover to the returned input clock includes
"phase buildout" to absorb the phase difference between the holdover clock phase and the input clock phase. See
Table 3, “AC Characteristics” for specifications.
5.6. PLL Bypass Mode
The Si5315 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output
buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling;
however, this path is not a low jitter path and will see significantly higher jitter on CKOUT. In PLL bypass mode, the
input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to
measure system performance with and without the jitter attenuation provided by the DSPLL. The DSBL2_BY pin is
used to select the PLL Bypass Mode according to Table 16. Bypass mode is not supported for CMOS clock outputs
(SFOUT = LH).
Table 16. DSBL2/BYPASS Pin Settings
DSBL2/BYPASS
Function
CKOUT2 Enabled
L
M
H
CKOUT2 Disabled
PLL Bypass Mode w/ CKOUT2 Enabled
32
Rev. 1.0
Si5315
Crystal or
Reference Clock
Xtal/Clock
XB
XA
PLL Bypass
0
1
2
CKOUT1+
CKOUT1–
2
2
CKIN1+
CKIN1–
0
1
fOSC
f3
DSPLL®
CKIN2+
CKIN2–
SFOUT[1:0]
2
CKOUT2+
CKOUT2–
LOS1
LOS2
LOL
DBL2_BY
Signal Detect
Control
AUTOSEL
CS/CA
RST
Bandwidth
Control
BWSEL[1:0]
VDD (1.8, 2.5, or 3.3 V)
GND
FRQSEL[3:0]
FRQTBL
Frequency
Control
Figure 10. Bypass Signal
Rev. 1.0
33
Si5315
6. High-Speed I/O
6.1. Input Clock Buffers
The Si5315 provides differential inputs for the CKINn clock inputs. These inputs are internally biased to a common
mode voltage [see Table 2, “DC Characteristics”] and can be driven by either a single-ended or differential source.
Figure 11 through Figure 14 show typical interface circuits for LVPECL, CML, LVDS, or CMOS input clocks. Note
that the jitter generation improves for higher levels on CKINn (within the limits in Table 3, “AC Characteristics”).
AC coupling the input clocks is recommended because it removes any issue with common mode input voltages.
However, either ac or dc coupling is acceptable. Figures 11 and 12 show various examples of different input
termination arrangements. Unused inputs can be left unconnected.
3.3 V
Si5315
130
130
C
CKIN+
300
40 k
LVPECL
Driver
40 k
VICM
±
CKIN _
82
82
C
Figure 11. Differential LVPECL Termination
3.3 V
Si5315
130
C
CKIN +
300
Driver
40 k
40 k
VICM
±
CKIN _
82
C
Figure 12. Single-ended LVPECL Termination
34
Rev. 1.0
Si5315
Si5315
C
CKIN +
300
40 k
CML/
LVDS
Driver
100
40 k
VICM
±
CKIN _
C
Figure 13. CML/LVDS Termination (1.8, 2.5, 3.3 V)
CMOS Driver
VDD
VDD
VDD
Si5315
R3
VICM
150 ohms
50
R1
R2
C1
R5 40 kohm
R6 40 kohm
CKIN+
CKIN–
See Table
33 ohms
100 nF
R4
150 ohms
C2
100 nF
VDD
R2
Notes
3.3 V
2.5 V
1.8 V
100 ohm
49.9 ohm
14.7 ohm
Locate R1 near CMOS driver
Locate other components near Si5317
Recalculate resistor values for other drive strengths
Additional Notes:
1. Attenuation circuit limits overshoot and undershoot.
2. Not to be used with non-square wave input clocks.
Figure 14. CMOS Termination (1.8, 2.5, 3.3 V)
Rev. 1.0
35
Si5315
6.2. Output Clock Drivers
The Si5315 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML,
and CMOS formats. The signal format is selected for both CKOUT1 and CKOUT2 outputs using the SFOUT [1:0]
pins. This modifies the output common mode and differential signal swing. See Table 2, “DC Characteristics” for
output driver specifications. The SFOUT [1:0] pins are three-level input pins, with the states designated as L
(ground), M (V /2), and H (V ). Table 17 shows the signal formats based on the supply voltage and the type of
DD
DD
load being driven.
Table 17. Output Signal Format Selection (SFOUT)
SFOUT[1:0]
Signal Format
CML
HL
HM
LVDS
LH
CMOS
LM
Disabled
LVPECL
MH
ML
Low-swing LVDS
Reserved
All Others
Si5315
Z0 = 50
100
CKOUTn
Z0 = 50
Rcvr
Figure 15. Typical Differential Output Circuit
Si5315
CMOS
Logic
CKOUTn
Optionally Tie CKOUTn
Outputs Together for Greater Strength
Figure 16. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together)
For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals. The CKOUT+/- can be
externally shorted together for greater drive strength specified in Table 2, “DC Characteristics”.
36
Rev. 1.0
Si5315
+
SFOUT[1:0] = LM (Output Disable)
100
100
CKOUTn
Output from
DSPLL
Figure 17. Disable CKOUTn Structure
The SFOUT [1:0] pins can also be used to disable both outputs. Disabling the output puts the CKOUTn+ and
CKOUTn– pins in a high-impedance state relative to V (common mode tri-state) while the two outputs remain
DD
connected to each other through a 200 on-chip resistance (differential impedance of 200 ). The maximum
amount of internal circuitry is powered down, minimizing power consumption and noise generation. Recovery from
the disable mode requires additional time as specified in Table 3, “AC Characteristics”.
Rev. 1.0
37
Si5315
7. Crystal/Reference Clock Input
The device can use an external crystal or external clock as a reference. If an external clock is used, it must be ac
coupled. With appropriate buffers, the same external reference clock can be applied to CKINn. Although the
reference clock input can be driven single ended (See Figure 18), the best performance is with a crystal or low
jitter, differential clock source. No external loading capacitors are required for normal crystal operation.
3.3 V
150
0.1F
3.3 V
Si5315
130
10 k
XA
XB
0.6 V
150
0.1F
CMOS buffer,
8 mA output current
For 2.5 V operation, change 130 to 82 .
Figure 18. CMOS External Reference Circuit
0 dBm into 50
1.2 V
Si5315
0.01 F
XA
10 pF
0.01 F
50
10 k
0.6 V
XB
External Clock Source
0.1 µF
Figure 19. Sinewave External Reference Clock Input Example
Si5315
1.2 V
0.01 F
XA
100
XB
LVPECL, CML, etc.
10 k
10 k
0.6 V
0.01 F
Figure 20. Differential External Reference Clock Input Example
38
Rev. 1.0
Si5315
7.1. Crystal/Reference Clock Selection
The Si5315 requires either a low-jitter external oscillator or a low-cost fundamental mode crystal to be connected to
its XA/XB pins. This serves both as a jitter reference for jitter attenuation and as a reference oscillator for stability
during holdover. The frequency the reference is not directly related to either the input or the output clock
frequencies. The range of the reference frequency is from 37 to 41 MHz. For recommendations on the selection of
the reference frequency and a list of approved crystals, see the application note AN591 which can be downloaded
from www.silabs.com/timing/.
In holdover, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference
when the DSPLL is in holdover will be tracked by the output of the device. Note that crystals can have temperature
sensitivities. Table 18 shows how the XTAL/CLOCK pin is used to select between a crystal and an external
oscillator.
Table 18. XA/XB Reference Sources
XTAL/CLOCK
Type
M
L
37–41 MHz external clock
40 MHz crystal
Because the crystal is used as a jitter reference, rapid changes of the crystal temperature can temporarily disturb
the output phase and frequency. For example, it is recommended that the crystal not be placed close to a fan that
is being turned off and on. If a situation such as this is unavoidable, the crystal should be thermally isolated with an
insulating cover.
7.1.1. Reference Drift
During holdover, long-term and temperature related drift of the reference input result in a one-to-one drift of the
output frequency. That is, the stability of the any-frequency output is identical to the drift of the reference frequency.
This means that for the most demanding applications where the drift of a crystal is not acceptable, an external
temperature compensated or ovenized oscillator will be required. Drift is not an issue unless the part is in holdover.
Also, the initial accuracy of the reference oscillator (or crystal) is not relevant.
Rev. 1.0
39
Si5315
7.1.2. Reference Jitter
Jitter on the reference input has a roughly one-to-one transfer function to the output jitter over the bandwidth
ranging from 100 Hz up to 30 kHz. If a crystal is used on the XA/XB pins, the reference will have low jitter if a
suitable crystal is in use. If the XA/XB pins are connected to an external reference oscillator, the jitter of the
external reference oscillator may contribute significantly to the output jitter.
A typical reference input-to-output jitter transfer function is shown in Figure 21.
Jitter Transfer XA/XB Reference to CKOUT
38.88 MHz XO, 38.88 MHz CKIN, 38.88 MHz CKOUT
5
0
-5
-10
-15
-20
-25
-30
1
10
100
1000
10000
100000
1000000
Jitter Frequency (Hz)
Figure 21. Typical XA/XB Reference Jitter Transfer Function
40
Rev. 1.0
Si5315
8. Power Supply Filtering
This device incorporates an on-chip voltage regulator with excellent PSRR to power the device from a supply
voltage of 1.8, 2.5, or 3.3 V. The device requires minimal supply decoupling and no stringent layout or ground plane
islands. Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply
voltage directly. Table 3, “AC Characteristics” gives the sensitivity of the on-chip oscillator to changes in the supply
voltage. Refer to the Si5315 evaluation board for an example.
The center ground pad under the device must be electrically and thermally connected to the ground plane.
See Figure 26, “Ground Pad Recommended Layout,” on page 50.
0.1 uF
System
C1 – C3
Power
Supply
(1.8, 2.5, or
3.3 V)
1.0 uF
Ferrite
Bead
C4
GND &
GND Pad
VDD
Si5315
Figure 22. Typical Power Supply Bypass Network
Power Supply Noise to Output Transfer Function
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
1
10
100
1000
Frequency of Power Supply Noise (kHz)
Figure 23. Fout = 155 MHz with 112 Hz Loop Bandwidth, 100 mVp-p Supply Noise
Rev. 1.0
41
Si5315
9. Typical Phase Noise Plots
The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF
Generator. The spectrum analyzer was either an Agilent model E5052B, model E4400A or model JS-500. The
Si5315 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input
from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by
the jitter at the input clock, not the Si5315. Except as noted, loop BWs of 60 to 240 Hz were in use.
9.1. 10G LAN SyncE Example
Frequency Plan
Fin=19.44 MHz Fin=19.44 MHz
Fin=25 MHz
Fin=25 MHz
Fout=156.25 MHz Fout=125 MHz Fout=156.25 MHz Fout=125 MHz
BW=167 Hz
BW=111 Hz
BW=111 Hz
BW=111 Hz
Jitter Integration Filter Band
IEEE802.3 (1.875 to 20 MHz)
RMS Jitter (fs)
232
483
302
467
470
422
511
240
575
303
564
565
524
584
251
525
300
510
517
471
533
240
550
294
537
541
503
557
SONET OC-192 (20 kHz to 80 MHz)
SONET OC-192 (4 to 80 MHz)
SONET OC-192 (50 kHz to 80 MHz)
SONET OC-48 (12 kHz to 20 MHz)
SONET OC-3 (12 kHz to 5 MHz)
BroadBand (800 Hz to 80 MHz)
42
Rev. 1.0
Si5315
10. Pin Descriptions: Si5315
36 35 34 33 32 31 30 29 28
RST
FRQTBL
LOS1
1
2
3
4
5
6
7
8
9
27 FRQSEL3
26
FRQSEL2
25 FRQSEL1
LOS2
24
23
FRQSEL0
BWSEL1
GND
Pad
VDD
XA
22 BWSEL0
XB
21
20
19
CS_CA
GND
GND
GND
AUTOSEL
10 11 12 13 14 15 16 17 18
Pin assignments are preliminary and subject to change.
Table 19. Si5315 Pin Descriptions
Signal Level Description
Pin #
Pin Name
I/O
1
I
LVCMOS
External Reset.
RST
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5315 will perform an internal self-calibration when
a valid input signal is present.
This pin has a weak pull-up.
2
FRQTBL
I
3-Level
Frequency Table Select.
Selects frequency table. (Table 9 on page 20.)
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
3
4
LOS1
LOS2
O
O
LVCMOS
LVCMOS
CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once trig-
gered, the alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
Rev. 1.0
43
Si5315
Table 19. Si5315 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
5, 10,
32
V
V
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V pins:
DD
DD
DD
5
10
32
0.1 µF
0.1 µF
0.1 µF
A 1.0 µF should also be placed as close to device as is prac-
tical.
7
6
XB
XA
I
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use
internal oscillator based reference. Crystal or reference clock
selection is set by the XTAL/CLOCK pin.
8,
15,19,
20,31
GND
GND
I
Supply
3-Level
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
9
AUTOSEL
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selec-
tion to be used.
L = Manual
M = Automatic non-revertive
H = Automatic revertive
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
11
XTAL/CLOCK
I
3-Level
External Crystal or Reference Clock Rate.
Three level input that selects the type and rate of external
crystal or reference clock to be applied to the XA/XB port.
This pin has both a weak pull-up and a weak pull-down and
defaults to M.
L = Crystal
M = Clock (Default)
H = Reserved
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
12
13
CKIN2+
CKIN2–
I
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
44
Rev. 1.0
Si5315
Table 19. Si5315 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled. Bypass mode is
not supported with CMOS clock outputs (SFOUT = LH).
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
I
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
18
21
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
CS_CA
I/O
LVCMOS
Input Clock Select/Active Clock Indicator.
Input: If manual clock selection mode is chosen
(AUTOSEL = L), this pin functions as the manual
input clock selector. This input is internally deglitched
to prevent inadvertent clock switching during
changes in the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If configured as input, must be set high or low.
Output: If automatic clock selection mode is chosen
(AUTOSEL = M or H), this pin indicates which of the
two input clocks is currently the active clock. If
alarms exist on both CKIN1 and CKIN2, indicating
that the holdover state has been entered, CA will
indicate the last active clock that was used before
entering the hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
23
22
BWSEL1
BWSEL0
I
3-Level
Loop Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. See Table 9 on page 20 for available settings.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Rev. 1.0
45
Si5315
Table 19. Si5315 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
27
26
25
24
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
I
3-Level
Frequency Select.
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
29
28
CKOUT1–
CKOUT1+
O
Multi
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
33
30
SFOUT0
SFOUT1
I
3-Level
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
SFOUT[1:0]
Signal Format
Reserved
HH
HM
HL
LVDS
CML
MH
MM
ML
LH
LVPECL
Reserved
LVDS—Low Swing
CMOS
LM
LL
Disable
Reserved
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
34
35
CKOUT2–
CKOUT2+
O
Multi
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
36
NC
—
—
No Connect.
Leave floating. Make no external connections to this pin for
normal operation.
GND
PAD
GND
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
46
Rev. 1.0
Si5315
Table 20. Si5315 Pull-Up/Pull-Down
Pin #
Si5315
RST
Pull
U
1
2
FRQTBL
AUTOSEL
U, D
U, D
U, D
9
11
XTAL/
CLOCK
14
21
22
23
24
25
26
27
30
33
DBL2_BY
CS_CA
U, D
U, D
U, D
U, D
U, D
U, D
U, D
U, D
U, D
U, D
BWSEL0
BWSEL1
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
SFOUT1
SFOUT0
Rev. 1.0
47
Si5315
11. Ordering Guide
Ordering Part Number Output Clock Freq Range
Pkg
ROHS6, Pb-Free Temp Range
Si5315A-C-GM
Si5315B-C-GM
Si5315-EVB
8 kHz–644.53 MHz
8 kHz–125 MHz
36-Lead 6x6 mm QFN
36-Lead 6x6 mm QFN
Evaluation Board
Yes
Yes
–40 to 85 °C
–40 to 85 °C
8 kHz–644.53 MHz
Note: Add an “R” at the end of the device to denote tape and reel options (i.e., Si5315A-C-GMR).
48
Rev. 1.0
Si5315
12. Package Outline: 36-Pin QFN
Figure 24 illustrates the package details for the Si5315. Table 21 lists the values for the dimensions shown in the
illustration.
Figure 24. 36-Pin Quad Flat No-Lead (QFN)
Table 21. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Min
0.50
—
Nom
0.60
—
Max
0.70
12º
A
A1
b
L
0.02
0.25
aaa
bbb
ccc
ddd
eee
—
—
0.10
0.10
0.08
0.10
0.05
D
6.00 BSC
4.10
—
—
D2
e
3.95
4.25
—
—
0.50 BSC
6.00 BSC
4.10
—
—
E
—
—
E2
3.95
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
49
Si5315
13. PCB Land Pattern
Figure 25 illustrates the PCB land pattern for the Si5315. Figure 26 illustrates the recommended ground pad
layout. Table 22 lists the land pattern dimensions.
Figure 25. PCB Land Pattern
Figure 26. Ground Pad Recommended Layout
50
Rev. 1.0
Si5315
Table 22. PCB Land Pattern Dimensions
Dimension
Min
Max
e
E
0.50 BSC.
5.42 REF.
5.42 REF.
D
E2
D2
GE
GD
X
4.00
4.00
4.53
4.53
—
4.20
4.20
—
—
0.28
Y
0.89 REF.
ZE
ZD
—
—
6.31
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.0
51
Si5315
14. Top Marking
14.1. Si5315 Top Marking (QFN)
14.2. Top Marking Explanation
Mark Method:
Font Size:
Laser
0.80 mm
Right-Justified
Line 1 Marking:
Line 2 Marking:
Line 3 Marking:
Si5315Q
Customer Part Number
Q = Speed Code: A, B
See Ordering Guide for options.
C-GM
C = Product Revision
G = Temperature Range –40 to 85 °C (RoHS6)
M = QFN Package
YYWWRF
YY = Year
WW = Work Week
R = Die Revision
F = Internal code
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
Line 4 Marking:
Pin 1 Identifier
XXXX
Circle = 0.75 mm Diameter
Lower-Left Justified
Internal Code
52
Rev. 1.0
Si5315
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Expanded/added numerous operating sections to
initial data sheet
Revision 0.2 to Revision 0.25
Updated features and application list
Updated Section 1. "Electrical Specifications”
Added voltage regulator block to Figure 7
Revised footnotes in Table 9
Removed plan #203 from Table 9
Removed Figure 17. Crystal Oscillator with
Feedback Resistor diagram from Section 7.
"Crystal/Reference Clock Input”
Added XA/XB jitter transfer plot to Section 7.
"Crystal/Reference Clock Input”
Added PSRR transfer function plot to Section 8.
"Power Supply Filtering”
Updated Typical phase noise plot and RMS jitter
table in Section 9. "Typical Phase Noise Plots”
Revision 0.25 to Revision 0.26
Corrected Section 11. "Ordering Guide” Output
Clock Frequency Range for Si5315B-C-GM to
8 kHz–125 MHz.
Revision 0.26 to Revision 1.0
Updated Table 2 on page 4.
Updated Table 3 on page 8.
Updated Table 7 on page 13.
Moved “Typical Application Circuit” to page 14.
Added reference to AN591.
Bypass mode not supported with CMOS outputs.
Changed G.8262 compliance language.
Added frequency plans 103, 129, and 130.
Rev. 1.0
53
Si5315
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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54
Rev. 1.0
相关型号：
SI5315B-C-GM
Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet
SILICON
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