SI5324 [SILICON]
Pin-Controlled 1_710 MHz Jitter Cleaning Clock; 销控1_710 MHz的抖动清洗时钟
| 型号： | SI5324 |
| 厂家： | 
SILICON |
| 描述： | Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| 文件： | 总50页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5317
PRELIMINARY DATA SHEET
PIN-CONTROLLED 1–710 MHZ JITTER CLEANING CLOCK
Features
Provides jitter attenuation on any
frequency
One clock input / two clock outputs
Input/output frequency range:
1–710 MHz
Selectable output clock signal
format: LVPECL, LVDS, CML or
CMOS
Single supply: 1.8, 2.5, or 3.3 V
VCO freeze during LOS/LOL
Loss of lock and loss of signal alarms
On-chip voltage regulator with high
PSRR
Ultra low jitter: 300 fs
(12 kHz–20 MHz) typical
Simple pin control interface
Selectable loop bandwidth for jitter
attenuation: 60 Hz–8.4 kHz
Small size: 6 x 6 mm, 36-QFN
Wide temperature range: –40 to
+85 ºC
Applications
Ordering Information:
See page 43.
Data converter clocking
Wireless infrastructure
Networking, SONET/SDH
Switches and routers
Medical instrumentation
Test and measurement
Pin Assignments
Description
The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications
that require jitter attenuation without clock multiplication. The Si5317 accepts a
single clock input ranging from 1 to 710 MHz and generates two low jitter clock
outputs at the same frequency. The clock frequency range and loop bandwidth are
selectable from a simple look-up table. The Si5317 is based on Silicon
Laboratories' 3rd-generation DSPLL® technology, which provides jitter attenuation
on any frequency in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is user
selectable, providing jitter performance optimization at the application level.
36 35 34 33 32 31 30 29 28
RST
FRQTBL
LOS
NC
1
2
3
4
5
6
7
8
9
27 FRQSEL3
26
FRQSEL2
25 FRQSEL1
24
23
FRQSEL0
BWSEL1
GND
Pad
VDD
XA
22 BWSEL0
XB
21
20
19
NC
GND
NC
DEC
INC
Functional Block Diagram
10 11 12 13 14 15 16 17 18
XTAL/Clock
Clock Out1
Clock In
DSPLL ®
Signal Format [1:0]
Clock Out2
Status/Control
High
PSRR
Regulator
VDD (1.8, 2.5, 3.3 V)
GND
Frequency Table
Loss of Lock
Frequency Select [3:0]
Bandwidth Select [1:0]
Phase Skew INC/DEC
Loss of Signal
XTAL/Clock Rate [1:0]
Preliminary Rev. 0.15 4/10
Copyright © 2010 by Silicon Laboratories
Si5317
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5317
2
Preliminary Rev. 0.15
Si5317
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2. Three-Level Input Pins (with External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Frequency Range Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Output Skew Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.4. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5. VCO Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.6. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1. Input Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.2. Output Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.1. Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
9. Pin Descriptions: Si5317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
11. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
12. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
13. Si5317 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Preliminary Rev. 0.15
3
Si5317
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
Test Condition
Min
–40
Typ
25
Max
85
Unit
ºC
V
T
A
V
3.3 V nominal
2.5 V nominal
1.8 V nominal
2.97
2.25
1.71
3.3
2.5
1.8
3.63
2.75
1.89
DD
V
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Current (Supply
current is independent of
I
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled
LVPECL Format
622.08 MHz Out
Only 1 CKOUT Enabled
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
—
251
279
mA
DD
1
V
)
DD
—
—
—
217
204
194
243
234
220
mA
mA
mA
1
2
CMOS Format
19.44 MHz Out
Only CKOUT1 Enabled
2
CKIN Input Pin
Input Common Mode
Voltage
(Input Threshold Voltage)
V
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Single-ended
0.9
1.0
1.1
20
0
—
—
—
40
—
—
1.4
1.7
1.95
60
V
V
ICM
V
Input Resistance
CKN
CKN
k
V
RIN
3
Input Voltage Level Limits
See note
V
DD
VIN
Single-ended Input Voltage
Swing
V
f
f
< 212.5 MHz
0.2
—
V
ISE
CKIN
PP
See Figure 2.
> 212.5 MHz
0.25
—
—
V
CKIN
PP
See Figure 2.
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.
4
Preliminary Rev. 0.15
Si5317
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Differential Input
Symbol
Test Condition
< 212.5 MHz
Min
Typ
Max
Units
V
f
f
0.2
—
—
V
ID
CKIN
PP
Voltage Swing
See Figure 2.
> 212.5 MHz
0.25
—
—
V
CKIN
PP
See Figure 2.
1
CKOUT Output Clock
Common Mode
V
LVPECL 100 load
V
1.42
–
—
—
V
1.25
–
V
OCM
DD
DD
line-to-line
Differential Output Swing
Single-ended Output Swing
Differential Output Voltage
V
LVPECL 100 load
1.1
0.5
350
—
1.9
V
OD
PP
PP
line-to-line
V
LVPECL 100 load
—
0.93
500
—
V
SE
line-to-line
CKO
CML 100 load
425
mV
PP
VD
line-to-line
Common Mode
Output Voltage
CKO
CML 100 load
V
–
V
VCM
DD
0.36
line-to-line
Differential
Output Voltage
CKO
LVDS 100 load
500
350
1.125
—
700
425
1.2
80
900
500
1.275
90
mV
VD
PP
line-to-line
Low swing LVDS 100 load
mV
PP
line-to-line
Common Mode
Output Voltage
CKO
LVDS 100 load
V
VCM
line-to-line
Output Short to GND
CKO
V
= 3.63 V
DD
mA
mA
mA
mA
µA
ISC
CML, LVDS, LVPECL
V
= 1.89 V
—
45
50
DD
CML, LVDS
V
= 3.63 V
—
165
65
175
70
DD
CMOS
V
= 1.89 V
—
DD
CMOS
Disable
—
0.1
0.2
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.
Preliminary Rev. 0.15
5
Si5317
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Output Short to V
Symbol
CKO
Test Condition
= 3.63 V
Min
Typ
Max
Units
V
DD
—
25
30
mA
DD
ISC+
CML, LVDS, LVPECL
V
= 1.89 V
—
—
—
25
190
70
30
200
80
mA
mA
mA
DD
CML, LVDS
V
V
= 3.63 V
CMOS
DD
= 1.89 V
DD
CMOS
Disable
—
1.5
2
µA
Differential Output
Resistance
CKO
CKO
CML, LVPECL, LVDS,
Disable
170
200
230
RD
Common Mode Output
CML, LVPECL, LVDS
Disable
85
1
100
—
115
—
M
V
RCM
Resistance (to V
)
DD
Output Voltage Low
Output Voltage High
CKO
CKO
CMOS
—
—
0.4
—
VOLLH
V
= 1.71 V
0.8 x V
—
V
VOHLH
DD
DD
CMOS
Output Drive Current
CKO
IO
CMOS
Driving into CKO
for out-
VOL
put low or CKO
for output
VOH
high. CKOUT+ and CKOUT–
shorted externally.
V
V
= 1.71 V
= 2.97 V
7.5
32
—
—
—
—
mA
mA
DD
DD
2-Level LVCMOS Input Pins
Input Voltage Low
V
V
V
V
V
V
V
= 1.71 V
= 2.25 V
= 2.97 V
= 1.89 V
= 2.25 V
= 3.63 V
—
—
—
—
—
—
—
—
—
—
75
0.5
0.7
0.8
—
V
V
IL
DD
DD
DD
DD
DD
DD
—
V
Input Voltage High
V
1.4
1.8
2.5
—
V
IH
—
V
—
V
Input Low Current
Input High Current
I
50
50
—
µA
µA
k
IL
I
—
IH
Weak Internal Input Pull-up
Resistor
R
—
PUP
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.
6
Preliminary Rev. 0.15
Si5317
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Weak Internal Input
Pull-down Resistor
R
—
75
—
k
PDN
3-Level Input Pins
Input Voltage Low
Input Voltage Mid
Input Voltage High
Input Low Current
Input Mid Current
Input High Current
LVCMOS Output Pins
Output Voltage Low
0.15 x VDD
V
—
0.45 x VDD
0.85 x VDD
–20
—
—
—
—
—
—
V
V
ILL
0.55 x VDD
V
IMM
V
—
—
2
V
IHH
2
I
µA
µA
µA
ILL
2
I
–2
IMM
2
I
—
20
IHH
V
I = 2 mA
—
—
—
—
—
—
0.4
0.4
—
V
V
V
V
OL
O
V
V
= 1.62 V
DD
I = 2 mA
O
= 2.97 V
DD
Output Voltage High
V
I = –2 mA
V
V
– 0.4
– 0.4
OH
O
DD
DD
V
= 1.62 V
DD
I = –2 mA
—
O
V
= 2.97 V
DD
Single-Ended Reference Clock Input Pin XA (XB with cap to gnd)
Input Resistance
XA
XA
XTAL/RefCLK
RATE[1:0] = LM, ML, MH, or
HM
8.5
10
—
—
11.5
1.2
k
RIN
VIN
Input Voltage Level Limits
Input Voltage Swing
0
V
XA
0.5
1.2
V
PP
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Resistance
XA/XB
XTAL/RefCLK
RATE[1:0] = LM, ML, MH, or
HM
8.5
0
10
—
11.5
1.2
k
RIN
VIN
Differential Input Voltage
Level Limits
XA/XB
V
Input Voltage Swing
XA
/XB
0.5
—
1.2
V
PP, each
VPP
VPP
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.
Preliminary Rev. 0.15
7
Si5317
V
SIGNAL +
Differential I/Os
SIGNAL – OCM
Single-Ended
Peak-to-Peak Voltage
V
ICM , V
VISE,VOSE
(SIGNAL +) – (SIGNAL –)
ICM, VOCM
Differential Peak-to-Peak Voltage
VID = (SIGNAL+) – (SIGNAL–)
V ,VOD
ID
V
t
SIGNAL +
SIGNAL –
Figure 1. Voltage Characteristics
80%
20%
DOUT, CLOUT
tF
tR
Figure 2. Rise/Fall Time Characteristics
8
Preliminary Rev. 0.15
Si5317
1.1. Three-Level (3L) Input Pins (No External Resistors)
VDD
Si5317
75 k
Iimm
75 k
External Driver
Figure 3. Three Level Input Pins
1.2. Three-Level Input Pins (with External Resistors)
VDD
18 k
VDD
Si5317
75 k
Iimm
18 k
75 k
External Driver
One of eight resistors from a Panasonic EXB-D10C183J
(or similar) resistor pack
Figure 4. Three-Level Input Pins
Table 3. Three-Level Input Pins1,2,3,4
Parameter
Input Low Current
Input Mid Current
Input High Current
Notes:
Symbol
Iill
Min
–30 µA
–11 µA
—
Max
—
Iimm
Iihh
–11 µA
–30 µA
1. The current parameters are the amount of leakage that the 3L inputs can tolerate from an external driver. In most
designs, an external resistor voltage divider is recommended.
2. Resistor packs are only needed if the leakage current of the external driver exceeds the listed currents.
Any resistor pack may be used (e.g. Panasonic EXB-D10C183J). PCB layout is not critical.
3. If a pin is tied to ground or V , no resistors are needed.
DD
4. If a pin is left open (no connect), no resistors are needed.
Preliminary Rev. 0.15
9
Si5317
Table 4. AC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Input Frequency
Symbol
Test Condition
Min
Typ
Max
Units
CKN
1
—
710
MHz
F
CKIN Input Pins
Input Duty Cycle (Minimum Pulse
Width)
Whichever is smaller
40
2
—
—
—
—
60
—
3
%
ns
pF
ns
CKN
DC
Input Capacitance
CKN
—
—
CIN
Input Rise/Fall Time
CKN
20–80%
11
TRF
See Figure 2
CKOUT Output Pins
Output Frequency (Output not
configured for CMOS or disable)
1
1
—
—
—
710
212.5
8
MHz
MHz
ns
CK
OF
Maximum Output Frequency in
CMOS Format
CKO
FMC
CMOS Output
—
Single-ended Output Rise/Fall
(20–80%)
V
= 1.62
DD
Cload = 5 pF
CKO
TRF
CMOS Output
—
—
2
ns
V
= 2.97
DD
Cload = 5 pF
20 to 80 %, f
= 622.08
—
—
230
—
350
±40
ps
ps
Differential Output Rise/Fall Time
CKO
OUT
TRF
Output Duty Cycle Differential
Uncertainty
CKO
100 Load
Line to Line
DC
Measured at 50% Point
(not for CMOS)
LVCMOS Pins
Input Capacitance
C
—
—
3
pF
IN
10
Preliminary Rev. 0.15
Si5317
Table 4. AC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
LVCMOS Output Pins
Rise/Fall Times
Symbol
Test Condition
Min
Typ
Max
Units
t
CLOAD = 20 pf
See Figure 2
—
25
—
ns
RF
LOS
t
From L
CKIN to LOS
—
—
750
220
µs
LOSn Trigger Window
TRIG
VST
Time to Clear LOS Alarm
Measured from appearance
of valid CKIN to of LOS
alarm
90
—
ms
LOSCLR
Time to Clear LOL after LOS Cleared t
f unchanged and XA/XB
10
—
ms
CLRLOL
in
stable.
LOS to LOL
PLL Performance
Lock Time
t
—
—
1.2
sec
dB
RST with valid CKIN to
LOCKHW
LOL; BW = 100 Hz
Closed Loop Jitter Peaking
Jitter Tolerance
J
0.05
—
0.1
—
PK
5000/
BW
ns pk-
pk
BW determined by
BWSEL[1:0]
J
TOL
Minimum Reset Pulse Width
Lock Time
t
1
—
35
—
—
µs
ms
RSTMIN
t
Reset b to of LOL
—
—
1000
–75
LOCKMP
Spurious Noise
Max spur @ n x f3
(n > 1, n x f3 < 100 MHz)
dBc
SP
SPUR
Preliminary Rev. 0.15
11
Si5317
Table 5. Performance Specifications1, 2, 3, 4, 5
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Generation
J
—
0.32
0.42
ps rms
GEN
f
= f
= 622.08 MHz,
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
100 Hz offset
1 kHz offset
IN
OUT
LVPECL output format
BW = 120 Hz
—
—
—
—
—
—
—
0.31
0.4
0.41
0.45
—
ps rms
ps rms
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise
CKO
–65
PN
f
= f
= 622.08 MHz
IN
OUT
–95
—
LVPECL output format
10 kHz offset
100 kHz offset
1 MHz offset
–110
–117
–130
—
—
—
Notes:
1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 22.
2. 114.285 MHz 3rd OT crystal used as XA/XB input.
3. VDD = 2.5 V
4. TA = 85 °C
5. Test condition: fIN = 622.08 MHz, fOUT = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
(20-80%), LVPECL clock output.
12
Preliminary Rev. 0.15
Si5317
Table 6. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Thermal Resistance
Junction to Ambient
Still Air
—
32
—
ºC/W
JA
Thermal Resistance
Junction to Case
—
14
—
ºC/W
JC
Table 7. Absolute Maximum Ratings
Parameter
DC Supply Voltage
Symbol
Value
Unit
V
–0.5 to 3.63
V
V
DD
DIG
JCT
STG
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
DD
Operating Junction Temperature
Storage Temperature Range
T
–55 to 150
–55 to 150
2
C
T
C
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except
kV
CKIN+/CKIN–
ESD MM Tolerance; All pins except CKIN+/CKIN–
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
ESD MM Tolerance; CKIN+/CKIN–
200
700
150
V
V
V
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.15
13
Si5317
2. Functional Description
External Crystal or
Reference Clock
RATE[1:0]
XB
XA
2
2
CKOUT+
CKOUT–
2
fOSC
f3
CKIN+
CKIN–
DSPLL®
SFOUT[1:0]
CKOUT+
CKOUT–
LOS
LOL
RST
Alarms
Control
DBL2_BY
Bandwidth
Control
BWSEL[1:0]
FRQSEL[3:0]
Frequency
Control
Voltage
Regulator with
High PSRR
VDD (1.8, 2.5, or 3.3 V)
GND
FRQTBL
INC
Skew Control
DEC
Figure 5. Detailed Block Diagram
2.1. Overview
The Si5317 is a 1:1 jitter-attenuating precision clock for applications requiring sub 1 ps jitter performance. The
Si5317 accepts one clock input ranging from 1 to 710 MHz and generates two clock outputs at the same frequency
ranging from 1 to 710 MHz. The Si5317 is based on Silicon Laboratories' 3rd-generation DSPLL® technology,
which provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The nominal operating frequency is selectable from a look-up table.
The Si5317 PLL loop bandwidth (BW) is selectable via the BWSEL[1:0] pins and supports a range from 60 Hz to
8.4 kHz.
The Si5317 monitors the input clock for loss-of-signal (LOS) and provides a LOS alarm when it detects missing
pulses on the input clock. The device monitors the lock status of the DSPLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock.
The Si5317 provides a VCO freeze capability that allows the device to continue generation of a stable output clock
when the selected input clock is lost. During VCO freeze, the DSPLL latches its VCO settings and uses its XA/XB
clock as its frequency reference.
The Si5317 has two output clock drivers and can be configured as four single-ended or two differential outputs.
The signal format of the clock output is selectable to support LVPECL, LVDS, CML, or CMOS loads. The device
operates from a single 1.8, 2.5, or 3.3 V supply. The use of LVPECL requires a VDD > 2.25 V.
14
Preliminary Rev. 0.15
Si5317
3. Frequency Plan Tables
For ease of use, the Si5317 is pin-controlled to enable simple device configuration of the frequency range plan and
PLL loop bandwidth via a predefined look-up table. The DSPLL has been optimized for jitter performance and
tunability for each frequency range and PLL loop bandwidth provided in Table 9 on page 22.
Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels
determined by the supply pins: V and Ground. If the input pin is left floating, it is driven to nominally half of V
.
DD
DD
Effectively, this creates three logic levels for these controls. See section 6. "Power Supply Filtering" on page 35 and
section 1.2. "Three-Level Input Pins (with External Resistors)" on page 9 for additional information.
3.1. Frequency Range Plan
The input to output clock frequency range is set by the 3-level FRQSEL[3:0] and FRQTBL pins. The CKIN and
CKOUT is the same frequency range as specified in Table 8. Due to the wide tunability of the Si5317, each
frequency plan provides overlap between adjacent settings. To select a frequency plan, the desired frequency
should be selected as close to the defined center frequency. In certain cases where the desired frequency is
exactly between two overlapping plans, either FRQTBL and FRQSEL can be used.
3.1.1. PLL Loop Bandwidth Plan
The Si5317's loop bandwidth ranges from 60 Hz to 8.4 kHz. For each frequency range, the corresponding loop
bandwidth is provided in a simple look-up table (see Table 9 on page 22). The loop bandwidth is digitally
programmable using the three-level BWSEL [1:0] input pins.
3.2. Output Skew Adjustment
The overall device skew (CKIN to CKOUTn phase delay) is adjustable via the INC and DEC input pins. A positive
edge triggered pulse applied to the INC pin increases the device skew defined by Table 8, INC/DEC step size, for
each given frequency plan. The identical operation on the DEC pin decreases the skew by the same amount.
Using the INC and DEC pins, there is no limit to the range of skew adjustment that can be made. Following a
powerup or reset, the overall device skew will revert to the reset value, although the input-to-output skew is
effectively random. The rate of change for each INC/DEC operation is defined by the selected loop bandwidth,
BWSEL[1:0].
Preliminary Rev. 0.15
15
Si5317
Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings
Frequency Range
(MHz)
BWSEL [1:0] (BW in Hz)
INC/DEC
Phase
Change
(ns)
Plan FRQTBL FRQSEL Min Center Max
LH
ML
MM MH HL HM
No
[3:0]
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
LLLL
1.00
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3814 927 230 114 57
3814 927 230 114 57
3834 931 231 115 57
4052 983 244 121 60
4251 1030 255 127 63
4451 1078 267 133 66
4652 1125 279 139 69
4852 1172 290 145 72
5054 1219 302 150 75
5256 1267 314 156 78
5256 1267 314 156 78
5459 1314 325 162 81
5866 1409 349 174 87
5866 1409 349 174 87
6071 1457 360 180 89
6276 1504 372 185 92
6483 1552 384 191 95
6688 1599 395 197 98
6895 1647 407 203 101
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.21
0.20
0.21
0.20
0.20
0.20
0.20
0.21
1
LLLM
LLLH
2
3
LLML
LLMM
LLMH
LLHL
4
5
6
7
LLHM
LLHH
LMLL
LMLM
LMLH
LMML
LMMM
LMMH
LMHL
LMHM
LMHH
LHLL
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
LHLM
LHLH
LHML
LHMM
LHMH
LHHL
LHHM
LHHH
MLLL
MLLM
MLLH
MLML
MLMM
MLMH
MLHL
2.00 4696 2285 560 139 69
2.10 4832 2350 575 143 71
2.20 4967 2415 591 147 73
2.30 5239 2544 622 154 77
—
—
—
—
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
—
—
—
—
—
—
—
—
—
—
—
4052 983 244 121 60
4251 1030 255 127 63
4451 1078 267 133 66
4651 1125 279 139 69
4852 1172 290 145 72
5054 1219 302 150 75
5255 1267 314 156 78
5458 1314 325 162 81
5859 1409 349 174 87
5859 1409 349 174 87
6071 1457 360 180 89
Note: For BWSEL[1:0] settings LL, LM, HH are reserved.
16
Preliminary Rev. 0.15
Si5317
Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings
Frequency Range
(MHz)
BWSEL [1:0] (BW in Hz)
INC/DEC
Phase
Change
(ns)
Plan FRQTBL FRQSEL Min Center Max
LH
ML
MM MH HL HM
No
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
[3:0]
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
MLHM
MLHH
MMLL
MMLM
MMLH
MMML
3.30
3.40
3.50
3.60
3.70
3.80
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.20
4.40
4.60
4.80
5.00
5.20
5.40
5.60
5.80
6.00
6.20
6.40
6.60
6.80
7.00
7.20
7.40
7.60
7.80
8.00
8.40
8.80
9.00
9.20
9.60
3.50
3.60
3.70
3.80
3.90
4.00
4.20
4.40
4.60
4.80
5.00
5.20
5.40
5.60
5.80
6.00
6.20
6.40
6.60
6.80
7.00
7.20
7.40
7.60
7.80
8.00
8.40
8.80
9.00
9.20
9.60
10.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6071 1457 360 180 89
6276 1504 372 185 92
6483 1552 384 191 95
6895 1647 407 203 101
6895 1647 407 203 101
4650 1125 279 139 69
4786 1156 286 143 71
4919 1188 294 147 73
5457 1314 325 162 81
5457 1314 325 162 81
5730 1378 341 170 85
6268 1504 372 185 92
6273 1504 372 185 92
6550 1568 387 193 96
6823 1631 403 201 100
6823 1631 403 201 100
6333 3064 748 185 92
6571 3176 774 192 96
6811 3289 801 199 99
6071 1457 360 180 89
6534 1567 387 193 96
6534 1567 387 193 96
6483 1552 384 191 95
6686 1599 395 197 98
6891 1647 407 203 101
4648 1125 279 139 69
4786 1156 286 143 71
4919 1188 294 147 73
6599 1580 391 195 97
7080 1693 418 209 104
7080 1693 418 209 104
5727 1377 341 170 85
6003 1441 356 178 88
6273 1504 372 185 92
0.21
0.21
0.21
0.21
0.21
0.20
0.21
0.21
0.20
0.20
0.21
0.20
0.20
0.20
0.20
0.20
0.20
0.20
0.20
0.21
0.20
0.20
0.21
0.20
0.20
0.20
0.21
0.21
0.20
0.19
0.19
0.20
0.21
0.20
MMMM 3.90
MMMH 4.00
MMHL
4.20
MMHM 4.40
MMHH
MHLL
MHLM
MHLH
MHML
4.60
4.80
5.00
5.20
5.40
MHMM 5.60
MHMH
MHHL
MHHM
MHHH
HLLL
5.80
6.00
6.20
6.40
6.60
6.80
7.00
7.20
7.40
7.60
7.80
8.00
8.40
8.80
9.00
9.20
HLLM
HLLH
HLML
HLMM
HLMH
HLHL
HLHM
HLHH
HMLL
HMLM
HMLH
HMML
9.60 10.00 10.50
HMMM 10.00 10.50 11.00
Note: For BWSEL[1:0] settings LL, LM, HH are reserved.
Preliminary Rev. 0.15
17
Si5317
Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings
Frequency Range
(MHz)
BWSEL [1:0] (BW in Hz)
INC/DEC
Phase
Change
(ns)
Plan FRQTBL FRQSEL Min Center Max
LH
ML
MM MH HL HM
No
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
[3:0]
L
L
HMMH 10.50 11.00 11.50
HMHL 11.00 11.50 12.00
HMHM 11.50 12.00 12.50
HMHH 12.00 12.50 13.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6992 1672 413 206 103
5866 1409 349 174 87
6155 1477 365 182 91
6446 1545 382 190 95
7034 1680 415 207 103
5408 1303 323 161 80
5633 1356 336 167 83
5861 1409 349 174 87
7383 1764 436 217 108
6321 1515 374 187 93
6321 1515 374 187 93
6774 1620 400 200 99
7230 1726 426 213 106
4422 1071 265 132 66
7342 1756 434 216 108
7342 1756 434 216 108
7298 1742 430 214 107
4995 1206 299 149 74
7518 1796 444 221 110
6208 1488 368 183 91
7429 1777 439 219 109
6155 1477 365 182 91
6155 1477 365 182 91
6739 1612 399 199 99
7613 1816 449 224 111
6817 1631 403 201 100
6817 1631 403 201 100
7640 1821 450 224 112
4941 1194 296 147 73
7658 1827 451 225 112
7658 1827 451 225 112
6774 1620 400 200 99
6774 1620 400 200 99
7692 1832 452 225 112
0.20
0.21
0.20
0.20
0.20
0.20
0.20
0.20
0.19
0.21
0.21
0.20
0.20
0.21
0.19
0.19
0.20
0.20
0.19
0.21
0.18
0.20
0.20
0.20
0.19
0.20
0.20
0.20
0.20
0.19
0.19
0.20
0.20
0.20
L
L
L
HHLL
12.50 13.00 13.50
L
HHLM 13.00 13.50 14.00
HHLH 13.50 14.00 14.50
HHML 14.00 14.50 15.00
HHMM 14.50 15.00 15.50
HHMH 15.00 15.50 16.00
HHHL 15.50 16.00 16.50
HHHM 16.00 16.50 17.00
HHHH 16.50 17.00 17.50
L
L
L
L
L
L
L
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
LLLL
LLLM
LLLH
LLML
17.00 17.50 18.00
17.50 18.00 18.50
18.00 18.50 19.00
18.50 19.00 19.50
LLMM 19.00 19.50 20.00
LLMH
LLHL
LLHM
LLHH
LMLL
19.50 20.00 21.00
20.00 21.00 22.00
21.00 22.00 23.00
22.00 23.00 24.00
23.00 24.00 25.00
LMLM 24.00 25.00 26.00
LMLH 25.26 26.00 27.00
LMML 26.00 27.00 28.00
LMMM 27.00 28.00 29.00
LMMH 28.00 29.00 30.00
LMHL
29.00 30.00 31.00
LMHM 30.31 31.00 32.00
LMHH 31.00 32.00 33.00
LHLL
LHLM
LHLH
32.00 33.00 34.00
33.00 34.00 35.00
34.00 35.00 36.00
Note: For BWSEL[1:0] settings LL, LM, HH are reserved.
18
Preliminary Rev. 0.15
Si5317
Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings
Frequency Range
(MHz)
BWSEL [1:0] (BW in Hz)
INC/DEC
Phase
Change
(ns)
Plan FRQTBL FRQSEL Min Center Max
LH
ML
MM MH HL HM
No
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
[3:0]
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
LHML
35.00 36.00 37.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7680 1833 453 226 113
7539 1803 446 222 111
7658 1827 451 225 112
7607 1818 449 224 112
7607 1818 449 224 112
5709 1373 340 169 84
7653 1828 452 225 112
7653 1828 452 225 112
6155 1477 365 182 91
7630 1823 450 225 112
7692 1832 452 225 112
7880 1882 465 232 116
6169 1481 366 183 91
7664 1826 451 225 112
7664 1826 451 225 112
7882 1882 465 232 116
7890 1883 465 232 116
7878 1882 465 232 116
7878 1882 465 232 116
6228 1494 369 184 92
7888 1883 465 232 116
7889 1883 465 232 116
7917 1884 465 232 116
7895 1883 465 232 116
7895 1883 465 232 116
6010 1445 357 178 89
6010 1445 357 178 89
6329 1518 375 187 93
7878 1882 465 232 116
7795 1864 461 230 114
7795 1864 461 230 114
7903 1884 465 232 116
7812 1866 461 230 115
6329 1518 375 187 93
7820 1867 461 230 115
0.19
0.18
0.19
0.18
0.18
0.21
0.18
0.18
0.20
0.18
0.20
0.18
0.20
0.20
0.20
0.18
0.18
0.18
0.18
0.20
0.18
0.18
0.20
0.19
0.19
0.20
0.20
0.20
0.18
0.18
0.18
0.19
0.18
0.20
0.18
LHMM 36.00 37.00 38.00
LHMH 37.00 38.00 39.00
LHHL
38.00 39.00 40.00
LHHM 39.00 40.00 42.00
LHHH 40.00 42.00 44.00
MLLL
MLLM 44.00 46.00 48.00
MLLH 46.00 48.00 50.00
43.30 44.00 46.00
MLML 48.00 50.00 52.00
MLMM 50.52 52.00 54.00
MLMH 52.00 54.00 56.00
MLHL
54.00 56.00 58.00
MLHM 56.00 58.00 60.00
MLHH 58.00 60.00 60.00
MMLL 60.00 62.00 64.00
MMLM 62.00 64.00 66.00
MMLH 64.00 66.00 68.00
MMML 66.00 68.00 70.00
MMMM 68.00 70.00 70.88
MMMH 70.00 72.00 74.00
MMHL 72.00 74.00 76.00
MMHM 75.78 76.00 78.00
MMHH 76.00 78.00 80.00
MHLL
78.00 80.00 84.00
MHLM 80.00 84.00 88.00
MHLH 84.00 88.00 88.59
MHML 88.00 90.00 92.00
MHMM 90.00 92.00 96.00
MHMH 92.00 96.00 100.00
MHHL 96.00 100.00 105.00
MHHM 101.04 105.00 110.00
MHHH 105.00 110.00 115.00
HLLL 110.00 115.00 118.13
HLLM 115.00 120.00 125.00
Note: For BWSEL[1:0] settings LL, LM, HH are reserved.
Preliminary Rev. 0.15
19
Si5317
Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings
Frequency Range
(MHz)
BWSEL [1:0] (BW in Hz)
INC/DEC
Phase
Change
(ns)
Plan FRQTBL FRQSEL Min Center Max
LH
ML
MM MH HL HM
No
[3:0]
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
H
HLLH 120.00 125.00 130.00
HLML 125.00 130.00 135.00
HLMM 130.00 135.00 140.00
HLMH 135.00 140.00 145.00
HLHL 140.00 145.00 150.00
HLHM 145.00 150.00 155.00
HLHH 151.56 155.00 160.00
HMLL 155.00 160.00 165.00
HMLM 160.00 165.00 170.00
HMLH 165.00 170.00 175.00
HMML 170.00 175.00 177.19
HMMM 175.00 180.00 185.00
HMMH 180.00 185.00 190.00
HMHL 185.00 190.00 195.00
HMHM 190.00 195.00 200.00
HMHH 195.00 200.00 202.50
HHLL 202.08 210.00 220.00
HHLM 210.00 220.00 230.00
HHLH 220.45 230.00 240.00
HHML 230.00 240.00 250.00
HHMM 242.50 250.00 260.00
HHMH 250.00 260.00 270.00
HHHL 260.00 270.00 280.00
HHHM 270.00 280.00 290.00
HHHH 280.00 290.00 300.00
LLLL 290.00 300.00 310.00
LLLM 303.13 310.00 320.00
LLLH 310.00 320.00 330.00
LLML 320.00 330.00 340.00
LLMM 330.00 340.00 350.00
LLMH 340.00 350.00 354.38
LLHL 350.00 360.00 370.00
LLHM 360.00 370.00 380.00
LLHH 370.00 380.00 390.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7812 1868 462 230 115
7878 1882 465 232 116
6873 1648 408 203 101
7851 1871 462 230 115
7826 1870 462 230 115
7240 1735 429 214 107
7853 1872 462 230 115
7890 1883 465 232 116
7831 1871 462 231 115
7831 1871 462 231 115
6912 1654 409 204 102
7140 1710 423 211 105
7846 1873 463 231 115
7878 1882 465 232 116
7878 1882 465 232 116
6993 1673 414 206 103
7903 1884 465 232 116
7069 1689 417 208 104
7903 1884 465 232 116
7507 1793 443 221 110
7910 1884 465 232 116
7878 1882 465 232 116
7429 1776 439 219 109
7908 1884 465 232 116
7879 1882 465 232 116
7571 1811 448 223 111
7903 1884 465 232 116
7890 1883 465 232 116
7878 1882 465 232 116
7878 1882 465 232 116
7344 1757 434 217 108
7900 1883 465 232 116
7889 1883 465 232 116
7878 1882 465 232 116
0.18
0.18
0.19
0.19
0.18
0.18
0.19
0.18
0.18
0.18
0.20
0.19
0.18
0.18
0.18
0.19
0.19
0.20
0.19
0.19
0.19
0.18
0.19
0.19
0.18
0.18
0.19
0.18
0.18
0.18
0.18
0.19
0.18
0.18
H
H
H
H
H
H
H
H
Note: For BWSEL[1:0] settings LL, LM, HH are reserved.
20
Preliminary Rev. 0.15
Si5317
Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings
Frequency Range
(MHz)
BWSEL [1:0] (BW in Hz)
INC/DEC
Phase
Change
(ns)
Plan FRQTBL FRQSEL Min Center Max
LH
ML
MM MH HL HM
No
[3:0]
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
LMLL 380.00 390.00 400.00
LMLM 390.00 400.00 405.00
LMLH 404.17 420.00 440.00
LMML 420.00 440.00 460.00
LMMM 440.91 460.00 480.00
LMMH 460.00 480.00 500.00
LMHL 485.00 500.00 520.00
LMHM 500.00 520.00 540.00
LMHH 520.00 540.00 560.00
LHLL 540.00 560.00 580.00
LHLM 560.00 580.00 600.00
LHLH 580.00 600.00 620.00
LHML 606.25 620.00 640.00
LHMM 620.00 640.00 660.00
LHMH 640.00 660.00 680.00
LHHL 660.00 680.00 700.00
LHHM 680.00 700.00 704.00
LHHH 700.00 710.00 710.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7878 1882 465 232 116
7755 1854 458 228 114
7903 1884 465 232 116
7848 1874 463 231 115
7903 1884 465 232 116
7507 1793 443 221 110
7910 1884 465 232 116
7878 1882 465 232 116
7704 1842 455 227 113
7908 1884 465 232 116
7879 1882 465 232 116
7571 1811 448 223 111
7903 1884 465 232 116
7890 1883 465 232 116
7878 1882 465 232 116
7878 1882 465 232 116
7831 1871 462 231 115
7908 1880 464 231 115
0.18
0.18
0.19
0.18
0.19
0.19
0.19
0.18
0.18
0.19
0.18
0.18
0.19
0.18
0.18
0.18
0.18
0.20
Note: For BWSEL[1:0] settings LL, LM, HH are reserved.
Preliminary Rev. 0.15
21
Si5317
3.3. PLL Self-Calibration
An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter
performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the self-
calibration state machine. The LOL alarm will be active during ICAL. The self-calibration time t
Table 4, “AC Characteristics”.
is given in
LOCKHW
Any of the following events will trigger a self-calibration:
Power-on-reset (POR)
Release of the external reset pin RST (transition of RST from 0 to 1)
Change in FRQSEL, FRQTBL, BWSEL, or RATE[1:0] pins
Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL
In any of the above cases, an ICAL will be initiated if a valid input clock exists with no input alarm. The external
crystal or reference clock must also be present for the self-calibration to begin. If no valid input clock is present, the
self-calibration state machine will wait until it appears, at which time the calibration will start.
After a successful ICAL has been performed with a valid input clock, no subsequent self-calibrations are performed
unless one of the above conditions are met. If the input clock is lost following self-calibration, the device enters
VCO freeze mode. When the input clock returns, the device relocks to the input clock without performing a self-
calibration.
3.3.1. Input Clock Stability during Internal Self-Calibration
An exit from reset must occur when the selected CKIN clock is stable in frequency with a frequency value that is
within the device operating range.
3.3.2. Self-Calibration caused by Changes in Input Frequency
If the selected CKIN frequency varies by 500 ppm or more within the frequency range defined by FRQSEL and
FRQTBL since the last calibration, the device may initiate a self-calibration.
3.3.3. Device Reset
Upon powerup, the device internally executes a power-on-reset (POR) which resets the internal device logic. The
pin RST can also be used to initiate a reset. The device stays in this state until a valid CKINn is present, when it
then performs a PLL self-calibration (refer to section 3.3. "PLL Self-Calibration”).
3.3.4. Recommended Reset Guidelines
Follow the recommended RESET guidelines in Table 9 that describe when reset should be applied to a device.
Table 9. Si5317 Pins and Reset
Pin #
2
Si5317 Pin Name
FRQTBL
Must Reset after Changing
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
11
RATE0
15
22
23
24
25
26
27
RATE1
BWSEL0
BWSEL1
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
22
Preliminary Rev. 0.15
Si5317
3.4. Alarms
Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all
the alarm conditions for that alarm output are cleared.
3.4.1. Loss-of-Signal
The device has loss-of-signal circuitry that continuously monitors CKIN for missing pulses.
An LOS condition on CKIN causes the LOS alarm to become active. Once a LOS alarm is asserted, it remains
asserted until the input clock is validated over a designated time period. The time to clear LOS after a valid input
clock appears is listed in Table 4, “AC Characteristics”. If another error condition on the same input clock is
detected during the validation time, then the alarm remains asserted and the validation time starts over.
3.4.1.1. LOS Algorithm
The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. The LOS circuitry
oversamples this divided down input clock using a 40 MHz clock to search for extended periods of time without
input clock transitions. If the LOS monitor detects twice the normal number of samples without a clock edge, a
LOS alarm is declared. Table 4, “AC Characteristics” gives the minimum and maximum amount of time for the
LOS monitor to trigger.
3.4.1.2. Lock Detect
The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time
between two consecutive phase cycle slips is greater than the retrigger time, the PLL is in lock. The LOL output
has a guaranteed minimum pulse width as shown in Table 4, “AC Characteristics”. The LOL pin is also held in the
active state during an internal PLL calibration. The retrigger time is automatically set based on the PLL closed loop
bandwidth (see Table 10).
Table 10. Lock Detect Retrigger Time
PLL Bandwidth Setting (BW)
60–120 Hz
Retrigger Time (ms)
53
26.5
13.3
6.6
120–240 Hz
240–480 Hz
480–960 Hz
960–1920 Hz
3.3
1920–3840 Hz
3840–7680 Hz
1.66
0.833
3.5. VCO Freeze
The Si5317 device features a VCO freeze mode whereby the DSPLL is locked to a frequency value.
If an LOS condition exists on the selected input clock, the device freezes the VCO. In this mode, the device
provides a stable output frequency until the input clock returns and is validated. When the device enters VCO
freeze, the internal oscillator is initially held to its last frequency value.
3.5.1. Recovery from VCO Freeze
When the input clock signal returns, the device transitions from VCO freeze to the selected input clock.
Preliminary Rev. 0.15
23
Si5317
3.6. PLL Bypass Mode
The Si5317 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output
buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling;
however, this path is not a low jitter path and will see significantly higher jitter on CKOUT. In PLL bypass mode, the
input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to
measure system performance with and without the jitter attenuation provided by the DSPLL. The DSBL2_BY pin is
used to select the PLL Bypass Mode according to Table 11.
Table 11. DSBL2/BYPASS Pin Settings
DSBL2/BYPASS
Function
CKOUT2 Enabled
L
M
H
CKOUT2 Disabled
PLL Bypass Mode w/ CKOUT2 Enabled
External Crystal or
Reference Clock
RATE[1:0]
XB
XA
PLL Bypass
0
1
2
CKOUT+
CKOUT–
2
fOSC
f3
CKIN+
CKIN–
DSPLL®
SFOUT[1:0]
2
CKOUT+
CKOUT–
LOS
LOL
RST
Alarms
Control
Bandwidth
Control
DBL2_BY
BWSEL[1:0]
FRQSEL[3:0]
Frequency
Control
Voltage
Regulator with
High PSRR
VDD (1.8, 2.5, or 3.3 V)
GND
FRQTBL
INC
Skew Control
DEC
Figure 6. Bypass Signal
24
Preliminary Rev. 0.15
Si5317
4. High-Speed I/O
4.1. Input Clock Buffer
The Si5317 provides differential inputs for the CKIN clock input. This input is internally biased to a common mode
voltage (see Table 2, “DC Characteristics”) and can be driven by either a single-ended or differential source. No
additional external bias is required. Figure 7 through Figure 10 shows typical interface circuits for LVPECL, CML,
LVDS, or CMOS input clocks. Note that the jitter generation improves for higher levels on CKINn within the limits in
Table 4, “AC Characteristics”.
AC coupling the input clocks is recommended because it removes any issue with common mode input voltages.
However, either ac or dc coupling is acceptable. Figure 7 and Figure 8 shows various examples of different input
termination arrangements. Unused inputs can be left unconnected.
3.3 V
Si5317
130
130
C
CKIN+
300
40 k
LVPECL
Driver
40 k
VICM
±
CKIN _
82
82
C
Figure 7. Differential LVPECL Termination
3.3 V
Si5317
130
C
CKIN +
300
Driver
40 k
40 k
VICM
±
CKIN _
82
C
Figure 8. Single-ended LVPECL Termination
Preliminary Rev. 0.15
25
Si5317
Si5317
C
CKIN +
300
40 k
CML/
LVDS
Driver
100
40 k
VICM
±
CKIN _
C
Figure 9. CML/LVDS Termination (1.8, 2.5, 3.3 V)
VDD
Si5317
VDD
39
CMOS
Driver
CKIN +
40 k
40 k
300
VICM
±
CKIN _
0.1 uF
Figure 10. CMOS Termination (1.8, 2.5, 3.3 V)
26
Preliminary Rev. 0.15
Si5317
50
1. Attenuation circuit limits overshoot and undershoot.
2. Not to be used with non-square wave input clocks.
Figure 11. CMOS Termination with Attenuation and AC-coupling (1.8, 2.5, 3.3 V)
Preliminary Rev. 0.15
27
Si5317
4.2. Output Clock Driver
The Si5317 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML,
and CMOS formats. The signal format is selected for CKOUT output using the SFOUT [1:0] pins. This modifies the
output common mode and differential signal swing. See Table 2, “DC Characteristics” for output driver
specifications. The SFOUT [1:0] pins are three-level input pins with the states designated as L (ground), M (V /2),
DD
and H (V ). Table 12 shows the signal formats based on the supply voltage and the type of load being driven.
DD
Table 12. Output Signal Format Selection (SFOUT)
SFOUT[1:0]
Signal Format
CML
HL
HM
LVDS
LH
CMOS
LM
Disabled
LVPECL
MH
ML
Low-swing LVDS
Reserved
All Others
Si5317
Z0 = 50
Z0 = 50
100
CKOUTn
Rcvr
Figure 12. Typical Differential Output Circuit
Si5317
CMOS
Logic
CKOUTn
Optionally Tie CKOUTn
Outputs Together for Greater Strength
Figure 13. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together)
For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals and should be
externally shorted together to obtain the drive strength specified in Table 2, “DC Characteristics”.
28
Preliminary Rev. 0.15
Si5317
+
SFOUT[1:0] = ML (Output disable)
100
100
CKOUT
Output from
DSPLL
Figure 14. Disable CKOUT Structure
The SFOUT [1:0] pins can also be used to disable both outputs. Disabling the output puts the CKOUT+ and
CKOUT– pins in a high-impedance state relative to V (common mode tri-state) while the two outputs remain
DD
connected to each other through a 200 on-chip resistance (differential impedance of 200 ). The maximum
amount of internal circuitry is powered down, minimizing power consumption and noise generation (see Figure 14).
Recovery from the disable mode requires additional time as specified in Table 4, “AC Characteristics”.
Preliminary Rev. 0.15
29
Si5317
5. Crystal/Reference Clock Input
The device can use an external crystal or external clock as a reference. If an external clock is used, it must be ac
coupled. With appropriate buffers, the same external reference clock can be applied to CKIN. Although the
reference clock input can be driven single ended (See Figure 15), the best performance is with a crystal or
differential clock source.
3.3 V
150
0.1F
3.3 V
Si5317
130
10 k
XA
XB
0.6 V
150
0.1F
CMOS buffer,
8 mA output current
For 2.5 V operation, change 130 to 82 .
Figure 15. CMOS External Reference Circuit
0 dBm into 50
1.2 V
Si5317
0.01 F
XA
10 pF
0.01 F
10 k
0.6 V
XB
External Clock Source
50
0.1 µF
Figure 16. Sinewave External Reference Clock Input Example
Si5317
1.2 V
0.01 F
0.01 F
XA
XB
100
LVPECL, CML, etc.
10 k
10 k
0.6 V
Figure 17. Differential External Reference Clock Input Example
30
Preliminary Rev. 0.15
Si5317
5.1. Crystal/Reference Clock Selection
An external low-jitter clock or a low-cost crystal is used as part of a fixed-frequency oscillator within the DSPLL.
This external clock is required for the device to perform jitter attenuation. Silicon Laboratories recommends using a
high-quality crystal.
In VCO freeze, the DSPLL remains locked to this external clock. Any changes in the frequency of this clock when
the DSPLL is in VCO freeze will be tracked by the output of the device. Note that crystals can have temperature
sensitivities. Table 13 shows the recommended crystals.
Table 13. Approved Crystals
Manufacturer
Part Number
Web Address
Stability
Initial
Accuracy
TXC
7MA1400014
http://www.txc.com.tw
http://www.conwin.com
http://www.conwin.com
http://www.ndk.com/en/
100 ppm
100 ppm
20 ppm
100 ppm
100 ppm
20 ppm
Connor Winfield
Connor Winfield
NDK
CS-018-114.285M
CS-023-114.285M
NX3225SA
100 ppm
100 ppm
EXS00A-CS00871
NDK
NX3225SA
EXS00A-CS00997
http://www.ndk.com/en/
http://www.siward.com
20 ppm
20 ppm
20 ppm
20 ppm
Siward
XTL573200NLG-
114.285 MHz-OR
Saronix/eCera
Mtron
FLB420001
M1253S071
http://www.pericom.com/saronix
http://www.mtronpti.com
100 ppm
100 ppm
100 ppm
100 ppm
Note: While these crystals meet the preceding criteria according to their data sheets, Silicon Laboratories, Inc. does not
guarantee operation with the Si5317, nor does Silicon Laboratories endorse one supplier of crystals over another.
Contact Silicon Labs for details and a current list of crystal vendors and recommended part numbers.
Preliminary Rev. 0.15
31
Si5317
Table 14. XA/XB Reference Sources and Frequencies
RATE[1:0]
HH
Type
Reserved
Recommended
—
Lower limit
—
Upper limit
—
HM
External clock
Reserved
171.4275 MHz
—
163 MHz
—
180 MHz
—
HL
MH
External clock
3rd overtone crystal
External clock
Reserved
114.285 MHz
114.285 MHz
57.1425 MHz
—
109 MHz
—
125.5 MHz
—
MM
ML
55 MHz
—
61 MHz
—
LH
LM
External clock
Reserved
38.88 MHz
—
37 MHz
—
41 MHz
—
LL
Because the crystal is used as a jitter reference, rapid changes of the crystal temperature can temporarily disturb
the output phase and frequency. For example, it is recommended that the crystal not be placed close to a fan that
is being turned off and on. If a situation such as this is unavoidable, the crystal should be thermally isolated with an
insulating cover.
5.1.1. XA/XB Clock Drift
During VCO freeze, long-term and temperature-related drift of the XA/XB clock input results in a one-to-one drift of
the output frequency. The stability of the any frequency output is identical to the drift of the XA/XB frequency. This
means that for the most demanding applications where the drift of a crystal is not acceptable, an external
temperature-compensated or ovenized oscillator will be required. Drift is not an issue unless the part is in VCO
freeze. Also, the initial accuracy of the XA/XB oscillator (or crystal) is not relevant.
5.1.2. XA/XB Jitter
Jitter on the XA/XB input has a roughly one-to-one transfer function to the output jitter over the bandwidth ranging
from 100 Hz up to 30 kHz. If a crystal is used on the XA/XB pins, this will have low jitter if a suitable crystal is in
use. If the XA/XB pins are connected to an external oscillator, the jitter of the external oscillator may contribute
significantly to the output jitter.
32
Preliminary Rev. 0.15
Si5317
5.1.3. Jitter Attenuation Performance
The internal VCO uses the XA/XB clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins
support either a crystal input or an input buffer single-ended or differential clock input, such that an external
oscillator can become the reference source. In either case, the device accepts a wide margin in absolute frequency
of the XA/XB input (refer to section 3.5.1. "Recovery from VCO Freeze" on page 23). In VCO freeze, the Si5317's
output clock stability matches the clock supplied on the XA/XB pins. The external crystal or clock must be selected
based on the stability requirements of the application if VCO freeze is a key requirement. However, care must be
exercised in certain areas for optimum performance. For examples of connections to the XA/XB pins, refer to
section 5. Figure 23, “Si5317 Typical Application Circuit,” on page 37.
Jitter Transfer XA/XB Reference to CKOUT
38.88 MHz Clock on XA/XB, RATE[1:0]=LM
5
0
-5
-10
-15
-20
-25
-30
1
10
100
1000
10000
100000
1000000
Jitter Frequency (Hz)
Figure 18. Typical XA-XB Jitter Transfer Function
Preliminary Rev. 0.15
33
Si5317
5.1.4. Reference Clock Frequency
Based on the application and desired output frequency, care should be exercised in selecting the frequency on the
reference used for XA/XB. When the CKOUT operating frequency is close to having a simple integer relationship,
significant spurs can occur. For example, compare the spurs when the CKOUT operating frequency is 622.08 MHz
with a reference of 114.285 MHz (see Figure 22) versus a reference frequency of 38.88 MHz, which is 16 times the
XA/XB reference (see Figure 19).
Figure 19. Effect of Reference Frequency on Spurs
34
Preliminary Rev. 0.15
Si5317
6. Power Supply Filtering
This device incorporates an on-chip voltage regulator to power the device from supply voltages of 1.8, 2.5, or 3.3 V.
Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply voltage
directly. Table 4, “AC Characteristics” gives the sensitivity of the on-chip oscillator to changes in the supply voltage.
The center ground pad under the device must be electrically and thermally connected to the ground plane. See
Figure 26, “Ground Pad Recommended Layout,” on page 45.
0.1 uF
System
C1 – C3
Power
Supply
(1.8, 2.5, or
3.3 V)
1.0 uF
Ferrite
Bead
C4
GND &
GND Pad
VDD
Si5317
Figure 20. Typical Power Supply Bypass Network
Power Supply Noise to Output Transfer Function
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
1
10
100
1000
Frequency of Power Supply Noise (kHz)
Figure 21. Fin = Fout = 155 MHz with 120 Hz Loop Bandwidth, 100 mV, pk-pk Supply Noise
Preliminary Rev. 0.15
35
Si5317
7. Typical Phase Noise Plots
The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF
Generator. The phase noise analyzer was an Agilent model E5052B. The Si5317 operates at 3.3 V with an ac
coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm.
Note that, as with any PLL, the output jitter that is below the loop BW is caused by the jitter at the input clock. The
loop BW was 120 Hz.
7.1. Example: SONET OC-192
Figure 22. Typical Phase Noise Plot
Jitter Band
Jitter, RMS
SONET_OC48, 12 kHz to 20 MHz
250 fs
SONET_OC192_A, 20 kHz to 80 MHz
SONET_OC192_B, 4 to 80 MHz
SONET_OC192_C, 50 kHz to 80 MHz
Brick Wall, 800 Hz to 80 MHz
274 fs
166 fs
267 fs
274 fs
36
Preliminary Rev. 0.15
Si5317
8. Typical Application Circuit
C4
C3
1 µF
System
Power
Supply
0.1 µF
Ferrite
Bead
C2
C1
0.1 µF
0.1 µF
0.1 µF
CKOUT1+
CKOUT1–
100
Clock Outputs
VDD = 3.3 V
0.1 µF
130
82
130
82
VDD
CKIN+
CKIN–
15 k
15 k
SFOUT[1:0]2
Signal Format Select
Input Clock1
0.1 µF
CKOUT2+
CKOUT2–
100
LOS
LOL
CKIN Loss of Signal Indicator
PLL Loss of Lock Indicator
XA
XB
Option 1:
Crystal
0.1 µF
Si5317
Option 2:
Ext. Refclk+
Ext. Refclk–
XA
XB
0.1 µF
VDD
15 k
RATE[1:0]2
Crystal/Ref Clk
15 k
VDD
FRQTBL3
Frequency Table
VDD
15 k
FRQSEL[3:0]2
Frequency Select
VDD
15 k
15 k
BWSEL[1:0]2
INC
Bandwidth Select
Skew Increment
Skew Decrement
15 k
DEC
Clock Output 2 Disable/
Bypass Mode Control
DBL2_BY2
RST
Reset
Notes:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. For schematic and layout examples, refer to Si5317-EVB User Manual.
Figure 23. Si5317 Typical Application Circuit
Preliminary Rev. 0.15
37
Si5317
9. Pin Descriptions: Si5317
36 35 34 33 32 31 30 29 28
RST
FRQTBL
LOS
1
2
3
4
5
6
7
8
9
27 FRQSEL3
26
FRQSEL2
25 FRQSEL1
NC
24
23
FRQSEL0
BWSEL1
GND
Pad
VDD
XA
22 BWSEL0
XB
21
20
19
NC
GND
NC
DEC
INC
10 11 12 13 14 15 16 17 18
Note: Pin assignments are preliminary and subject to change.
Table 15. Si5317 Pin Descriptions
Pin #
Pin Name
I/O Signal Level
Description
1
I
LVCMOS
External Reset.
RST
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5317 will perform an internal self-calibration when
a valid input signal is present.
This pin has a weak pull-up.
2
3
I
3-level
LVCMOS
Supply
Frequency Table.
FRQTBL
LOS
Selects frequency table.
This pin has a weak pull-up and weak pull-down and defaults
to M. Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
CKIN Loss of Signal.
O
Active high loss-of-signal indicator for CKIN. Once triggered,
the alarm will remain active until CKIN is validated.
0 = CKIN present
1 = LOS on CKIN
Supply.
5, 10, 32
V
V
DD
DD
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V pins:
DD
5
10
32
0.1 µF
0.1 µF
0.1 µF
A 1.0 µF should also be placed as close to device as is
practical.
38
Preliminary Rev. 0.15
Si5317
Table 15. Si5317 Pin Descriptions (Continued)
Pin #
7
6
Pin Name
XB
I/O Signal Level
Description
External Crystal or Reference Clock.
I
Analog
XA
External crystal should be connected to these pins to use
internal oscillator-based reference. Crystal or reference clock
selection is set by the XTAL/CLOCK pin.
Ground.
8,31
GND
GND
I
Supply
3-Level
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
External Crystal or Reference Clock Rate.
Note: L setting corresponds to ground. M setting corresponds to
VDD/2. H setting corresponds to VDD. Some designs may
require an external resistor voltage divider when driven by
an active device that will tri-state. See Table 14 for settings.
11
15
RATE0
RATE1
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Input.
16
17
CKIN+
CKIN–
I
Multi
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from Table 9
on page 22.
18
19
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
Skew Decrement.
DEC
I
I
LVCMOS
LVCMOS
This edge-triggered pin decreases the input to output device
skew. There is no limit on the range of skew adjustment by
this method. Detailed operations and timing characteristics
for this pin are found in Section 3.2, Table 8.
This pin has a weak pull-down.
20
INC
Skew Increment.
This edge-triggered pin increases the input to output device
skew. There is no limit on the range of skew adjustment by
this method. Detailed operations and timing characteristics
for this pin are found in Section 3.2, Table 8.
This pin has a weak pull-down.
Preliminary Rev. 0.15
39
Si5317
Table 15. Si5317 Pin Descriptions (Continued)
Pin #
23
22
Pin Name
BWSEL1
BWSEL0
I/O Signal Level
Description
Loop Bandwidth Select.
I
3-Level
Three level inputs that select the DSPLL closed loop band-
width. See Table 9 on page 22 for available settings.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Frequency Select.
27
26
25
24
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
Three level inputs that select the input clock and clock range.
See Table 9 on page 22.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
29
28
CKOUT1–
CKOUT1+
O
I
Multi
Clock Output 1.
Output signal format is selected by SFOUT pins. Differential
formats supported for LVPECL, LVDS, and CML compatible
modes. For single-ended CMOS format, both output pins
drive identical, in-phase clock outputs.
33
30
SFOUT0
SFOUT1
3-Level
Signal Format Select.
Three-level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
SFOUT[1:0]
Signal Format
Reserved
HH
HM
HL
LVDS
CML
MH
MM
ML
LH
LVPECL
Reserved
LVDS—Low Swing
CMOS
LM
LL
Disable
Reserved
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.*
34
35
CKOUT2–
CKOUT2+
O
Multi
Clock Output 2.
Output signal format is selected by SFOUT pins. Differential
formats supported for LVPECL, LVDS, and CML compatible
modes. For single-ended CMOS format, both output pins
drive identical, in-phase clock outputs.
40
Preliminary Rev. 0.15
Si5317
Table 15. Si5317 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
4,9,12,13,
21,36
NC
—
—
No Connect.
Leave floating. Make no external connections to this pin for
normal operation.
GND PAD
GND
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
*Note: LVPECL requires VDD > 2.25 V
Preliminary Rev. 0.15
41
Si5317
Table 16. Si5317 Pull-Up/-Down
Pin #
1
Si5317
RST
Pull?
U
2
FRQTBL
RATE0
U, D
U, D
U, D
U, D
U, D
U, D
U, D
U, D
U, D
U, D
U, D
11
15
22
23
24
25
26
27
30
33
RATE1
BWSEL0
BWSEL1
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
SFOUT1
SFOUT0
42
Preliminary Rev. 0.15
Si5317
10. Ordering Guide
Ordering Part Number Output Clock Freq Range
Device Pkg
ROHS6, Pb-Free Temp Range
Si5317A-C-GM
Si5317B-C-GM
Si5317C-C-GM
Si5317D-C-GM
Si5317-EVB
1–710 MHz
1–350 MHz
1–200 MHz
1–100 MHz
1–710 MHz
36-Lead 6 x 6 mm QFN
36-Lead 6 x 6 mm QFN
36-Lead 6 x 6 mm QFN
36-Lead 6 x 6 mm QFN
Evaluation Board
Yes
Yes
Yes
Yes
—
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
—
Note: Add an “R” at the end of the device to denote tape and reel options (i.e., Si5317A-C-GMR).
Table 17. DSPLL Precision Clock Product Selection Guide
Part
Number
Control
Clock
Inputs/
Outputs
Input
Frequency
(MHz)
Output
Frequency
(MHz)
Jitter (12 kHz
to 20 MHz)
PLL
Hitless
Digital Freerun
Hold
VCO
Freeze
Signal
Format
Package
Bandwidth Switching
Si5315
Si5316
Si5317
Si5319
Si5322
Si5323
Pin
Pin
Pin
2/2
2/1
1/2
1/1
2/2
2/2
0.008 to 644 0.008 to 644 450 fs ms typ
60 Hz to
8.4 kHz
36-QFN
36-QFN
36-QFN
36-QFN
36-QFN
36-QFN
19 to 710
1 to 710
19 to 710
1 to 710
300 fs ms typ
300 fs ms typ
60 Hz to
8.4 kHz
60 Hz to
8.4 kHz
2
I C / SPI
0.002 to 710 0.002 to 1417 300 fs ms typ
60 Hz to
8.4 kHz
Pin
Pin
19 to 707
19 to 1050
600 fs ms typ
30 kHz to
1.3 MHz
0.008 to 707 0.008 to 1050 300 fs ms typ
60 Hz to
8.4 kHz
CMOS,
LVDS,
LVPECL,
CML
2
Si5324
Si5325
I C / SPI
2/2
2/2
0.002 to 710 0.002 to 1417 290 fs ms typ 4 to 525 Hz
36-QFN
36-QFN
2
I C/ SPI
10 to 710
10 to 1417
600 fs ms typ
30 kHz to
1.3 MHz
2
Si5326
Si5365
Si5366
Si5367
Si5368
I C / SPI
2/2
4/5
4/5
4/5
4/5
0.002 to 710 0.002 to 1417 300 fs ms typ
60 Hz to
8.4 kHz
36-QFN
Pin
Pin
19 to 710
19 to 1050
600 fs ms typ
30 kHz to
1.3 MHz
100-TQFP
100-TQFP
100-TQFP
100-TQFP
0.008 to 707 0.008 to1050 300 fs ms typ
60 Hz to
8.4 kHz
2
I C / SPI
10 to 710
10 to 1417
600 fs ms typ
30 kHz to
1.3 MHz
2
I C / SPI
0.002 to 710 0.002 to 1417 300 fs ms typ
60 Hz to
8.4 kHz
Preliminary Rev. 0.15
43
Si5317
11. Package Outline: 36-Pin QFN
Figure 24 illustrates the package details for the Si5317. Table 18 lists the values for the dimensions shown in the
illustration.
Figure 24. 36-Pin Quad Flat No-Lead (QFN)
Table 18. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Min
0.50
—
Nom
0.60
—
Max
0.70
12º
A
A1
b
L
0.02
0.25
aaa
bbb
ccc
ddd
eee
—
—
0.10
0.10
0.08
0.10
0.05
D
6.00 BSC
4.10
—
—
D2
e
3.95
4.25
—
—
0.50 BSC
6.00 BSC
4.10
—
—
E
—
—
E2
3.95
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
44
Preliminary Rev. 0.15
Si5317
12. Recommended PCB Layout
Figure 25. PCB Land Pattern Diagram
Figure 26. Ground Pad Recommended Layout
Preliminary Rev. 0.15
45
Si5317
Table 19. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
E
0.50 BSC.
5.42 REF.
5.42 REF.
D
E2
D2
GE
GD
X
4.00
4.00
4.53
4.53
—
4.20
4.20
—
—
0.28
Y
0.89 REF.
ZE
ZD
—
—
6.31
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
46
Preliminary Rev. 0.15
Si5317
13. Si5317 Device Top Mark
q: Speed Code: A, B, C, D
C: Product Revision
S i 5 3 1 7 q
C - G M
G: Temperature Range –40 to 85 °C
M: Package: QFN
Y Y WW R F
X X X X
YY: Year
WW: Week
R: Die Rev
F: Internal SiLabs Code
X: Lot Code
Preliminary Rev. 0.15
47
Si5317
NOTES:
48
Preliminary Rev. 0.15
Si5317
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.15
Updated corresponding sections and pinouts to add
CKOUT2, INC/DEC, and DBL2_BY functionality.
Updated functional block diagram on page 1.
Updated Table 2 IDD (DD is subscript).
Added Differential Rise/Fall Time spec to Table 2.
Updated pin assignment symbol and pin description
on page 1 and in section 9 to add CKOUT2,
INC/DEC, and DBL2_BY.
Added section 3.6. "PLL Bypass Mode”.
Updated section 8 diagram to add CKOUT2 and
DBL2_BY.
Added additional CMOS Termination with
attenuation figure.
Corrected pin name assignment (pin28) diagram on
page 1 and section 9, page 35 to match pin
description name.
Updated all the frequency plans in Table 8 to provide
coverage over the entire frequency range.
Material
Material
Preliminary Rev. 0.15
49
Si5317
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
50
Preliminary Rev. 0.15
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