SI5330F-A00216-GMR [SILICON]
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| 型号： | SI5330F-A00216-GMR |
| 厂家： | 
SILICON |
| 描述： | 暂无描述 转换器 电平转换器 时钟 |
| 文件： | 总20页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5330
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW
CLOCK BUFFER/LEVEL TRANSLATOR
Features
Supports single-ended or
Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
differential input clock signals
Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
Provides signal level translation
Differential to single-ended
Single-ended to differential
Differential to differential
Single-ended to single-ended
Wide frequency range
Loss of Signal (LOS) indicator
Ordering Information:
allows system clock monitoring
See page 14.
Output Enable (OEB) pin allows
glitchless control of output clocks
Low power: 10 mA typical core
Pin Assignments
LVPECL, LVDS: 5 to 710 MHz
HCSL: 5 to 250 MHz
SSTL, HSTL: 5 to 350 MHz
CMOS: 5 to 200 MHz
current
Industrial temperature range:
°
–40 to +85 C
Small size: 24-lead, 4 x 4 mm
24
23
22
21
20
19
Additive jitter: 150 fs RMS typ
QFN
CLK1A
CLK1B
VDDO1
IN1
IN2
Applications
IN3
GND
High Speed Clock Distribution
Ethernet Switch/Router
SONET / SDH
PCI Express 2.0/3.0
Fibre Channel
MSAN/DSLAM/PON
Telecom Line Cards
RSVD_GND
RSVD_GND
VDDO2
CLK2A
RSVD_GND
CLK2B
7
8
9
10
11
12
Functional Block Diagram
VDD
VDDO0
CLK0
Si5330
VDDO1
CLK1
Single-ended
Single-ended
or
Differential
IN
or
VDDO2
CLK2
Differential
VDDO3
CLK3
LOS
Control
OEB
Rev. 1.0 4/12
Copyright © 2012 by Silicon Laboratories
Si5330
Si5330
1. Functional Block Diagrams Based on Orderable Part Number*
1:8 Single-Ended to Single-Ended Buffer
1:4 Differential to Differential Buffer
VDDO0
VDDO0
Si5330A/B/C
Si5330F
CLK0A
CLK0A
CLK0B
CLK0B
VDDO1
IN1
IN2
VDDO1
IN3
CLK1A
CLK1A
CLK1B
CLK1B
IN1
IN2
VDDO2
VDDO2
IN3
CLK2A
CLK2A
CLK2B
CLK2B
LOS
OEB
LOS
OEB
VDDO3
Control
VDDO3
Control
CLK3A
CLK3A
CLK3B
CLK3B
1:4 Single-Ended to Differential Buffer
1:8 Differential to Single-Ended Buffer
VDDO0
VDDO0
Si5330K/L/M
Si5330G/H/J
CLK0A
CLK0A
CLK0B
VDDO1
CLK0B
VDDO1
IN1
IN2
IN3
CLK1A
CLK1A
CLK1B
CLK1B
IN1
IN2
VDDO2
VDDO2
IN3
CLK2A
CLK2A
CLK2B
CLK2B
LOS
OEB
LOS
OEB
VDDO3
Control
VDDO3
Control
CLK3A
CLK3A
CLK3B
CLK3B
Figure 1. Si5330 Functional Block Diagrams
*Note: See Table 11 for detailed ordering information.
2
Rev. 1.0
Si5330
TABLE OF CONTENTS
Section
Page
1. Functional Block Diagrams Based on Orderable Part Number* . . . . . . . . . . . . . . . . . . .2
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. VDD and VDDO Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2. Loss Of Signal Indicator (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3. Output Enable (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4. Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5. Output Driver Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.6. Input and Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering the Si5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6. Orderable Part Numbers and Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
7. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
9.1. Si5330 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev. 1.0
3
Si5330
2. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
–40
2.97
Typ
25
Max
85
Unit
°C
Ambient Temperature
T
A
3.3
3.63
V
V
2.25
1.71
2.5
1.8
2.75
1.98
V
V
Core Supply Voltage
DD
Output Buffer Supply
Voltage
V
DDOn
1.4
—
3.63
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
50 MHz refclk
Min
—
Typ
10
—
Max
—
Unit
mA
mA
mA
Core Supply Current
I
DD
LVPECL, 710 MHz
LVDS, 710 MHz
—
30
8
—
—
HCSL, 250 MHz
2 pF load capacitance
—
—
—
—
—
—
20
19
28
mA
mA
mA
SSTL, 350 MHz
Output Buffer Supply Current
I
DDOx
CMOS, 50 MHz
15 pF load capacitance
CMOS, 200 MHz
2 pF load capacitance
—
—
—
—
28
19
mA
mA
HSTL, 350 MHz
4
Rev. 1.0
Si5330
Table 3. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
CLKIN Loss of Signal Assert
Time
t
—
2.6
5
1
µs
LOS
CLKIN Loss of Signal De-Assert
Time
After initial start-up time has
expired
t
0.01
—
0.2
2.5
—
µs
ns
ps
LOS_B
Input-to-Output Propagation
Delay
t
4.0
100
2
PROP
Outputs at same signal
format
Output-Output Skew
t
—
DSKEW
Start-up time for output
clocks
POR to Output Clock Valid
t
—
—
ms
START
Table 4. Input and Output Clock Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Input Clock (AC Coupled Differential Input Clocks on Pin IN1/2)
fIN
VPP
tR/tF
DC
5
—
—
710
2.4
1.0
60
MHz
VPP
ns
Frequency
710 MHz input
20%–80%
0.4
—
Differential Voltage Swing
Rise/Fall Time
—
< 1 ns tr/tf
40
10
—
50
—
%
Duty Cycle
RIN
CIN
—
k
pF
Input Impedance
Input Capacitance
3.5
—
Input Clock (DC-Coupled Single-Ended Input Clock on Pin IN3)
CMOS
5
5
—
—
—
200
350
MHz
MHz
V
fIN
VI
Frequency
HSTL, SSTL
–0.1
VDD
Input Voltage
Input Voltage Swing
(CMOS Standard)
200 MHz, Tr/Tf = 1.3 ns
0.8
—
—
Vpp
tR/tF
DC
20%–80%
< 2 ns tr/tf
—
40
—
—
50
2
4
ns
%
Rise/Fall Time
60
—
Duty Cycle
CIN
pF
Input Capacitance
Output Clocks (Differential)
LVPECL, LVDS
HCSL
5
5
—
—
710
250
MHz
MHz
fOUT
Frequency
Rev. 1.0
5
Si5330
Table 4. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
VDDO
1.45 V
–
VOC
common mode
—
—
V
LVPECL Output Voltage
peak-to-peak single-
ended swing
VSEPP
VOC
VSEPP
VOC
VSEPP
VOC
VSEPP
tR/tF
0.55
1.125
0.25
0.8
0.8
0.96
1.275
0.45
VPP
V
common mode
1.2
LVDS Output Voltage
(2.5/3.3 V)
peak-to-peak single-
ended swing
0.35
0.875
0.35
0.375
0.725
VPP
V
common mode
0.95
LVDS Output Voltage
(1.8 V)
peak-to-peak single-
ended swing
0.25
0.35
0.575
0.45
VPP
V
common mode
0.400
0.85
HCSL Output Voltage
Rise/Fall Time
peak-to-peak single-
ended swing
VPP
20%–80%
—
—
—
450
55
ps
%
CKn < 350 MHz
45
DC
Duty Cycle*
350 MHz < CLKn <
710 MHz
40
—
60
%
Output Clocks (Single-Ended)
CMOS
5
5
—
—
200
350
MHz
MHz
fOUT
Frequency
SSTL, HSTL
CMOS 20%-80%
Rise/Fall Time
tR/tF
tR/tF
2 pF load
—
—
—
0.45
—
0.85
1.7
—
ns
ns
CMOS 20%-80%
Rise/Fall Time
15 pF load
CMOS Output
Resistance
50
—
—
50
50
—
—
—
—
—
V
V
V
SSTL Output Resistance
HSTL Output Resistance
VOH
VOL
VOH
4 mA load
4 mA load
VDDO–0.3
CMOS Output Voltage
0.3
—
0.45xVDDO+0.41
SSTL-3 VDDOx = 2.97 to
3.63 V
0.45xVDDO
–0.41
VOL
VOH
VOL
VOH
VOL
—
—
—
—
—
—
V
V
V
V
V
0.5xVDDO+0.41
—
SSTL-2 VDDOx = 2.25 to
2.75 V
SSTL Output Voltage
0.5xVDDO–
0.41
—
0.5xVDDO+0.34
—
SSTL-18 VDDOx = 1.71
to 1.98 V
0.5xVDDO–
0.34
6
Rev. 1.0
Si5330
Table 4. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
VOH
0.5xVDDO +0.3
—
—
V
VDDO = 1.4 to 1.6 V
HSTL Output Voltage
Duty Cycle*
0.5xVDDO
–0.3
VOL
DC
—
—
—
V
45
55
%
*Note: Input clock has a 50% duty cycle.
Table 5. OEB Input Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
Max
Unit
V
—
—
—
0.3 x V
—
V
V
Input Voltage Low
Input Voltage High
Input Resistance
IL
DD
V
0.7 x V
20
IH
DD
R
—
k
IN
Table 6. Output Control Pins (LOS)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Condition
Min
Typ
Max
0.4
10
Unit
V
I
= 3 mA
0
—
—
V
Output Voltage Low
Rise/Fall Time 20–80%
OL
SINK
t /t
C < 10 pf, pull up 1 k
—
ns
R F
L
Table 7. Jitter Specifications
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
0.7 V pk-pk differential input
clock at 622.08 MHz with
70 ps rise/fall time
Additive Phase Jitter
(12 kHz–20 MHz)
—
—
0.150
0.225
—
ps RMS
t
RPHASE
0.7 V pk-pk differential input
clock at 622.08 MHz with
70 ps rise/fall time
Additive Phase Jitter
(50 kHz–80 MHz)
—
ps RMS
t
RPHASEWB
Table 8. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance
Junction to Ambient
Still Air
37
25
°C/W
JA
Thermal Resistance
Junction to Case
Still Air
°C/W
JC
Rev. 1.0
7
Si5330
Table 9. Absolute Maximum Ratings1,2,3,4,5
Parameter
Symbol
Test Condition
Value
Unit
V
V
–0.5 to 3.8
–55 to 150
DC Supply Voltage
Storage Temperature Range
DD
T
°C
STG
HBM
(100 pF, 1.5 k)
2.5
kV
ESD Tolerance
CDM
MM
550
175
V
V
ESD Tolerance
ESD Tolerance
JESD78 Compliant
Latch-up Tolerance
Junction Temperature
Soldering Temperature
T
150
260
°C
°C
J
T
PEAK
5
(Pb-free profile)
T
20–40
sec
Soldering Temperature Time at T
(Pb-free profile)
P
PEAK
5
Notes:
1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2. 24-QFN package is RoHS compliant.
3. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. Moisture sensitivity level is MSL3.
5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
8
Rev. 1.0
Si5330
3.3. Output Enable (OEB)
3. Functional Description
The output enable (OEB) pin allows disabling or
enabling of the outputs clocks (CLK0-CLK3). The output
enable is logically controlled to ensure that no glitches
or runt pulses are generated at the output as shown in
Figure 3.
The Si5330 is a low-jitter, low-skew fanout buffer
optimized for high-performance PCB clock distribution
applications. The device produces four differential or
eight single-ended, low-jitter output clocks from a single
input clock. The input can accept either a single-ended
or a differential clock allowing the device to function as a
clock level translator.
IN
3.1. V and V
Supplies
DDO
DD
CLKn
Disable
Disable
The core V and output V
and independent supply pins allowing the core supply to
operate at a different voltage than the I/O voltage levels.
supplies have separate
DDO
DD
OEB
Enable
Enable
Figure 3. OEB Glitchless Operation
The V supply powers the core functions of the device,
which operates from 1.8, 2.5, or 3.3 V. Using a lower
supply voltage helps minimize the device’s power
DD
All outputs are enabled when the OEB pin is connected
to ground or below the V voltage for this pin.
IL
Connecting the OEB pin to VDD or above the V level
IH
consumption. The V
supply pins are used to set the
DDO
will disable the outputs. Both V and V are specified
IL
IH
output signal levels and must be set at a voltage level
compatible with the output signal format.
in Table 5. All outputs are forced to a logic “low” when
disabled. The OEB pin is 3.3 V tolerant.
3.2. Loss Of Signal Indicator (LOS)
3.4. Input Signals
The input is monitored for a valid clock signal using an
LOS circuit that monitors input clock edges and
declares an LOS condition when signal edges are not
detected over a 1 to 5 μs observation period. The LOS
pin is asserted “low” when activity on the input clock pin
is present. A “high” level on the LOS pin indicates a loss
of signal (LOS). The LOS pin must be pulled to VDD as
shown in Figure 2.
The Si5330 can accept single-ended and differential
input clocks. See “AN408: Termination Options for Any-
Frequency, Any-Output Clock Generators and Clock
Buffers—Si5338, Si5334, Si5330” for details on
connecting a wide variety of signals to the Si5330
inputs.
3.5. Output Driver Formats
The Si5330 supports single-ended output formats of
CMOS, SSTL, and HSTL and differential formats of
LVDS, LVPECL, and HCSL. It is normally required that
the LVDS driver be dc-coupled to the 100 termination
at the receiver end. If your application requires an ac-
coupled 100 load, contact the applications team for
advice. See AN408 for additional information on the
terminations for these driver types.
VDDO0
Si5330
CLK0
VDDO1
CLK1
IN
VDDO2
3.6. Input and Output Terminations
See AN408 for detailed information.
CLK2
VDD
4. Ordering the Si5330
VDDO3
1k
The Si5330 can be ordered to meet the requirements of
the most commonly-used input and output signal types,
such as CMOS, SSTL, HSTL, LVPECL, LVDS, and
HSCL. See Figure 1, “Si5330 Functional Block
Diagrams,” on page 2 and Table 11, “Order Numbers
and Device Functionality,” on page 14 for specific
ordering information.
CLK3
LOS
Control
Valid Clock
0
1
No Clock
Figure 2. LOS Indicator with External Pull-Up
Rev. 1.0
9
Si5330
5. Pin Descriptions
23
22
21
20
19
24
CLK1A
CLK1B
VDDO1
IN1
IN2
IN3
GND
RSVD_GND
RSVD_GND
VDDO2
CLK2A
RSVD_GND
CLK2B
7
8
9
10
11
12
Note: Center pad must be tied to GND for normal operation.
Table 10. Si5330 Pin Descriptions
Signal Type
Pin #
Pin Name
IN1
I/O
Description
1
I
I
Multi
Multi
Si5330A/B/C/G/H/J Differential Input Devices.
IN2
These pins are used as the differential clock input. IN1 is
the positive input; IN2 is the negative input. Refer to
“AN408: Termination Options for Any-Frequency, Any-
Output Clock Generators and Clock Buffers—Si5338,
Si5334, Si5330” for interfacing and termination details.
Si5330F/K/L/M Single-Ended Input Devices.
These pins are not used. Leave IN1 unconnected and
IN2 connected to ground.
2
3
Si5330F/K/L/M Single-Ended Devices.
This is the single-ended clock input. Refer to AN408 for
interfacing and termination details.
IN3
I
Multi
Si5330A/B/C/G/H/J Differential Input Devices.
This pin is not used. Connect to ground.
Ground.
4
5
6
RSVD_GND
RSVD_GND
RSVD_GND
Must be connected to system ground.
Ground.
Must be connected to system ground.
Ground.
Must be connected to system ground.
10
Rev. 1.0
Si5330
Table 10. Si5330 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 µF bypass capacitor should be located very close to
this pin.
7
VDD
VDD
Supply
Loss of Signal Indicator.
0 = CLKIN present.
1 = Loss of signal (LOS).
This pin requires an external 1 kpull-up resistor.
8
9
LOS
O
O
Open Drain
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK3 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK3 outputs. Both
CLK3A and CLK3B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
CLK3B
Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK3 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
10
CLK3A
O
Multi
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK3 outputs. Both
CLK3A and CLK3B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Output Clock Supply Voltage.
Supply voltage for CLK3A/B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK3 is not used, this
11
12
VDDO3
VDD
Supply
pin must be tied to V (pin 7 and/or pin 24).
DD
Ground.
RSVD_GND
Must be connected to system ground.
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK2 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
13
CLK2B
O
Multi
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK2 outputs. Both
CLK2A and CLK2B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Rev. 1.0
11
Si5330
Table 10. Si5330 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK2 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
14
CLK2A
O
Multi
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK2 outputs. Both
CLK2A and CLK2B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Output Clock Supply Voltage.
Supply voltage for CLK2A/B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK2 is not used, this
15
16
VDDO2
VDDO1
VDD
VDD
Supply
Supply
pin must be tied to V (pin 7 and/or pin 24).
DD
Output Clock Supply Voltage.
Supply voltage for CLK1A,B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK1 is not used, this
pin must be tied to V (pin 7 and/or pin 24).
DD
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
17
CLK1B
O
Multi
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
18
CLK1A
O
Multi
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Output Enable.
All outputs are enabled when the OEB pin is connected
to ground or below the V voltage for this pin. Connect-
IL
19
20
OEB
I
CMOS
Supply
ing the OEB pin to V or above the V level will dis-
DD
IH
able the outputs. Both V and V are specified in
IL
IH
Table 5. All outputs are forced to a logic “low” when dis-
abled. This pin is 3.3 V tolerant.
Output Clock Supply Voltage.
Supply voltage for CLK0A,B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK2 is not used, this
VDDO0
VDD
pin must be tied to V (pin 7 and/or pin 24).
DD
12
Rev. 1.0
Si5330
Table 10. Si5330 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK0 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
21
CLK0B
O
Multi
Si5330F/G/H/J Single-ended Output Devices.
This is one of the single-ended CLK0 outputs. Both
CLK0A and CLK0B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK0 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
22
CLK0A
O
Multi
Si5330F/G/H/J Single-ended Devices.
This is one of the single-ended CLK0 outputs. Both
CLK0A and CLK0B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Ground.
23
24
RSVD_GND
VDD
Must be connected to system ground.
Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 µF bypass capacitor should be located very close to
this pin.
VDD
GND
Supply
Supply
Ground Pad.
This is main ground connection for this device. It is
located at the bottom center of the package. Use as
many vias as possible to connect this pad to the main
ground plane. The device will not function as specified
unless this ground pad is properly connected to ground.
GND
PAD
GND
Rev. 1.0
13
Si5330
6. Orderable Part Numbers and Device Functionality
Table 11. Order Numbers and Device Functionality
1,2
Input Signal
Format
Output Signal
Format
Number
of
Outputs
Frequency
Range
Part Number
LVPECL Buffers
Differential
Differential
3.3 V LVPECL
2.5 V LVPECL
4
4
5 to 710 MHz
5 to 710 MHz
Si5330A-A00200-GM
Si5330A-A00202-GM
LVDS Buffers
Differential
Differential
Differential
3.3 V LVDS
2.5 V LVDS
1.8 V LVDS
4
4
4
5 to 710 MHz
5 to 710 MHz
5 to 710 MHz
Si5330B-A00204-GM
Si5330B-A00205-GM
Si5330B-A00206-GM
HCSL Buffers
Differential
Differential
Differential
3.3 V HCSL
2.5 V HCSL
1.8 V HCSL
4
4
4
5 to 250 MHz
5 to 250 MHz
5 to 250 MHz
Si5330C-A00207-GM
Si5330C-A00208-GM
Si5330C-A00209-GM
CMOS Buffers
Single-Ended
Single-Ended
Single-Ended
3.3 V CMOS
2.5 V CMOS
1.8 V CMOS
8
8
8
5 to 200 MHz
5 to 200 MHz
5 to 200 MHz
Si5330F-A00214-GM
Si5330F-A00215-GM
Si5330F-A00216-GM
CMOS Buffers (Differential Input)
Differential
Differential
Differential
3.3 V CMOS
2.5 V CMOS
1.8 V CMOS
8
8
8
5 to 200 MHz
5 to 200 MHz
5 to 200 MHz
Si5330G-A00217-GM
Si5330G-A00218-GM
Si5330G-A00219-GM
SSTL Buffers (Differential Input)
Differential
Differential
Differential
3.3 V SSTL
2.5 V SSTL
1.8 V SSTL
8
8
8
5 to 350 MHz
5 to 350 MHz
5 to 350 MHz
Si5330H-A00220-GM
Si5330H-A00221-GM
Si5330H-A00222-GM
HSTL Buffers (Differential Input)
Differential
1.5 V HSTL
8
5 to 350 MHz
Si5330J-A00223-GM
LVPECL Buffers (Single-Ended Input)
Single-Ended
Single-Ended
3.3 V LVPECL
2.5 V LVPECL
4
4
5 to 350 MHz
5 to 350 MHz
Si5330K-A00224-GM
Si5330K-A00226-GM
Notes:
1. Custom configurations with mixed output types are also available. Please contact the factory for ordering details.
2. Add an “R” to the part number to specify tape and reel shipment media. When specifying non-tape-and-reel shipment
media, contact your sales representative for more information.
14
Rev. 1.0
Si5330
Table 11. Order Numbers and Device Functionality (Continued)
1,2
Input Signal
Format
Output Signal
Format
Number
of
Outputs
Frequency
Range
Part Number
LVDS Buffers (Single-Ended Input)
Single-Ended
Single-Ended
Single-Ended
3.3 V LVDS
2.5 V LVDS
1.8 V LVDS
4
4
4
5 to 350 MHz
5 to 350 MHz
5 to 350 MHz
Si5330L-A00228-GM
Si5330L-A00229-GM
Si5330L-A00230-GM
HCSL Buffers (Single-Ended Input)
Single-Ended
Single-Ended
Single-Ended
3.3 V HCSL
2.5 V HCSL
1.8 V HCSL
4
4
4
5 to 250 MHz
5 to 250 MHz
5 to 250 MHz
Si5330M-A00231-GM
Si5330M-A00232-GM
Si5330M-A00233-GM
Notes:
1. Custom configurations with mixed output types are also available. Please contact the factory for ordering details.
2. Add an “R” to the part number to specify tape and reel shipment media. When specifying non-tape-and-reel shipment
media, contact your sales representative for more information.
Rev. 1.0
15
Si5330
7. Package Outline: 24-Lead QFN
Figure 4. 24-Lead Quad Flat No-Lead (QFN)
Table 12. Package Dimensions
Dimension
Min
Nom
Max
A
A1
b
0.80
0.00
0.18
0.85
0.02
0.90
0.05
0.30
0.25
D
4.00 BSC.
2.50
D2
e
2.35
2.65
0.50 BSC.
4.00 BSC.
2.50
E
E2
L
2.35
0.30
2.65
0.50
0.40
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.08
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
5. J-STD-020 MSL rating: MSL3.
6. Terminal base alloy: Cu.
7. Terminal plating/grid array material: Au/NiPd.
8. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
16
Rev. 1.0
Si5330
8. Recommended PCB Layout
Table 13. PCB Land Pattern
Dimension
Min
2.50
2.50
0.20
0.75
Nom
2.55
2.55
Max
2.60
2.60
P1
P2
X1
Y1
C1
C2
E
0.25
0.80
0.30
0.85
3.90
3.90
0.50
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. Connect the center ground pad to a ground plane with no less than five vias to a ground plane that is no more than
20 mils below it. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is allowed if
more vias are used to keep the inductance from increasing.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Rev. 1.0
17
Si5330
9. Top Marking
9.1. Si5330 Top Marking
Si5330
Xxxxxx
RTTTTT
YYWW
9.2. Top Marking Explanation
Mark Method:
Line 1 Marking:
Line 2 Marking:
Laser
Device Part Number
Si5330
Xxxxxx
X = Frequency and configuration code.
xxxxx = Input and output format configu-
ration code.
See "6. Orderable Part Numbers and
Device Functionality" on page 14 for more
information.
Line 3 Marking:
Line 4 Marking:
R = Product revision (A).
TTTTT = Manufacturing trace code.
RTTTTT
Pin 1 indicator.
Circle with 0.5 mm diameter;
left-justified
YY = Year.
YYWW
WW = Work week.
Characters correspond to the year and
work week of package assembly.
18
Rev. 1.0
Si5330
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Clarified documentation to reflect that Pin 19 is OEB
(OE Enable Low).
Updated Table 4, “Jitter Specifications” on page 7.
Revision 0.2 to Revision 0.3
Major editorial updates to improve clarity.
Updated “Additive Jitter” Specification Table.
Updated “Core Supply Current” Specification in
Table 2.
Removed the Low-Power LVPECL output options
from the ordering table in section 6.
Removed D/E ordering options.
Revision 0.3 to Revision 0.35
Typo of 150 ps on front page changed to 150 fs.
Updated PCB layout notes.
Added no ac coupling for LVDS outputs.
Changed input rise/fall time spec to 2 ns.
Revision 0.35 to Revision 1.0
Added maximum junction temperature specification
to Table 9 on page 8.
Added minimum and maximum duty cycle
specifications to Table 4 on page 5.
Updated Table 3, “Performance Characteristics,” on
page 5.
Added maximum propagation delay spec (4 ns).
Added test condition to t
in Table 3 on page 5.
LOS_B
Removed reference to frequency in Output-Output
Skew.
Updated Table 4, “Input and Output Clock
Characteristics,” on page 5.
Input voltage (max) changed “3.63” to “VDD”
Input voltage swing (max) change “3.63” with “—”.
Added Table 6, “Output Control Pins (LOS),” on
page 7.
Added tape and reel ordering information to "6.
Orderable Part Numbers and Device Functionality"
on page 14.
Added "9. Top Marking" on page 18.
Rev. 1.0
19
Si5330
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
20
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