SI53315-B-GMR [SILICON]
Clock Driver;
SILICON 
Si53315
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ)
Features
10 differential or 20 LVCMOS outputs Low propagation delay variation:
<400 ps
Independent VDD and VDDO
1.8/2.5/3.3 V
Ultra-low additive jitter: 100 fs rms
Wide frequency range:
1 MHz to 1.25 GHz
:
Any-format input with pin selectable
output formats: LVPECL, Low Power
LVPECL, LVDS, CML, HCSL,
LVCMOS
2:1 mux with hot-swappable inputs
Asynchronous output enable
Individual output enable
Excellent power supply noise
rejection (PSRR)
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
Small size: 44-QFN (7 mm x 7 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
Low output-output skew: <50 ps
See page 25.
Applications
Pin Assignments
Si53315
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
Storage
Telecom
Industrial
Servers
PCI Express Gen 1/2/3
Backplane clock distribution
Description
1
2
3
33
32
31
OE2
OE7
SFOUT[0]
SFOUT[1]
OE1
Q2
OE8
The Si53315 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53315 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53315 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to
1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53315 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
4
5
30
29
28
27
26
25
24
23
Q7
Q7
NC
Q8
Q2
GND
PAD
6
GND
Q1
7
8
Q1
Q8
Q9
9
Q0
Q0
10
11
Q9
OE0
OE9
Patents pending
Functional Block Diagram
Power
Vref
Supply
VREF
Generator
Filtering
VDDOA
OE[0:4]
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
CLK0
CLK0
SFOUT[1:0]
VDDOB
CLK1
CLK1
OE[5:9]
Q5, Q6, Q7, Q8, Q9
Switching
Logic
Q5, Q6, Q7, Q8, Q9
CLK_SEL
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
Si53315
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si53315
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.4. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.5. Power Supply (V and V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DD
DDOX
2.6. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.7. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.8. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.9. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.10. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3. Pin Description: 44-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.1. 7x7 mm 44-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7.1. Si53315 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
Preliminary Rev. 0.4
Si53315
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Ambient Operating
Temperature
T
–40
—
85
°C
A
Supply Voltage Range*
V
LVDS, CML, HCSL, LVCMOS
1.71
2.38
2.97
1.71
2.38
2.97
1.8
2.5
3.3
—
1.89
2.63
3.63
1.89
2.63
3.63
V
V
V
V
V
V
DD
LVPECL, low power LVPECL,
LVDS, CML, HCSL, LVCMOS
Output Buffer Supply
Voltage*
V
LVDS, CML, HCSL, LVCMOS
DDO
LVPECL, low power LVPECL,
LVDS, CML, HCSL, LVCMOS
—
—
*Note: Core supply V
and output buffer supplies VDDO are independent.
DD
Table 2. Input Clock Specifications
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA = –40 to 85 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Differential Input Common
Mode Voltage
V
V
= 2.5 V 5%, 3.3 V 10%
DD
0.05
—
—
V
CM
Input Swing
(single-ended, peak-to-
peak)
V
V
0.1
—
1.1
—
V
IN
IH
Input Voltage High
Input Voltage Low
Input Capacitance
V
x
—
—
5
V
V
DD
0.7
V
C
—
V
x
DD
IL
0.3
—
—
pF
IN
Preliminary Rev. 0.4
3
Si53315
Table 3. DC Common Characteristics
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Supply Current
I
—
—
—
—
—
—
—
TBD
35
30
20
30
35
5
100
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
DD
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz
I
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)
LVDS (3.3 V)
DDOX
CML (3.3 V)
HCSL, 100 MHz, 2 pF load (3.3 V)
CMOS (1.8 V, SFOUT = Open/0),
per output, C = 5 pF, 200 MHz
L
CMOS (2.5 V, SFOUT = Open/0),
—
—
—
—
—
8
—
—
mA
mA
µA
per output, C = 5 pF, 200 MHz
L
CMOS (3.3 V, SFOUT = 0/1),
15
—
—
per output, C = 5 pF, 200 MHz
L
Leakage Current
I
Input leakage at all inputs except
TBD
TBD
L
CLKIN, V = 0 V
IN
Input leakage at CLKIN
µA
V
= 0 V
IN
Voltage Reference
Input High Voltage
V
V
pin
REF
VDD/2
—
—
—
V
V
REF
V
SFOUTX, DIVX
3-level input pins
0.85 x
VDD
IH
Input Mid Voltage
Input Low Voltage
V
SFOUTX, DIVX
3-level input pins
0.45 x
VDD
0.5 x
VDD
0.55 x
VDD
V
V
IM
V
SFOUTX, DIVXpin
3-level input pins
—
—
—
—
25
25
0.15 x
VDD
IL
Internal Pull-down
Resistor
R
CLK_SEL, DIVA, DIVB, SFOUTA[1],
SFOUTB[1]
—
kΩ
kΩ
DOWN
Internal Pull-up
Resistor
R
SFOUTA[1], SFOUTB[1], DIVA,
DIVB, OEX, OEX
—
UP
4
Preliminary Rev. 0.4
Si53315
Table 4. DC Characteristics—LVPECL and Low Power LVPECL
(VDD = 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Output Voltage High
V
R = 50 Ω to V
– 2 V
V
V
V
–
—
V
V
V
–
V
OH
L
DDOX
DDOX
DDOX
1.145
0.895
Output Voltage Low
V
R = 50 Ω to V
– 2 V
–
—
—
–
V
V
V
OL
L
DDOX
DDOX
DDOX
1.945
1.695
Output DC Common
Mode Voltage
V
–
–
DDOX
1.425
COM
DDOX
1.895
Single-Ended
Output Swing
V
Terminate unused outputs to
R = 50 Ω to V – 2 V
0.25
0.60
0.85
SE
L
DDOX
Table 5. DC Characteristics—CML
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Single-Ended Output
Swing
V
Terminated as shown in Figure 6
(CML termination).
300
400
500
mV
SE
Table 6. DC Characteristics—LVDS
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Single-Ended Output
Swing
V
R = 100 Ω across Q and Q
247
—
454
mV
SE
L
N
N
Output Common
Mode Voltage
V
V
= 2.38 to 2.63 V, 2.97 to
1.10
0.85
1.25
0.97
1.35
1.10
V
V
COM1
COM2
DDOX
3.63 V, R = 100 Ω across Q
L
N
and Q
(V
= 2.5 V or
N
DDO
3.3 V)
Output Common
Mode Voltage
V
V
= 1.71 to 1.89 V,
DDOX
R = 100 Ω across Q
L
N
(V
= 1.8 V)
and Q
DDO
N
Preliminary Rev. 0.4
5
Si53315
Table 7. DC Characteristics—LVCMOS
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
*
Output Voltage High
V
0.8 x
—
—
V
OH
V
DDOX
*
Output Voltage Low
V
—
—
0.2 x
V
OL
V
DDOX
*Note: IOH and IOL per the Output Signal Format Table for specific V
and SFOUTX settings.
DDOX
Table 8. DC Characteristics—HCSL
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Symbol
Test Condition
R = 50 Ω to GND
Min
Typ
Max
Unit
Parameter
Output Voltage High
Output Voltage Low
V
550
–150
—
700
0
850
150
—
mV
mV
mV
OH
L
V
V
R = 50 Ω to GND
L
OL
SE
Single-Ended
Output Swing
R = 50 Ω to GND
700
L
Crossing Voltage
V
R = 50 Ω to GND
250
350
550
mV
C
L
6
Preliminary Rev. 0.4
Si53315
Table 9. AC Characteristics
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Frequency
F
LVPECL, low power LVPECL,
LVDS, CML, HCSL
1
—
1250
MHz
LVCMOS
1
—
200
MHz
%
Duty Cycle
D
200 MHz, 50 toV /220/80%
TBD
TBD
TBD
C
DD
T /T <10% of period (LVCMOS)
Note: 50% input duty
cycle.
R
F
20/80% T /T <10% of period
48
50
—
52
—
%
R
F
(Differential)
Minimum Input Clock
Slew Rate
SR
Required to meet prop delay and
additive jitter specifications
(20–80%)
0.75
V/ns
1
Output Rise/Fall Time
T /T
LVPECL, LVDS, CML, HCSL,
20/80%
350
750
ps
ps
R
F
200 MHz, 50 20/80%,
TBD
TBD
2 pF load (LVCMOS)
Minimum Input Pulse
Width
T
500
—
—
—
ps
fs
W
Additive Jitter
(Differential Clock
Input)
J
V
= 2.5/3.3 V, LVPECL/LVDS,
F = 725 MHz, 0.75 V/ns
input slew rate
60
80
DD
Propagation Delay
T
T
Low to high, high to low
Single-ended
TBD
TBD
—
—
TBD
TBD
ns
ns
PLH,
PHL
Low to high, high to low
Differential
2
Output Enable Time
T
F = 1 MHz
F = 100 MHz
F = 725 MHz
F = 1 MHz
—
—
—
—
—
—
2
—
—
—
—
—
—
s
ns
ns
s
ns
ns
EN
60
50
2
2
Output Disable Time
T
DIS
F = 100 MHz
F = 725 MHz
25
15
Notes:
1. For clock division applications, a minimum input clock slew rate of 30 mV/ns is required.
2. See Figure 4.
3. Defined as skew between outputs on different devices operating at the same supply voltages, temperatures, and equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (1.8 V = 50 mVPP
,
2.5/3.3 V = 100 mVPP) and noise spur amplitude measured. See AN491 for further details.
Preliminary Rev. 0.4
7
Si53315
Table 9. AC Characteristics (Continued)
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Output to Output
Skew
T
Identical Configuration,
—
—
100
ps
SK
Single-ended (Q to Q )
N
M
Identical Configuration,
Differential (Q to Q )
—
—
50
ps
N
M
3
Part to Part Skew
T
Identical configuration
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
—
—
—
—
—
50
—
—
—
—
—
ps
PS
Power Supply Noise
PSRR
–90
–90
–80
–70
dBc
dBc
dBc
dBc
4
Rejection
Notes:
1. For clock division applications, a minimum input clock slew rate of 30 mV/ns is required.
2. See Figure 4.
3. Defined as skew between outputs on different devices operating at the same supply voltages, temperatures, and equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (1.8 V = 50 mVPP
,
2.5/3.3 V = 100 mVPP) and noise spur amplitude measured. See AN491 for further details.
8
Preliminary Rev. 0.4
Si53315
Table 10. Thermal Conditions
Symbol
Test Condition
Value
Unit
Parameter
Thermal Resistance,
Junction to Ambient
JA
JC
Still air
46.2
°C/W
Thermal Resistance,
Junction to Case
Still air
27.1
°C/W
Table 11. Absolute Maximum Ratings
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Storage Temperature
Supply Voltage
T
–55
–0.5
–0.5
—
—
—
150
3.8
C
V
S
V
DD
Input Voltage
V
V
+
V
IN
DD
0.3
Output Voltage
V
—
—
V
+
V
OUT
DD
0.3
ESD Sensitivity
ESD Sensitivity
HBM
CDM
HBM, 100 pF, 1.5 kΩ
2000
500
—
—
—
—
—
—
V
V
Peak Soldering Reflow
Temperature
T
Pb-Free; Solder reflow profile per
JEDEC J-STD-020
260
C
PEAK
Maximum Junction
Temperature
T
—
—
125
C
J
Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Preliminary Rev. 0.4
9
Si53315
2. Functional Description
The Si53315 is a low jitter, low skew 1:10 differential buffer with an integrated 2:1 input mux and individual OE
control. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock
select pin is used to select the active input clock. The selected clock input is routed to two independent banks of
outputs. Each output bank features control pins to select signal format and LVCMOS drive strength settings. In
addition, each clock output has an independent OE pin for individual clock enable/disable.
2.1. Universal, Any-Format Input
The Si53315 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including
LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 12 and 13 summarize the various input ac- and dc-coupling
options supported by the device. Figures 1 and 2 show the recommended input clock termination options.
Table 12. LVPECL, LVCMOS, and LVDS
LVPECL
LVCMOS
LVDS
AC-Couple
AC-Couple
DC-Couple
N/A
AC-Couple
DC-Couple
Yes
DC-Couple
No
1.8 V
N/A
Yes
No
No
Yes
Yes
2.5/3.3 V
Yes
Yes
Yes
Table 13. HCSL and CML
HCSL
CML
AC-Couple
DC-Couple
No
AC-Couple
DC-Couple
1.8 V
No
No
Yes
Yes
No
No
2.5/3.3 V
Yes (3.3 V)
Si533xx
0.1 uF
0.1 uF
CLKx
100
/CLKx
Figure 1. Differential LVPECL, LVDS, CML AC-Coupled Input Termination
VDDO
VDD
= 3.3V, 2.5V, 1.8V
Si533xx
Rs
CM OS
Driver
CLKx
50
/CLKx
VREF
0.1 uF
Note: VDDO and VDD m ust be at the sam e voltage level.
Figure 2. LVCMOS DC-Coupled Input Termination
10
Preliminary Rev. 0.4
Si53315
VDDO
DC Coupled LVPECL Termination Scheme 1
VDD
R1
R1
VDDO
= 3.3V or 2.5V
Si533xx
CLKx
/CLKx
50
50
“Standard”
LVPECL
Driver
VTERM = VDDO – 2V
R1 // R2 = 50 Ohm
R2
R2
3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm
2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm
DC Coupled LVPECL Termination Scheme 2
VDD
VDDO
= 3.3V or 2.5V
Si533xx
50
50
CLKx
“Standard”
LVPECL
Driver
/CLKx
50
50
VTERM = VDDO – 2V
DC Coupled LVDS Termination
VDD
VDDO = 3.3V or 2.5V
Si533xx
CLKx
50
50
Standard
LVDS
Driver
/CLKx
100
DC Coupled HCSL Termination Scheme
VDD
VDDO
= 3.3V
33
33
Si533xx
50
50
CLKx
/CLKx
Standard
HCSL Driver
50
50
Note: 33 Ohm series termination is optional depending on the location of the receiver.
Figure 3. Differential DC-Coupled Input Terminations
Preliminary Rev. 0.4
11
Si53315
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The noninverting input is biased with a 18.75 k pulldown to GND and a 75 k pullup to V . The inverting input is
DD
biased with a 75 k pullup to V
.
DD
VDD
RPU
RPU
+
–
RPD
CLK0 or
CLK1
RPU = 75 kohm
RPD = 18.75 kohm
Figure 4. Input Bias Resistors
2.3. Universal, Any-Format Output Buffer
The Si53315 has highly flexible output drivers that support a wide range of clock signal formats, including LVPECL,
low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUT[0] and SFOUT[1] are 3-level inputs that can be
pin-strapped to select the clock signal formats for all of the outputs, Q0 through Q9. This feature enables the device
to be used for format/level translation in addition to clock distribution, minimizing the number of unique buffer part
numbers required in a typical application and simplifying design reuse. For EMI reduction applications, four
LVCMOS drive strength options are available for each V
setting.
DDO
Table 14. Output Signal Format Selection
SFOUT[1]
SFOUT[0]
V
= 3.3 V
V
= 2.5 V
V
= 1.8 V
DDOX
DDOX
DDOX
Open*
Open*
LVPECL
LVDS
LVPECL
LVDS
N/A
LVDS
0
0
0
1
LVCMOS, 24 mA drive LVCMOS, 18 mA drive
LVCMOS, 18 mA drive LVCMOS, 12 mA drive
LVCMOS, 12 mA drive LVCMOS, 9 mA drive
LVCMOS, 6 mA drive LVCMOS, 4 mA drive
LVCMOS, 12 mA drive
LVCMOS, 9 mA drive
LVCMOS, 6 mA drive
LVCMOS, 2 mA drive
N/A
1
0
1
Open*
Open*
0
1
0
1
LVPECL Low power
LVPECL Low power
Open*
Open*
CML
CML
CML
1
HCSL
HCSL
HCSL
*Note: SFOUT[1:0] are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to
VDD/2.
12
Preliminary Rev. 0.4
Si53315
2.4. Input Mux and Output Enable Logic
The Si53315 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 15. Input Mux and Output Enable Logic
OE1
Q2
CLK_SEL
CLK0
CLK1
L
L
H
X
X
X
X
X
L
H
L
L
H
H
H
L
H
L
H
H
H
X
H
3
X
L
Notes:
1. Output enable active high
2. On the next negative transition of CLK0 or CLK1.
3. Single-end: Q=low, Q=high
Differential: Q=low, Q=high
2.5. Power Supply (V and VDDO
)
X
DD
The device includes separate core (V ) and output driver supplies (V
). This feature allows the core to
DDOX
DD
operate at a lower voltage than V
, reducing current consumption in mixed supply applications. The core V
DDO
DD
supports 3.3, 2.5, or 1.8 V. Each output bank has its own V
supply, supporting 3.3, 2.5, or 1.8 V.
DDOX
Preliminary Rev. 0.4
13
Si53315
2.6. Output Clock Termination Options
The recommended output clock termination options are shown below. Unused output clocks should be left floating.
VDDO
DC Coupled LVPECL Termination Scheme 1
R1
R1
VDDO
= 3.3V or 2.5V
VDD = VDDO
Si533xx
50
50
Q
LVPECL
Receiver
Qn
VTERM = VDDO – 2V
R1 // R2 = 50 Ohm
R2
R2
3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm
2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm
DC Coupled LVPECL Termination Scheme 2
VDDO
= 3.3V or 2.5V
VDD = VDDO
50
50
Si533xx
Q
LVPECL
Receiver
Qn
50
50
VTERM = VDDO – 2V
VDDO
AC Coupled LVPECL Termination Scheme 1
R1
R1
VDDO = 3.3V or 2.5V
0.1 uF
VDD
= 3.3V or 2.5V
Si533xx
50
50
Q
LVPECL
Receiver
Qn
0.1 uF
VBIAS = VDD – 1.3V
R1 // R2 = 50 Ohm
R2
R2
Rb
Rb
3.3V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm
2.5V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm
AC Coupled LVPECL Termination Scheme 2
VDDO
= 3.3V or 2.5V
0.1 uF
0.1 uF
VDD
= 3.3V or 2.5V
Si533xx
50
50
Q
LVPECL
Receiver
Qn
50
50
Rb
Rb
3.3V LVPECL: Rb = 120 Ohm
2.5V LVPECL: Rb = 90 Ohm
Figure 5. LVPECL Output Termination
14
Preliminary Rev. 0.4
Si53315
DC Coupled LVDS and Low-Power LVPECL Termination
VDDO
= 3.3V or 2.5V or 1.8V
VDD
Si533xx
50
50
Q
LVDS
Receiver
Qn
100
AC Coupled LVDS Termination
VDDO
0.1 uF
= 3.3V or 2.5V or 1.8V
VDD
Si533xx
50
50
Q
LVDS
Receiver
Qn
0.1 uF
50
50
AC Coupled CML Termination
VDDO
0.1 uF
= 3.3V or 2.5V or 1.8V
VDD
Si533xx
50
50
Q
CML
Receiver
100
Qn
0.1 uF
DC Coupled HCSL Receiver Termination
VDDO = 3.3V
VDD
Si533xx
50
50
Q
Standard
HCSL
Receiver
Qn
50
50
DC Coupled HCSL Source Termination
VDDO = 3.3V
42.2
VDD
Si533xx
50
Q
Standard
HCSL
Receiver
42.2
Qn
50
86.6
86.6
Figure 6. LVDS, CML, and HCSL Output Termination
Preliminary Rev. 0.4
15
Si53315
CMOS
Receivers
Si533xx
CMOS Driver
Zo
50
Rs
Zout
CL = 15 pF
Figure 7. LVCMOS Output Termination
Table 16. Recommended LVCMOS RS Series Termination
SFOUT[1]
SFOUT[0]
RS (ohms)
3.3 V
33
33
0
2.5 V
33
33
0
1.8 V
33
33
0
0
1
1
0
1
0
1
Open
0
0
0
16
Preliminary Rev. 0.4
Si53315
2.7. AC Timing Waveforms
TPHL
TSK
VPP/2
VPP/2
CLK
QN
QM
VPP/2
VPP/2
Q
TPLH
TSK
Propagation Delay
Output-Output Skew
TF
80% VPP
20% VPP
Q
80% VPP
20% VPP
Q
TR
Rise/Fall Time
Figure 8. AC Waveforms
Preliminary Rev. 0.4
17
Si53315
2.8. Typical Phase Noise Performance
22.77fs@625MHz
30.26fs@312.5MHz
39.34fs@156.25MHz
Source Jitter
55.00fs@625MHz
106.37fs@312.5MHz
191.58fs@156.25MHz
Total Jitter
Figure 9. Si53315 Phase Noise
Note: Measured single-endedly.
18
Preliminary Rev. 0.4
Si53315
Table 17. Si53315 Additive Jitter
Frequency
(MHz)
Source Jitter
(fs)
Total Jitter
(fs)
Additive Jitter
(fs)
156.25
312.5
625
39.34
30.26
22.77
191.58
106.37
55.00
187.50
101.98
50.07
2.9. Input Mux Noise Isolation
LVPECL output@156.25MHz;
Selected clk is active
Unselected clk is static
Mux Isolation = 61dB
LVPECL output@156.25MHz;
Selected clk is static
Unselected clk is active
Figure 10. Input Mux Noise Isolation
Preliminary Rev. 0.4
19
Si53315
2.10. Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low
jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and
SoCs and may reduce board-level filtering requirements. For more information, see AN491: Power Supply
Rejection for Low Jitter Clocks.
ꢀꢃꢀ
ꢁꢂꢀꢃꢀ
ꢁꢅꢀꢃꢀ
)F ꢆꢇꢄꢃꢂꢇ0+]ꢈ
ꢁꢄꢀꢃꢀ
ꢁꢉꢀꢃꢀ
ꢁꢆꢀꢀꢃꢀ
ꢁꢆꢂꢀꢃꢀ
ꢀꢃꢀꢆ
ꢀꢃꢆ
ꢆ
Figure 11. Power Supply Noise Rejection (100 mVpp Sinusoidal Power Supply Noise Applied)
20
Preliminary Rev. 0.4
Si53315
3. Pin Description: 44-Pin QFN
1
33
32
31
OE2
OE7
2
SFOUT[0]
SFOUT[1]
3
OE1
OE8
4
30
29
28
27
26
25
24
23
Q2
Q7
Q7
NC
Q8
5
Q2
GND
PAD
6
GND
7
Q1
8
Q1
Q8
9
Q9
Q0
10
Q9
Q0
11
OE0
OE9
Table 18. Pin Description
Description
Pin #
Name
1
OE2
Output enable—Output 2
When OE = high, the Q2 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE2 contains an internal pull-up resistor.
2
3
SFOUT[0]
OE1
Output signal format control pin [0]
Three-level input control. Internally biased at V /2. Can be left floating or tied to
DD
ground or V
.
DD
Output enable—Output 1
When OE = high, the Q1 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE1 contains an internal pull-up resistor.
4
5
Q2
Q2
Output clock 2 (complement)
Output clock 2
6
7
GND
Q1
Ground
Output clock 1 (complement)
Preliminary Rev. 0.4
21
Si53315
Table 18. Pin Description (Continued)
Output clock 1
8
9
Q1
Q0
Output clock 0 (complement)
Output clock 0
10
11
Q0
OE0
Output enable—Output 0
When OE = high, the Q0 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE0 contains an internal pull-up resistor.
12
13
V
Core voltage supply
Bypass with 1.0 µF capacitor and place close to the V pin as possible
DD
DD
OE3
Output Enable 3
When OE = high, the Q3 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE3 contains an internal pull-up resistor.
14
15
CLK0
CLK0
Input clock 0
Input clock 0 (complement)
When CLK0 is driven by a single-ended input, connect V
CLK0 contains an internal pull-up resistor.
to CLK0.
REF
16
17
OE4
Output Enable 4
When OE = high, Q4 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE4 contains an internal pull-up resistor.
V
Input reference voltage
REF
When driven by a LVCMOS clock input, connect the unused clock input to V
and a
REF
0.1 µF cap to ground. When driven by a differential clock, do not connect the V
pin.
REF
18
19
OE5
Output Enable 5
When OE = high, Q5 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE5 contains an internal pull-up resistor.
CLK1
Input clock 1
22
Preliminary Rev. 0.4
Si53315
Table 18. Pin Description (Continued)
Input clock 1 (complement)
When CLK1 is driven by a single-ended input, connect V
CLK1 contains an internal pull-up resistor
20
21
CLK1
OE6
to CLK1.
REF
Output Enable 6
When OE = high, Q6 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE6 contains an internal pull-up resistor.
22
23
GND
OE9
Ground
Output Enable 9
When OE = high, the Output 9 outputs are enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE9 contains an internal pull-up resistor.
24
25
26
27
28
29
30
31
Q9
Q9
Output clock 9 (complement)
Output clock 9
Q8
Output clock 8 (complement)
Output clock 8
Q8
NC
Q7
No Connect
Output clock 7 (complement)
Output clock 7
Q7
OE8
Output Enable 8
When OE = high, Q8 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE8 contains an internal pull-up resistor.
32
33
SFOUT[1]
OE7
Output signal format control pin [1]
Three-level input control. Internally biased at V /2. Can be left floating or tied to
DD
ground or V
.
DD
Output Enable 7
When OE = high, Q7 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE7 contains an internal pull-up resistor.
34
35
V
Output voltage supply – Bank B (Outputs Q5 through Q9)
DDOB
Bypass with 1.0 µF capacitor and place as close to V
pin as possible.
DDOB
Q6
Output clock 6 (complement)
Preliminary Rev. 0.4
23
Si53315
Table 18. Pin Description (Continued)
Output clock 6
36
37
38
39
Q6
Q5
Output clock 5 (complement)
Output clock 5
Q5
CLK_SEL
MUX input select pin (LVCMOS)
When CLK_SEL is high, CLK1 is selected
When CLK_SEL is low, CLK0 is selected
CLK_SEL contains an internal pull-down resistor
40
41
42
43
44
Q4
Q4
Q3
Q3
Output clock 4 (complement)
Output clock 4
Output clock 3 (complement)
Output clock 3
V
Output voltage supply – Bank A (Outputs Q0 to Q4)
Bypass with 1.0 µF capacitor and place as close to V
DDOA
pin as possible.
DDOA
GND
Pad
GND
Ground Pad
Power supply ground and thermal relief
24
Preliminary Rev. 0.4
Si53315
4. Ordering Guide
Part Number
Package
PB-Free, ROHS-6
Temperature
–40 to 85 C
Si53315-B-GM
44-QFN
Yes
Preliminary Rev. 0.4
25
Si53315
5. Package Outline
5.1. 7x7 mm 44-QFN Package Diagram
Figure 12. Si53315 7x7 mm 44-QFN Package Diagram
Table 19. Package Diagram Dimensions
Dimension
MIN
0.80
0.00
0.18
NOM
0.85
MAX
0.90
0.05
0.30
A
A1
0.02
b
0.25
D
7.00 BSC
2.80
D2
e
2.65
2.95
0.50 BSC
7.00 BSC
2.80
E
E2
2.65
0.30
—
2.95
0.50
0.10
0.10
0.08
0.10
L
0.40
aaa
bbb
ccc
ddd
Notes:
—
—
—
—
—
—
—
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
26
Preliminary Rev. 0.4
Si53315
6. PCB Land Pattern
6.1. 7x7 mm 44-QFN Package Land Pattern
Figure 13. Si53315 7x7 mm 44-QFN Package Land Pattern
Table 20. PCB Land Pattern
Dimension
Min
6.80
6.80
Max
6.90
6.90
Dimension
Min
2.85
0.75
2.85
Max
2.95
0.85
2.95
C1
C2
E
X2
Y1
Y2
0.50 BSC
X1
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to
be 60 µm minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2x2 array of 1.0 mm square openings on 1.45 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Preliminary Rev. 0.4
27
Si53315
7. Top Marking
7.1. Si53315 Top Marking
ꢀ
7.2. Top Marking Explanation
Mark Method:
Font Size:
Laser
1.9 Point (26 mils)
Right-Justified
Line 1 Marking: Device Part Number
53315-B-GM
Line 2 Marking: YY = Year
Assigned by Assembly Supplier.
Corresponds to the year and work
week of the mold date.
WW = Work Week
TTTTTT = Mfg Code
Manufacturing Code from the
Assembly Purchase Order form.
Line 3 Marking: Circle = 1.3 mm Diameter
“e3” Pb-Free Symbol
Center-Justified
Country of Origin
TW
ISO Code Abbreviation
Line 4 Marking Circle = 0.75 mm Diameter Pin 1 Identification
Filled
28
Preliminary Rev. 0.4
Si53315
NOTES:
Preliminary Rev. 0.4
29
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相关型号：
SI53321-B-GM
Low Skew Clock Driver, 53321 Series, 20 True Output(s), 0 Inverted Output(s), CMOS, ROHS COMPLIANT, MO-220, QFN-32
SILICON
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