Si53326-B-GM [SILICON]
Output Enable option;
| 型号： | Si53326-B-GM |
| 厂家： | 
SILICON |
| 描述： | Output Enable option 驱动 逻辑集成电路 |
| 文件： | 总51页 (文件大小：1073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si53320-28 Data Sheet
Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVPECL
Outputs from Any-Format Input and Wide Frequency Range from
DC up to 1250 MHz
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 LVPECL Outputs
The Si53320–28 family of LVPECL fanout buffers is ideal for clock/data distribution and
redundant clocking applications. These devices feature typical ultra-low jitter character-
istics of 50 fs and operate over a wide frequency range from dc to 725/1250 MHz. Built-
in LDOs deliver high PSRR performance and reduce the need for external components,
simplifying low-jitter clock distribution in noisy environments.
• Any-format Inputs (LVPECL, Low-power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range: dc to 1250 MHz
• Output Enable option
The Si53320–28 family is available in multiple configurations, with some versions offer-
ing a selectable input clock using a 2:1 input mux. Other features include independent
output enable and built-in format translation. These buffers can be paired with the
Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance.
• Multiple configuration options
• Dual Bank option
• 2:1 Input Mux operation
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
VDD
VDD
Power Supply Filtering
Power Supply Filtering
4
4 Outputs
Si53323
Si53320
OEb
Si53322
2
2 Outputs
CLK
5
5 Outputs
0
1
CLK0*
VDDOA
OEAb
CLK1*
3 Outputs
3 Outputs
3
VDD
CLK_SEL
Si53327/28
Si53321/26
3
Power Supply Filtering
OEBb
VDDOB
5 Outputs
5 Outputs
CLK0
CLK1
5
5
Si53325
10 Outputs
10
*Si53326/28 require Single-ended Inputs
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Si53320-28 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si5332x Ordering Guide
Part Number
Input
LVPECL Output
Output Enable
Frequency Range
Package
2:1 selectable MUX
Any-format
Si53320-B-GT
1 bank / 5 Outputs
Single
dc to 725 MHz
20-TSSOP
2:1 selectable MUX
Any-format
32-QFN
5 x 5 mm
Si53321-B-GM
1 bank / 10 Outputs
1 bank / 10 Outputs
1 bank / 2 Outputs
1 bank / 4 Outputs
2 banks / 5 Outputs
2 banks / 5 Outputs
1 bank / 10 Outputs
2 banks / 3 Outputs
2 banks / 3 Outputs
—
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 200 MHz
dc to 1250 MHz
dc to 200 MHz
2:1 selectable MUX
Any-format
32-eLQFP
7 x 7 mm
Si53321-B-GQ
Si53322-B-GM
—
1 bank / 1 Input
Any-format
16-QFN
3 x 3 mm
—
2:1 selectable MUX
Any-format
16-QFN
3 x 3 mm
Si53323-B-GM
Si53325-B-GM
Si53325-B-GQ
Si53326-B-GM
Si53327-B-GM
Si53328-B-GM
—
2 banks / 2 Inputs
Any-format
32-QFN
5 x 5 mm
—
—
2 banks / 2 Inputs
Any-format
32-eLQFP
7 x 7 mm
2:1 selectable MUX
LVCMOS
32-QFN
5 x 5 mm
—
2:1 selectable MUX
Any-format
24-QFN
4 x 4 mm
1 per bank
1 per bank
2:1 selectable MUX
LVCMOS
24-QFN
4 x 4 mm
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Si53320-28 Data Sheet
Functional Description
2. Functional Description
The Si53320-28 are a family of low-jitter, low-skew, fixed-format (LVPECL) buffers. All devices except the Si53326 and Si53328 have a
universal input that accepts most common differential or LVCMOS input signals. The Si53326 and Si53328 accept only single-ended
LVCMOS inputs. These devices are available in multiple configurations customized for the end application (refer to 1. Ordering Guide
for more details on configurations).
2.1 Universal, Any-Format Input Termination (Si53320/21/22/23/25/27)
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL,
LVCMOS, LVDS, HCSL, and CML. The tables below summarize the various ac- and dc-coupling options supported by the device. For
the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks,
the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance.
Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats.
See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information.
Table 2.1. Clock Input Options
Clock Format
1.8 V
2.5/3.3 V
AC-Coupled
LVPECL/Low-power LVPECL
N/A
No
Yes
Yes
LVCMOS
LVDS
Yes
No
Yes
HCSL
CML
Yes (3.3 V)
Yes
Yes
DC-Coupled
LVPECL/Low-power LVPECL
N/A
No
No
No
No
Yes
Yes
LVCMOS
LVDS
Yes
HCSL
CML
Yes (3.3 V)
No
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Si53320-28 Data Sheet
Functional Description
VDD
0.1 µF
0.1 µF
Si53320/21/22/23/25/27
CLKx
100
CLKxb
Figure 2.1. Differential (HCSL, LVPECL, Low-Power LVPECL, LVDS, CML) AC-Coupled Input Termination
VDD
DC-Coupled
VDD
1 k
V
DD = 3.3 V or 2.5 V
Si53320/21/22/23/25/27
CLKx
CMOS
Driver
50
CLKxb
Rs
V
TERM = VDD/2
1 k
VDD
VDD
AC-Coupled
1 k
VDD
1 k
VBIAS = VDD/2
V
DD = 3.3 V or 2.5 V
Si53320/21/22/23/25/27
CLKx
CMOS
Driver
50
CLKxb
Rs
1 k
1 k
Note:
Value for Rs should be chosen so that the total
source impedance matches the characteristic
impedance of the PCB trace.
V
TERM = VDD/2
Figure 2.2. Single-Ended (LVCMOS) Input Termination
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Si53320-28 Data Sheet
Functional Description
VDD
DC Coupled LVPECL Input Termination Scheme 1
VDD
R1
R1
V
DD = 3.3 V or 2.5 V
Si53320/21/22/23/25/27
CLKx
CLKxb
50
50
“Standard”
LVPECL
Driver
VTERM = VDD – 2V
R1 // R2 = 50 Ohm
R2
R2
3.3 V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm
2.5 V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm
DC Coupled LVPECL Input Termination Scheme 2
VDD
V
DD = 3.3 V or 2.5 V
Si53320/21/22/23/25/27
50
50
CLKx
“Standard”
LVPECL
Driver
CLKxb
50
50
VTERM = VDD – 2 V
DC Coupled LVDS Input Termination
VDD
VDD
= 3.3 V or 2.5 V
Si53320/21/22/23/25/27
CLKx
50
50
Standard
LVDS
Driver
100
CLKxb
DC Coupled HCSL Input Termination Scheme
VDD
VDD
= 3.3 V
Si53320/21/22/23/25/27
33
33
50
50
CLKx
Standard
HCSL Driver
CLKxb
50
50
Note: 33 Ohm series termination is optional depending on the location of the receiver.
Figure 2.3. Differential DC-Coupled Input Terminations (Si53320/21/22/23/25/27)
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Si53320-28 Data Sheet
Functional Description
2.2 LVCMOS Input Termination (Si53326/28 Only)
The table below summarizes the various ac- and dc-coupling options supported by the LVCMOS device, and the figure shows the rec-
ommended input clock termination.
Note: 1.8 V LVCMOS inputs are not supported for Si53326/28.
Table 2.2. LVCMOS Input Clock Options
LVCMOS
AC-Coupled
DC-Coupled
1.8 V
No
No
2.5/3.3 V
Yes
Yes
VDD
DC-Coupled
V
DD = 3.3 V or 2.5 V
Si53326/28
CLKx
NC
CMOS
Driver
50
Rs
VDD
1 k
VDD
AC-Coupled
V
DD = 3.3 V or 2.5 V
Si53326/28
CLKx
NC
CMOS
Driver
50
Rs
1 k
VBIAS = VDD/2
Note:
Value for Rs should be chosen so that the total
source impedance matches the characteristic
impedance of the PCB trace.
Figure 2.4. Recommended Input Clock Termination (Si53326/28)
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Si53320-28 Data Sheet
Functional Description
2.3 Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting
input is biased with a 18.75 kΩ pull-down to GND and a 75 kΩ pull-up to VDD. The inverting input is biased with a 75 kΩ pull-up to VDD
.
VDD
RPU
RPU
+
CLK0 or
CLK1
RPD
–
RPU = 75 k
RPD = 18.75 k
Figure 2.5. Input Bias Resistors
Note: To minimize the possibility of system noise coupling into the Si5332x differential inputs and adversely affecting the buffered out-
put, Silicon Labs recommends 1 PPS clocks and disabled/gapped clocks be dc-coupled and driven “stop-low”.
2.4 Input Mux
The Si53320/21/23/26/27/28 provide two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The following table summarizes the input and output clock based on the input mux and
output enable pin settings.
Table 2.3. Input Mux Logic
Q1
L
CLK_SEL
CLK0
CLK1
Qb
L
L
L
H
X
X
X
X
L
H
L
H
L
H
H
H
L
H
H
Note:
1. On the next negative transition of CLK0 or CLK1.
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Si53320-28 Data Sheet
Functional Description
2.5 Output Clock Termination Options
The recommended output clock termination options for dc and ac are shown below. Unused outputs should be left unconnected.
DC Coupled LVPECL Output Termination Scheme 1
VDDO
R1
R1
VDDXX
VDD = VDDO
Si5332x
50
50
Q
LVPECL
Receiver
Qb
VTERM = VDDO – 2 V
R1 // R2 = 50 Ohm
R2
R2
3.3 V LVPECL: R1 = 127 Ohm; R2 = 82.5 Ohm
2.5 V LVPECL: R1 = 250 Ohm; R2 = 62.5 Ohm
DC Coupled LVPECL Output Termination Scheme 2
VDDXX
VDD = VDDO
Si5332x
50
50
Q
LVPECL
Receiver
Qb
50
50
VTERM = VDDO – 2 V
Note:
For Si53320/21/22/23/25/26, VDDXX = VDD = 3.3 V, 2.5 V
For Si53327/28, VDDXX = VDDOA or VDDOB = 3.3 V, 2.5 V
Figure 2.6. LVPECL DC Output Terminations
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Si53320-28 Data Sheet
Functional Description
AC Coupled LVPECL Output Termination Scheme 1
VDDO
R1
R1
VDDXX
0.1 uF
VDD = 3.3 V or 2.5 V
Si5332x
50
50
Q
LVPECL
Receiver
Qb
0.1 uF
VBIAS = VDD – 1.3 V
R1 // R2 = 50 Ohm
R2
R2
Rb
Rb
3.3 V LVPECL: R1 = 82.5 Ohm; R2 = 127 Ohm; Rb = 120 Ohm
2.5 V LVPECL: R1 = 62.5 Ohm; R2 = 250 Ohm; Rb = 90 Ohm
AC Coupled LVPECL Output Termination Scheme 2
VDDXX
0.1 uF
VDD = 3.3 V or 2.5 V
Si5332x
50
50
Q
LVPECL
Receiver
Qb
0.1 uF
50
50
Rb
Rb
VBIAS = VDD – 1.3 V
3.3 V LVPECL: Rb = 120 Ohm
2.5 V LVPECL: Rb = 90 Ohm
Note:
For Si53320/21/22/23/25/26, VDDXX = VDD = 3.3 V, 2.5 V
For Si53327/28, VDDXX = VDDOA or VDDOB = 3.3 V, 2.5 V
Figure 2.7. LVPECL AC Output Terminations
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Si53320-28 Data Sheet
Functional Description
2.6 AC Timing Waveforms
TPHL
TSK
VPP/2
VPP/2
CLK
Q
QN
QM
VPP/2
VPP/2
TPLH
TSK
Propagation Delay
Output-Output Skew
TF
80% VPP
20% VPP
Q
80% VPP
20% VPP
Q
TR
Rise/Fall Time
Figure 2.8. AC Timing Waveforms
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Si53320-28 Data Sheet
Functional Description
2.7 Typical Phase Noise Performance: Differential Input Clock
Each of the phase noise plots superimposes Source Jitter, Total SE Jitter, and Total Diff Jitter on the same diagram.
• Source Jitter—Reference clock phase noise (measured Single-ended to PNA).
• Total Jitter (SE)—Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer
and integrated from 12 kHz to 20 MHz.
• Total Jitter (Diff)—Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer
and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. For more infor-
mation, see 3. Electrical Specifications.
Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS).
Total jitter (Single-Ended)
measured here
AG E5052 Phase Noise
Analyzer
PSPL 5310A
Balun
PSPL 5310A
CLKx
CLK SYNTH
SMA103A
50
50
Si5332x
DUT
50 Ohm
CLKxb
Balun
Source jitter
measured here
Total jitter (Differential)
measured here
Figure 2.9. Differential Measurement Method Using a Balun
The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calcula-
ted (via root-sum-square addition).
Frequency
(MHz)
Differential
Input Slew Rate (V/ns)
Source Jitter Total Jitter
Additive Jitter
(SE) (fs)
Total Jitter
(Differential) (fs)
Additive Jitter
(Differential) (fs)
(fs)
(SE) (fs)
156.25
1.0
38.2
147.8
142.8
118.3
112.0
Figure 2.10. Total Jitter Differential Input (156.25 MHz)
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Si53320-28 Data Sheet
Functional Description
Frequency
(MHz)
Differential
Input Slew Rate (V/ns)
Source Jitter Total Jitter
Additive Jitter
(SE) (fs)
Total Jitter
(Differential) (fs)
Additive Jitter
(Differential) (fs)
(fs)
(SE) (fs)
312.5
1.0
33.10
94.39
88.39
83.80
76.99
Figure 2.11. Total Jitter Differential Input (312.5 MHz)
Frequency
(MHz)
Differential
Input Slew Rate (V/ns)
Source Jitter Total Jitter
Additive Jitter
(SE) (fs)
Total Jitter
(Differential) (fs)
Additive Jitter
(Differential) (fs)
(fs)
(SE) (fs)
625
1.0
23
57
52
59
54
Figure 2.12. Total Jitter Differential Input (625 MHz)
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Si53320-28 Data Sheet
Functional Description
2.8 Typical Phase Noise Performance: Single-Ended Input Clock
For single-ended input phase noise measurements, the input was connected directly without the use of a balun.
The following figure shows three phase noise plots superimposed on the same diagram.
Frequency
(MHz)
Single-Ended
Input Slew Rate (V/ns)
Source Jitter Total Jitter
Additive Jitter
(SE) (fs)
Total Jitter
(Differential) (fs)
Additive Jitter
(Differential) (fs)
(fs)
(SE) (fs)
156.25
1.0
40.74
182.12
177.51
125.22
118.41
Figure 2.13. Total Jitter Single-Ended Input (156.25 MHz)
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Si53320-28 Data Sheet
Functional Description
2.9 Input Mux Noise Isolation
The input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when
clocks are present at both the CLK0 and CLK1 inputs. The following figure shows a measurement of the input mux’s noise isolation.
Figure 2.14. Input Mux Noise Isolation (Differential Input Clock, 44-QFN Package)
Figure 2.15. Input Mux Noise Isolation (Single-Ended Input Clock, 24-QFN Package)
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Si53320-28 Data Sheet
Functional Description
2.10 Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject power supply noise and simplify low-jitter operation in real-world envi-
ronments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements.
See “AN491: Power Supply Rejection for Low-Jitter Clocks” for more information.
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Si53320-28 Data Sheet
Electrical Specifications
3. Electrical Specifications
Table 3.1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
–40
Typ
—
Max
85
Unit
°C
V
TA
Ambient Operating Temperature
2.38
2.97
2.5
3.3
2.63
3.63
VDD
Supply Voltage Range
LVPECL
V
Table 3.2. Input Clock Specifications
VDD = 2.5 V ± 5% or 3.3 V ± 10%; TA = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Differential Input Common
Mode Voltage
VCM
0.05
—
—
V
Differential Input Swing
(peak-to-peak)
VIN
0.2
—
2.2
V
VIH
VIL
VDD x 0.7
—
LVCMOS Input High Voltage
LVCMOS Input Low Voltage
—
—
—
V
V
VDD x 0.3
CLK0 and CLK1 pins with re-
spect to GND
CIN
Input Capacitance
—
5
—
pF
Table 3.3. DC Common Characteristics
VDD = 2.5 V ± 5% or 3.3 V ± 10%; TA = –40 to 85 °C
Parameter
Symbol
Test Condition
Si53320
Min
—
Typ
260
440
130
210
80
Max
—
Unit
mA
mA
mA
mA
mA
mA
Si53321/25/26
Si53322
—
—
1
Core Supply Current
IDD
—
—
Si53323
—
—
Si53327/28
Si53327/28
—
—
1
Output Supply Current
(Per Clock Output)
—
35
—
IDDOx
VIH
VIL
V
DD x 0.8
Input High Voltage
Input Low Voltage
CLK_SEL, OExb
CLK_SEL, OExb
CLK_SEL, OExb
—
—
25
—
VDD x 0.2
—
V
V
—
—
RDOWN
Internal Pull-down Resistor
kΩ
Note:
1. Measured using ac-coupled termination at VDD/VDDOX = 3.3 V.
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Si53320-28 Data Sheet
Electrical Specifications
Table 3.4. Output Characteristics (LVPECL)
VDD = 2.5 V ± 5% or 3.3 V ± 10%; TA = –40 to 85 °C
Parameter
Symbol
VSE
Test Condition
Min
0.55
Typ
0.80
—
Max
1.05
Unit
V
Single-Ended Output Swing1
Output Common Mode Voltage
Note:
VCOM
VDD – 1.595
VDD – 1.245
V
1. Unused outputs can be left floating. Do not short unused outputs to ground.
Table 3.5. AC Characteristics
VDD = 2.5 V ± 5% or 3.3 V ± 10%; TA = –40 to 85 °C
Parameter
Symbol
Test Condition
Si53326/28
Min
dc
Typ
Max
200
Unit
MHz
MHz
MHz
—
—
—
Frequency
F
Si53320
dc
725
Si53321/22/23/25/27
dc
1250
20/80% TR/TF<10% of period
(Differential input clock)
47
45
50
50
53
55
%
%
Duty Cycle
(50% input duty cycle)
DC
20/80% TR/TF<10% of period
(Single-Ended input clock)
SRdiff
SRse
Required to meet prop delay
and additive jitter specifications
(20–80%)
0.75
1.00
—
—
—
—
V/ns
V/ns
Minimum Input Clock Slew Rate
TR/TF
TW
Output Rise/Fall Time
Minimum Input Pulse Width
Propagation Delay
20–80%
—
360
600
—
—
—
350
—
ps
ps
ps
ps
TPLH, TPHL
TSK
800
25
1000
60
Output-to-Output Skew1
Part-to-Part Skew2
TPS
—
—
—
—
—
—
–65
150
—
ps
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
dBc
dBc
dBc
dBc
–62.5
–60
—
Power Supply Noise Rejection3
PSRR
—
–55
—
Note:
1. Output-to-output skew specified for outputs with identical configuration.
2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load con-
dition. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDD (3.3 V = 100 mVPP) and noise spur amplitude meas-
ured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for more information.
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Si53320-28 Data Sheet
Electrical Specifications
Table 3.6. Additive Jitter, Differential Clock Input
Additive Jitter (fs rms, 12
kHz to 20 MHz)3
Input1, 2
Amplitude VIN
(Single-Ended,
Peak-to-Peak)
Output
VDD
Differential 20% to
80% Slew Rate
(V/ns)
Freq (MHz)
Clock Format
Clock Format
Typ
Max
3.3
3.3
725
156.25
725
Differential
Differential
Differential
Differential
0.15
0.5
0.637
0.458
0.637
0.458
LVPECL
LVPECL
LVPECL
LVPECL
45
160
45
95
185
95
2.5
0.15
0.5
2.5
156.25
145
185
Note:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Addi-
tive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 2.9 Differential Measurement Method Using a
Balun on page 10.
Table 3.7. Additive Jitter, Single-Ended Clock Input
Additive Jitter (fs rms, 12
kHz to 20 MHz)3
Input1, 2
Amplitude VIN
Output
VDD
Single-Ended 20%
Freq (MHz)
Clock Format
to 80% Slew Rate Clock Format
(V/ns)
Typ
Max
(Single-Ended,
Peak-to-Peak)
3.3
2.5
156.25
156.25
Single-ended
Single-ended
2.18
2.18
1
1
LVPECL
LVPECL
160
145
185
185
Note:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Addi-
tive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 2.9 Differential Measurement Method Using a
Balun on page 10.
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Si53320-28 Data Sheet
Electrical Specifications
Table 3.8. Thermal Conditions
Symbol
Parameter
Test Condition
Still air
Value
57.6
41.5
93.88
37
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
16-QFN Thermal Resistance, Junction to Ambient
16-QFN Thermal Resistance, Junction to Case
20-TSSOP Thermal Resistance, Junction to Ambient
24-QFN Thermal Resistance, Junction to Ambient
24-QFN Thermal Resistance, Junction to Case
32-eLQFP Thermal Resistance, Junction to Ambient
32-eLQFP Thermal Resistance, Junction to Case
32-QFN Thermal Resistance, Junction to Ambient
32-QFN Thermal Resistance, Junction to Case
θJA
θJC
θJA
θJA
θJC
θJA
θJC
θJA
θJC
Still air
Still air
Still air
Still air
25
Still air
54.9
Still air
Still air
Still air
10.0
99.6
10.3
°C/W
°C/W
°C/W
Table 3.9. Absolute Maximum Ratings1
Parameter
Storage Temperature
Supply Voltage
Input Voltage
Symbol
TS
Test Condition
Min
–55
–0.5
–0.5
—
Typ
—
Max
Unit
°C
V
150
3.8
VDD
—
VIN
VDD + 0.3
VDD + 0.3
2000
—
V
VOUT
HBM
CDM
Output Voltage
—
V
HBM, 100 pF, 1.5 kΩ
—
—
V
ESD Sensitivity
—
—
500
V
Peak Soldering Reflow
Temperature
Pb-Free; Solder reflow profile
per JEDEC J-STD-020
TPEAK
—
—
—
—
260
125
°C
°C
Maximum Junction
Temperature
TJ
Note:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compli-
ance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability.
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Si53320-28 Data Sheet
Detailed Block Diagrams
4. Detailed Block Diagrams
VDD
Power Supply
Filtering
Q0
Q0b
Q1
CLK0
0
1
Q1b
Q2
CLK0b
Q2b
Q3
CLK1
CLK1b
Q3b
Q4
Q4b
Switching
Logic
CLK_SEL
OEb
Si53320 - 20-TSSOP
Figure 4.1. Si53320 Block Diagram
VDD
Q0
Power Supply
Filtering
Q0b
Q1
Q1b
Q2
Q2b
Q3
Q3b
Q4
CLK0
0
1
CLK0b
Q4b
Q5
CLK1
Q5b
Q6
CLK1b
Q6b
Q7
Switching
Logic
CLK_SEL
Q7b
Q8
Q8b
Q9
Q9b
Si53321
32-QFN (5x5 mm)
32-eLQFP (7x7 mm)
Figure 4.2. Si53321 Block Diagram
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Si53320-28 Data Sheet
Detailed Block Diagrams
VDD
Power Supply
Filtering
Q0
Q0b
Q1
CLK0
CLK0b
Q1b
Si53322 - 16-QFN (3x3 mm)
Figure 4.3. Si53322 Block Diagram
VDD
Power Supply
Filtering
Q0
Q0b
CLK0
0
1
Q1
CLK0b
Q1b
CLK1
Q2
CLK1b
Q2b
Q3
Switching
Logic
Q3b
CLK_SEL
Si53323 - 16-QFN (3x3 mm)
Figure 4.4. Si53323 Block Diagram
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Si53320-28 Data Sheet
Detailed Block Diagrams
VDD
Q0
Q0b
Q1
Power Supply
Filtering
Q1b
Q2
CLK0
CLK0b
Q2b
Q3
Q3b
Q4
Q4b
Q5
Q5b
Q6
Q6b
Q7
CLK1
CLK1b
Q7b
Q8
Q8b
Q9
Q9b
Si53325
32-QFN (5x5mm)
32-eLQFP (7x7mm)
Figure 4.5. Si53325 Block Diagram
VDD
Q0
Q0b
Q1
Power Supply
Filtering
Q1b
Q2
Q2b
Q3
Q3b
Q4
CLK0
0
1
Q4b
Q5
Q5b
Q6
CLK1
Q6b
Q7
Switching
Logic
CLK_SEL
Q7b
Q8
Q8b
Q9
Q9b
Si53326 - 32-QFN (5x5 mm)
Figure 4.6. Si53326 Block Diagram
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Si53320-28 Data Sheet
Detailed Block Diagrams
VDD
VDDOA
OEAb
Q0
Power Supply
Filtering
Q0b
Q1
Q1b
CLK0
0
1
Q2
CLK0b
Q2b
Q3
CLK1
CLK1b
Q3b
Q4
Switching
Logic
Q4b
Q5
CLK_SEL
Q5b
OEBb
VDDOB
Si53327 - 24-QFN (4x4 mm)
Figure 4.7. Si53327 Block Diagram
VDD
VDDOA
OEAb
Q0
Power Supply
Filtering
Q0b
Q1
Q1b
CLK0
CLK1
0
1
Q2
Q2b
Q3
Q3b
Q4
Switching
Logic
Q4b
Q5
CLK_SEL
Q5b
OEBb
VDDOB
Si53328 - 24-QFN (4x4 mm)
Figure 4.8. Si53328 Block Diagram
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Si53320-28 Data Sheet
Pin Descriptions
5. Pin Descriptions
5.1 Si53320 Pin Descriptions
1
2
3
4
5
6
7
8
9
20 VDD
19 OEb
18 VDD
17 CLK1b
16 CLK1
15 NC
Q0
Q0b
Q1
Q1b
Q2
Q2b
Q3
14 CLK0b
13 CLK0
12 CLK_SEL
11 GND
Q3b
Q4
Q4b 10
Si53320
20-TSSOP
Table 5.1. Si53320 20-Pin TSSOP Descriptions
Type1
O
Pin #
Name
Q0
Description
1
2
Output clock 0.
Q0b
Q1
O
Output clock 0 (complement).
Output clock 1.
3
O
4
Q1b
Q2
O
Output clock 1 (complement).
Output clock 2.
5
O
6
Q2b
Q3
O
Output clock 2 (complement).
Output clock 3.
7
O
8
Q3b
Q4
O
Output clock 3 (complement).
Output clock 4.
9
O
10
11
Q4b
GND
O
Output clock 4 (complement).
Ground.
GND
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
12
13
14
CLK_SEL
CLK0
I
I
I
Input clock 0.
Input clock 0 (complement). When CLK0 is driven by a single-ended input, connect
CLK0b to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2).
CLK0b
15
16
NC
—
I
No connect. Leave this pin unconnected.
Input clock 1.
CLK1
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Si53320-28 Data Sheet
Pin Descriptions
Type1
Pin #
Name
Description
Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect
CLK1b to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2).
17
CLK1b
I
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
18
19
20
VDD
OEb
VDD
P
I
Output enable. When OEb = low, the clock outputs are enabled. When OEb = high, Qx is
held low and Qxb is held high. OEb features an internal pull-down resistor and may be
left unconnected.
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
P
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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Si53320-28 Data Sheet
Pin Descriptions
5.2 Si53321 and Si53326 Pin Descriptions
24 Q3
23 Q3b
22 Q4
21 Q4b
20 Q5
19 Q5b
18 Q6
17 Q6b
VDD
CLK_SEL
CLK0
1
2
3
4
5
6
7
8
24 Q3
23 Q3b
22 Q4
21 Q4b
20 Q5
19 Q5b
18 Q6
17 Q6b
VDD
CLK_SEL
CLK0
1
2
3
4
5
6
7
8
CLK0b
NC
CLK0b
NC
GND
PAD
GND
PAD
CLK1
CLK1
CLK1b
GND
CLK1b
GND
Si53321
32-eLQFP
Si53321
32-QFN
24 Q3
23 Q3b
22 Q4
21 Q4b
20 Q5
19 Q5b
18 Q6
17 Q6b
VDD
CLK_SEL
CLK0
NC
1
2
3
4
5
6
7
8
GND
PAD
NC
CLK1
NC
Si53326
32-QFN
GND
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Si53320-28 Data Sheet
Pin Descriptions
Table 5.2. Si53321 32-QFN/32-eLQFP and Si53326 32-QFN Pin Descriptions
Type1
Pin #
Name
Description
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
1
VDD
P
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
2
3
CLK_SEL
CLK0
I
I
I
Input clock 0.
Input clock 0 (complement). When CLK0 is driven by a single-ended LVCMOS input,
connect CLK0b to an appropriate bias voltage (e.g. VDD/2).
CLK0b
(Si53321 only)
4
NC
—
No connect. Leave this pin unconnected.
(Si53326 only)
5
6
NC
No connect. Leave this pin unconnected.
Input clock 1.
CLK1
I
I
Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect
CLK1b to VDD/2.
CLK1b
(Si53321 only)
7
NC
—
GND
P
No connect. Leave this pin unconnected.
Ground.
(Si53326 only)
8
9
GND
VDD
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
10
11
12
13
14
15
Q9b
Q9
O
O
O
O
O
O
Output clock 9 (complement).
Output clock 9.
Q8b
Q8
Output clock 8 (complement).
Output clock 8.
Q7b
Q7
Output clock 7 (complement).
Output clock 7.
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
16
VDD
P
17
18
19
20
21
22
23
24
Q6b
Q6
O
O
O
O
O
O
O
O
Output clock 6 (complement).
Output clock 6.
Q5b
Q5
Output clock 5 (complement).
Output clock 5.
Q4b
Q4
Output clock 4 (complement).
Output clock 4.
Q3b
Q3
Output clock 3 (complement).
Output clock 3.
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
25
26
VDD
Q2b
P
O
Output clock 2 (complement).
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Si53320-28 Data Sheet
Pin Descriptions
Type1
Pin #
27
Name
Q2
Description
O
O
O
O
O
Output clock 2.
28
Q1b
Q1
Output clock 1 (complement).
Output clock 1.
29
30
Q0b
Q0
Output clock 0 (complement).
Output clock 0.
31
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
32
VDD
P
Power supply ground and thermal relief. The exposed ground pad is thermally connected
to the die to improve the heat transfer out of the package. The ground pad must be con-
nected to GND to ensure device specifications are met.
Exposed
ground pad
GND Pad
GND
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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Si53320-28 Data Sheet
Pin Descriptions
5.3 Si53322 Pin Descriptions
Q1b
Q1
GND
NC
1
2
3
4
12
11
10
9
GND
PAD
NC
Q0b
Q0
Si53322
16-QFN
NC
Table 5.3. Si53322 16-QFN Pin Descriptions
Type1
GND
—
Pin
1
Name
GND
NC
Description
Ground.
2
No connect. Leave this pin unconnected.
No connect. Leave this pin unconnected.
No connect. Leave this pin unconnected.
3
NC
—
4
NC
—
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
5
6
7
VDD
CLK
P
I
Input Clock
Input clock (complement). When CLK is driven by a single-ended LVCMOS input, con-
nect CLKb to an appropriate bias voltage (e.g. VDD/2).
CLKb
I
8
NC
Q0
—
O
No connect. Leave this pin unconnected.
Output Clock 0.
9
10
11
12
13
14
15
16
Q0b
Q1
O
Output Clock 0 (complement).
Output Clock 1.
O
Q1b
NC
NC
NC
NC
O
Output Clock 1 (complement).
No connect. Leave this pin unconnected.
No connect. Leave this pin unconnected.
No connect. Leave this pin unconnected.
No connect. Leave this pin unconnected.
—
—
—
—
Power supply ground and thermal relief. The exposed ground pad is thermally connected
to the die to improve the heat transfer out of the package. The ground pad must be con-
nected to GND to ensure device specifications are met.
Exposed
ground pad
GND Pad
GND
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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Si53320-28 Data Sheet
Pin Descriptions
5.4 Si53323 Pin Descriptions
Q1b
Q1
GND
CLK_SEL
CLK1
1
2
3
4
12
11
10
9
GND
PAD
Q0b
Q0
Si53323
16-QFN
CLK1b
Table 5.4. Si53323 16-QFN Pin Descriptions
Type1
Pin
Name
Description
1
GND
GND
Ground.
Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When
CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
2
3
4
CLK_SEL
CLK1
I
I
I
Input clock 1.
Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect
CLK1b to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2).
CLK1b
Core and Output Voltage Supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
5
6
7
VDD
CLK0
CLK0b
P
I
Input Clock 0.
Input Clock 0 (complement). When CLK0 is driven by a single-ended input, connect
CLK0b to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2).
I
8
NC
Q0
—
O
O
O
O
O
O
O
O
No connect. Leave this pin unconnected.
Output Clock 0.
9
10
11
12
13
14
15
16
Q0b
Q1
Output Clock 0 (complement).
Output Clock 1.
Q1b
Q2
Output Clock 1 (complement).
Output Clock 2.
Q2b
Q3
Output Clock 2 (complement).
Output Clock 3.
Q3b
Output Clock 3 (complement).
Power supply ground and thermal relief. The exposed ground pad is thermally connected
to the die to improve the heat transfer out of the package. The ground pad must be con-
nected to GND to ensure device specifications are met.
Exposed
ground pad
GND Pad
GND
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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Si53320-28 Data Sheet
Pin Descriptions
5.5 Si53325 Pin Descriptions
24 Q3
24 Q3
23 Q3b
22 Q4
21 Q4b
20 Q5
19 Q5b
18 Q6
17 Q6b
VDD
NC
1
2
3
4
5
6
7
8
VDD
NC
1
2
3
4
5
6
7
8
23 Q3b
22 Q4
21 Q4b
20 Q5
19 Q5b
18 Q6
17 Q6b
CLK0
CLK0b
NC
CLK0
CLK0b
NC
GND
PAD
GND
PAD
CLK1
CLK1b
GND
CLK1
CLK1b
GND
Si53325
32-eLQFP
Si53325
32-QFN
Table 5.5. Si53325 32-QFN and 32-eLQFP Pin Descriptions
Name1
Pin #
Type
Description
Core and Output voltage supply.
Bypass with 1.0 µF capacitor and place as close to the VDD pin as possible.
1
VDD
P
2
3
4
5
6
7
8
NC
CLK0
CLK0b
NC
—
No connect. Leave this pin unconnected.
Input clock 0.
I
I
Input clock 0 (complement).
No connect. Leave this pin unconnected.
Input clock 1.
—
CLK1
CLK1b
GND
I
I
Input clock 1 (complement).
Ground.
GND
Core voltage supply. Bypass with 1.0 µF capacitor and place as close to the VDD pin as
possible.
9
VDD
P
10
11
12
13
14
15
Q9b
Q9
O
O
O
O
O
O
Output clock 9 (complement).
Output clock 9.
Q8b
Q8
Output clock 8 (complement).
Output clock 8.
Q7b
Q7
Output clock 7 (complement).
Output clock 7.
Core voltage supply. Bypass with 1.0 µF capacitor and place as close to the VDD pin as
possible.
16
VDD
P
17
18
19
20
Q6b
Q6
O
O
O
O
Output clock 6 (complement).
Output clock 6.
Q5b
Q5
Output clock 5 (complement).
Output clock 5.
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Si53320-28 Data Sheet
Pin Descriptions
Name1
Q4b
Q4
Pin #
21
Type
O
Description
Output clock 4 (complement).
Output clock 4.
22
O
23
Q3b
Q3
O
Output clock 3 (complement).
Output clock 3.
24
O
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
25
VDD
P
26
27
28
29
30
31
Q2b
Q2
O
O
O
O
O
O
Output clock 2 (complement).
Output clock 2.
Q1b
Q1
Output clock 1 (complement).
Output clock 1.
Q0b
Q0
Output clock 0 (complement).
Output clock 0.
Core and Output voltage supply. Bypass with 1.0 µF capacitor and place as close to the
VDD pin as possible.
32
VDD
P
Power supply ground and thermal relief. The exposed ground pad is thermally connected
to the die to improve the heat transfer out of the package. The ground pad must be con-
nected to GND to ensure device specifications are met.
Exposed
ground pad
GND Pad
GND
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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Si53320-28 Data Sheet
Pin Descriptions
5.6 Si53327 and Si53328 Pin Descriptions
OEAb
1
OEAb
Q1b
Q1
18
17 Q4
1
2
3
4
5
6
18
17 Q4
OEBb
OEBb
Q1b
Q1
2
3
4
5
6
Q4b
Q4b
16
15
14
13
16
15
14
13
GND
PAD
GND
PAD
Q5
Q5
Q0b
Q0
Q0b
Q0
Q5b
Q5b
Si53327
24-QFN
Si53328
24-QFN
VDD
VDD
CLK_SEL
CLK_SEL
Table 5.6. Si53327 and Si53328 24-QFN Pin Descriptions
Type1
Pin
Name
Description
Output Enable for Bank A (Q0, Q1, Q2). When OEAb = LOW, outputs Q0, Q1, and Q2
are enabled. This pin contains an active pull-down resistor, and leaving the pin discon-
nected enables the outputs. When OEAb = HIGH, Q0, Q1, and Q2 are disabled.
1
OEAb
I
2
3
4
5
Q1b
Q1
O
O
O
O
Output clock 1 (Complement).
Output clock 1.
Q0b
Q0
Output clock 0 (complement).
Output clock 0.
Core voltage supply. Bypass with 1.0 μF capacitor and place as close to the VDD pin as
possible.
6
7
VDD
P
I
Input clock 0. Bypass with 1.0 µF capacitor and place as close to the VDD pin as possi-
ble.
CLK0
Input clock 0 (complement). When CLK0 is driven by a single-ended input, connect
CLK0b to VDD/2.
CLK0b
(Si53327 only)
O
—
8
NC
No connect. Leave this pin unconnected.
(Si53328 only)
9
NC
NC
—
—
I
No connect. Leave this pin unconnected.
No connect. Leave this pin unconnected.
Input clock 1.
10
11
CLK1
CLK1b
(Si53327 only)
Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect
CLK1b to VDD/2.
I
—
I
12
NC
No connect. Leave this pin unconnected.
(Si53328 only)
Mux input select pin. When CLK_SEL=HIGH, CLK1 is selected. When CLK_SEL=LOW,
CLK0 is selected. CLK_SEL contains an internal pull-down resistor.
13
CLK_SEL
14
15
Q5b
Q5
O
O
Output clock 5 (complement).
Output clock 5.
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Si53320-28 Data Sheet
Pin Descriptions
Type1
Pin
16
Name
Q4b
Q4
Description
O
O
Output clock 4 (complement).
Output clock 4.
17
Output Enable for Bank B (Q3, Q4, Q5). When OEBb = LOW, outputs Q3, Q4, and Q5
are enabled. This pin contains an active pull-down resistor, and leaving the pin discon-
nected enables the outputs. When OEBb = HIGH, Q3, Q4, and Q5 are disabled.
18
19
OEBb
I
Output voltage supply—Bank B (Outputs: Q3 to Q5). Bypass with 1.0 µF capacitor and
place as close to the VDDOB pin as possible.
VDDOB
P
20
21
22
23
Q3b
Q3
O
O
O
O
Output clock 3 (complement).
Output clock 3.
Q2b
Q2
Output clock 2 (complement).
Output clock 2.
Output voltage supply—Bank A (Outputs: Q0 to Q2). Bypass with 1.0 μF capacitor and
place as close to the VDDOA pin as possible.
24
VDDOA
P
Ground Pad—Power supply ground and thermal relief. The exposed ground pad is ther-
mally connected to the die to improve the heat transfer out of the package. The ground
pad must be connected to GND to ensure device specifications are met.
Exposed
ground pad
GND Pad
GND
Note:
1. I = Input; O = Output; P = Power; GND = Ground.
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Rev. 1.2 | 33
Si53320-28 Data Sheet
Package Outlines
6. Package Outlines
6.1 16-Pin QFN Package
Figure 6.1. 16-Pin QFN Package
Table 6.1. 16-QFN Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
A
A1
0.02
b
0.25
D
3.00 BSC.
1.70
D2
1.65
1.75
e
0.50 BSC.
3.00 BSC.
1.70
E
E2
1.65
0.30
—
1.75
0.50
0.10
0.10
0.08
0.10
0.05
L
0.40
aaa
—
bbb
—
—
ccc
—
—
ddd
—
—
eee
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Si53320-28 Data Sheet
Package Outlines
6.2 20-Pin TSSOP Package
Figure 6.2. 20-Pin TSSOP Package
Table 6.2. 20-TSSOP Package Dimensions
Dimension
Min
—
Nom
—
Max
1.20
0.15
1.05
0.30
0.20
6.60
Dimension
Min
0.45
0°
Nom
Max
0.75
8°
A
e
L
0.65 BSC
0.60
A1
0.05
0.80
0.19
0.09
6.40
—
A2
1.00
—
L2
q
0.25 BSC
—
b
c
D
—
aaa
bbb
ccc
0.10
6.50
6.40 BSC
4.40
0.10
E
0.20
E1
4.30
4.50
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si53320-28 Data Sheet
Package Outlines
6.3 24-Pin QFN Package
Figure 6.3. 24-Pin QFN Package
Table 6.3. 24-QFN Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
A
A1
0.02
b
0.25
D
4.00 BSC.
2.50
D2
2.35
2.65
e
0.50 BSC.
4.00 BSC.
2.50
E
E2
2.35
0.30
2.65
0.50
L
0.40
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.05
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Si53320-28 Data Sheet
Package Outlines
6.4 32-Pin QFN Package
Figure 6.4. 32-Pin QFN Package
Table 6.4. 32-QFN Package Dimensions
Dimension
Min
0.80
0.00
0.18
0.20
Nom
0.85
Max
1.00
0.05
0.30
0.30
A
A1
0.02
b
0.25
c
0.25
D
5.00 BSC
2.15
D2
2.00
2.30
e
0.50 BSC
5.00 BSC
2.15
E
E2
2.00
0.30
2.30
0.50
L
0.40
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
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Si53320-28 Data Sheet
Package Outlines
6.5 32-Pin eLQFP Package
Figure 6.5. 32-Pin eLQFP Package
Table 6.5. 32-eLQFP Package Dimensions
Dimension
Min
—
Nom
—
Max
1.60
0.15
1.45
0.45
0.20
Dimension
Min
Nom
Max
A
E1
E2
7.00 BSC
1.92
A1
0.05
1.35
0.30
0.09
—
1.87
0.45
0°
1.97
0.75
7°
A2
1.40
L
0.60
b
0.37
θ
3.5°
c
—
aaa
bb
0.20
D
D1
9.00 BSC
7.00 BSC
1.92
0.20
0.10
ccc
dddd
eee
D2
1.87
1.97
0.20
e
0.80 BSC
9.00 BSC
0.05
E
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC MS-026.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si53320-28 Data Sheet
Land Patterns
7. Land Patterns
7.1 16-Pin QFN Land Pattern
Figure 7.1. 16-Pin QFN Land Pattern
Table 7.1. 16-QFN Land Pattern Dimensions
Dimension
mm
3.00
3.00
0.50
0.30
0.80
1.75
1.75
C1
C2
E
X1
Y1
X2
Y2
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-
cation Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2 x 2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.2 | 39
Si53320-28 Data Sheet
Land Patterns
7.2 20-Pin TSSOP Land Pattern
Figure 7.2. 20-Pin TSSOP Land Pattern
Table 7.2. 20-TSSOP Land Pattern Dimensions
Dimensions
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
C1
5.80
0.65
0.45
1.40
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 specifications for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.2 | 40
Si53320-28 Data Sheet
Land Patterns
7.3 24-Pin QFN Land Pattern
Figure 7.3. 24-Pin QFN Land Pattern
Table 7.3. 24-QFN Land Pattern Dimensions
Dimension
mm
2.55
2.55
0.25
0.80
3.90
3.90
0.50
P1
P2
X1
Y1
C1
C2
E
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2 x 2 array of 1.10 mm x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.2 | 41
Si53320-28 Data Sheet
Land Patterns
7.4 32-Pin QFN Land Pattern
Figure 7.4. 32-Pin QFN Land Pattern
Table 7.4. 32-QFN Land Pattern Dimensions
Dimension
Min
4.52
4.52
Max
4.62
4.62
Dimension
Min
2.20
0.59
2.20
Max
2.30
0.69
2.30
C1
C2
E
X2
Y1
Y2
0.50 BSC
X1
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 2 x 2 array of 0.75 mm square openings on 1.15 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si53320-28 Data Sheet
Land Patterns
7.5 32-Pin eLQFP Land Pattern
Figure 7.5. 32-Pin eLQFP Land Pattern
Table 7.5. 32-eLQFP Land Pattern Dimensions
Dimension
Min
8.40
8.40
1.84
1.84
Max
C1
8.50
8.50
2.00
2.00
C2
D1
D2
E
0.80 BSC
X1
0.40
1.25
0.50
1.35
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A single 1.5 x 1.5 mm stencil aperture should be used for the center ground pad to achieve between 50-60% solder coverage.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.2 | 43
Si53320-28 Data Sheet
Top Markings
8. Top Markings
8.1 Si53320 Top Marking
Figure 8.1. Si53320 Top Marking
Table 8.1. Si53320 Top Marking Explanation
Mark Method:
Font Size:
Laser
2.0 Point (0.71 mm)
Right-Justified
Line 1 Marking:
Line 2 Marking:
Line 3 Marking:
Customer Part Number
TTTTTT = Mfg Code
Si53320
Manufacturing Code from Assembly Purchase Order form.
“e3” Pb-Free Symbol
Circle = 1.2 mm Diameter
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to year and work week of
the build date.
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Rev. 1.2 | 44
Si53320-28 Data Sheet
Top Markings
8.2 Si53321/25/26 Top Markings
Figure 8.4. Si53326 Top Marking
Figure 8.2. Si53321 Top Marking
Figure 8.3. Si53325 Top Marking
Table 8.2. Si53321/25/26 Top Marking Explanation
Mark Method:
Font Size:
Laser
2.0 Point (28 mils)
Center-Justified
Line 1 Marking:
Device Part Number
53321 for Si53321
53325 for Si53325
53326 for Si53326
Line 2 Marking:
Line 3 Marking:
Line 4 Marking
Device Revision/Type
TTTTTT = Mfg Code
B-GM for Si53321 and Si53325. Blank for Si53326.
Manufacturing Code from the Assembly Purchase Order form.
Pin 1 Identifier
Circle = 0.50 mm Diameter
Lower-Left Justified
YY = Year
Corresponds to the year and work week of the mold date.
WW = Work Week
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Si53320-28 Data Sheet
Top Markings
8.3 Si53322/23 Top Markings
Figure 8.5. Si53322 Top Marking
Figure 8.6. Si53323 Top Marking
Table 8.3. Si53322/23 Top Marking Explanation
Mark Method:
Font Size:
Laser
0.635 mm (25 mils)
Right-Justified
Line 1 Marking:
Product ID
3322 for Si53322
3323 for Si53323
Manufacturing Code
Pin 1 Identifier
Line 2 Marking:
Line 3 Marking
TTTT = Mfg Code
Circle = 0.5 mm Diameter
Bottom-Left Justified
YWW = Date Code
Corresponds to the last digit of the current year (Y) and the workweek (WW)
of the mold date.
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Si53320-28 Data Sheet
Top Markings
8.4 Si53327/28 Top Markings
Figure 8.7. Si53327 Top Marking
Figure 8.8. Si53328 Top Marking
Table 8.4. Si53327/28 Top Marking Explanation
Mark Method:
Font Size:
Laser
2.0 Point (28 mils)
Center-Justified
Line 1 Marking:
Device Part Number
53327 for Si53327
53328 for Si53328
B-GM
Line 2 Marking:
Line 3 Marking:
Line 4 Marking:
Device Revision/Type
TTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase Order form.
Pin 1 Identifier
Circle = 0.5 mm Diameter
Lower-Left Justified
YY = year
WW = Work Week
Assigned by the Assembly House. Corresponds to the year and work week
of the mold date.
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Rev. 1.2 | 47
Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Universal, Any-Format Input Termination (Si53320/21/22/23/25/27) . . . . . . . . . . . . 2
2.2 LVCMOS Input Termination (Si53326/28 Only). . . . . . . . . . . . . . . . . . . 5
2.3 Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Input Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . 7
2.6 AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 Typical Phase Noise Performance: Differential Input Clock. . . . . . . . . . . . . . .10
2.8 Typical Phase Noise Performance: Single-Ended Input Clock . . . . . . . . . . . . . .12
2.9 Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.10 Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . .14
3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Si53320 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.2 Si53321 and Si53326 Pin Descriptions . . . . . . . . . . . . . . . . . . . . .25
5.3 Si53322 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.4 Si53323 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.5 Si53325 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.6 Si53327 and Si53328 Pin Descriptions . . . . . . . . . . . . . . . . . . . . .32
6. Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 16-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.2 20-Pin TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . .35
6.3 24-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6.4 32-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.5 32-Pin eLQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . .38
7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 16-Pin QFN Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.2 20-Pin TSSOP Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .40
7.3 24-Pin QFN Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . .41
7.4 32-Pin QFN Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . .42
7.5 32-Pin eLQFP Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .43
8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table of Contents 48
8.1 Si53320 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . .44
8.2 Si53321/25/26 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . .45
8.3 Si53322/23 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . .46
8.4 Si53327/28 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table of Contents 49
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parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
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