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SI5341A-B04430-GMR [SILICON]

Processor Specific Clock Generator,;
SI5341A-B04430-GMR
型号： SI5341A-B04430-GMR
厂家： SILICON    SILICON
描述：

Processor Specific Clock Generator,

时钟 控制器 微控制器 微控制器和处理器 时钟发生器
文件： 总53页 (文件大小：5459K)
中文：  中文翻译
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Si5341/40 Rev D Data Sheet  
Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock  
Generator  
KEY FEATURES  
• Generates any combination of output  
frequencies from any input frequency  
The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL  
with proprietary MultiSynth™ fractional synthesizer technology to offer a versatile and  
high performance clock generator platform. This highly flexible architecture is capable  
of synthesizing a wide range of integer and non-integer related frequencies up to 1  
GHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter per-  
formance with 0 ppm error. Each of the clock outputs can be assigned its own format  
and output voltage enabling the Si5341/40 to replace multiple clock ICs and oscillators  
with a single device making it a true "clock tree on a chip."  
• Ultra-low jitter of 90 fs rms  
• Input frequency range:  
• External crystal: 25 to 54 MHz  
• Differential clock: 10 to 750 MHz  
• LVCMOS clock: 10 to 250 MHz  
• Output frequency range:  
• Differential: 100 Hz to 1028 MHz  
The Si5341/40 can be quickly and easily configured using ClockBuilderPro software.  
• LVCMOS: 100 Hz to 250 MHz  
Custom part numbers are automatically assigned using a ClockBuilder Pro™ for fast,  
free, and easy factory pre-programming or the Si5341/40 can be programmed via I2C  
and SPI serial interfaces.  
• Highly configurable outputs compatible with  
LVDS, LVPECL, LVCMOS, CML, and HCSL  
with programmable signal amplitude  
• Si5341: 4 input, 10 output, 64-QFN 9x9 mm  
• Si5340: 4 input, 4 output, 44-QFN 7x7 mm  
Applications:  
• Clock tree generation replacing XOs, buffers, signal format translators  
• Any-frequency clock translation  
• Clocking for FPGAs, processors, memory  
• Ethernet switches/routers  
• OTN framers/mappers/processors  
• Test equipment and instrumentation  
• Broadcast video  
25-54 MHz XTAL  
XA  
XB  
4 Input  
Clocks  
OSC  
÷INT  
MultiSynth  
MultiSynth  
MultiSynth  
MultiSynth  
MultiSynth  
÷INT  
OUT0  
OUT1  
OUT2  
OUT3  
IN0  
IN1  
IN2  
÷INT  
÷INT  
÷INT  
÷INT  
÷INT  
÷INT  
PLL  
OUT4  
Up to 10  
Output Clocks  
OUT5  
÷INT  
÷INT  
÷INT  
÷INT  
÷INT  
Zero Delay  
÷INT  
OUT6  
OUT7  
OUT8  
OUT9  
FB_IN  
Status Flags  
I2C / SPI  
Status Monitor  
Control  
NVM  
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Rev. 1.0  
Si5341/40 Rev D Data Sheet  
Features List  
1. Features List  
The Si5341/40 Rev D features are listed below:  
• Generates any combination of output frequencies from any in-  
put frequency  
• DCO mode: as low as 0.001 ppb steps  
• Core voltage  
• Ultra-low jitter of 90 fs rms  
• Input frequency range:  
• VDD: 1.8 V ±5%  
• VDDA: 3.3 V ±5%  
• External crystal: 25 to 54 MHz  
• Differential clock: 10 to 750 MHz  
• LVCMOS clock: 10 to 250 MHz  
• Output frequency range:  
• Independent output clock supply pins  
• 3.3 V, 2.5 V, or 1.8 V  
• Serial interface: I2C or SPI  
• In-circuit programmable with non-volatile OTP memory  
• ClockBuilder Pro software simplifies device configuration  
• Si5341: 4 input, 10 output, 64-QFN 9x9 mm  
• Si5340: 4 input, 4 output, 44-QFN 7x7 mm  
• Temperature range: –40 to +85 °C  
• Differential: 100 Hz to 1028 MHz  
• LVCMOS: 100 Hz to 250 MHz  
• Highly configurable outputs compatible with LVDS, LVPECL,  
LVCMOS, CML, and HCSL with programmable signal ampli-  
tude  
• Pb-free, RoHS-6 compliant  
• Locks to gapped clock inputs  
• Optional zero delay mode  
• Glitchless on the fly output frequency changes  
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Rev. 1.0 | 1  
Si5341/40 Rev D Data Sheet  
Ordering Guide  
2. Ordering Guide  
Table 2.1. Si5341/40 Ordering Guide  
Number of In-  
put/Output  
Clocks  
Ordering Part Number  
(OPN)  
Output Clock Frequency  
Range (MHz)  
Frequency Syn-  
thesis Mode  
Temperature  
Package  
Range  
Si5341  
Si5341A-D-GM1, 2  
Si5341B-D-GM1, 2  
Si5341C-D-GM1, 2  
Integer and  
Fractional  
0.0001 to 1028 MHz  
0.0001 to 350 MHz  
0.0001 to 1028 MHz  
0.0001 to 350 MHz  
64-QFN  
9x9 mm  
4/10  
–40 to 85 °C  
Integer Only  
Si5341D-D-GM1, 2  
Si5340  
Si5340A-D-GM1, 2  
Si5340B-D-GM1, 2  
Si5340C-D-GM1, 2  
Integer and  
Fractional  
0.0001 to 1028 MHz  
0.0001 to 350 MHz  
0.0001 to 1028 MHz  
0.0001 to 350 MHz  
44-QFN  
7x7 mm  
4/4  
–40 to 85 °C  
Integer Only  
Si5340D-D-GM1, 2  
Si5341/40-D-EVB  
Si5341-D-EVB  
Si5340-D-EVB  
Note:  
Evaluation  
Board  
—
—
—
—
1. Add an R at the end of the OPN to denote tape and reel ordering options.  
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuild-  
er Pro software utility. Custom part number format is: e.g., Si5341A-Dxxxxx-GM, where "xxxxx" is a unique numerical sequence  
representing the preprogrammed configuration.  
3. See 3.9 Custom Factory Preprogrammed Devicesand 3.10 Enabling Features and/or Configuration Settings Not Available in  
ClockBuilder Pro for Factory Pre-Programmed Devices for important notes about specifying a preprogrammed device to use fea-  
tures or device register settings not yet available in CBPro.  
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Si5341/40 Rev D Data Sheet  
Ordering Guide  
Si534fg-Rxxxxx-GM  
Timing product family  
f = Multi-PLL clock family member (7, 6)  
g = Device grade (A, B, C, D)  
Product Revision*  
Custom ordering part number (OPN) sequence ID**  
Package, ambient temperature range (QFN, -40°C to +85°C)  
*See Ordering Guide table for current product revision  
** 5 digits; assigned by ClockBuilder Pro  
Figure 2.1. Ordering Part Number Fields  
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Si5341/40 Rev D Data Sheet  
Functional Description  
3. Functional Description  
The Si5340/41-D combines a wide band PLL with next generation MultiSynth technology to offer the industry's most versatile and high  
performance clock generator. The PLL locks to either an external crystal between XA/XB or to an external clock connected to XA/XB  
or IN0, 1, 2. A fractional or integer multiplier takes the selected input clock or cystal frequency up to a very high frequency that is then  
divided by the MultiSynth output stage to any frequency in the range of 100 Hz to 1 GHz on each output. The MultiSynth stage can  
divide by both integer and fractional values. The high-resolution fractional MultiSynth dividers enable true any-frequency input to any-  
frequency on any of the outputs. The output drivers offer flexible output formats which are independently configurable on each of the  
outputs. This clock generator is fully configurable via its serial interface (I2C/SPI) and includes in-circuit programmable non-volatile  
memory.  
3.1 Power-up and Initialization  
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from  
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-  
tion period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A hard reset  
is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to  
their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft reset  
bypasses the NVM download. It is simply used to initiate register configuration changes.  
Hard Reset  
bit asserted  
RSTb  
pin asserted  
Power-Up  
NVM download  
Initialization  
Soft Reset  
bit asserted  
Serial interface  
ready  
Figure 3.1. Si5341 Power-Up and Initialization  
3.2 Frequency Configuration  
The phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is to phase lock to  
the selected input and provide a common reference to the MultiSynth high-performance fractional dividers.  
A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional output integer dividers  
provide further frequency division by an even integer from 2 to (2^25)-2. The frequency configuration of the device is programmed by  
setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth fractional dividers (Nn/Nd), and the output  
integer dividers (R). Silicon Labs's ClockBuilder Pro configuration utility determines the optimum divider values for any desired input  
and output frequency plan.  
3.3 Inputs  
The Si5340/41-D requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0, 1, 2.  
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Si5341/40 Rev D Data Sheet  
Functional Description  
3.3.1 XA/XB Clock and Crystal Input  
An internal crystal oscillator exists between pin XA and XB. When this oscillator is enabled, an external crystal connected across these  
pins will oscillate and provide a clock input to the PLL. A crystal frequency of 25 MHz can be used although crystals in the frequency  
range of 48 MHz to 54 MHz are recommended for best jitter performance. Frequency offsets due to CL mismatch can be adjusted using  
the frequency adjustment feature which allows frequency adjustments of ± 1000 ppm. The Si5340/41 Family Reference Manual pro-  
vides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Refer to Table  
5.12 Crystal Specifications on page 31 for crystal specifications.  
To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. A clock (e.g.,  
XO) may be used in lieu of the crystal, but it will result in higher output jitter. See the Si5340/41 Reference Manual for more information.  
Selection between the external XTAL or input clock is controlled by register configuration. The internal crystal load capacitors (CL) are  
disabled in the input clock mode. Refer to Table 5.3 Input Clock Specifications on page 20 for the input clock requirements at XAXB.  
Both a single-ended or a differential input clock can be connected to the XA/XB pins as shown in the figure below. A PXAXB divider is  
available to accommodate external clock frequencies higher than 54 MHz.  
Differential Connection  
Single-ended XO Connection  
X1  
X1  
nc  
nc  
X2  
nc  
X2  
nc  
Note:2. 0 Vpp_ se max  
2xC  
L
2xC  
L
0. 1uf  
0. 1uf  
XA  
XB  
XA  
OSC  
OSC  
XB  
XO with Clipped Sine Wave  
Output  
0. 1uf  
2xC  
2xC  
L
L
Si5341/40  
Si5341/40  
0. 1uf  
Note:2. 5 Vpp diff max  
Crystal Connection  
Single-ended Connection  
X1  
nc  
X2  
nc  
Note:2. 0 Vpp_ se max  
X1  
2xCL  
2xC  
L
CMOS Output  
XA  
0. 1uf  
R1  
XA  
XB  
XTAL  
OSC  
OSC  
R2  
XO VDD  
R1  
R2  
0. 1uf  
0. 1uf  
XB  
X2  
442 ohms  
3. 3V 523 ohms  
2xC  
2xC  
L
2. 5V 475ohms 649 ohms  
1. 8V 158ohms 866 ohms  
L
Si5341/40  
Si5341/40  
Figure 3.2. XAXB External Crystal and Clock Connections  
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Si5341/40 Rev D Data Sheet  
Functional Description  
3.3.2 Input Clocks (IN0, IN1, IN2)  
A differential or single-ended clock can be applied at IN2, IN1, or IN0. The recommended input termination schemes are shown in the  
figure below.  
Standard AC Coupled Differential LVDS  
Si5341/40  
Standard  
50  
INx  
100  
INxb  
3.3V, 2.5V  
LVDS or  
50  
CML  
Pulsed CMOS  
Standard AC Coupled Differential LVPECL  
Si5341/40  
50  
Standard  
INx  
100  
INxb  
50  
3.3V, 2.5V  
LVPECL  
Pulsed CMOS  
Standard AC Coupled Single Ended  
Si5341/40  
Standard  
INx  
50  
3.3V, 2.5V, 1.8V  
INxb  
LVCMOS  
Pulsed CMOS  
Pulsed CMOS DC Coupled Single Ended  
R1  
Si5341/40  
Standard  
50  
INx  
3.3V, 2.5V, 1.8V  
LVCMOS  
R2  
INxb  
R1 (Ohm) R2 (Ohm)  
VDD  
1.8 V  
2.5 V  
3.3 V  
324  
511  
634  
665  
475  
365  
Pulsed CMOS  
Figure 3.3. Termination of Differential and LVCMOS Input Signals  
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Si5341/40 Rev D Data Sheet  
Functional Description  
3.3.3 Input Selection (IN0, IN1, IN2, XA/XB)  
The active clock input is selected using the IN_SEL[1:0] pins or by register control. A register bit determines input selection as pin or  
register selectable. There are internal pull ups on the IN_SEL pins.  
Table 3.1. Manual Input Selection Using IN_SEL[1:0] Pins  
IN_SEL[1:0]  
Selected Input  
0
0
1
1
0
1
0
1
IN0  
IN1  
IN2  
XA/XB  
3.4 Fault Monitoring  
The Si5340/41-D provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of  
lock (LOL) for the PLL as shown in the figure below.  
Si5341/40  
IN0  
LOS0  
÷P  
0
IN0b  
LOL  
IN1  
LOS1  
÷P  
1
IN1b  
PLL  
PD  
LPF  
Mn  
IN2  
LOS2  
÷P  
2
IN2b  
÷
Md  
LOSXAB  
XA  
XB  
OSC  
FB_IN  
LOSFB  
÷P  
fb  
FB _INb  
Figure 3.4. LOS and LOL Fault Monitors  
3.4.1 Status Indicators  
The state of the status monitors are accessible by reading registers through the serial interface or with dedicated pin (LOLb). Each of  
the status indicator register bits has a corresponding sticky bit in a separate register location. Once a status bit is asserted its corre-  
sponding sticky bit (_FLG) will remain asserted until cleared. Writing a logic zero to a sticky register bit clears its state.  
3.4.2 Interrupt Pin (INTRb)  
An interrupt pin (INTRb) indicates a change in state with any of the status registers. All status registers are maskable to prevent asser-  
tion of the interrupt pin. The state of the INTRb pin is reset by clearing the status registers.  
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Si5341/40 Rev D Data Sheet  
Functional Description  
3.5 Outputs  
The Si5341 supports 10 differential output drivers which can be independently configured as differential or LVCMOS. The Si5340 sup-  
ports 4 output drivers independently configurable as differential or LVCMOS.  
3.5.1 Output Signal Format  
The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal  
formats including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS  
(3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs.  
3.5.2 Differential Output Terminations  
The differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below.  
DC Coupled LVDS  
AC Coupled LVDS/LVPECL  
VDDO =3.3V,2.5V,1.8V  
VDDO =3.3V,2.5V,1.8V  
50  
50  
50  
50  
OUTx  
OUTx  
100  
OUTxb  
100  
OUTxb  
Internally  
self-biased  
Si5341/40  
Si5341/40  
AC Coupled LVPECL/CML  
AC Coupled HCSL  
VDD– 1.3V  
VDD  
RX  
VDDO =3.3V,2.5V,1.8V  
VDDO =3.3V,2.5V  
50  
50  
R1  
R1  
R2  
OUTx  
OUTxb  
50  
50  
50  
50  
OUTx  
OUTxb  
Standard  
HCSL  
Receiver  
Si5341/40  
Si5341/40  
R2  
Option1  
For V =0. 37V  
CM  
VDDRX  
R1  
R2  
442 ohms 56.2 ohms  
332 ohms 59 ohms  
243 ohms 63.4 ohms  
3. 3V  
2. 5V  
1. 8V  
Figure 3.5. Supported Differential Output Terminations  
3.5.3 Programmable Common Mode Voltage for Differential Outputs  
The common mode voltage (VCM) for the differential modes are programmable so that LVDS specifications can be met and for the best  
signal integrity with different supply voltages. When dc coupling the output driver it is essential that the receiver should have a relatively  
high common mode impedance so that the common mode current from the output driver is very small.  
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Si5341/40 Rev D Data Sheet  
Functional Description  
3.5.4 LVCMOS Output Terminations  
LVCMOS outputs are typically dc-coupled, as shown in the figure below.  
DC Coupled LVCMOS  
3.3V,2.5V,1.8V  
LVCMOS  
VDDO =3.3V,2.5V,1.8V  
50  
50  
Rs  
Rs  
OUTx  
OUTxb  
Figure 3.6. LVCMOS Output Terminations  
3.5.5 LVCMOS Output Impedance and Drive Strength Selection  
Each LVCMOS driver has a configurable output impedance. It is highly recommended that the minimum output impedance (strongest  
drive setting) is selected and a suitable series resistor (Rs) is chosen to match the trace impedance.  
Table 3.2. Nominal Output Impedance vs. OUTx_CMOS_DRV (register)  
VDDO  
CMOS_DRIVE_Selection  
OUTx_CMOS_DRV=1  
OUTx_CMOS_DRV=2  
OUTx_CMOS_DRV=3  
3.3 V  
2.5 V  
1.8 V  
38 Ω  
43 Ω  
—
30 Ω  
35 Ω  
46 Ω  
22 Ω  
24 Ω  
31 Ω  
Note: Refer to the Si5340/41 Family Reference Manual for more information on register settings.  
3.5.6 LVCMOS Output Signal Swing  
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own  
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.  
3.5.7 LVCMOS Output Polarity  
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on  
the OUTxb pin is generated with complementary polarity with the clock on the OUTx pin. The LVCMOS OUTx and OUTxb outputs can  
also be generated in phase.  
3.5.8 Output Enable/Disable  
The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high all outputs will be  
disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be individually disabled through register control.  
3.5.9 Output Driver State When Disabled  
The disabled state of an output driver is configurable as: disable low or disable high.  
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Si5341/40 Rev D Data Sheet  
Functional Description  
3.5.10 Synchronous/Asynchronous Output Disable Feature  
Outputs can be configured to disable synchronously or asynchronously. The default state is synchronous output disable. In synchro-  
nous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt  
pulses from occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately without waiting  
for the period to complete.  
3.5.11 Output Delay Control (t0-t4)  
The Si5341/40 uses independent MultiSynth dividers (N0 - N4) to generate up to 5 unique frequencies to its 10 outputs through a cross-  
point switch. By default all clocks are phase aligned. A delay path (t0 - t4) associated with each of these dividers is available for applica-  
tions that need a specific output skew configuration. Each delay path is controlled by a register parameter call Nx_DELAY with a resolu-  
tion of ~0.28 ps over a range of ~±9.14 ns. This is useful for PCB trace length mismatch compensation. After the delay controls are  
configured, the soft reset bit SOFT_RST must be set high so that the output delay takes effect and the outputs are re-aligned.  
VDDO0  
OUT0  
OUT0b  
÷R  
0
t0  
t1  
t2  
t3  
t4  
÷N0  
÷N1  
÷N2  
÷N3  
÷N4  
VDDO1  
OUT1  
OUT1b  
÷R  
1
VDDO2  
OUT2  
OUT2b  
÷R  
2
VDDO3  
OUT3  
OUT3b  
÷R  
3
VDDO4  
OUT4  
OUT4b  
÷R  
4
VDDO5  
OUT5  
OUT5b  
÷R  
5
VDDO6  
OUT6  
OUT6b  
÷R  
6
VDDO7  
OUT7  
OUT7b  
÷R  
7
VDDO8  
OUT8  
OUT8b  
÷R  
8
VDDO9  
OUT9  
OUT9b  
÷R  
9
Figure 3.7. Example of Independently Configurable Path Delays  
All delay values are restored to their NVM programmed values after power-up or after a hard reset. Delay default values can be written  
to the NVM allowing a custom delay offset configuration at power-up or after a hardware reset.  
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Functional Description  
3.5.12 Zero Delay Mode  
A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.  
The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally  
as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the  
output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest  
trace length will help to minimize the input-to-output delay. It is recommended to connect OUT9 (Si5341) or OUT3 (Si5340) to FB_IN for  
external feedback. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external  
feedback path connection is necessary for best performance.  
VDDO0  
OUT0  
OUT0b  
Si5341  
VDDO1  
OUT1  
OUT1b  
IN0  
P
÷
÷
÷
0
IN0b  
fIN  
IN1  
VDDO2  
OUT2  
OUT2b  
P
1
IN1b  
IN2  
P2  
VDDO3  
OUT3  
IN2b  
OUT3b  
IN_SEL[1:0]  
MultiSynth  
& Dividers  
PLL  
Zero Delay  
Mode  
FB_IN  
PD  
VDDO7  
OUT7  
OUT7b  
fFB =fIN  
LPF  
P
fb  
÷
Mn  
Md  
VDDO8  
OUT8  
OUT8b  
÷
FB_INb  
VDDO9  
N9n  
OUT9  
OUT9b  
÷
÷R9  
N9d  
External Feedback Path  
Figure 3.8. Si5341 Zero Delay Mode Setup  
3.5.13 Sync Pin (Synchronizing R Dividers)  
All the output R dividers are reset to the default NVM register state after a power-up or a hard reset. This ensures consistent and re-  
peatable phase alignment across all output drivers to within ±100 ps of the expected value from the NVM download. Resetting the de-  
vice using the RSTb pin or asserting the hard reset bit will have the same result. The SYNCb pin provides another method of re-aligning  
the R dividers without resetting the device, however, the outputs will only align to within 50 ns when using the SYNCb pin. This pin is  
positive edge triggered. Asserting the sync register bit provides the same function as the SYNCb pin. A soft reset will align the outputs  
to within ±100 ps of the expected value based upon the Nx_DELAY parameter.  
3.5.14 Output Crosspoint  
The output crosspoint allows any of the N dividers to connect to any of the clock outputs.  
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Si5341/40 Rev D Data Sheet  
Functional Description  
3.5.15 Digitally Controlled Oscillator (DCO) Modes  
Each MultiSynth can be digitally controlled so that all outputs connected to the MultiSynth change frequency in real time without any  
transition glitches. There are two ways to control the MultiSynth to accomplish this task:  
• Use the Frequency Increment/Decrement Pins or register bits.  
• Write directly to the numerator of the MultiSynth divider.  
An output that is controlled as a DCO is useful for simple tasks such as frequency margining or CPU speed control. The output can also  
be used for more sophisticated tasks such as FIFO management by adjusting the frequency of the read or write clock to the FIFO or  
using the output as a variable Local Oscillator in a radio application.  
3.5.15.1 DCO with Frequency Increment/Decrement Pins/Bits  
Each of the MultiSynth fractional dividers can be independently stepped up or down in predefined steps with a resolution as low as  
0.001 ppb. Setting of the step size and control of the frequency increment or decrement is accomplished by setting the step size with  
the 44 bit Frequency Step Word (FSTEPW). When the FINC or FDEC pin or register bit is asserted the output frequency will increment  
or decrement respectively by the amount specified in the FSTEPW.  
3.5.15.2 DCO with Direct Register Writes  
When a MultiSynth numerator and its corresponding update bit is written, the new numerator value will take effect and the output fre-  
quency will change without any glitches. The MultiSynth numerator and denominator terms can be left and right shifted so that the least  
significant bit of the numerator word represents the exact step resolution that is needed for your application.  
3.6 Power Management  
Several unused functions can be powered down to minimize power consumption. Consult the Si5340/41 Family Reference Manual and  
ClockBuilder Pro configuration utility for details.  
3.7 In-Circuit Programming  
The Si5341/40 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values  
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-  
erate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power sup-  
ply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the  
old configuration is no longer accessible. Refer to the Si5340/41 Family Reference Manual for a detailed procedure for writing registers  
to NVM.  
3.8 Serial Interface  
Configuration and operation of the Si5341/40 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL  
pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or  
3-wire. See the Si5340/41 Family Reference Manual for details.  
3.9 Custom Factory Preprogrammed Devices  
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered  
with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Custom, factory-pre-  
programmed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly  
and easily request and generate a custom part number for your configuration. In less than three minutes, you will be able to generate a  
custom part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation  
email with the data sheet addendum, simply place an order with your local Silicon Labs sales representative. Samples of your pre-pro-  
grammed device will ship to you typically within two weeks.  
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Rev. 1.0 | 12  
Si5341/40 Rev D Data Sheet  
Functional Description  
3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-Programmed Devices  
As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at http://  
www.silabs.comand opting in for updates to software, you will be notified whenever changes are made and what the impact of those  
changes are. This update process will ultimately enable ClockBuilder Pro users to access all features and register setting values docu-  
mented in this data sheet and the Si5341/40 Family Reference Manual. However, if you must enable or access a feature or register  
setting value so that the device starts up with this feature or a register setting, but the feature or register setting is NOT yet available in  
CBPro, you must contact a Silicon Labs applications engineer for assistance. An example of this type of feature or custom setting is the  
customizable amplitudes for the clock outputs. After careful review of your project file and custom requirements, a Silicon Labs applica-  
tions engineer will email back your CBPro project file with your specific features and register settings enabled, using what is referred to  
as the manual "settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file.  
Examples of setting "overrides" in a CBPro design report are shown below:  
Table 3.3. Setting Overrides  
Location  
Name  
Type  
Target  
Dec Value  
Hex Value  
0128[6:4]  
OUT6_AMPL  
User  
OPN & EVB  
5
5
Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after  
startup with the values in the NVM file, including the Silicon Labs-supplied override settings.  
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Rev. 1.0 | 13  
Si5341/40 Rev D Data Sheet  
Functional Description  
End: Place  
sample order  
Start  
Do I need a  
pre-programmed device with  
a feature or setting which is  
unavailable in ClockBuilder  
Pro?  
Generate  
Custom OPN  
in CBPro  
Configure device  
using CBPro  
No  
Yes  
Contact Silicon Labs  
Technical Support  
to submit & review  
your  
Yes  
non-standard  
configuration  
request & CBPro  
project file  
Receive  
updated CBPro  
project file  
from  
Silicon Labs  
with “Settings  
Override”  
Does the updated  
CBPro Project file  
match your  
Load project file  
into CBPro and test  
requirements?  
Figure 3.9. Flowchart to Order Custom Parts with Features not Available in CBPro  
Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx.  
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Rev. 1.0 | 14  
Si5341/40 Rev D Data Sheet  
Register Map  
4. Register Map  
The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible  
registers such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as  
frequency configuration, and general device settings. A high level map of the registers is shown in 4.2 High-Level Register Map. Refer  
to the Si5340/41 Family Reference Manual for a complete list of register descriptions and settings.  
4.1 Addressing Scheme  
The device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register address. By default  
the page address is set to 0x00. Changing to another page is accomplished by writing to the ‘Set Page Address’ byte located at ad-  
dress 0x01 of each page.  
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Si5341/40 Rev D Data Sheet  
Register Map  
4.2 High-Level Register Map  
Table 4.1. High-Level Register Map  
16-Bit Address  
Content  
8-bit Page Address  
8-bit Register Address Range  
00  
00  
01  
Revision IDs  
Set Page Address  
02-0A  
0B-15  
17-1B  
1C  
Device IDs  
Alarm Status  
INTR Masks  
Reset controls  
2C-E1  
E2-E4  
FE  
Alarm Configuration  
NVM Controls  
Device Ready Status  
01  
02  
01  
Set Page Address  
08-3A  
41-42  
FE  
Output Driver Controls  
Output Driver Disable Masks  
Device Ready Status  
01  
Set Page Address  
02-05  
08-2F  
30  
XTAL Frequency Adjust  
Input Divider (P) Settings  
Input Divider (P) Update Bits  
PLL Feedback Divider (M) Settings  
PLL Feedback Divider (M) Update Bit  
Output Divider (R) Settings  
User Scratch Pad Memory  
Device Ready Status  
35-3D  
3E  
47-6A  
6B-72  
FE  
03  
01  
Set Page Address  
02-37  
0C  
MultiSynth Divider (N0-N4) Settings  
MultiSynth Divider (N0) Update Bit  
MultiSynth Divider (N1) Update Bit  
MultiSynth Divider (N2) Update Bit  
MultiSynth Divider (N3) Update Bit  
MultiSynth Divider (N4) Update Bit  
FINC/FDEC Settings N0-N4  
Output Delay (Dt) Settings  
Frequency Readback N0-N4  
Device Ready Status  
17  
22  
2D  
38  
39-58  
59-62  
63-94  
FE  
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Rev. 1.0 | 16  
Si5341/40 Rev D Data Sheet  
Register Map  
16-Bit Address  
8-bit Register Address Range  
Content  
8-bit Page Address  
04-08  
09  
00-FF  
01  
Reserved  
Set Page Address  
Input Settings  
49  
1C  
Zero Delay Mode Settings  
Reserved  
A0-FF  
00-FF  
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Rev. 1.0 | 17  
Si5341/40 Rev D Data Sheet  
Electrical Specifications  
5. Electrical Specifications  
Table 5.1. Recommended Operating Conditions1  
(VDD=1.8 V ± 5%, VDDA=3.3 V ± 5%, TA= –40 to 85°C)  
Parameter  
Ambient Temperature  
Symbol  
Min  
–40  
—
Typ  
25  
Max  
Units  
°C  
°C  
V
TA  
85  
Junction Temperature  
Core Supply Voltage  
TJMAX  
VDD  
—
125  
1.71  
3.14  
3.14  
2.37  
1.71  
1.80  
3.30  
3.30  
2.50  
1.80  
1.89  
3.47  
3.47  
2.62  
1.89  
VDDA  
VDDO  
V
Output Driver Supply Voltage  
V
V
V
Note:  
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-  
ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.  
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Rev. 1.0 | 18  
Si5341/40 Rev D Data Sheet  
Electrical Specifications  
Table 5.2. DC Characteristics  
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDO=1.8V ± 5%, 2.5V ± 5%, or 3.3V ± 5%, TA= -40 to 85°C)  
Parameter  
Symbol  
IDD  
Test Condition  
Si5340/41  
Min  
—
Typ  
115  
120  
22  
Max  
230  
130  
26  
Units  
mA  
Core Supply Current1, 2  
IDDA  
Si5340/41  
—
mA  
LVPECL Output3  
@ 156.25 MHz  
Output Buffer Supply Current  
IDDOx  
—
mA  
LVDS Output3  
—
—
—
—
15  
22  
18  
12  
18  
30  
23  
16  
mA  
mA  
mA  
mA  
@ 156.25 MHz  
3.3 V LVCMOS4 output  
@ 156.25 MHz  
2.5 V LVCMOS4 output  
@ 156.25 MHz  
1.8 V LVCMOS4 output  
@ 156.25 MHz  
Si5341  
Total Power Dissipation1, 5  
Pd  
—
—
880  
680  
1150  
875  
mW  
mW  
Si5340  
Note:  
1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.  
2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.  
3. Differential outputs terminated into an ac-coupled 100 Ω load.  
4. LVCMOS outputs measured into a 6-inch 50 W PCB trace with 5 pF load. The LVCMOS outputs were set to  
OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5341/40 Family Reference Manual for more details on  
register settings.  
Differential Output Test Configuration  
LVCMOS Output Test Configuration  
IDDO  
IDDO  
0. 1uF  
6 inch  
50  
50  
50  
OUT  
OUTa  
OUTb  
100  
OUTb  
5pF  
0. 1 uF  
5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not  
available. All EVBs support detailed current measurements for any configuration.  
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Rev. 1.0 | 19  
Si5341/40 Rev D Data Sheet  
Electrical Specifications  
Table 5.3. Input Clock Specifications  
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, TA=-40 to 85°C)  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Standard Input Buffer with Differential or Single-Ended - AC-Coupled (IN0/IN0b, IN1/IN1b, IN2/IN2b, FB_IN/FB_INb)  
Input Frequency Range  
Input Voltage Swing1  
fIN  
Differential  
0.008  
0.008  
—
—
750  
250  
MHz  
MHz  
All Single-ended Signals  
(including LVCMOS)  
Differential AC-coupled  
fIN < 250 MHz  
VIN  
100  
225  
100  
400  
—
—
—
—
1800  
1800  
3600  
—
mVpp_se  
mVpp_se  
mVpp_se  
V/μs  
Differential AC-coupled  
250 MHz < fIN < 750 MHz  
Single-ended AC-coupled  
fIN < 250 MHz  
Slew Rate2, 3  
SR  
Duty Cycle  
DC  
CIN  
RIN  
40  
—
—
—
0.3  
16  
60  
—
—
%
pF  
kΩ  
Input Capacitance  
Input Resistance  
Pulsed CMOS Input Buffer - DC Coupled (IN0, IN1, IN2)4  
Input Frequency  
Input Voltage  
fIN  
VIL  
VIH  
SR  
0.008  
–0.2  
0.8  
—
—
—
—
250  
0.4  
—
MHz  
V
V
Slew Rate2, 3  
400  
—
V/μs  
Duty Cycle  
DC  
PW  
RIN  
Clock Input  
Pulse Input  
40  
1.6  
—
—
—
8
60  
—
—
%
ns  
kΩ  
Minimum Pulse Width  
Input Resistance  
REFCLK (Applied to XA/XB)  
Input Frequency Range  
fIN  
Full operating range. Jitter  
performance may be re-  
duced.  
10  
—
200  
MHz  
Range for best jitter.  
48  
—
—
54  
MHz  
Input Single-ended Voltage  
Swing  
VIN_SE  
365  
2000  
mVpp_se  
Input Differential Voltage Swing  
Slew Rate2, 3  
VIN_DIFF  
SR  
365  
400  
—
—
2500  
—
mVpp_diff  
V/μs  
Imposed for best jitter per-  
formance  
Input Duty Cycle  
DC  
40  
—
60  
%
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Rev. 1.0 | 20  
Si5341/40 Rev D Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Note:  
1. Voltage swing is specified as single-ended mVpp.  
Vpp_se  
Vpp_se  
Vcm  
Vcm  
Vpp_diff = 2*Vpp_se  
2. Imposed for jitter performance.  
3. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because  
they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since  
the input thresholds (VIL, VIH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for  
DC-coupled Pulsed LVCMOS in the Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard  
AC-Coupled, Single-ended input mode.  
4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended LVCMOS inputs  
to IN0,1,2 it is required to ac-couple into the differential input buffer.  
Table 5.4. Control Input Pin Specifications  
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDS=3.3V ± 5%, 1.8V ± 5%, TA=-40 to 85°C)  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Si5341 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, A1, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO)  
1
Input Voltage  
VIL  
VIH  
—
—
—
V
V
0.3xVDDIO  
—
1
0.7xVDDIO  
Input Capacitance  
Input Resistance  
CIN  
RIN  
—
—
2
—
—
—
pF  
kW  
ns  
20  
—
Minimum Pulse Width  
TPW  
RSTb, SYNCb, FINC, and  
FDEC  
100  
Frequency Update Rate  
FUR  
FINC and FDEC  
—
—
1
MHz  
Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, SDA/SDIO)  
1
Input Voltage  
VIL  
VIH  
—
—
—
V
V
0.3xVDDIO  
—
1
0.7xVDDIO  
Input Capacitance  
Input Resistance  
Minimum Pulse Width  
Note:  
CIN  
RIN  
—
—
2
—
—
—
pF  
kW  
ns  
20  
—
TPW  
RSTb only  
100  
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Family Reference Manual for more  
details on register settings.  
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Si5341/40 Rev D Data Sheet  
Electrical Specifications  
Table 5.5. Differential Clock Output Specifications  
(VDD=1.8 V ± 5%, VDDA=3.3V ± 5%, VDDO=1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 5%, TA= -40 to 85°C)  
Parameter  
Output Frequency  
Symbol  
Test Condition  
Min  
0.0001  
733.33  
825  
Typ  
—
—
—
—
—
—
—
Max  
720  
800.00  
1028  
720  
52  
Units  
fOUT  
MultiSynth not used  
MHz  
MultiSynth used  
fOUT < 400 MHz  
0.0001  
48  
MHz  
%
Duty Cycle  
DC  
400 MHz < fOUT < 1028 MHz  
Outputs on same MultiSynth  
(Measured at 712.5 MHz)  
45  
55  
%
Output-Output Skew  
Using Same MultiSynth  
Output-Output Skew  
Between MultiSynths  
TSKS  
—
65  
ps  
TSKD  
Outputs from different  
MultiSynths  
—
—
—
0
90  
50  
ps  
(Measured at 712.5 MHz)  
OUT-OUTb Skew  
TSK_OUT  
Measured from the positive  
to negative output pins  
ps  
Output Voltage Swing1  
VOUT  
LVDS  
350  
640  
1.10  
1.90  
1.1  
430  
750  
1.2  
2.0  
1.2  
510  
900  
1.3  
2.1  
1.3  
mVpp_se  
LVPECL  
Common Mode Voltage1, 2  
VCM  
VDDO = 3.3 V  
LVDS  
LVPECL  
LVPECL  
LVDS  
V
V
DDO = 2.5 V  
VDDO = 1.8 V Sub-LVDS  
0.8  
—
0.9  
1.0  
Rise and Fall Times  
(20% to 80%)  
tR/tF  
100  
150  
ps  
Differential Output Impedance  
ZO  
—
—
—
—
—
—
—
100  
–101  
–96  
–99  
–97  
–72  
–88  
—
—
—
—
—
—
—
Ω
Power Supply Noise Rejection2  
PSRR  
10 kHz sinusoidal noise  
100 kHz sinusoidal noise  
500 kHz sinusoidal noise  
1 MHz sinusoidal noise  
Si5341  
dBc  
Output-Output Crosstalk3  
XTALK  
dBc  
dBc  
Si5340  
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Rev. 1.0 | 22  
Si5341/40 Rev D Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Notes:  
1. Output amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each out-  
put driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the  
TIA/EIA-644 maximum. Refer to the Si5341/40 Family Reference Manual for more suggested output settings. Not all combina-  
tions of voltage amplitude and common mode voltages settings are possible.  
OUTx  
Vcm  
Vcm  
Vpp_se  
Vpp_se  
Vpp_ diff =2*Vpp_se  
OUTxb  
2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude meas-  
ured.  
3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25  
MHz. Refer to application note, AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems,  
guidance on crosstalk minimization.  
Table 5.6. LVCMOS Clock Output Specifications  
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDO=1.8V ± 5%, 2.5V ± 5%, or 3.3V ± 5%, TA= -40 to 85°C)  
Parameter  
Output Frequency  
Duty Cycle  
Symbol  
Test Condition  
Min  
0.0001  
48  
Typ  
—
Max  
250  
52  
Units  
MHz  
%
DC  
fOUT < 100 MHz  
—
100 MHz < fOUT < 250 MHz  
Outputs on same MultiSynth.  
FOUT = 156.25 MHz  
45  
—
55  
Output-to-Output Skew  
Output Voltage High1, 2, 3  
TSK  
—
30  
140  
ps  
V
VOH  
VDDO = 3.3 V  
OUTx_CMOS_DRV=1  
OUTx_CMOS_DRV=2  
OUTx_CMOS_DRV=3  
IOH = -10 mA VDDO x 0.85  
IOH = -12 mA  
—
—
—
—
—
—
IOH = -17 mA  
VDDO = 2.5 V  
OUTx_CMOS_DRV=1  
OUTx_CMOS_DRV=2  
OUTx_CMOS_DRV=3  
IOH = -6 mA  
IOH = -8 mA  
IOH = -11 mA  
VDDO x 0.85  
—
—
—
—
—
—
V
V
VDDO = 1.8 V  
VDDO x 0.85  
OUTx_CMOS_DRV=2  
OUTx_CMOS_DRV=3  
IOH = -4 mA  
IOH = -5 mA  
—
—
—
—
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Rev. 1.0 | 23  
Si5341/40 Rev D Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Output Voltage Low1, 2, 3  
VOL  
VDDO = 3.3 V  
OUTx_CMOS_DRV=1  
IOL = 10 mA  
IOL = 12 mA  
IOL = 17 mA  
—
—
—
—
VDDO x 0.15  
V
OUTx_CMOS_DRV=2  
OUTx_CMOS_DRV=3  
—
—
VDDO = 2.5 V  
OUTx_CMOS_DRV=1  
OUTx_CMOS_DRV=2  
OUTx_CMOS_DRV=3  
IOL = 6 mA  
IOL = 8 mA  
IOL = 11 mA  
—
—
—
—
VDDO x 0.15  
V
—
—
VDDO = 1.8 V  
OUTx_CMOS_DRV=2  
OUTx_CMOS_DRV=3  
IOL = 4 mA  
IOL = 5 mA  
—
—
—
—
—
—
VDDO x 0.15  
V
—
LVCMOS Rise and Fall  
Times3  
tr/tf  
VDDO = 3.3V  
400  
450  
550  
600  
600  
750  
ps  
ps  
ps  
VDDO = 2.5 V  
VDDO = 1.8 V  
(20% to 80%)  
Notes:  
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the  
Family Reference Manual for more details on register settings.  
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.  
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 W PCB trace. A 5 pF capacitive  
load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.  
AC Test Configuration  
DC Test Configuration  
Trace length 5 inches  
499  
DC Block  
56  
IDDO  
IOL/IOH  
50  
50 probe, scope  
50 probe, scope  
OUT  
4.7 pF  
Zs  
OUTb  
VOL/VOH  
499  
DC Block  
56  
50  
4.7 pF  
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Electrical Specifications  
Table 5.7. Output Status Pin Specifications  
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, VDDS= 3.3V ± 5%, 1.8V ± 5%, TA= -40 to 85°C)  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Si5341/40 Status Output Pins (INTRb, SDA/SDIO)1  
VDDIO2 x  
0.85  
Output Voltage  
VOH  
IOH = -2 mA  
IOL = 2 mA  
—
—
—
V
V
VDDIO2x  
0.15  
VOL  
—
Si5341 Status Output Pins (LOLb)  
VDDIO2 x  
0.85  
Output Voltage  
VOH  
IOH = -2 mA  
IOL = 2 mA  
—
—
—
V
V
VDDIO2 x  
0.15  
VOL  
—
Si5340 Status Output Pins (LOLb, LOS_XAXBb)  
Output Voltage  
VOH  
VOL  
IOH = -2 mA  
IOL = 2 mA  
VDDS x 0.85  
—
—
—
—
V
V
VDDSx 0.15  
Notes:  
1. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused  
with I2C_SEL pulled high. VOL remains valid in all cases.  
2. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Family Reference Manual for more  
details on register settings.  
Table 5.8. Performance Characteristics  
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, TA= -40 to 85°C)  
Parameter  
VCO Frequency Range  
PLL Loop Bandwidth  
Initial Start-Up Time  
Symbol  
FVCO  
Test Condition  
Min  
13.5  
—
Typ  
—
Max  
14.4  
—
Units  
GHz  
MHz  
ms  
fBW  
1.0  
30  
tSTART  
Time from power-up to  
when the device gener-  
ates clocks (Input Fre-  
quency >48 MHz)  
—
45  
PLL Lock Time1  
tACQ  
tDELAY_frac  
tDELAY_int  
tRANGE  
fIN = 19.44 MHz  
fVCO = 14 GHz  
15  
—
—
—
—
—
0.28  
71.4  
±9.14  
—
150  
—
ms  
ps  
Output Delay Adjustment  
—
ps  
Delay is controlled by the  
MultiSynth  
—
ns  
POR2 to Serial Interface Ready  
tRDY  
15  
ms  
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Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Integer Mode4  
Min  
Typ  
Max  
Units  
Jitter Generation Locked to Ex-  
ternal Clock3  
JGEN  
—
140  
180  
fs rms  
12 kHz to 20 MHz  
Fractional/DCO Mode5  
12 kHz to 20 MHz  
—
160  
210  
fs rms  
JPER  
JCC  
JPER  
JCC  
Derived from integrated  
phase noise  
—
—
—
—
110  
180  
—
—
—
—
fs pk-pk  
fs pk  
N = 10,000 cycles Integer  
7400  
6700  
fs pk-pk  
fs pk  
or Fractional Mode4, 5  
.
Measured in the time do-  
main. Performance is limi-  
ted by the noise floor of  
the equipment.  
Jitter Generation Locked to Ex-  
ternal XTAL  
XTAL Frequency = 48 MHz  
Integer Mode4  
12 kHz to 20 MHz  
Fractional/DCO Mode5  
12 kHz to 20 MHz  
JGEN  
—
90  
140  
170  
fs rms  
fs rms  
—
115  
JPER  
JCC  
JPER  
JCC  
Derived from integrated  
phase noise  
—
—
—
—
110  
180  
—
—
—
—
fs pk-pk  
fs pk  
N = 10, 000 cycles Integer  
7400  
6600  
fs pk-pk  
fs pk  
or Fractional Mode.4, 5  
Measured in the time do-  
main. Performance is limi-  
ted by the noise floor of  
the equipment.  
XTAL Frequency = 25 MHz  
Integer Mode4  
JGEN  
115  
140  
190  
fs rms  
fs rms  
12 kHz to 20 MHz  
Fractional Mode5  
12 kHz to 20 MHz  
140  
Notes:  
1. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input clock. The  
time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.  
2. Measured as time from valid VDD and VDD33 rails (90% of their value) to when the serial interface is ready to respond to com-  
mands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.  
3. Jitter generation test conditions fIN = 100 MHz, fOUT = 156.25 MHz LVPECL.  
4. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.  
5. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the feedback divid-  
er is integer.  
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Electrical Specifications  
Table 5.9. I2C Timing Specifications (SCL,SDA)  
Parameter  
Symbol  
Test Condition  
Standard Mode  
100 kbps  
Fast Mode  
400 kbps  
Min  
Units  
Min  
—
Max  
100  
—
Max  
400  
—
SCL Clock Frequency  
fSCL  
—
kHz  
μs  
Hold Time (Repeated)  
START Condition  
tHD:STA  
4.0  
0.6  
Low Period of the SCL Clock  
tLOW  
tHIGH  
4.7  
4.0  
—
—
1.3  
0.6  
—
—
μs  
μs  
HIGH Period of the SCL  
Clock  
Set-up Time for a Repeated  
START Condition  
tSU:STA  
4.7  
—
0.6  
—
μs  
Data Hold Time  
tHD:DAT  
tSU:DAT  
tr  
100  
250  
—
—
—
100  
100  
20  
—
—
ns  
ns  
ns  
Data Set-up Time  
Rise Time of Both SDA and  
SCL Signals  
1000  
300  
Fall Time of Both SDA and  
SCL Signals  
tf  
—
300  
—
—
300  
—
ns  
μs  
μs  
Set-up Time for STOP Con-  
dition  
tSU:STO  
4.0  
4.7  
0.6  
1.3  
Bus Free Time between a  
tBUF  
—
—
STOP and START Condition  
Data Valid Time  
tVD:DAT  
tVD:ACK  
—
—
3.45  
3.45  
—
—
0.9  
0.9  
μs  
μs  
Data Valid Acknowledge  
Time  
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Electrical Specifications  
Figure 5.1. I2C Serial Port Timing Standard and Fast Modes  
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Electrical Specifications  
Table 5.10. SPI Timing Specifications (4-Wire)  
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, TA= -40 to 85°C)  
Parameter  
Symbol  
fSPI  
Min  
—
40  
50  
—
—
—
5
Typ  
—
Max  
20  
60  
—
Units  
MHz  
%
SCLK Frequency  
SCLK Duty Cycle  
SCLK Period  
TDC  
TC  
—
—
ns  
Delay Time, SCLK Fall to SDO Active  
Delay Time, SCLK Fall to SDO  
Delay Time, CSb Rise to SDO Tri-State  
Setup Time, CSb to SCLK  
TD1  
12.5  
10  
10  
—
18  
15  
15  
—
ns  
TD2  
ns  
TD3  
ns  
TSU1  
TH1  
TSU2  
TH2  
ns  
Hold Time, CSb to SCLK Rise  
5
—
—
ns  
Setup Time, SDI to SCLK Rise  
Hold Time, SDI to SCLK Rise  
5
—
—
ns  
5
—
—
ns  
Delay Time Between Chip Selects (CSb)  
TCS  
2
—
—
TC  
TD1  
TC  
TSU1  
SCLK  
CSb  
TH1  
TSU2  
TH2  
TCS  
SDI  
TD2  
TD3  
SDO  
Figure 5.2. 4-Wire SPI Serial Interface Timing  
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Electrical Specifications  
Table 5.11. SPI Timing Specifications (3-Wire)  
(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, TA= -40 to 85°C)  
Parameter  
Symbol  
fSPI  
Min  
—
40  
50  
—
—
—
5
Typ  
—
Max  
20  
60  
—
Units  
MHz  
%
SCLK Frequency  
SCLK Duty Cycle  
SCLK Period  
TDC  
TC  
—
—
ns  
Delay Time, SCLK Fall to SDO Turn-on  
Delay Time, SCLK Fall to SDO Next-bit  
Delay Time, CSb Rise to SDO Tri-State  
Setup Time, CSb to SCLK  
TD1  
12.5  
10  
10  
—
20  
15  
15  
—
ns  
TD2  
ns  
TD3  
ns  
TSU1  
TH1  
TSU2  
TH2  
ns  
Hold Time, CSb to SCLK Rise  
5
—
—
ns  
Setup Time, SDI to SCLK Rise  
5
—
—
ns  
Hold Time, SDI to SCLK Rise  
5
—
—
ns  
Delay Time Between Chip Selects (CSb)  
TCS  
2
—
—
TC  
TSU1  
TC  
SCLK  
TH1  
TD1  
TD2  
CSb  
TSU2  
TH2  
TCS  
SDIO  
TD3  
Figure 5.3. 3-Wire SPI Serial Interface Timing  
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Electrical Specifications  
Table 5.12. Crystal Specifications  
Test Condition  
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
Crystal Frequency Range  
fXTAL  
Full operating range. Jitter per-  
formance may be reduced.  
24.97  
—
54.06  
MHz  
Range for best jitter.  
48  
—
—
—
8
54  
—
MHz  
pF  
Load Capacitance  
CL  
dL  
Crystal Drive Level  
—
200  
μW  
Equivalent Series Resistance  
Shunt Capacitance  
rESR  
CO  
Refer to the Si5341/40 Family Reference Manual to determine ESR and shunt ca-  
pacitance.  
Note:  
1. Refer to the Si5341/40 Family Reference Manual for recommended 48 to 54 MHz crystals. The Si5341/40 are designed to work  
with crystals that meet these specifications.  
Table 5.13. Thermal Characteristics  
Test Condition1  
Parameter  
Symbol  
Value  
Units  
Si5341 - 64QFN  
Thermal Resistance  
Junction to Ambient  
ϴJA  
Still Air  
22  
°C/W  
Air Flow 1 m/s  
Air Flow 2 m/s  
19.4  
18.3  
9.5  
Thermal Resistance  
Junction to Case  
ϴJC  
Thermal Resistance  
Junction to Board  
ϴJB  
ΨJB  
ΨJT  
9.4  
9.3  
0.2  
Thermal Resistance  
Junction to Top Center  
Si5340 - 44QFN  
Thermal Resistance  
Junction to Ambient  
ϴJA  
Still Air  
22.3  
19.4  
18.4  
10.9  
°C/W  
Air Flow 1 m/s  
Air Flow 2 m/s  
Thermal Resistance  
Junction to Case  
ϴJC  
Thermal Resistance  
Junction to Board  
ϴJB  
ΨJB  
ΨJT  
9.3  
9.2  
Thermal Resistance  
Junction to Top Center  
Note:  
0.23  
1. Based on PCB Dimension: 3 x 4.5 mm, PCB Land/Via under GND pad: 36, Number of Cu Layers: 4  
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Electrical Specifications  
Table 5.14. Absolute Maximum Ratings1, 2, 3, 4  
Parameter  
Storage Temperature Range  
DC Supply Voltage  
Symbol  
TSTG  
Test Condition  
Value  
Units  
°C  
V
-55 to +150  
-0.5 to 3.8  
-0.5 to 3.8  
-0.5 to 3.8  
VDD  
VDDA  
V
5
V
VDDO  
Input Voltage Range  
VI1  
VI2  
IN0-IN2, FB_IN  
-0.85 to 3.8  
-0.5 to 3.8  
V
V
IN_SEL[1:0], RSTb, OEb,  
SYNCb, I2C_SEL, SDI, SCLK,  
A0/CSb, A1, SDA/SDIO, FINC/  
FDEC  
VI3  
LU  
XA/XB  
-0.5 to 2.7  
V
Latch-up Tolerance  
JESD78 Compliant  
ESD Tolerance  
HBM  
TJCT  
TPEAK  
100 pF, 1.5 kΩ  
2.0  
125  
260  
kV  
°C  
°C  
Maximum Junction Temperature in Operation  
Soldering Temperature (Pb-free profile)5  
Soldering Temperature Time at TPEAK  
TP  
20 to 40  
sec  
(Pb-free profile)5  
Notes:  
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to  
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-  
tended periods may affect device reliability.  
2. 64-QFN and 44-QFN packages are RoHS-6 compliant.  
3. Moisture sensitivity level is MSL2. For more packaging information, go to the Silicon Labs RoHS information page.  
4. The minimum voltage at these pins can be as low as –1.0 V when an AC input signal of 10 MHz or greater is applied. See Table  
5.3 Input Clock Specifications on page 20 spec for single-ended AC-coupled fIN < 250 MHz.  
5. The device is compliant with JEDEC J-STD-020.  
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Typical Application Schematic  
6. Typical Application Schematic  
Buffer  
Buffer  
161.1328125  
MHz  
133.33 MHz  
2x 161.1328125 MHz  
LVDS  
2x 133.33 MHz  
1.8V LVCMOS  
Buffer  
Level  
Delay Line  
Translator  
3x 125 MHz  
LVPECL  
125 MHz  
Buffer  
Clock  
Generator  
4x 125 MHz  
3.3V LVCMOS  
Level  
Translator  
XA  
25 MHz  
200 MHz  
2.5V LVCMOS  
XB  
“Traditional Discrete” Clock Tree  
One Si5341 replaces:  
3x crystal oscillators (XO)  
2x buffers  
1x Clock Generator  
2x level translators  
1x delay line  
1x 161.1328125 MHz  
LVDS  
1x 161.1328125 MHz  
LVDS  
XA  
XB  
2x 133.33 MHz  
1.8V LVCMOS  
25 MHz  
1x 125 MHz  
LVPECL  
1x 125 MHz  
LVPECL  
Si5341  
1x 125 MHz  
LVPECL  
2x 125 MHz  
3.3V LVCMOS  
2x 125 MHz  
3.3V LVCMOS  
2x 200 MHz  
2.5V LVCMOS  
“Clock Tree  
On-a-Chip”  
2x 200 MHz  
2.5V LVCMOS  
Figure 6.1. Using the Si5341 to Replace a Traditional Clock Tree  
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Detailed Block Diagrams  
7. Detailed Block Diagrams  
3
IN_SEL[1:0]  
Si5341  
Dividers/  
Drivers  
Clock  
Generator  
VDDO0  
OUT0  
OUT0b  
IN0  
÷P0  
÷P1  
÷P2  
÷R0  
IN0b  
VDDO1  
OUT1  
OUT1b  
IN1  
PLL  
PD  
IN1b  
÷R1  
÷R2  
÷R3  
÷R4  
÷R5  
÷R6  
÷R7  
÷R8  
÷R9  
IN2  
VDDO2  
OUT2  
OUT2b  
LPF  
IN2b  
Mn  
÷
VDDO3  
OUT3  
OUT3b  
M
d
VDDO4  
OUT4  
OUT4b  
P
XAXB  
÷
MultiSynth  
N0n  
XB  
25-54 MHz  
XTAL  
VDDO5  
OUT5  
OUT5b  
÷
÷
÷
÷
÷
t0  
OSC  
N0d  
XA  
N1n  
N1d  
t1  
t2  
VDDO6  
OUT6  
OUT6b  
Zero Delay  
Mode  
N2n  
N2d  
VDDO7  
OUT7  
OUT7b  
FB_IN  
÷Pfb  
FB_INb  
N3n  
N3d  
VDDO8  
OUT8  
OUT8b  
t3  
t4  
N4n  
N4d  
I2C_SEL  
VDDO9  
OUT9  
OUT9b  
SDA/SDIO  
SPI /  
I2C  
A1/SDO  
SCLK  
NVM  
Frequency  
Control  
Status  
Monitors  
A0/CSb  
Figure 7.1. Si5341 Block Diagram  
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Detailed Block Diagrams  
2
1
4
Si5340  
Clock  
÷PXAXB  
OSC  
Generator  
XB  
XA  
25-54 MHz  
XTAL  
Dividers/  
Drivers  
MultiSynth  
Nn0  
VDDO0  
OUT0  
OUT0b  
÷
t0  
t1  
t2  
t3  
÷R0  
Nd0  
PLL  
VDDO1  
OUT1  
OUT1b  
Nn1  
Nd1  
÷
÷
÷
÷R1  
÷R2  
÷R3  
IN0  
LPF  
PD  
÷P  
0
Md  
÷
IN0b  
VDDO2  
OUT2  
OUT2b  
Mn  
N2n  
N2d  
IN1  
÷P  
1
IN1b  
VDDO3  
OUT3  
OUT3b  
IN2  
N3n  
N3d  
÷P  
2
IN2b  
IN_SEL[1:0]  
Zero Delay  
Mode  
FB_IN  
÷P  
fb  
SPI/  
I2C  
Status  
Monitors  
FB_INB  
NVM  
Figure 7.2. Si5340 Detailed Block Diagram  
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Typical Operating Characteristics  
8. Typical Operating Characteristics  
Figure 8.1. Integer Mode--48 MHz Crystal, 625 MHz Output (2.5 V LVDS)  
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Typical Operating Characteristics  
Figure 8.2. Integer Mode--48 MHz Crystal, 156.25 MHz Output (2.5 V LVDS)  
Figure 8.3. Fractional Mode--48 MHz Crystal, 155.52 MHz Output (2.5 V LVDS)  
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Si5341/40 Rev D Data Sheet  
Pin Descriptions  
9. Pin Descriptions  
Si 5341 64QFN  
Top View  
Si 5340 44QFN  
Top View  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
1
IN1  
FINC  
2
IN1b  
LOLb  
3
IN_SEL0  
VDD  
1
2
33  
IN1  
IN1b  
INTRb  
4
5
IN_SEL1  
SYNCb  
RSTb  
X1  
OUT 6  
OUT6b  
VDDO6  
OUT5  
32  
VDD  
3
31 OUT2  
IN_SEL0  
6
30  
4
OUT2b  
X1  
XA  
7
29  
5
VDDO2  
XA  
8
OUT5b  
VDDO 5  
I2C_SEL  
OUT4  
GND  
Pad  
GND  
Pad  
6
28 LOS_XAXBb  
XB  
9
XB  
27  
7
LOLb  
X2  
10  
11  
X2  
26 VDDS  
25 OUT1  
8
VDDA  
OEb  
9
VDDA  
IN2  
INTRb 12  
OUT4b  
VDDO4  
OUT3  
10  
11  
24  
23  
OUT1b  
VDDO1  
13  
14  
15  
VDDA  
IN2  
IN2b  
IN2b  
OUT3b  
VDDO 3  
SCLK 16  
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Pin Descriptions  
Table 9.1. Pin Descriptions  
Pin Type1  
Pin Name  
Pin Number  
Function  
Si5341  
Si5340  
Inputs  
XA  
XB  
8
9
5
6
I
I
Crystal and External Clock Input. These pins are used to con-  
nect an external crystal or an external clock. See 3.3.1 XA/XB  
Clock and Crystal Input and Figure 3.2 XAXB External Crystal and  
Clock Connections on page 5 for connection information. If  
IN_SEL[1:0] = 11b, then the XAXB input is selected. If the XAXB  
input is not used and powered down, then both inputs can be left  
unconnected. ClockBuilder Pro will power down an input that is  
set as "Unused".  
X1  
X2  
7
4
7
I
I
XTAL Shield. Connect these pins directly to the XTAL ground  
pins. X1, X2, and the XTAL ground pins must not be connected to  
the PCB ground plane. DO NOT GROUND THE CRYSTAL  
GROUND PINS. Refer to the Si5341/40 Family Reference Manual  
for layout guidelines. These pins should be left disconnected  
when connecting XA/XB pins to an external reference clock.  
10  
IN0  
IN0b  
IN1  
63  
64  
1
43  
44  
1
I
I
I
I
I
I
I
I
Clock Inputs. These pins accept both differential and single-  
ended clock signals. Refer 3.3.2 Input Clocks (IN0, IN1, IN2) for  
input termination options. These pins are high-impedance and  
must be terminated externally. If both the INx and INx (with over-  
strike) inputs are un-used and powered down, then both inputs  
can be left floating. ClockBuilder Pro will power down an input that  
is set as "Unused".  
IN1b  
IN2  
2
2
14  
15  
61  
62  
10  
11  
41  
42  
IN2b  
FB_IN  
FB_INb  
External Feedback Input. These pins are used as the external  
feedback input (FB_IN/FB_INb) for the optional zero delay mode.  
See 3.5.12 Zero Delay Mode for details on the optional zero delay  
mode. If FB_IN and FB_IN (with overstrike) are un-used and pow-  
ered down, then both inputs can be left floating. ClockBuilder Pro  
will power down an input that is set as "Unused".  
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Rev. 1.0 | 39  
Si5341/40 Rev D Data Sheet  
Pin Descriptions  
Pin Type1  
Pin Name  
Pin Number  
Function  
Si5341  
Si5340  
Outputs  
OUT0  
OUT0b  
OUT1  
24  
23  
28  
27  
31  
30  
35  
34  
38  
37  
42  
41  
45  
44  
51  
50  
54  
53  
59  
58  
20  
19  
25  
24  
31  
30  
36  
35  
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Output Clocks. These output clocks support a programmable  
signal amplitude when configured as a differential output. Desired  
output signal format is configurable using register control. Termi-  
nation recommendations are provided in 3.5.2 Differential Output  
Terminations and 3.5.4 LVCMOS Output Terminations. Unused  
outputs should be left unconnected.  
OUT1b  
OUT2  
OUT2b  
OUT3  
OUT3b  
OUT4  
OUT4b  
OUT5  
OUT5b  
OUT6  
OUT6b  
OUT7  
OUT7b  
OUT8  
OUT8b  
OUT9  
OUT9b  
Serial Interface  
I2C_SEL  
I2C Select.2 This pin selects the serial interface mode as I2C  
(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled  
up by a ~ 20 kΩ resistor to the voltage selected by the  
IO_VDD_SEL register bit.  
39  
18  
38  
13  
I
Serial Data Interface.2 This is the bidirectional data pin (SDA) for  
SDA/SDIO  
I/O  
the I2C mode, or the bidirectional data pin (SDIO) in the 3-wire  
SPI mode, or the input data pin (SDI) in 4-wire SPI mode. When  
in I2C mode, this pin must be pulled-up using an external resistor  
of at least 1 kΩ. No pull-up resistor is needed when in SPI mode.  
Address Select 1/Serial Data Output.2 In I2C mode, this pin  
functions as the A1 address input pin and does not have an inter-  
nal pull up or pull down resistor. In 4-wire SPI mode this is the se-  
rial data output (SDO) pin (SDO) pin and drives high to the volt-  
age selected by the IO_VDD_SEL pin.  
A1/SDO  
SCLK  
17  
16  
15  
14  
I/O  
Serial Clock Input.2 This pin functions as the serial clock input  
I
for both I2C and SPI modes.This pin is internally pulled up by a  
~20 kΩ resistor to the voltage selected by the IO_VDD_SEL regis-  
ter bit. In I2C mode this pin should have an external pull up of at  
least 1 kΩ. No pull-up resistor is needed when in SPI mode.  
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Rev. 1.0 | 40  
Si5341/40 Rev D Data Sheet  
Pin Descriptions  
Pin Type1  
Pin Name  
Pin Number  
Function  
Si5341  
Si5340  
Address Select 0/Chip Select.2 This pin functions as the hard-  
A0/CSb  
19  
16  
I
ware controlled address A0 in I2C mode. In SPI mode, this pin  
functions as the chip select input (active low). This pin is internally  
pulled up by a ~20 kΩ resistor to the voltage selected by the  
IO_VDD_SEL register bit.  
Control/Status  
Interrupt. 2 This pin is asserted low when a change in device sta-  
tus has occurred. This interrupt has a push pull output and should  
be left unconnected when not in use.  
INTRb  
12  
6
33  
17  
O
I
Device Reset. 2 Active low input that performs power-on reset  
(POR) of the device. Resets all internal logic to a known state and  
forces the device registers to their default values. Clock outputs  
are disabled during reset. This pin is internally pulled up with a  
~20 kΩ resistor to the voltage selected by the IO_VDD_SEL bit.  
RSTb  
Output Enable.2 This pin disables all outputs when held high.  
This pin is internally pulled low and can be left unconnected when  
not in use.  
OEb  
11  
47  
—
12  
—
27  
I
Loss Of Lock.2 This output pin indicates when the DSPLL™ is  
locked (high) or out-of-lock (low). An external pull up or pull down  
is not needed.  
LOLb  
O
O
Loss Of Lock.3 This output pin indicates when the DSPLL is  
locked (high) or out-of-lock (low). An external pull up or pull down  
is not needed.  
Loss Of Signal.3 This output pin indicates a loss of signal at the  
XA/XB pins.  
LOS_XAXBb  
SYNCb  
—
5
28  
—
O
I
Output Clock Synchronization.2 An active low signal on this pin  
resets the output dividers for the purpose of re-aligning the output  
clocks. For a tighter alignment of the clocks, a soft reset should be  
applied. This pin is internally pulled up with a ~20 kΩ resistor to  
the voltage selected by the IO_VDD_SEL bit and can be left un-  
connected when not in use.  
Frequency Decrement Pin.2 This pin is used to step-down the  
output frequency of a selected output. The affected output driver  
and its frequency change step size is register configurable. This  
pin is internally pulled low with a ~20 kΩ resistor and can be left  
unconnected when not in use.  
FDEC  
FINC  
25  
48  
—
—
I
I
Frequency Increment Pin.2 This pin is used to step-up the out-  
put frequency of a selected output. The affected output and its fre-  
quency change step size is register configurable. This pin is inter-  
nally pulled low with a ~20 kΩ resistor and can be left unconnec-  
ted when not in use.  
Input Reference Select.2 The IN_SEL[1:0] pins are used in the  
manual pin controlled mode to select the active clock input. These  
pins are internally pulled up with a ~20 kΩ resistor to the voltage  
selected by the IO_VDD_SEL bit and can be left unconnected  
when not in use.  
IN_SEL0  
IN_SEL1  
3
4
3
I
I
37  
RSVD  
20  
21  
55  
56  
—
—
—
—
—
—
—
—
Reserved. These pins are connected to the die. Leave discon-  
nected.  
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Rev. 1.0 | 41  
Si5341/40 Rev D Data Sheet  
Pin Descriptions  
Pin Type1  
Pin Name  
Pin Number  
Function  
Si5341  
Si5340  
NC  
—
22  
—
No Connect. These pins are not connected to the die. Leave dis-  
connected.  
Power  
VDD  
32  
46  
60  
—
13  
—
—
21  
32  
39  
40  
8
P
Core Supply Voltage. The device core operates from a 1.8 V  
supply. A 1.0 µf bypass capacitor is recommended.  
VDDA  
VDDS  
P
P
P
Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V  
power source. A 1.0 µf bypass capacitor is recommended.  
9
26  
Status Output Voltage. The voltage on this pin determines the  
VOL/VOH on LOLb and LOS_XAXBb status output pins. A 0.1 µf to  
1.0 µf bypass capacitor is recommended.  
VDDO0  
VDDO1  
VDDO2  
VDDO3  
VDDO4  
VDDO5  
VDDO6  
VDDO7  
VDDO8  
VDDO9  
GND PAD  
22  
26  
29  
33  
36  
40  
43  
49  
52  
57  
18  
23  
29  
34  
—
—
—
—
—
—
P
P
P
P
P
P
P
P
P
P
P
Output Clock Supply Voltage 0–9. Supply voltage (3.3 V, 2.5 V,  
1.8 V) for OUTx, OUTx outputs. See the Si5341/40 Family Refer-  
ence Manual for power supply filtering recommendations. Leave  
VDDO pins of unused output drivers unconnected. An alternate  
option is to connect the VDDO pin to a power supply and disable  
the output driver to minimize current consumption.  
Ground Pad This pad provides electrical and thermal connection  
to ground and must be connected for proper operation. Use as  
many vias as practical and keep the via length to an internal  
ground plan as short as possible.  
Note:  
1. I = Input, O = Output, P = Power.  
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.  
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.  
4. Refer to the Family Reference Manual for more information on register setting names.  
5. All status pins except I2C and SPI are push-pull.  
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Rev. 1.0 | 42  
Si5341/40 Rev D Data Sheet  
Package Outlines  
10. Package Outlines  
10.1 Si5341 9x9 mm 64-QFN Package Diagram  
The figure below illustrates the package details for the Si5341. The table below lists the values for the dimensions shown in the illustra-  
tion.  
Figure 10.1. 64-Pin Quad Flat No-Lead (QFN)  
Table 10.1. Package Dimensions  
Dimension  
Min  
0.80  
0.00  
0.18  
Nom  
0.85  
Max  
0.90  
0.05  
0.30  
A
A1  
b
0.02  
0.25  
D
9.00 BSC  
5.20  
D2  
e
5.10  
5.30  
0.50 BSC  
9.00 BSC  
5.20  
E
E2  
L
5.10  
0.30  
—
5.30  
0.50  
0.15  
0.10  
0.08  
0.10  
0.05  
0.40  
aaa  
bbb  
ccc  
ddd  
eee  
—
—
—
—
—
—
—
—
—
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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Rev. 1.0 | 43  
Si5341/40 Rev D Data Sheet  
Package Outlines  
10.2 Si5340 7x7 mm 44-QFN Package Diagram  
The figure below illustrates the package details for the Si5340. The table below lists the values for the dimensions shown in the illustra-  
tion.  
Figure 10.2. 44-Pin Quad Flat No-Lead (QFN)  
Table 10.2. Package Dimensions  
Dimension  
Min  
0.80  
0.00  
0.18  
Nom  
0.85  
Max  
0.90  
0.05  
0.30  
A
A1  
b
0.02  
0.25  
D
7.00 BSC  
5.20  
D2  
e
5.10  
5.30  
0.50 BSC  
7.00 BSC  
5.20  
E
E2  
L
5.10  
0.30  
—
5.30  
0.50  
0.15  
0.10  
0.08  
0.10  
0.40  
aaa  
bbb  
ccc  
ddd  
—
—
—
—
—
—
—
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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Rev. 1.0 | 44  
Si5341/40 Rev D Data Sheet  
PCB Land Pattern  
11. PCB Land Pattern  
The figure below illlustrates the PCB land pattern details for the devices. The table below lists the values for the dimensions shown in  
the illustration.  
Si5341  
Si5340  
Figure 11.1. PCB Land Pattern  
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Rev. 1.0 | 45  
Si5341/40 Rev D Data Sheet  
PCB Land Pattern  
Table 11.1. PCB Land Pattern Dimensions  
Dimension  
Si5341 (Max)  
8.90  
Si5340 (Max)  
C1  
C2  
E
6.90  
6.90  
0.50  
0.30  
0.85  
5.30  
5.30  
8.90  
0.50  
X1  
Y1  
X2  
Y2  
0.30  
0.85  
5.30  
5.30  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication  
Allowance of 0.05 mm.  
Solder Mask Design  
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
Stencil Design  
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
2. The stencil thickness should be 0.125 mm (5 mils).  
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.  
4. A 3×3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.  
Card Assembly  
1. A No-Clean, Type-3 solder paste is recommended.  
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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Rev. 1.0 | 46  
Si5341/40 Rev D Data Sheet  
Top Marking  
12. Top Marking  
Si 5341g-  
Si 5340g-  
Rxxxxx- GM  
YYWWTTTTTT  
Rxxxxx- GM  
YYWWTTTTTT  
e 4  
TW  
e 4  
TW  
64-QFN  
44-QFN  
Figure 12.1. Si5341-40 Top Markings  
Table 12.1. Si5341-40 Top Marking Explanation  
Line  
Characters  
Si5341g-  
Description  
1
Base part number and Device Grade for Low Jitter, Any-Frequency, 10-output Clock  
Generator.  
Si5340g-  
Si5341: 10-output, 64-QFN  
Si5340: 4-output, 44-QFN  
g = Device Grade (A, B, C, D). See " " on page 26 for more information.  
– = Dash character.  
2
Rxxxxx-GM  
R = Product revision. (See ordering guide for current revision).  
xxxxx = Customer specific NVM sequence number. Optional NVM code assigned for  
custom, factory pre-programmed devices.  
Characters are not included for standard, factory default configured devices. See Or-  
dering Guide for more information.  
–GM = Package (QFN) and temperature range (–40 to +85 °C)  
3
YYWWTTTTTT  
YYWW = Characters correspond to the year (YY) and work week (WW) of package  
assembly.  
TTTTTT = Manufacturing trace code.  
4
Circle w/ 1.6 mm (64-QFN) or Pin 1 indicator; left-justified  
1.4 mm (44-QFN) diameter  
e4  
Pb-free symbol; Center-Justified  
TW  
TW = Taiwan; Country of Origin (ISO Abbreviation)  
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Rev. 1.0 | 47  
Si5341/40 Rev D Data Sheet  
Device Errata  
13. Device Errata  
Please log in or register at www.silabs.com to access the device errata document.  
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Rev. 1.0 | 48  
Si5341/40 Rev D Data Sheet  
Document Change List  
14. Document Change List  
14.1 Revision 1.0  
July 15, 2016  
• Initial release.  
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Rev. 1.0 | 49  
Table of Contents  
1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
3.1 Power-up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 4  
3.2 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
3.3 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
3.3.1 XA/XB Clock and Crystal Input . . . . . . . . . . . . . . . . . . . . . . . 5  
3.3.2 Input Clocks (IN0, IN1, IN2) . . . . . . . . . . . . . . . . . . . . . . . . 6  
3.3.3 Input Selection (IN0, IN1, IN2, XA/XB) . . . . . . . . . . . . . . . . . . . . . 7  
3.4 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3.4.1 Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3.4.2 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3.5 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.5.1 Output Signal Format. . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.5.2 Differential Output Terminations . . . . . . . . . . . . . . . . . . . . . . . 8  
3.5.3 Programmable Common Mode Voltage for Differential Outputs. . . . . . . . . . . . . 8  
3.5.4 LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . . 9  
3.5.5 LVCMOS Output Impedance and Drive Strength Selection . . . . . . . . . . . . . . 9  
3.5.6 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . . 9  
3.5.7 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.5.8 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.5.9 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . . . 9  
3.5.10 Synchronous/Asynchronous Output Disable Feature. . . . . . . . . . . . . . . .10  
3.5.11 Output Delay Control (t -t ) . . . . . . . . . . . . . . . . . . . . . . . .10  
0 4  
3.5.12 Zero Delay Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
3.5.13 Sync Pin (Synchronizing R Dividers) . . . . . . . . . . . . . . . . . . . . .11  
3.5.14 Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
3.5.15 Digitally Controlled Oscillator (DCO) Modes. . . . . . . . . . . . . . . . . . .12  
3.5.15.1 DCO with Frequency Increment/Decrement Pins/Bits . . . . . . . . . . . . . . .12  
3.5.15.2 DCO with Direct Register Writes . . . . . . . . . . . . . . . . . . . . . .12  
3.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
3.7 In-Circuit Programming. . . . . . . . . . . . . . . . . . . . . . . . . . .12  
3.8 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
3.9 Custom Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . .12  
3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-  
Programmed Devices  
. . . . . . . . . . . . . . . . . . . . . . . . . . 13.  
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
4.1 Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . .15  
4.2 High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . .16  
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 33  
Table of Contents 50  
7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
8. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . 36  
9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
10.1 Si5341 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . .43  
10.2 Si5340 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . .44  
11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
14. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
14.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49  
Table of Contents 51  
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code libraries & more. Available for  
Windows and iOS (CBGo only).  
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Disclaimer  
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or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and  
"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to  
make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the  
included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses  
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相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

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SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

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SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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