SI5350B-A01201-GTR [SILICON]
Clock Generator;
| 型号： | SI5350B-A01201-GTR |
| 厂家： | 
SILICON |
| 描述： | Clock Generator |
| 文件： | 总24页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5350B
FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS
CLOCK GENERATOR + VCXO
Features
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
Exact frequency synthesis at each
output (0 ppm error)
Highly linear VCXO gain (kv)
Glitchless frequency changes
Configurable Spread Spectrum
selectable at each output
Operates from a low-cost, fixed
frequency AT-cut, non-pullable
crystal: 25 or 27 MHz
Separate voltage supply pins:
Core VDD: 2.5 V or 3.3 V
Output VDDO: 2.5 V or 3.3 V
Excellent PSRR eliminates external
power supply filtering
10-MSOP
24-QSOP
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Low output period jitter: 100 ps pp
Very low power consumption
(<40 mA)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Supports static phase offset
Rise/fall time control
Available in 3 packages types:
10-MSOP: 3 outputs
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
20-QFN
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Residential gateways
Networking/communication
Servers, storage
Ordering Information:
XO replacement
See page 19
Description
The Si5350B combines a clock generator and VCXO function into a single device. A
flexible architecture enables this user definable custom timing device to generate
any of the specified output frequencies from either the internal PLL or the VCXO.
This allows the Si5350B to replace multiple crystals, crystal oscillators, and VCXOs.
Custom pin-controlled Si5350B devices are requested using the ClockBuilder web-
based utility (www.silabs.com/ClockBuilder).
Functional Block Diagram
20-QFN, 24-QSOP
Multi
Synth
0
CLK0
CLK1
10-MSOP
XA
Multi
Synth
1
XA
XB
Vc
OSC
PLL
Multi
Synth
2
Multi
Synth
0
XB
Vc
CLK2
CLK3
CLK0
CLK1
OSC
PLL
Multi
Synth
3
Multi
Synth
1
VCXO
VCXO
Multi
Synth
4
Multi
Synth
2
CLK4
CLK5
CLK6
CLK7
CLK2
Multi
Synth
5
P0
P1
P2
P3
Control
Logic
P0
Control
Logic
Multi
Synth
6
Si5350B
Multi
Synth
7
Si5350B
Rev. 0.9 5/11
Copyright © 2011 by Silicon Laboratories
Si5350B
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5350B
2
Rev. 0.9
Si5350B
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si5350B Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Replacing a Crystal with a Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4. Configuring the Si5350B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.3. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.4. Voltage Control Input (VC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5. Pin Descriptions (20-QFN, 24-QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6. Pin Descriptions (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8. Package Outline (24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
9. Package Outline (20-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
10. Package Outline (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Rev. 0.9
3
Si5350B
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
–40
3.0
Typ
25
Max
85
Unit
°C
V
Ambient Temperature
T
A
3.3
2.5
2.5
3.3
3.60
2.75
2.75
3.60
Core Supply Voltage
Output Buffer Voltage
V
DD
2.25
2.25
3.0
V
V
V
DDOx
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Enabled 3 outputs
Min
—
Typ
20
Max
30
Unit
mA
mA
µA
Core Supply Current*
I
Enabled 8 outputs
—
25
40
DD
Power Down (PDN = V
)
—
—
15
DD
Output Buffer Supply Current
(Per Output)*
I
C = 5 pF
—
2.0
4.5
mA
DDOx
L
Pins P0, P1, P2, P3
Vin < 3.6 V
I
—
—
—
—
10
30
µA
µA
P0-P3
Input Current
I
VC
VC
8 mA output drive current,
see Design Considerations
section
Output Impedance
Z
—
85
—
OI
*Note: Output clocks less than or equal to 133 MHz.
4
Rev. 0.9
Si5350B
Table 3. AC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Vc
Test Condition
Min
0
Typ
Max
Unit
V
VCXO Control Voltage Range
VCXO Gain (configurable)
VCXO Control Voltage Linearity
V
/2
V
DD
DD
kv
Vc = 10–90% of V
Vc = 10–90% of V
18
–5
—
150
+5
ppm/V
%
DD
DD
KVL
—
0
VCXO Pull Range
(configurable)*
V
= 3.3 V
DD
PR
±30
—
±240
—
ppm
kHz
Vc = 10–90% of V
DD
VCXO Modulation Bandwidth
10
From V = V
to valid
DDmin
DD
Power-Up Time
TRDY
output clock, C = 5 pF,
—
—
—
2
5
10
100
10
ms
ms
µs
L
f
> 1 MHz
CLKn
From V = V
,
DDmin
DD
Power-Down Time
Output Enable Time
T
T
PD
C = 5 pF, f
> 1 MHz
L
CLKn
From OEB assertion to valid
clock output, C = 5 pF,
—
OE
L
f
> 1 MHz
CLKn
Output Frequency Transition
Time
T
f
> 1 MHz
—
–0.5
30
—
—
10
–2.5
33
µs
%
FREQ
CLKn
Spread Spectrum Frequency
Deviation
SS
Down spread
DEV
Spread Spectrum Modulation
Rate
SS
31.5
kHz
MOD
*Note: Contact Silicon Labs for VCXO operation at 2.5 V.
Table 4. Input Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
—
Max
Units
k
V
VC Input Resistance
P0-P3 Input Low Voltage
P0-P3 Input High Voltage
100
–0.1
—
0.3 x V
3.60
VIL-P0-3
VIH_P0-3
—
DD
V
0.7 x V
—
DD
Rev. 0.9
5
Si5350B
Table 5. Output Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
F < 100 MHz
CLK
Min
0.008
—
Typ
—
—
50
1
Max
160
15
Units
MHz
pF
Frequency Range
Load Capacitance
Duty Cycle
FCLK
C
L
DC
Measured at V /2
45
55
%
DD
Rise/Fall Time
t /t
20% - 80%, C = 5 pF
0.5
1.5
—
ns
r f
L
Output High Voltage
Output Low Voltage
Period Jitter
VOH
VOL
V
– 0.6
—
—
60
60
50
V
DD
—
0.6
100
110
90
V
JPER
—
—
—
ps pk-pk
ps pk-pk
ps pk
Measured over 10k cycles
Measured over 10k cycles
12 kHz–20 MHz
Period Jitter, VCXO
Cycle-to-Cycle Jitter
JPER_VCXO
JCC
Cycle-to-Cycle Jitter,
VCXO
JCC_VCXO
—
50
95
ps pk
RMS Phase Jitter
RMS Phase Jitter
JRMS
—
—
3.5
8.5
11
ps
JRMS_VCXO
18.5
ps rms
Table 6. 25 MHz Crystal Requirements1,2
Parameter
Symbol
Min
—
6
Typ
Max
Unit
MHz
pF
Crystal Frequency
Load Capacitance
f
25
—
—
XTAL
C
12
L
Equivalent Series Resistance
r
—
—
—
—
150
100
ESR
Crystal Max Drive Level
d
µW
L
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors. Adding external 2 pF load
capacitors can minimize jitter by 20%.
2. Refer to “AN551: Crystal Selection Guide” for more details.
6
Rev. 0.9
Si5350B
Table 7. 27 MHz Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
f
—
27
—
MHz
XTAL
Load Capacitance
C
6
TBD
12
pF
L
Equivalent Series Resistance
r
—
—
—
—
150
100
ESR
Crystal Max Drive Level Spec
d
µW
L
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors. Adding external 2 pF load
capacitors can minimize jitter by 20%.
2. Refer to “AN551: Crystal Selection Guide” for more details.
Table 8. Thermal Characteristics
Parameter
Symbol
Test Condition
Package
10-MSOP
24-QSOP
20-QFN
Value
131
80
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junc-
tion to Ambient
Still Air
JA
51
10-MSOP
24-QSOP
20-QFN
43
Thermal Resistance Junc-
tion to Case
Still Air
31
JC
16
Table 9. Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Value
Unit
V
DC Supply Voltage
V
–0.5 to 3.8
–0.5 to 3.8
DD_max
VIN_P0-3 Pins P0, P1, P2, P3
V
VIN_VC
VC
–0.5 to (VDD+0.3)
V
Input Voltage
VIN_XA/
B
Pins XA, XB
–0.5 to 1.3 V
–55 to 150
V
Temperature Range
T
°C
J
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Rev. 0.9
7
Si5350B
2. Typical Application
2.1. Si5350B Replaces Multiple Clocks and XOs
The Si5350B is a clock generation device that provides both synchronous and free-running clocks for applications
where power, board size, and cost are critical. An application where both free-running and synchronous clocks are
required is shown in Figure 1.
Ethernet
PHY
XA
XB
CLK0
CLK1
Multi
Synth
0
125 MHz
48 MHz
OSC
PLL
27 MHz
Multi
Synth
1
USB
Controller
CLK2
CLK3
Multi
Synth
2
28.322 MHz
74.25 MHz
HDMI
Port
Multi
Synth
3
VC
VCXO
CLK4
CLK5
Multi
Synth
4
74.25/1.001 MHz
24.576 MHz
Video/Audio
Processor
Multi
Synth
5
Si5350B
Figure 1. Example of an Si5350B in an Audio/Video Application
2.2. Replacing a Crystal with a Clock
The Si5350B can be driven with a clock signal through the XA input pin.
VIN = 1 VPP
25/27 MHz
Multi
Synth
0
PLLA
PLLB
XA
Multi
Synth
1
0.1 µF
OSC
XB
Multi
Synth
N
Note: Float the XB input while driving
the XA input with a clock
Figure 2. Si5350B Driven by a Clock Signal
8
Rev. 0.9
Si5350B
2.3. HCSL Compatible Outputs
The Si5350B can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair.
ZO = 70
R1
Multi
Synth
0
PLLA
PLLB
0
0
511
240
R2
OSC
HCSL
CLKIN
ZO = 70
R1
Multi
Synth
1
511
240
R2
Multi
Synth
N
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
Figure 3. Si5350B Output is HCSL Compatible
Rev. 0.9
9
Si5350B
3. Functional Description
The Si5350B features a high-frequency PLL, a high-frequency VCXO and a high-resolution fractional MultiSynthTM
divider on each output. A block diagram of both the 3-output and the 8-output clock generators are shown in
Figure 4. Free-running clocks are generated from the on-chip oscillator + PLL, and a separate voltage controlled
oscillator (VCXO) is used to generate synchronous clocks. A fixed-frequency non-pullable standard AT-cut crystal
provides frequency stability for both the internal oscillator and VCXO. The flexible synthesis architecture of the
Si5350B generates up to eight non-integer related frequencies and any combination of free-running and/or
synchronous clocks.
VDDO
VDD
10-MSOP
MultiSynth 0
F1_0
XA
XB
PLL
R0
R1
R2
CLK0
CLK1
CLK2
OSC
F2_0
FS
FS
FS
MultiSynth 1
F1_1
VCXO
VC
F2_1
MultiSynth 2
F1_2
Control
Logic
P0
F2_2
MultiSynth 3
GND
VDD
20-QFN, 24-QSOP
MultiSynth 0
VDDOA
CLK0
F1_0
R0
F2_0
XA
XB
PLL
FS
FS
FS
FS
FS
FS
OSC
MultiSynth 1
CLK1
F1_1
R1
VCXO
VC
F2_1
MultiSynth 2
VDDOB
CLK2
F1_2
R2
F2_2
MultiSynth 3
CLK3
F1_3
R3
F2_3
MultiSynth 4
VDDOC
CLK4
F1_4
R4
F2_4
MultiSynth 5
CLK5
P0
P1
P2
P3
F1_5
R5
F2_5
Control
Logic
VDDOD
CLK6
MultiSynth 6
F1_6
R6
R7
MultiSynth 7
CLK7
F1_7
GND
Figure 4. Block Diagram of the 3 and 8 Output Si5350B Devices
10
Rev. 0.9
Si5350B
4. Configuring the Si5350B
The Si5350B is a factory-programmed custom clock generator that is user definable with a simple to use web-
based utility (www.silabs.com/ClockBuilder). The ClockBuilder utility provides a simple graphical interface that
allows the user to enter input and output frequencies along with other custom features as described in the following
sections. All synthesis calculations are automatically performed by ClockBuilder to ensure an optimum
configuration. A unique part number is assigned to each custom configuration.
4.1. Crystal Inputs (XA, XB)
The Si5350B uses a fixed-frequency non-pullable standard AT-cut crystal as a reference to synthesize its output
clocks and to provide the frequency stability for the VCXO.
4.1.1. Crystal Frequency
The Si5350B can operate using either a 25 MHz or a 27 MHz crystal.
4.1.2. Internal XTAL Load Capacitors
Internal load capacitors (C ) are provided to eliminate the need for external components when connecting a XTAL
L
to the Si5350B. Options for internal load capacitors are 6, 8, or 10 pF. XTALs with alternate load capacitance
requirements are supported using external load capacitors < 2 pF as shown in Figure 5.
CL
XA
XB
CL
Optional internal
load capacitors
6 pF, 8 pF, 10 pF
Optional additional
external load
capacitors
CL
CL
(< 2 pF)
Figure 5. External XTAL with Optional Load Capacitors
4.2. Output Clocks (CLK0–CLK7)
The Si5350B is orderable as a 3-output (10-MSOP) or 8-output (24-QSOP, 20-QFN) clock generator. Output clocks
CLK0 to CLK5 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the optional
frequency select pins (FS0/1). See “4.3.2. Frequency Select (FS_0, FS_1)” for more details on the operation of the
frequency select pins. Each output clock can select its reference either from the PLL or from the VCXO.
4.2.1. Output Clock Frequency
Outputs can be configured at any frequency from 8 kHz up to 100 MHz. In addition, the device can generate any
two non-integer related frequencies up to 160 MHz. See “AN554: Si5350/51 PCB Layout Guide” for details.
4.2.2. .Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. See AN554 for details. Note that
spread spectrum is not available on clocks synchronized to PLLB or to the VCXO.
The Si5350B supports several levels of spread spectrum allowing the designer to choose an ideal compromise
between system performance and EMI compliance. An optional spread spectrum enable pin (SSEN) is
configurable to enable or disable the spread spectrum feature. See “4.3.1. Spread Spectrum Enable (SSEN)” for
details.
Rev. 0.9
11
Si5350B
Reduced
Amplitude
and EMI
Center
Frequency
Amplitude
fc
fc
No Spread
Spectrum
Down Spread
Figure 6. Available Spread Spectrum Profiles
4.2.3. Invert/Non-Invert
By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to
invert any of the clock outputs is also available.
4.2.4. Output State When Disabled
There are up to three output enable pins configurable on the Si5350B as described in “5. Pin Descriptions (20-
QFN, 24-QSOP)” . The output state when disabled for each of the outputs is configurable as one of the following:
disable low, disable high, or disable in high-impedance.
4.2.5. Powering Down Unused Outputs
Unused clock outputs can be completely powered down to conserve power.
4.3. Programmable Control Pins (P0–P3) Options
Up to four programmable control pins (P0-P3) are configurable allowing direct pin control of the following features:
4.3.1. Spread Spectrum Enable (SSEN)
An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with
spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient
method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.
4.3.2. Frequency Select (FS_0, FS_1)
The Si5350B offers the option of configuring up to two frequencies per clock output (CLK0-CLK5) for either free-
running or synchronous clocks. This is a useful feature for applications that need to support more than one free-
running or synchronous clock rate on the same output. An example of this is shown in Figure 7. The FS pins select
which frequency is generated from the clock output. In this example FS0 select the output frequency on CLK0, and
FS1 selects the frequency on CLK1.
27 MHz
FS0
Bit Level
XA
XB
Free-running Frequency
0
F1_0:
F2_0:
74.25 MHz
Free-running Clock
74.25
74.25
MHz
1.001
1
MHz
74.25 MHz or
FS0
FS1
1.001
CLK0
CLK1
Video/Audio
Processor
Si5350B
Synchronous Clock
24.576 MHz or 22.5792 MHz
FS1
Bit Level
Synchronous Frequency
0
1
F1_1:
F2_1:
24.576 MHz
VC
22.5792 MHz
Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output
12
Rev. 0.9
Si5350B
Up to two frequency select pins are available on the Si5350B. Each of the frequency select pins can be linked to
any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency
selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and
CLK4. Any other combination is also possible.
The Si5350B uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock
always completes its last cycle before starting a new clock cycle of a different frequency.
Customizable FS Control
Glitchless Frequency Changes
FS
MultiSynth 0
CLK0
CLK1
FS
New frequency starts
at its leading edge
MultiSynth 1
FS_0
FS_1
FS_0
Output Frequency
F1_0, F1_3, F1_5
F2_0, F2_3, F2_5
0
1
FS
MultiSynth 2
CLK2
CLK3
Frequency_A
Frequency_B
FS
Frequency_A
MultiSynth 3
CLKx
FS
MultiSynth 4
CLK4
CLK5
CLK6
CLK7
FS_1
Output Frequency
F1_1, F1_2, F1_4
F2_1, F2_2, F2_4
0
1
MultiSynth 5
FS
Full cycle completes before
changing to a new frequency
Cannot be controlled
by FS pins
Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)
4.3.3. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350B. Similar to the FS pins, each OEB pin can
be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3,
and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and
CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin
forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
Customizable OEB Control
Glitchless Output Enable
CLK0
OEB
OEB_0
Output State
CLK Enabled
CLK Disabled
OEB_0
OEB_1
CLK1
0
1
OEB
Clock continues until
cycle is complete
Clock starts on the
first leading edge
CLK2
CLK3
OEB
OEB
OEB_1
Output State
CLK Enabled
CLK Disabled
CLKx
OEBx
0
1
CLK4
CLK5
CLK6
CLK7
OEB
OEB
OEB_2
Output State
CLK Enabled
CLK Disabled
OEB_2
OEB
OEB
0
1
Figure 9. Example Configuration of a Pin-Controlled Output Enable
Rev. 0.9
13
Si5350B
4.3.4. Power Down (PDN)
An optional power down control pin allows a full shutdown of the Si5350B to minimize power consumption when its
output clocks are not being used. The Si5350B is in normal operation when the PDN pin is held low and is in power
down mode when held high. Power consumption when the device is in power down mode is indicated in Table 2 on
page 4.
4.4. Voltage Control Input (VC)
The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, low-
cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 3 on page 5 for VCXO specification details.
A unique feature of the Si5350B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 10.
XA
XB
Fixed Frequency
Crystal (non-pullable)
Multi
Synth
1
OSC
CLK0
CLK1
CLK2
VC
Multi
Synth
0
Control
Voltage
VCXO
Additional MultiSynths can be
added to generate multiple
synchronous clocks with
Multi
Synth
2
different output frequencies
Figure 10. Generating One Or More Synchronous Clocks
4.4.1. Control Voltage Gain (kV)
The voltage level on the VC pin directly controls the output frequency. The rate of change in output clock frequency
(kv) is configurable from 18 ppm/V up to 150 ppm/V. This allows a configurable pull range from ±30 ppm to
±150 ppm @ V = 3.3 V as shown in Figure 11. Consult the factory for other pull range values.
DD
A key advantage of the VCXO design in the Si5350B is its highly linear tuning range. This allows better control of
PLL stability and jitter performance over the entire control voltage range.
14
Rev. 0.9
Si5350B
Pull-in Range
@ VDD = 3.3 V
1000
750
500
250
0
10
-10
-250
VDD
2
VDD
-500
-750
-1000
VC (Volts)
Figure 11. User-definable VCXO Pull Range
4.5. Design Considerations
The Si5350B is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance.
4.5.1. Power Supply Decoupling/Filtering
The Si5350B has built-in power supply filtering circuitry to help keep the number of external components to a
minimum. All that is recommended is one 0.1 µF decoupling capacitor per power supply pin. This capacitor should
be mounted as close to the VDD and VDDO pins as possible without using vias.
4.5.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. It is important that power is applied to all supply pins (VDD, VDDOx) at the same
time. Unused VDDOx pins should be tied to VDD.
4.5.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
4.5.4. External Crystal Load Capacitors
The Si5350B provides the option of using internal and external crystal load capacitors. If external load capacitors
are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for
more details.
4.5.5. Unused Pins
Unused control pins (P0–P4) should be tied to GND.
Unused voltage control pin should be tied to GND.
Unused output pins (CLK0–CLK7) should be left floating.
4.5.6. Trace Characteristics
The Si5350B features various output current drives ranging from 2 to 8 mA (default). It is recommended to
configure the trace characteristics as shown in Figure 12 when an output drive setting of 8 mA is used.
Rev. 0.9
15
Si5350B
ZO = 85 ohms
R = 0 ohms
CLK
(Optional resistor for
EMI management)
Length = No Restrictions
Figure 12. Recommended Trace Characteristics with 8 mA Drive Strength Setting
Note: Jitter is only specified at 6 and 8 mA drive strength.
16
Rev. 0.9
Si5350B
5. Pin Descriptions (20-QFN, 24-QSOP)
Si5350B 20-QFN
Top View
Si5350B 24-QSOP
Top View
CLK5
VDDOC
CLK4
CLK6
1
2
3
24
23
22
CLK7
VDD0D
XA
XB
VC
P0
P1
1
2
3
4
5
15 CLK7
VDD
GND
XA
CLK0
CLK1
GND
4
21
20
19
18
17
16
15
14
13
12
VDDOD
CLK0
5
GND
PAD
6
CLK1
XB
VDDOA
GND
7
11 VDDOA
GND
VC
8
VDD0B
CLK2
9
P0
10
P1
P2
CLK3
P3
11
12
14
13
Pin Name
Pin Number
Pin Type*
Function
QFN-20
1
QSOP-24
XA
XB
6
7
I
I
Input pin for external XTAL
Input pin for external XTAL
VCXO control voltage input
Output clock 0
2
VC
3
9
I
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
P0
13
12
9
21
20
15
14
3
O
O
O
O
O
O
O
O
I
Output clock 1
Output clock 2
8
Output clock 3
19
17
16
15
4
Output clock 4
1
Output clock 5
24
23
10
11
12
13
4
Output clock 6
Output clock 7
User configurable input pin 0
User configurable input pin 1
User configurable input pin 2
User configurable input pin 3
Core voltage supply pin
P1
5
I
P2
6
I
P3
7
I
VDD
VDDOA
VDDOB
VDDOC
VDDOD
GND
20
11
10
18
14
P
P
P
P
P
P
18
16
2
Output voltage supply pin for CLK0 and CLK1
Output voltage supply pin for CLK2 and CLK3
Output voltage supply pin for CLK4 and CLK5
Output voltage supply pin for CLK6 and CLK7
Ground
22
Center Pad 5, 8, 17, 19
*Note: Pin Types: I = Input, O = Output, P = Power.
Rev. 0.9
17
Si5350B
6. Pin Descriptions (10-Pin MSOP)
Si5350B 10-MSOP
Top View
VDD
XA
CLK0
CLK1
GND
1
2
3
10
9
8
XB
VC
P0
VDDO
CLK2
4
5
7
6
Pin Name
Pin
Pin Type*
Function
Number
MSOP-10
XA
XB
2
3
I
I
Input pin for external XTAL
Input pin for external XTAL
VCXO control voltage input
Output clock 0
Vc
4
I
CLK0
CLK1
CLK2
P0
10
9
O
O
O
I
Output clock 1
6
Output clock 2
5
User configurable input pin 0
Core voltage supply pin
VDD
VDDO
GND
1
P
P
P
7
Output supply pin for CLK0, CLK1, and CLK2
Ground
8
*Note: Pin Types: I = Input, O = Output, P = Power.
18
Rev. 0.9
Si5350B
7. Ordering Information
Factory programmed Si5350B devices can be requested using the ClockBuilder web-based utility available at:
www.silabs.com/ClockBuilder. A unique part number is assigned to each custom configuration as indicated in
Figure 13.
XX
Si5350B
AXXXXX
GT - 10-MSOP
GM - 20-QFN
GU – 24-QSOP
A
= Product Revision A
XXXXX = Unique Custom Code. A five character code will be
assigned for each unique custom configuration
Figure 13. Custom Clock Part Numbers
An evaluation kit containing ClockBuilder Desktop software and hardware allows easy evaluation of the Si5350B.
Rev. 0.9
19
Si5350B
8. Package Outline (24-Pin QSOP)
Table 10. 24-QSOP Package Dimensions
Dimension
Min
Nom
Max
A
A1
b
—
—
—
1.75
0.25
0.30
0.25
8.75
0.10
0.19
0.15
8.55
—
c
—
D
8.65
E
6.00 BSC
3.90
E1
e
3.81
0.40
0
3.99
1.27
8
0.635 BSC
—
L
L2
0.25 BSC
—
aaa
bbb
ccc
0.10
0.17
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
20
Rev. 0.9
Si5350B
9. Package Outline (20-Pin QFN)
Table 11. Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
A
A1
b
0.90
0.05
0.30
0.02
0.25
D
4.00 BSC
2.70
D2
e
2.65
2.75
0.50 BSC
4.00 BSC
2.70
E
E2
L
2.65
0.30
2.75
0.50
0.10
0.10
0.08
0.10
0.10
0.40
aaa
bbb
ccc
ddd
eee
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 0.9
21
Si5350B
10. Package Outline (10-Pin MSOP)
Table 12. 24-QSOP Package Dimensions
Dimension
Min
—
Nom
Max
1.10
0.15
0.95
0.33
0.23
A
A1
A2
b
—
—
0.00
0.75
0.17
0.08
0.85
—
c
—
D
3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
E
E1
e
L
0.40
0.80
L2
q
0.25 BSC
—
0
8
aaa
bbb
ccc
ddd
—
—
—
—
—
0.20
0.25
0.10
0.08
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
22
Rev. 0.9
Si5350B
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.9
Updated maximum output frequency.
Updated kV values in Table 3 on page 5.
Added "2.3. HCSL Compatible Outputs" on page 9.
Updated "4.2.2. .Spread Spectrum" on page 11.
Added "4.5.6. Trace Characteristics" on page 15.
Rev. 0.9
23
Si5350B
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
24
Rev. 0.9
相关型号：
SI5350C-A-GM
Processor Specific Clock Generator, 133MHz, CMOS, 4 X 4 MM, MO-220VGGD-8, QFN-20
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