SI5383A-D07172-GMR_技术文档

Si5383/84 Rev D Data Sheet

Network Synchronizer Clocks Supporting 1 PPS to 750 MHz

Inputs

KEY FEATURES

• One or three independent DSPLLs in a

single monolithic IC supporting flexible

SyncE/IEEE 1588 and SETS architectures

The Si5383/84 combines the industry’s smallest footprint and lowest power network syn-

chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The

Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless

communications systems, and data center switches requiring both traditional and packet

based network synchronization.

• Input frequency range:

• External crystal: 25-54 MHz

• REF clock: 5-250 MHz

The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588

DCO, or a general-purpose PLL for processor/FPGA clocking. The Si5383/84 can also

be used in legacy SETS systems needing Stratum 3/3E compliance. In addition, locking

to a 1 PPS input frequency is available on DSPLL D. The DCO mode provides precise

timing adjustment to 1 part per trillion (ppt). The unique design of the Si5383/84 allows

the device to accept a TCXO/OCXO reference with a wide frequency range, and the ref-

erence clock jitter does not degrade the output performance. The Si5383/84 is configura-

ble via a serial interface and programming the Si5383/84 is easy with ClockBuilder Pro

software. Factory pre-programmed devices are also available.

• Diff clock: 8 kHz - 750 MHz

• LVCMOS clock: 1 PPS, 8 kHz - 250

MHz

• Output frequency range:

• Differential: 1 PPS, 100 Hz - 718.5 MHz

• LVCMOS: 1 PPS, 100 Hz - 250 MHz

• Ultra-low jitter of less than 150 fs

Applications

• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2

• Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1

• Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G.

8273.2

• IEEE 1588 (PTP) slave clock synchronization

• Stratum 3/3E, G.812, G.813, GR-1244, GR-253 network synchronization

• 1 Hz/1 PPS Clock Multiplier

XTAL

OCXO/

TCXO

REF

REFb

XA

XB

OSC

Si5383/84

IN4

IN3

÷INT

OUT0

DSPLL

D

÷INT

OUT1

OUT2

OUT3

OUT4

IN2

IN1

IN0

÷FRAC

I²C

DSPLL A

÷INT

OUT5

OUT6

DSPLL C

Control/

Status

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Table of Contents

1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.1 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.2 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.3 DSPLL Loop Bandwidth in Standard Input Mode . . . . . . . . . . . . . . . . . . 4

3.3.1 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.4 DSPLL Loop Bandwidth in 1 PPS Mode . . . . . . . . . . . . . . . . . . . . . 4

3.4.1 Smartlock Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.5.1 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.5.2 Free-run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.5.3 Lock Acquisition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.5.4 Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.5.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.6 Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . 7

3.6.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC) . . . . . . . . . . . 7

3.6.2 Frequency Increment/Decrement Using the Serial Interface . . . . . . . . . . . . . . 8

3.7 External Reference (XA/XB, REF/REFb) . . . . . . . . . . . . . . . . . . . . . 8

3.7.1 External Crystal (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.7.2 External Reference (REF/REFb) . . . . . . . . . . . . . . . . . . . . . . .10

3.8 Inputs (IN0, IN1, IN2, IN3, IN4) . . . . . . . . . . . . . . . . . . . . . . . .11

3.8.1 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.8.2 Manual Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.8.3 Automatic Input Selection in Standard Input Mode . . . . . . . . . . . . . . . . .11

3.8.4 Input Configuration and Terminations . . . . . . . . . . . . . . . . . . . . .12

3.8.5 Hitless Input Switching in Standard Input Mode . . . . . . . . . . . . . . . . . .13

3.8.6 Ramped Input Switching in Standard Input Mode . . . . . . . . . . . . . . . . .13

3.8.7 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . .13

3.8.8 Synchronizing to Gapped Input Clocks in Standard Input Mode . . . . . . . . . . . .13

3.9 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.9.1 Input LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.9.2 XA/XB LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.9.3 OOF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.9.4 Precision OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.9.5 Fast OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.9.6 LOL Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.9.6.1 LOL Detection Standard Input Mode . . . . . . . . . . . . . . . . . . . . .17

3.9.6.2 LOL Detection in 1 PPS Mode . . . . . . . . . . . . . . . . . . . . . . .17

3.9.7 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.10 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

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3.10.1 Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.10.2 Support For 1 Hz Output . . . . . . . . . . . . . . . . . . . . . . . . .20

3.10.3 Differential Output Terminations. . . . . . . . . . . . . . . . . . . . . . .21

3.10.4 Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.10.5 Programmable Common-Mode Voltage For Differential Outputs . . . . . . . . . . . .21

3.10.6 LVCMOS Output Impedance Selection . . . . . . . . . . . . . . . . . . . .22

3.10.7 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . .22

3.10.8 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . .22

3.10.9 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.10.10 Output Disable During LOL . . . . . . . . . . . . . . . . . . . . . . . .22

3.10.11 Output Disable During XAXB_LOS . . . . . . . . . . . . . . . . . . . . .22

3.10.12 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . .22

3.10.13 Synchronous/Asynchronous Output Disable . . . . . . . . . . . . . . . . . .22

3.10.14 Output Divider (R) Synchronization . . . . . . . . . . . . . . . . . . . . .23

3.10.15 Programmable Phase Offset in 1 PPS Mode . . . . . . . . . . . . . . . . . .23

3.11 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.12 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.13 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.14 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .23

3.15 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-

programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4. Register Map

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6. Typical Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 38

7. Detailed Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . 40

8. Typical Operating Characteristics (Jitter and Phase Noise) . . . . . . . . . . . . . 41

9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

14.1 Revision 0.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

14.2 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

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Si5383/84 Rev D Data Sheet

Feature List

1. Feature List

The Si5383/84 highlighted features are listed below.

• One or three DSPLLs in a single monolithic IC supporting

flexible SyncE/IEEE 1588 and SETS architectures

• TCXO/OCXO reference input determines DSPLL free-run/hold-

over accuracy and stability

• Meets the requirements of:

• Excellent jitter performance

• ITU-T G.8273.1 T-GM

• Programmable loop bandwidth per DSPLL:

• 1 PPS inputs: 1 mHz and 10 mHz

• All other inputs: 1 mHz to 4 kHz

• ITU-T G.8273.2 T-BC, T-TSC

• ITU-T G.8262 (SyncE) EEC Options 1 & 2

• ITU-T G.812 Type III, IV

• Highly configurable output drivers: LVDS, LVPECL, LVCMOS,

HCSL, CML

• ITU-T G.813 Option 1

• Telcordia GR-1244, GR-253 (Stratum-3/3E)

• Core voltage:

• Each DSPLL generates any output frequency from any input

frequency

• VDD: 1.8 V ±5%

• VDDA: 3.3 V ±5%

• Input frequency range:

• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V

• Built-in power supply filtering

• Status monitoring:

• External crystal: 25 - 54 MHz

• REF clock: 5 - 250 MHz

• Diff clock: 8 kHz - 750 MHz

• LOS, LOL: 1 PPS-750 MHz

• OOF: 8 kHz-750 MHz

I²C Serial Interface

ClockBuilder^TMPro software tool simplifies device configura-

tion

• LVCMOS clock: 1 PPS, 8 kHz - 250 MHz

• Output frequency range:

•

• Differential: 1 PPS, 100 Hz - 718.5 MHz

• LVCMOS: 1 PPS, 100 Hz - 250 MHz

• Pin or software controllable DCO on each DSPLL with typical

resolution to 1 ppt/step

• 5 input, 7 output, 56-pin LGA

• Temperature range: –40 to +85 °C

• Pb-free, RoHS-6 compliant

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Si5383/84 Rev D Data Sheet

Ordering Guide

2. Ordering Guide

Table 2.1. Ordering Guide

Ordering Part Number (OPN)^1,2

# of DSPLLs Maximum Out-

Package

RoHS-6, Pb- Temperature Range

Free

put Frequency

718.5 MHz

350 MHz

718.5 MHz

350 MHz

—

Si5383A-Dxxxxx-GM

Si5383B-Dxxxxx-GM

Si5384A-Dxxxxx-GM

Si5384B-Dxxxxx-GM

3

1

56-Lead 8×8 LGA

Yes

–40 to 85 °C

Si5383-D-EVB³

SiOCXO1-EVB

—

Evaluation Board

—

OCXO Evaluation

Board

Notes:

1. Add an R at the end of the OPN to denote tape and reel ordering options.

2. Custom, factory preprogrammed devices are available as well as unconfigured base devices. See figures below for 5-digit numer-

ical sequence nomenclature.

3. The Si5383-D-EVB ships with an SiOCXO1-EVB board included. Additional SiOCXO1-EVB boards may be ordered separately if

needed.

2.1 Ordering Part Number Fields

Si538fg

R00xxx-GM

-

Timing product family

f = Network Sync family member (3, 4)

g = Device grade (A, B)

Product Die Revision (D)

Base device indicator*

Firmware revision indicator**

Package, ambient temperature range (LGA, -40°C to + 85°C)

* Firmware is preprogrammed into base devices, but no configuration settings are present in the device

** 3 digits corresponding to the firmware revision preprogrammed into base devices

Figure 2.1. Ordering Guide Part Number Fields for Base Devices

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Si5383/84 Rev D Data Sheet

Ordering Guide

Si538fg

-

-GM

Rxxxxx

Timing product family

f = Network Sync family member (3, 4)

g = Device grade (A, B)

Product Die Revision (D)

Custom ordering part number (OPN) sequence ID**

Package, ambient temperature range (LGA, -40°C to +85°C)

** 5 digits; assigned by ClockBuilder Pro for custom, factory-preprogrammed OPN devices.

The firmware revision for custom OPN devices is determined by ClockBuilder Pro when a custom part number is created.

Figure 2.2. Ordering Guide Part Number Fields for Custom OPN Devices

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Si5383/84 Rev D Data Sheet

Functional Description

3. Functional Description

The Si5383 offers three DSPLLs and the Si5384 offers one DSPLL that can be independently configured and controlled through the

serial interface. In standard input mode, all DSPLLs support high frequency inputs. DSPLL D can be configured to operate in 1 PPS

input mode to lock to a 1 Hz input clock. Regardless of the input mode, any of the DSPLLs can be used to generate any valid output

frequency.

Each of the DSPLLs have locked, free-run, and holdover modes of operation with an optional DCO mode for IEEE 1588 applications.

The device requires an external crystal and an external reference (TCXO or OCXO) to operate. The reference input (REF/REFb) deter-

mines the frequency accuracy and stability while in free-run and holdover modes. The external crystal completes the internal oscillator

circuit (OSC) which is used by the DSPLL for intrinsic jitter performance. There are three main inputs (IN0 - IN2) for synchronizing the

DSPLLs. Input selection can be manual or automatically controlled using an internal state machine. Two additional single-ended inputs

are available to DSPLL D. Any of the output clocks (OUT0 to OUT6) can be configured to any of the DSPLLs using a flexible crosspoint

connection. Output 5 is the only output that can be configured for a 1 Hz output to support 1 PPS.

3.1 Standards Compliance

Each of the DSPLLs meet the applicable requirements of ITU-T G.8262 (SyncE), G.812, G.813, G.8273.2 (T-BC), in addition to Telcor-

dia GR-1244 and GR-253 as shown in the compliance report for standard input mode. The DCO feature enables IEEE1588 (PTP) im-

plementations in addition to hybrid SyncE + IEEE1588 (T-BC).

3.2 Frequency Configuration

The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile

memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division

(Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a

specific frequency plan are easily determined using the ClockBuilder Pro utility.

3.3 DSPLL Loop Bandwidth in Standard Input Mode

The DSPLL loop bandwidth determines the amount of input clock jitter and wander attenuation. Register configurable DSPLL loop

bandwidth settings of 1 mHz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,

each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.

Table 3.1. Loop Bandwidth Requirements

SONET (Telcordia)

GR-253 Stratum 3E

GR-253 Stratum 3

—

SDH (ITU-T)

G.812 Type III

G.812 Type IV

G.813 Option 1

SyncE (ITU-T)

—

Loop Bandwidth

0.001 Hz

G.8262 EEC Option 2

G.8262 EEC Option 1

< 0.1 Hz

1 - 10 Hz

3.3.1 Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. In standard input mode, the fast-

lock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop

bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are availa-

ble for selection. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Band-

width setting. The fastlock feature can be enabled or disabled independently for each of the DSPLLs for input frequencies > 8 kHz..

3.4 DSPLL Loop Bandwidth in 1 PPS Mode

When operating in 1 PPS input mode, the Si5383/84 offers two choices of loop bandwidth for DSPLL D: 1 mHz or 10 mHz.

3.4.1 Smartlock Feature

When operating in 1 PPS input mode, the Si5383/84 offers the Smartlock feature to achieve fast locking to 1 PPS inputs. The Smart-

lock feature locks to 1 PPS inputs in two phases. During the first phase, large adjustments are made to eliminate the majority of the

frequency and phase error. During the second phase, finer adjustments are made until the PLL is locked. Once the PLL is locked, the

DSPLLs loop bandwidth will automatically revert to the DSPLL loop bandwidth setting.

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Si5383/84 Rev D Data Sheet

Functional Description

3.5 Modes of Operation

Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition

Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation

on page 5. The following sections describe each of these modes in greater detail.

3.5.1 Initialization and Reset

Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from

NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-

tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard

reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-

stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard register

reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all

DSPLLs, while a soft reset can either affect all or each DSPLL individually. It is recommended that the device be held in reset during

power-up by asserting the RSTb pin. RSTb should be released once all supplies have reached operational levels. The RSTb pin func-

tions as an open-drain output, which drives low during POR. External devices must be configured as open-drain to avoid contention.

Power-Up

Reset and

Initialization

No valid input

Free-run

clocks selected

An input is

qualified and

available for

selection

Valid input clock

selected

Lock Acquisition

(Fast Lock or

Smart Lock)

Phase lock on

selected input

clock is achieved

An input is

qualified and

available for

selection

No valid input

clocks available

for selection

Holdover

Mode (1 PPS)

Locked

Mode

No valid input

clocks available

for selection

Holdover

Mode

Selected input

clock fails (1 PPS

input mode)

Selected input clock fails

(Standard input mode)

Input Clock

Switch

Yes

No

Other Valid

Clock Inputs

Available?

Yes

Holdover

History

Valid?

No

Figure 3.1. Modes of Operation

3.5.2 Free-run Mode

Once power is applied to the Si5383/84 and initialization is complete, all three DSPLLs will automatically enter freerun if no clock input

is applied. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of

the clock source at the reference inputs (REF/REFb). A TCXO or OCXO is recommended for applications that need frequency accuracy

and stability to meet the synchronization standards as shown in the following table:

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Si5383/84 Rev D Data Sheet

Functional Description

Table 3.2. Free-run Accuracy for North American and European Synchronization Standards

SONET (Telcordia)

GR-253 Stratum 3E

GR-253 Stratum 3

—

SDH (ITU-T)

G.812 Type III

G.812 Type IV

G.813 Option 1

SyncE (ITU-T)

—

Free-run Accuracy

±4.6 ppm

G.8262 EEC Option 2

G.8262 EEC Option 1

3.5.3 Lock Acquisition Mode

Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-

zation, a DSPLL will automatically start the lock acquisition process.If the fast lock feature is enabled for inputs > 8 kHz, a DSPLL will

acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition

is complete. If the input frequency is configured for 1 PPS, the Smartlock mode is used. During lock acquisition the outputs will gener-

ate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.

3.5.4 Locked Mode

Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point,

any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is

achieved. Refer to Section 3.9.6 LOL Detection for more details on the operation of the loss of lock circuit.

3.5.5 Holdover Mode

Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input

clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the

disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores

several seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calcula-

ted from a programmable window within the stored historical frequency data. Both the window size and delay are programmable as

shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring

frequency data that may be corrupt just before the input clock failure.

Clock Failure and Entry

into Holdover

Historical Frequency Data Collected

time

Programmable historical data window used to

Programmable delay

determine the final holdover value

(Seconds)

0s

(Seconds)

Figure 3.2. Programmable Holdover Window

When entering holdover, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in holdover,

the output frequency drift is entirely dependent on the external reference clock connected to the REF/REFb pins. When the clock input

becomes valid, a DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves

pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in process is glitchless.

In standard input mode, the DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initi-

ated, the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated differ-

ence and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000

ppm/s, or any of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro

defaults to ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching.

For more information on ramped input switching see Section 3.8.6 Ramped Input Switching in Standard Input Mode.

Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable

holdover exit BW.

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Si5383/84 Rev D Data Sheet

Functional Description

3.6 Digitally-Controlled Oscillator (DCO) Mode

The DSPLLs support a DCO mode where their output frequencies are adjustable in pre-defined steps defined by frequency step words

(FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increments (FINC) or

decrements (FDEC). However due to slower update rates over the I²C interface, it is recommended to use pin controls for adjusting the

frequency in DCO mode. A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it.

The DCO mode is available when the DSPLL is operating in locked mode. The DCO mode is mainly used with standard input mode in

IEEE1588 (PTP) applications where a clock needs to be generated based on recovered timestamps. In this case timestamps are recov-

ered by the PHY/MAC. A processor containing servo software controls the DCO to close the timing loop between the master and slave

nodes. The processor has the option of using the FINC/FDEC pin controls to update the DCO frequency or by controlling it through the

serial interface.

When operating in 1 PPS input mode, an additional enhanced DCO mode is enabled in the holdover state to facilitate DCO steering.

This is useful for applications that require Assisted Partial Timing Support (APTS).

3.6.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC)

Controlling the output frequency with pin controls is available in standard input mode. This feature involves asserting the FINC or FDEC

pins to step (increment or decrement) the DSPLL’s output frequency. Both the step size and DSPLL selection (A, C, D) is made through

the serial interface by writing to register bits.

Si5383/84

PD

LPF

FSW_MASK_A

0x0422

M_{n_A}

M_{d_A}

÷

DSPLL A

+

-

Frequency

Step Word

FINC

FDEC

0x0423 – 0x0429

0x001D

PD

LPF

FSW_MASK_C

0x0622

M_{n_C}

M_{d_C}

÷

DSPLL C

+

-

Frequency

Step Word

0x0623 – 0x0629

PD

LPF

FSW_MASK_D

0x0723

M_{n_D}

M_{d_D}

÷

DSPLL D

SDA

SCL

I²C

+

-

Frequency

Step Word

0x0724 – 0x072A

Figure 3.3. Controlling the DCO Mode By Pin Control

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Rev. 1.0 | 7

Si5383/84 Rev D Data Sheet

Functional Description

3.6.2 Frequency Increment/Decrement Using the Serial Interface

Controlling the DSPLL frequency through the serial interface is available. This feature involves asserting the FINC or FDEC bits to acti-

vate the frequency change defined by the frequency step word. A set of mask bits selects the DSPLL(s) that is affect by the frequency

change.

3.7 External Reference (XA/XB, REF/REFb)

The external crystal at the XA/XB pins determines jitter performance of the output clocks, and the external reference clock at the REF/

REFb pins determines the frequency accuracy and stability during free-run or holdover modes, and the MTIE/TDEV performance when

the DSPLL is locked. Jitter from the external clock on the REF/REFb pins will have little to no effect on the output jitter performance,

depending upon the selected bandwidth. This allows using a lower-cost TCXO/OCXO with a higher phase noise floor or an external

reference clock distributed over long PCB traces or across a backplane, without impacting output jitter.

External Reference Clock

Determines

Output Frequency

Accuracy and Stability,

and MTIE/TDEV

XTAL + OSC Determines

Output

XTAL

Jitter Performance

TCXO/

OCXO

Performance

XA

XB

REF REFb

OSC

Si5383/84

Figure 3.4. External Reference Connections

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Rev. 1.0 | 8

Si5383/84 Rev D Data Sheet

Functional Description

3.7.1 External Crystal (XA/XB)

The external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the

DSPLLs. The device includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the ben-

efit of reduced noise coupling from external sources. A crystal in the range of 48 to 54 MHz is recommended for best jitter performance.

Although the device includes built-in XTAL load capacitors (CL) of 8 pF, crystals with load capacitances up to 18 pF can also be accom-

modated. Frequency offsets due to CL mismatch can be adjusted using the frequency adjustment feature which allows frequency ad-

justments of ±1000 ppm. The Si5383/84 Reference Manual provides additional information on PCB layout recommendations for the

crystal to ensure optimum jitter performance. Although it is not recommended, the device can also accommodate an external clock at

the XA/XB pins instead of a crystal. Selection between the external crystal or clock is controlled by register configuration. The internal

crystal loading capacitors (CL) are disabled in this mode. Refer to Chapter 5. Electrical Specifications for reference clock requirements

when using this mode. The Si5383/84 Reference Manual provides additional information on PCB layout recommendations for the crys-

tal to ensure optimum jitter performance.

48-54 MHz

XTAL

XA

XB

2xC_L

2xCL

OSC

PXAXB

÷

Si5383/84

Crystal Resonator

Connection

Figure 3.5. Crystal Resonator Connections

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Si5383/84 Rev D Data Sheet

Functional Description

3.7.2 External Reference (REF/REFb)

The external reference at the REF/REFb pins is used to determine output frequency accuracy and stability during free-run and holdover

modes. This reference is usually from a TCXO or OCXO and can be connected differentially or single-ended as shown in the figure

below:

5 – 250 MHz

TCXO/OCXO

5 – 250 MHz

TCXO/OCXO

100

REF

REFb

REF

Si5383/84

Differential External

Reference

Single-ended

External Reference

Connection

Figure 3.6. External Reference Connections

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Rev. 1.0 | 10

Si5383/84 Rev D Data Sheet

Functional Description

3.8 Inputs (IN0, IN1, IN2, IN3, IN4)

Inputs IN0, IN1 and IN2 can be used to synchronize any of the DSPLLs. The inputs accept both differential and single-ended clocks. A

crosspoint between the inputs and the DSPLLs allows inputs IN0-IN2 to connect to any of the DSPLLs as shown in the figure below.

DSPLL D has two additional inputs (IN3-IN4) that are CMOS only inputs. If both IN3 and IN4 are used, they must be the same frequen-

cy.

Si5383/84

Input

Crosspoint

IN0

P_0n

P_0d

0

1

2

÷

DSPLL

IN0b

A

0

1

2

P_1n

P_1d

DSPLL

C

IN1

÷

IN1b

0

1

2

IN2

P_2n

P_2d

DSPLL

D

IN2b

3

4

IN3

IN4

Figure 3.7. Si5383/84 DSPLL Input Selection Crosspoint

3.8.1 Input Selection

Input selection for each of the DSPLLs can be made manually through register control or automatically using an internal state machine.

3.8.2 Manual Input Selection

In manual mode the input selection is made by writing to a register. IN0-IN2 is available to DSPLL A and C, IN0-IN4 is available to

DSPLL D. If there is no clock signal on the selected input, the DSPLL will automatically enter holdover mode.

3.8.3 Automatic Input Selection in Standard Input Mode

When configured in this mode, a DSPLL automatically selects a valid input that has the highest configured priority. The priority scheme

is independently configurable for each DSPLL and supports revertive or non-revertive selection. All inputs are continuously monitored

for loss of signal (LOS) and inputs IN0-IN2 can be monitored for invalid frequency range (OOF). Only inputs that do not assert both the

LOS and OOF monitors can be selected for synchronization by the automatic state machine. The DSPLL(s) will enter either holdover or

freerun mode if there are no valid inputs available.

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Rev. 1.0 | 11

Si5383/84 Rev D Data Sheet

Functional Description

3.8.4 Input Configuration and Terminations

Inputs IN0-IN2 can be configured as differential or single-ended LVCMOS. Inputs IN3-IN4 are single-ended only. The recommended

input termination schemes are shown in the figure below. Inputs IN0-IN2 can be disabled and left unconnected when not in use.

LVCMOS inputs IN3-IN4 should be externally pulled low when not in use.

Standard AC-coupled Differential LVDS (IN0-IN2)

Si5383/84

Standard

50

INx

100

INxb

3.3 V, 2.5 V

LVDS or

50

CML

Pulsed CMOS

Standard AC-coupled Differential LVPECL (IN0-IN2)

Si5383/84

Standard

50

INx

100

INxb

50

3.3 V, 2.5 V

LVPECL

Pulsed CMOS

Standard AC-coupled Single-Ended (IN0-IN2)

Si5383/84

Standard

INx

50

3.3 V, 2.5 V, 1.8 V

LVCMOS

INxb

Pulsed CMOS

Pulsed CMOS DC-coupled Single-Ended

(IN0-IN2)

Si5383/84

R1

Standard

INx

50

R2

3.3 V, 2.5 V, 1.8 V

LVCMOS

INxb

VDD

R1 (Ω)

324

511

R2 (Ω)

665

475

Pulsed CMOS

1.8 V

2.5 V

3.3 V

Resistor values for

f_{IN_PULSED}< 1 MHz

634

365

IN3, IN4 – DC-coupled LVCMOS

Si5383/84

INx

50

Figure 3.8. Termination of Differential and LVCMOS Input Signals

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Rev. 1.0 | 12

Si5383/84 Rev D Data Sheet

Functional Description

3.8.5 Hitless Input Switching in Standard Input Mode

Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that

have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that

they have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled,

the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase differ-

ence between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching

feature is not available in 1 PPS input mode. Hitless switching can be enabled on a per DSPLL basis.

3.8.6 Ramped Input Switching in Standard Input Mode

When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input

switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients

and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off

when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp

rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see Section

3.5.5 Holdover Mode.

3.8.7 Glitchless Input Switching

The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart for standard input mode,

and ±10 ppm apart for 1 PPS input mode. The DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the

Fastlock or Smartlock Loop Bandwidth if it is enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the

new clock frequency. There will be no output runt pulses generated at the output during the transition. All clock inputs, including 3 and

4, support glitchless input switching.

3.8.8 Synchronizing to Gapped Input Clocks in Standard Input Mode

Each of the DSPLLs support locking to an input clock that has missing periods in standard input mode. This is also referred to as a

gapped clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its

cycles. Gapping a clock severely increases its jitter, so a phase-locked loop with high jitter tolerance and low loop bandwidth is required

to produce a low-jitter periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input

with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic

non-gapped output clock. This is shown in the figure below:

Gapped Input Clock

Periodic Output Clock

100 MHz clock

1 missing period every 10

90 MHz non-gapped clock

100 ns

DSPLL

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

10

Period Removed

10 ns

11.11111... ns

Figure 3.9. Generating an Averaged Clock Output Frequency from a Gapped Clock Input

A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every eight. Lock-

ing to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the

hitless switching specification in Table 5.8 Performance Characteristics on page 33 when the switch occurs during a gap in either

input clock.

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Si5383/84 Rev D Data Sheet

Functional Description

3.9 Fault Monitoring

All input clocks and the reference input (REF/REFb) are monitored for loss of signal (LOS). In addition, inputs IN0-IN2 and REF/REFb

are monitored for out-of-frequency (OOF) as shown in the figure below. The reference at the XA/XB pins is also monitored for LOS

since it provides a critical reference clock for the DSPLLs. Each of the DSPLLs also has an LOL indicator, which is asserted when

synchronization is lost with their selected input clock.

XA XB

REFb

REF

Si5383/84

OSC

LOS

DSPLL A

DSPLL C

DSPLL D

LOL

PD

IN0

Precision

Fast

P_0n

÷

OOF

0

1

2

LOS

IN0b

P_0d

LPF

÷M

LOL

PD

0

1

2

Precision

Fast

P_1n

÷

IN1

LOS

OOF

LPF

÷M

P_1d

IN1b

0

1

2

LOL

PD

IN2

Precision

Fast

P_2n

÷

IN2b

P_2d

LPF

÷M

3

4

IN3

IN4

LOS

Figure 3.10. Si5383/84 Fault Monitors

3.9.1 Input LOS Detection

The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of

the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal

sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status

register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option

to disable any of the LOS monitors is also available.

Sticky

Monitor

LOS

en

Live

Figure 3.11. LOS Status Indicators

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Si5383/84 Rev D Data Sheet

Functional Description

3.9.2 XA/XB LOS Detection

A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when

XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is

detected.

3.9.3 OOF Detection

In standard input mode, input clocks IN0, IN1, IN2 are monitored for frequency accuracy with respect to an OOF reference, which it

considers as its “0_ppm” reference. The final OOF status is determined by the combination of both a precise OOF monitor and a fast

OOF monitor as shown in the figure below. An option to disable either monitor is also available. The live OOF register always displays

the current OOF state and its sticky register bit stays asserted until cleared.

Sticky

Monitor

Precision

Fast

en

LOS

OOF

Live

Figure 3.12. OOF Status Indicator

3.9.4 Precision OOF Monitor

The precision OOF monitor circuit measures the frequency of all input clocks to within ±1/16 ppm accuracy with respect to the selected

OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range, which is register configu-

rable up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from tog-

gling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequen-

cy range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 – IN2) as the 0 ppm OOF reference

instead of the REF/REFb pins is available. This option is register-configurable. XA/XB can also be used as the 0 ppm reference.

OOF Declared

OOF Cleared

f_IN

Hysteresis

-4 ppm

(Clear)

-6 ppm

(Set)

+4 ppm

(Clear)

+6 ppm

(Set)

0 ppm

OOF Reference

Figure 3.13. Example of Precise OOF Monitor Assertion and De-assertion Triggers

3.9.5 Fast OOF Monitor

Because the precision OOF monitor needs to provide 1 ppm of frequency measurement accuracy, it must measure the monitored input

clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequen-

cy. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect

a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than ±4000

ppm.

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Si5383/84 Rev D Data Sheet

Functional Description

3.9.6 LOL Detection

There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts the LOL register bits when a DSPLL has lost synchroniza-

tion with its selected input clock. Separate LOL register bits are used to indicate LOL for standard input mode versus 1 PPS mode.

There is also a dedicated LOL pin that reflects the loss of lock condition for each of the DSPLLs (LOL_Ab, LOL_Cb, LOL_Db) and also

for the reference.

Sticky

Si5383/84

LOS

LOL Status Registers

Live

DSPLL A (Si5383)

DSPLL C (Si5383)

DSPLL D (Si5383/84)

Standard Input Mode

LOL Monitor (DSPLLs A, C, D)

LOL_Ab

LOL

Clear

LOL_Cb

LOL_Db

t

LOL

Set

1 PPS Input Mode

LOL Monitor (DSPLL D)

LOL

Clear

t

LOL

Set

t

DSPLL D

f_IN

PD

LPF

÷M

Figure 3.14. Si5383/84 LOL Status Indicators

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Rev. 1.0 | 16

Si5383/84 Rev D Data Sheet

Functional Description

3.9.6.1 LOL Detection Standard Input Mode

There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An

optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input

clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The

live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects

the current state of the LOL monitor.

Each of the LOL frequency monitors has adjustable sensitivity, which is register-configurable from 0.1 ppm to 10,000 ppm. Having two

separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is

indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is

more than 1 ppm frequency difference is shown in the figure below.

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

Lost Lock

LOL

Hysteresis

LOCKED

0

0.1

1

10,000

Phase Detector Frequency Difference (ppm)

Figure 3.15. LOL Set and Clear Thresholds

An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input

clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The

configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using

the ClockBuilderPro utility.

3.9.6.2 LOL Detection in 1 PPS Mode

DSPLL D implements a phase-based LOL detector when operating in PPS mode. Two independent phase error thresholds are inclu-

ded: one for LOL trigger and one for LOL clear. Having two separate phase error thresholds allows for hysteresis to help prevent chat-

tering of the LOL status. An additional level of filtering is provided with trigger and clear counters. These counters represent the number

of consecutive clock cycles a threshold must be met before the LOL alarm changes state. These counters prove useful when dealing

with transient events, fault conditions, and locking to inputs with noise. For example, the DSPLL may see a large phase error between

the time the input signal is lost and the LOS alarm is raised. The user must ensure LOL does not occur during this time to guarantee

entry into holdover. This is accomplished by adjusting the LOL trigger counter to a larger value to compensate for this interval.

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Si5383/84 Rev D Data Sheet

Functional Description

3.9.7 Interrupt Pin (INTRb)

In standard input mode, an interrupt pin (INTRb) indicates a change in state with any of the status indicators for any of the DSPLLs. All

status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the sticky status

registers.

In 1 PPS input mode, the INTRb pin does not provide status indication for DSPLL D. When operating in this mode, loss of lock for

DSPLL D can be monitored using the LOL_Db pin.

Si5383/84

LOSXAXB_FLG

(IN0) LOS_FLG[0]

(IN1) LOS_FLG[1]

(IN2) LOS_FLG[2]

LOS

(REF) LOS_FLG[3]

(IN3) LOS_CMOS[0]

LOS_CMOS

(IN4) LOS_CMOS[1]

OOF_FLG[0]

OOF

OOF_FLG[1]

OOF_FLG[2]

LOL_FLG_PLLA¹

INTRb

LOL_FLG_PLLB

LOL_FLG_PLLC¹

LOL_FLG_PLLD²

LOL

HOLD_FLG_PLLA¹

HOLD_FLG_PLLC¹

HOLD_FLG_PLLD²

HOLD

CAL_FLG_PLLA¹

CAL_FLG_PLLB

CAL_FLG_PLLC¹

CAL

CAL_FLG_PLLD²

SYSINCAL_FLG

Notes:

1. Si5383 only

2. Standard input mode only

Figure 3.16. Interrupt Triggers and Masks

3.10 Outputs

The Si5383/84 supports seven differential output drivers. Each driver has a configurable voltage amplitude and common-mode voltage

covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential

signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 14 single-ended outputs,

or a combination of differential and single-ended outputs. LVMOS outputs can also be set for in-phase or complementary mode.

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Si5383/84 Rev D Data Sheet

Functional Description

3.10.1 Output Crosspoint

A crosspoint allows any of the output drivers to connect with any of the DSPLLs as shown in the figure below. The crosspoint configura-

tion is programmable and can be stored in NVM so that the desired output configuration is ready at power-up.

Si5383/84

Output

Crosspoint

VDDO0

OUT0

A

C

D

÷R₀

÷R₁

OUT0b

VDDO1

OUT1

OUT1b

A

C

D

DSPLL

A

VDDO2

OUT2

A

C

D

÷R₂

÷R₃

OUT2b

VDDO3

OUT3

OUT3b

A

C

D

DSPLL

C

A

C

D

VDDO4

OUT4

DSPLL

D

÷R₄

÷R₅

OUT4b

VDDO5

OUT5

OUT5b

A

C

D

R6

VDDO6

OUT6

OUT6b

A

C

D

÷R₆

Figure 3.17. DSPLL to Output Driver Crosspoint

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Si5383/84 Rev D Data Sheet

Functional Description

3.10.2 Support For 1 Hz Output

Output 5 of the Si5383/84 can be configured to generate a 1 Hz clock by cascading the R6 and R5 dividers. Output 6 cannot be pow-

ered down if Output 5 is used for generating a 1Hz clock. Output 6 is still usable in this case but is limited to a maximum frequency of

33.5 MHz. ClockBuilder Pro automatically determines the optimum configuration when generating a 1 Hz output (1 PPS).

VDDO4

OUT4

OUT4b

A

C

D

÷R₄

÷R₅

VDDO5

OUT5

OUT5b

A

C

D

R6

VDDO6

OUT6

OUT6b

A

C

D

÷R₆

Figure 3.18. Generating a 1 Hz Output using the Si5383/84

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Si5383/84 Rev D Data Sheet

Functional Description

3.10.3 Differential Output Terminations

Note: In this document, the terms LVDS and LVPECL refer to driver formats that are compatible with these signaling standards.

The differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below:

AC-coupled LVDS/LVPECL

DC-coupled LVDS

V

_DDO= 3.3 V, 2.5 V, 1.8 V

V

_DDO= 3.3 V, 2.5 V, 1.8 V

50

OUTx

100

OUTxb

100

OUTxb

Internally

self-biased

Si5383/84

AC-coupled LVPECL

DC-coupled LVCMOS

3.3 V, 2.5 V, 1.8 V

LVCMOS

VDD – 1.3 V

V

_DDO= 3.3 V, 2.5 V, 1.8 V

V

_DDO= 3.3 V, 2.5 V

50

Rs

OUTx

50

OUTx

OUTxb

50

Si5383/84

AC-coupled HCSL

VDD_RX

V_DDO

= 3.3 V, 2.5 V, 1.8 V

R1

R2

OUTx

50

Standard

HCSL

Receiver

OUTxb

Si5383/84

R2

For V_CM= 0.35 V

VDD_RX

R1

R2

56.2 Ω

59 Ω

442 Ω

332 Ω

3.3 V

2.5 V

1.8 V

243 Ω

63.4 Ω

Figure 3.19. Supported Differential Output Terminations

3.10.4 Output Signal Format

The differential output amplitude and common-mode voltage are both programmable and compatible with a wide variety of signal for-

mats, including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3

V, 2.5 V, or 1.8 V) drivers providing up to 14 single-ended outputs or a combination of differential and single-ended outputs.

3.10.5 Programmable Common-Mode Voltage For Differential Outputs

The common-mode voltage (V_CM) for the differential modes is programmable and depends on the voltage available at the output’s

VDDO pin. Setting the common-mode voltage is useful when dc-coupling the output drivers.

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Si5383/84 Rev D Data Sheet

Functional Description

3.10.6 LVCMOS Output Impedance Selection

Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source

termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-

ble output impedance selections for each VDDO options as shown in the table below. Note that selecting a lower source impedance

may result in higher output power consumption.

Table 3.3. Typical Output Impedance (Z_S)

VDDO

CMOS_DRIVE_Selection

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

3.3 V

2.5 V

1.8 V

38 Ω

43 Ω

—

30 Ω

35 Ω

46 Ω

22 Ω

24 Ω

31 Ω

3.10.7 LVCMOS Output Signal Swing

The signal swing (V_OL/V_OH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

3.10.8 LVCMOS Output Polarity

When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on

the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-

ble, which enables complementary clock generation and/or inverted polarity with respect to other output drivers.

3.10.9 Output Enable/Disable

The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high, all outputs are

disabled. When held low, the outputs are enabled. Outputs in the enabled state can be individually disabled through register control.

3.10.10 Output Disable During LOL

By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. In standard input

mode, there is an option to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into hold-

over.

3.10.11 Output Disable During XAXB_LOS

The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the

DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during asser-

tion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy

and stability will be indeterminate during this fault condition.

3.10.12 Output Driver State When Disabled

The disabled state of an output driver is register configurable as disable low or high.

3.10.13 Synchronous/Asynchronous Output Disable

Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output will wait until a clock

period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In

asynchronous disable mode, the output clock will disable immediately without waiting for the period to complete. By default, ClockBuild-

er Pro configures outputs for synchronous disable.

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Rev. 1.0 | 22

Si5383/84 Rev D Data Sheet

Functional Description

3.10.14 Output Divider (R) Synchronization

All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable

phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same

result.

3.10.15 Programmable Phase Offset in 1 PPS Mode

When 1 PPS mode is enabled, the Si5383/84 can be programmed to provide a static phase offset on all outputs generated by DSPLL

D. This can be used for compensation of PCB trace delays to achieve accurate system phase alignment for 1 PPS.

3.11 Power Management

Unused inputs, output drivers, and DSPLLs can be powered down when unused. Consult the Si5383/84 Reference Manual and Clock-

Builder Pro configuration utility for details.

3.12 In-Circuit Programming

The Si5383/84 is fully configurable using the I²C interface. At power-up the device downloads its default register values from internal,

flash-based, non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-

erate specific clock frequencies at power-up. Firmware updates may also be written into NVM.

The NVM is in-circuit programmable with normal operating power supply voltages using the I²C interface. The NVM update process

starts by using ClockBuilder Pro to generate a boot record file. Once the boot record has been generated, it is necessary to place the

device into bootloader mode via one of the following methods:

• Pin control: Drive the BLMDb pin low prior to negating the RSTb pin

Register control: Write a boot reset sequence to the device over I²C

•

Once the device has entered bootloader mode, the boot record file can be written to the device over I²C. Refer to the Si5383/84 Refer-

ence Manual for a detailed procedure for writing registers to NVM.

3.13 Serial Interface

Configuration and operation of the Si5383/84 is controlled by reading and writing registers using the I²C interface. Communication re-

quires a 3.3 V I/O voltage. The A0 and A1 pins may be used to set the lower two bits of the I²C base address if desired. Alternatively,

the entire I²C base address may be configured using ClockBuilder Pro.

3.14 Custom Factory Preprogrammed Parts

Custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory pre-programmed part will gener-

ate clocks at power-up. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly and easily

request and generate a custom part number for your configuration.

In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your

design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local

Silicon Labs sales representative. Samples of your pre-programmed device will typically ship in two weeks.

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Rev. 1.0 | 23

Si5383/84 Rev D Data Sheet

Functional Description

3.15 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices

As with essentially all modern software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.si-

labs.com, you will be notified whenever changes are made and what the impact of those changes are. This update process will ulti-

mately enable ClockBuilder Pro users to access all features and register setting values documented in this data sheet and the

Si5383/84 Reference Manual.

However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register

setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assis-

tance. One example of this type of feature or custom setting is the customizable output amplitude and common-mode voltages for the

clock outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your

CBPro project file with your specific features and register settings enabled using what is referred to as the manual "settings override"

feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in

a CBPro design report are shown in the table below:

Table 3.4. Setting Overrides

Location

0x0435[0]

0x0B48[4:0]

Customer Name

FORCE_HOLD_PLLA

OOF_DIV_CLK_DIS

Type

No NVM

User

Target

N/A

Dec Value

Hex Value

0x1

1

OPN and EVB

31

0x1F

Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the

NVM file. The flowchart for this process is shown in the figure below:

End: Place

sample order

Start

Do I need a

pre-programmed device

with a feature or setting

which is unavailable in

ClockBuilder Pro?

Generate

Custom OPN

in CBPro

Configure device

using CBPro

No

Yes

Contact Silicon

Labs Technical

Support to submit

& review your

non-standard

Yes

configuration

request & CBPro

project file

Receive

updated

CBPro project

file from

Silicon Labs

with “Settings

Override”

Does the updated

CBPro Project file

match your

Load project file

into CBPro and

test

requirements?

Figure 3.20. Process for Requesting Non-Standard CBPro Features

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Rev. 1.0 | 24

Si5383/84 Rev D Data Sheet

Register Map

4. Register Map

Registers in the Si5383/84 require an I²C command sequence to enable the reading and writing. Once the I²C command sequences

have been sent, it is necessary for the host to poll the status bits to indicate that the read or write command is complete. For read

commands, data is available once the status bit indicates the command is complete. Refer to the Si5383/84 Reference Manual for a

complete list of register descriptions and settings.

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Rev. 1.0 | 25

Si5383/84 Rev D Data Sheet

Electrical Specifications

5. Electrical Specifications

Table 5.1. Recommended Operating Conditions

Parameter

Symbol

T_A

Min

–40

—

Typ

25

Max

85

Unit

°C

V

Ambient Temperature

Junction Temperature

Core Supply Voltage

TJ_MAX

V_DD

—

125

1.89

3.47

2.62

1.89

1.71

3.14

2.37

1.71

1.80

3.30

2.50

1.80

V_DDA

V_DDO

V

Output Driver Supply Voltage

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-

ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 5.2. DC Characteristics

(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5383, 1 PPS Input Mode¹

Si5383, Standard Input Mode²

Si5384, 1 PPS Input Mode¹

Si5383, 1 PPS Input Mode¹

Si5383, Standard Input Mode²

Si5384, 1 PPS Input Mode¹

LVPECL Output³@ 156.25 MHz

LVDS Output³@ 156.25 MHz

Core Supply Current

I_DD

—

245

390

mA

—

240

165

160

155

22

380

265

190

180

26

mA

I_DDA

Output Buffer Supply Current

I_DDOx

15

18

3.3 V LVCMOS⁴

22

30

Output @ 156.25 MHz

2.5 V LVCMOS⁴

Output @ 156.25 MHz

—

18

12

23

16

mA

1.8 V LVCMOS⁴

Output @ 156.25 MHz

Total Power Dissipation⁵

Si5383, 1 PPS Input Mode¹

Si5383, Standard Input Mode²

P_d

—

10

1265

1255

1100

—

1620

1610

1410

—

mW

µs

Si5384, 1 PPS Input Mode¹

Time to V_DDA> 2.2 V

Analog Supply Voltage Ramp

Time

t_{RMP_VDDA}

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Rev. 1.0 | 26

Si5383/84 Rev D Data Sheet

Electrical Specifications

Parameter

Notes:

Symbol

Test Condition

Min

Typ

Max

Unit

1. Test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. 1 PPS input enabled on DSPLL D. Excludes power in termi-

nation resistors.

2. Test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. 1 PPS input not enabled. Excludes power in termination re-

sistors.

3. Differential outputs terminated into an AC coupled 100 Ω load.

4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV=

3, which is the strongest driver setting. Refer to the Si5383/84 Reference Manual for more details on register settings.

5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not

available. All EVBs support detailed current measurements for any configuration.

LVCMOS Output Test Configuration

Differential Output Test Configuration

Trace length 5

inches

0.1 uF

56 Ω

0.1 uF

56 Ω

I_DDO

499 Ω

4.7 pF

I_DDO

0.1 uF

50

50 Ω Scope Input

50

OUT

OUTb

OUT

100

OUTb

499 Ω

4.7 pF

50

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Rev. 1.0 | 27

Si5383/84 Rev D Data Sheet

Electrical Specifications

Table 5.3. Input Clock Specifications

(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Standard Input Buffer with Differential or Single-Ended/LVCMOS Configuration - AC-Coupled (IN0, IN1, IN2, REF)

Input Frequency Range

Voltage Swing ¹

f_IN

Differential

Single-ended/LVCMOS

REF

0.008

5

—

750

250

MHz

250

V_IN

Differential AC-coupled

f_IN< 250 MHz

100

1800

mVpp_se

V/μs

Differential AC-coupled

250 MHz < f_IN< 750 MHz

225

100

400

—

1800

3600

—

Single-Ended AC-coupled

f_IN< 250 MHz

Slew Rate ^2,3

SR

Duty Cycle

DC

C_IN

R_IN

40

—

0.3

16

8

60

—

%

pF

kΩ

Input Capacitance

Input Resistance

Differential

Single-ended/LVCMOS

Pulsed CMOS - DC-coupled (IN0, IN1, IN2) ⁴

Input Frequency

f_{IN_}

Standard Mode

1 PPS Mode

0.008

—

1

250

—

MHz

Hz

V

PULSED

Input Voltage

V_IL

V_IH

SR

PW

—

0.4

—

0.8

400

V

Slew Rate ^2,3

—

V/μs

Minimum Pulse Width

Standard Mode

1 PPS Mode

1.6

10

—

8

—

ns

us

kΩ

Input Resistance

R_IN

LVCMOS - DC Coupled (IN3, IN4)

Input Frequency

f_{IN_PULSE}

Standard Mode

1 PPS Mode

0.008

—

1

2.048

MHz

Hz

V

D

—

Input Voltage

V_IL

V_IH

PW

—

0.7xV_DDA

50

—

20

0.3xV_DDA

—

V

Minimum Pulse Width

Input Resistance

Standard Mode, Pulse Input

1 PPS Mode, Pulse Input

ns

us

kΩ

10

R_IN

—

XA/XB (if driven from external oscillator)

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Rev. 1.0 | 28

Si5383/84 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

XA/XB Frequency

f_{IN_XAXB}

Full operating range. Jitter

24.97

—

54.06

MHz

performance may be reduced.

Frequency range for best output jitter

performance.

48

—

54

MHz

Input Voltage Swing

V_{IN_SE}

V_{IN_DIFF}

SR

Single-ended

Differential

365

400

40

—

2000

2500

—

mVpp_se

mVpp_diff

V/μs

Slew rate ^2,3

Input Duty Cycle

Note:

Imposed for best jitter performance

DC

60

%

1. Voltage swing is specified as single-ended mVpp.

OUTx

Vcm

Vpp_se

Vpp_diff = 2*Vpp_se

Vcm

OUTxb

2. Imposed for jitter performance.

3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20= ((0.8 - 0.2) x V_{IN_Vpp_se}) / SR.

4. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because

they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since

the input thresholds (V_IL, V_IH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for

DC-coupled Pulsed LVCMOS in the Si5383/84 Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Stand-

ard AC-coupled, Single-ended input mode.

Table 5.4. Control Input Pin Specifications

(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5383/84 Control Input Pins (FINC, FDEC, OEb)

Input Voltage

V_IL

V_IH

—

0.3 x

V_DDA

V

0.7 x

V_DDA

—

Input Capacitance

Input Resistance

Minimum Pulse Width

Update Rate

C_IN

R_L

—

2

—

1

pF

kΩ

20

—

PW

F_UR

FINC, FDEC

100

—

ns

MHz

Si5383/84 Control Input Pin (SCL, SDA, A1, A0, BLMDb, RSTb)

Input Voltage

V_IL

—

0.3 x

V_DDA

V

V_IH

0.7 x

V_DDA

—

Input Capacitance

C_IN

PW

—

7

—

pF

μs

Minimum Reset Pulse Width

15

—

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Rev. 1.0 | 29

Si5383/84 Rev D Data Sheet

Electrical Specifications

Table 5.5. Differential Clock Output Specifications

(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Standard input mode

DSPLL D in 1 PPS mode

Min

0.0001

—

Typ

—

1

Max

718.5

685

Unit

MHz

Hz

Output Frequency

f_OUT

f_OUT1Hz

1 PPS signal only available on

Output 5

—

Duty Cycle

DC

f_OUT< 400 MHz

48

45

—

52

55

65

%

ps

400 MHz < f_OUT< 712.5 MHz

Output-Output Skew

OUT-OUTb Skew

T_SK

T_{SK_OUT}

V_OUT

Outputs on same DSPLL

(measured at 712.5 MHz)

Measured from the positive to negative

output pins

—

0

50

ps

Output Voltage Amplitude ¹

Common-Mode Voltage ¹

V_DDO= 3.3 V, 2.5 V, or 1.8 V

V_DDO= 3.3 V, or 2.5 V

V_DDO= 3.3 V

LVDS

350

640

430

750

510

900

mVpp_se

LVPECL

LVDS

V_CM

1.10

1.90

1.10

1.20

2.00

1.20

1.30

2.10

1.30

V

LVPECL

V_DDO= 2.5 V

V_DDO= 1.8 V

LVPECL

, LVDS

sub-

LVDS

0.80

—

0.90

100

1.00

150

Rise and Fall Times

(20% to 80%)

t_R/t_F

ps

Differential Output Impedance

Z_O

—

100

–99

–96

–94

–93

–86

—

Ω

Power Supply Noise

Rejection ²

PSRR

10 kHz sinusoidal noise

100 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

dBc

Output-output Crosstalk ³

Measured spur from adjacent output ³

XTALK

dBc

Notes:

1. Output amplitude and common-mode voltage are programmable through register settings and can be stored in NVM. Each output

driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/

EIA-644 maximum. Refer to the Si5383/84 Family Reference Manual for more suggested output settings. Not all combinations of

voltage amplitude and common-mode voltages settings are possible.

2. Measured for 156.25 MHz carrier frequency. 100mVpp of sinewave noise added to VDDO = 3.3V and noise spur amplitude

measured.

3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25

MHz. Refer to application note, AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems,

for guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk.

OUTx

Vpp_se

Vcm

Vpp_diff = 2*Vpp_se

OUTxb

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Rev. 1.0 | 30

Si5383/84 Rev D Data Sheet

Electrical Specifications

Table 5.6. LVCMOS Clock Output Specifications

(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

f_OUT

Test Condition

Min

0.0001

—

Typ

—

1

Max

250

—

Unit

MHz

Hz

Output Frequency

f_OUT1Hz

DC

Only Available on Output 5

f_OUT<100 MHz

Duty Cycle

48

—

30

52

%

100 MHz < f_OUT< 250 MHz

45

55

Output-to-Output Skew

T_SK

When outputs are on same DSPLLs

with the same R dividers

—

140

ps

V

Output Voltage High ^{1 ,2 ,3}

V_OH

V_DDO= 3.3 V

OUTx_CMOS_DRV=1 I_{OH =}-10 mA

OUTx_CMOS_DRV=2 I_{OH =}-12 mA

OUTx_CMOS_DRV=3 I_{OH =}-17 mA

V_DDO

0.85

x

—

V_DDO= 2.5 V

OUTx_CMOS_DRV=1 I_{OH =}-6 mA

OUTx_CMOS_DRV=2 I_{OH =}-8 mA

OUTx_CMOS_DRV=3 I_{OH =}-11 mA

V_DDO

0.85

x

—

V

V_DDO= 1.8 V

OUTx_CMOS_DRV=2 I_{OH =}-4 mA

OUTx_CMOS_DRV=3 I_{OH =}-5 mA

V_DDO

0.85

x

—

V

Output Voltage Low ^{1 ,2 ,3}

V_OL

V_DDO= 3.3 V

OUTx_CMOS_DRV=1 I_OL= 10 mA

OUTx_CMOS_DRV=2 I_OL= 12 mA

OUTx_CMOS_DRV=3 I_OL= 17 mA

—

V_DDO

0.15

x

—

V_DDO= 2.5 V

OUTx_CMOS_DRV=1 I_OL= 6 mA

OUTx_CMOS_DRV=2 I_OL= 8 mA

OUTx_CMOS_DRV=3 I_OL= 11 mA

—

V_DDO

0.15

V

—

V_DDO= 1.8 V

OUTx_CMOS_DRV=2 I_OL= 4 mA

OUTx_CMOS_DRV=3 I_OL= 5 mA

VDDO = 3.3 V

—

V_DDO

0.15

V

—

LVCMOS Rise and Fall Times ³

(20% to 80%)

tr/tf

400

450

550

600

750

ps

VDDO = 2.5 V

VDDO = 1.8 V

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Rev. 1.0 | 31

Si5383/84 Rev D Data Sheet

Electrical Specifications

Parameter

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the

Si5383/84 Reference Manual for more details on register settings.

2. I_OL/I_OHis measured at V_OL/V_OHas shown in the dc test configuration.

DC Test Configuration

I_OL/I_OH

Zs

V_OL/V_OH

3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, at 156.25 MHz.

LVCMOS Output Test Configuration

Differential Output Test Configuration

Trace length 5

inches

0.1 uF

56 Ω

0.1 uF

56 Ω

I_DDO

499 Ω

4.7 pF

I_DDO

0.1 uF

50

50 Ω Scope Input

50

OUT

OUTb

OUT

100

OUTb

499 Ω

4.7 pF

50

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Rev. 1.0 | 32

Si5383/84 Rev D Data Sheet

Electrical Specifications

Table 5.7. Output Status Pin Specifications

(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5383/84 Status Output Pins ( INTRb, LOL_Ab, LOL_Cb, LOL_Db, and LOL_REF)

Output Voltage

V_OH

V_OL

I_OH= -2 mA

I_OL= 2 mA

V_DDAx 0.85

—

V

V_DDAx 0.15

V

Si5383/84 Status Output Pins (SDA, SCL and RSTb)^{1, 2}

Output Voltage

V_OL

I_OL= 6.5 mA

—

0.6

V

Note:

1. V_OHspecifications do not apply apply to open-drain outputs.

2. SCL driven low during clock stretching. RSTb driven low during power up and when VDDA falls below minimum operating thresh-

old.

Table 5.8. Performance Characteristics

(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

PLL Loop Bandwidth Pro-

gramming Range ²

f_BW

0.001

—

4000

Hz

Initial Start-Up Time¹

t_START

1 PPS Input Mode, after

Power-Up or Hardware

Reset

—

3.1

0.04

280

4.25

0.17

300

s

Standard Input Mode, after

Power-Up or Hardware

Reset

PLL Lock Time

t_ACQ

Standard Mode, with

Fastlock enabled ³

ms

1 PPS Mode ⁹

—

5

min

ms

Serial Interface Ready

Time ⁴

t_RDY

After Power-Up

or Hardware Reset

75

Flash Memory Endurance

(Write/Erase Cycles)

N_WE

20 k

—

100 k

—

Cycles

dB

Jitter Peaking

J_PK

Measured with a frequency

plan running a 25 MHz in-

put, 25 MHz output, and a

loop bandwidth of 4 Hz

0.1

Jitter Tolerance

J_TOL

Compliant with G.8262 Op-

tions 1&2, Standard Input

Mode

—

3180

—

UI pk-pk

Carrier Frequency =

10.3125 GHz

Jitter Modulation Frequency

= 10 Hz

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Rev. 1.0 | 33

Si5383/84 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Maximum Phase Transient

During a Hitless Switch ⁷

t_SWITCH

Standard input mode, single

manual or automatic switch

between two input clocks at

same frequency.

—

1.2

ns

Pull-in Range ⁶

ωP

Standard mode

1 PPS mode

-500

-10

0

—

+500

+10

1.8

ppm

ns

ωP_1PPS

t_IODELAY

Input-to-Output Delay Varia-

tion⁸

Standard input mode

1 PPS Input-to-Output

Phase Delay

t_{DELAY_1PPS}

1 PPS mode. Assumes

noise-free 1 PPS and refer-

ence inputs. Measured be-

tween a 1 PPS input and 1

PPS output from DSPLL D

after fully settling.

-10

—

10

ns

RMS Phase Jitter ⁵

J_GEN

12 kHz to 20 MHz

—

0.130

—

ps RMS

Notes:

1. Time from hardware reset or when VDD reaches 90% of nominal value to when the device generates free-running clocks.

2. Actual loop bandwidth might be lower; please refer to CBPro for actual value on your frequency plan.

3. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock

time was measured with fastlock bandwidth set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively, using IN0 as clock

reference by removing the reference and enabling it again, then measuring the delta time between the first rising edge of the

clock reference and the LOL indicator de-assertion.

4. Time from hardware reset or when VDD reaches 90% of nominal value to when the serial interface is ready to respond to com-

mands.

5. Jitter generation test conditions: f_IN= 19.44 MHz, f_OUT= 156.25 MHz LVPECL. (Does not include jitter from input reference).

6. With respect to 0 ppm assuming REF input is ±5 ppm.

7. For input frequency configurations which have F_PFD> 1 MHz. Consult your CBPro design report for the F_PFDfrequency of your

configuration.

8. Measured from input to one or more outputs with the same input and output frequencies and F_PFD> 1 MHz. Higher variation may

be present when F_PFD< 1 MHz.

9. Assumes noise-free 1 PPS and reference inputs, and 1 mHz or 10 mHz loop bandwidth. Lock declared when the settling error is

below 75/F_VCO

.

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Rev. 1.0 | 34

Si5383/84 Rev D Data Sheet

Electrical Specifications

Table 5.9. I2C Timing Specifications (SCL,SDA)

(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Con-

dition

Standard Mode

100 kbps

Fast Mode

400 kbps

Max

Unit

Min

-

Max

100

—

Min

—

SCL Clock Frequency

f_SCL

t_HD:STA

t_LOW

400

—

kHz

μs

Hold time (repeated) START condition

Low period of the SCL clock

HIGH period of the SCL clock

4.0

4.7

4.0

4.7

0.6

1.3

0.6

—

μs

t_HIGH

—

μs

Set-up time for a repeated START

condition

t_SU:STA

—

μs

Data hold time

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

100

250

4.0

—

100

0.6

—

ns

μs

Data set-up time

Set-up time for STOP condition

Bus free time between a STOP and

START condition

4.7

1.3

Figure 5.1. I²C Serial Port Timing Standard and Fast Modes

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Rev. 1.0 | 35

Si5383/84 Rev D Data Sheet

Electrical Specifications

Table 5.10. Crystal Specifications¹

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Crystal Frequency Range

f_XTAL

Full operating range. Jitter

24.97

—

54.06

MHz

performance may be reduced.

Range for best jitter.

48

—

8

54

—

MHz

pF

Load Capacitance

Crystal Drive Level

C_L

d_L

—

200

μW

Equivalent Series Resistance

Shunt Capacitance

r_{ESR CO}Refer to the Si5383/84 Reference Manual to determine ESR and shunt capacitance.

Note:

1. Refer to the Si534x/8x Jitter Attenuating Clock, Recommended Crystal, TCXO and OCXO Reference Manual for recommended

48 to 54 MHz crystals. The Si5383 and Si5384 are designed to work with crystals that meet these specifications.

Table 5.11. Thermal Characteristics

Test Condition ¹

Parameter

Symbol

Value

Unit

Si5383-56LGA and Si5384-56LGA

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

Thermal Resistance Junction to Board

Thermal Resistance Junction to Top Center

Note:

ϴ_JA

ϴ_JC

ϴ_JB

Ψ_JT

24.0

9.5

7.7

0.5

Still Air

°C/W

1. Based on PCB Dimension: 4" × 4.5", PCB Thickness: 1.6 mm, Number of Cu Layers: 4.

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Rev. 1.0 | 36

Si5383/84 Rev D Data Sheet

Electrical Specifications

Table 5.12. Absolute Maximum Ratings ^{1, 2, 3}

Parameter

Symbol

T_STG

V_DD

Test Condition

Value

Unit

°C

V

Storage Temperature Range

DC Supply Voltage

–55 to 150

–0.3 to 3.8

V_DDA

V_DDO

V_I1

V

Input Voltage Range

IN0 - IN2, REF

–1.0 to V_DDA

0.3

+

V

V_I2

IN3, IN4, OEb, FINC, FDEC

–0.5 to V_DDA

0.3

V

V_I3

V_I4

XA/XB

–0.5 to 2.7

V

RSTb, SDA, SCL, A1, A0, BLMDb

–0.3 to V_DDA

0.3

+

Latch-up Tolerance

LU

JESD78 Compliant

ESD Tolerance

HBM

T_JCT

T_PEAK

100 pF, 1.5 kΩ

2.0

125

260

kV

°C

Max Junction Temperature in Operation

Soldering Temperature (Pb-free profile) ³

Soldering Temperature Time at T_PEAK(Pb-

free profile) ⁴

T_P

20-40

s

Note:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to

the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

2. 56-LGA package is RoHS-6 compliant.

3. For detailed MSL and packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.

4. The device is compliant with JEDEC J-STD-020.

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Rev. 1.0 | 37

Si5383/84 Rev D Data Sheet

Typical Application Diagrams

6. Typical Application Diagrams

Telecom Boundary Clock (T-BC)

Master Ports

Slave Ports

Ethernet

Packets

Ethernet

Packets

FPGA/CPU

1588 Stack

PHY

1588 Servo

Loop

MAC

DCO

Control

Si5383

DSPLL D

1 PPS

÷

1 PPS

GPS

System

Clock(s)

Serial I/F

DSPLL C

÷

General Purpose

Clocks or

Wireless/LTE Clocks

DSPLL A

Figure 6.1. Using the Si5383/84 as a Telecom Boundary Clock

SyncE Jitter/Wander Attenuator

Master Ports

Slave Ports

Ethernet

Packets

Ethernet

Packets

PHY

FPGA/CPU

MAC

Si5384

DSPLL

÷

System

Clock(s)

Serial I/F

Figure 6.2. Si5384 as a SyncE Jitter/Wander Attenuator

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Rev. 1.0 | 38

Si5383/84 Rev D Data Sheet

Typical Application Diagrams

IEEE 1588 DCO

FPGA/CPU

1588 Stack

PHY

1588 Servo

Loop

MAC

DCO Control

Si5384

1 PPS

System Clocks

DSPLL

÷

TCXO/

OCXO

Figure 6.3. Si5384 as an IEEE 1588 DCO

GPS 1 PPS Clock Multiplier

Si5384

1 PPS

DSPLL

÷

1 PPS

GPS

System Clocks

Figure 6.4. Si5384 as a 1 Hz/1 PPS Clock Multiplier

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Rev. 1.0 | 39

Si5383/84 Rev D Data Sheet

Detailed Block Diagram

7. Detailed Block Diagram

5MHz – 250MHz

TCXO/OCXO

or REFCLK

XTAL

XB

REF

XA

REFb

Si5383/84

OSC

Output

Crosspoint

DSPLL_A

PD LPF

DCO

VDDO0

OUT0

OUT0b

A

C

D

÷R₀

f

M_{n_A}

VDDO1

OUT1

OUT1b

÷

A

C

D

M_{d_A}

÷R₁

IN0

IN0b

P_0n

P_0d

÷

DSPLL_C

PD LPF

DCO

f

VDDO2

OUT2

OUT2b

A

C

D

IN1

P_1n

P_1d

÷

÷R₂

÷R₃

IN1b

IN2

P_2n

P_2d

VDDO3

OUT3

OUT3b

IN2b

M_{n_C}

A

C

D

÷

M_{d_C}

VDDO4

OUT4

OUT4b

A

C

D

DSPLL_D

PD LPF

DCO

f

÷R₄

÷R₅

IN3

IN4

VDDO5

OUT5

OUT5b

M_{n_D}

A

C

D

÷

M_{d_D}

R6

SDA

SCL

VDDO6

OUT6

OUT6b

I²C

D

C

A

A0

A1

÷R₆

Status

Monitors

BLMDb

RSTb

NVM

Figure 7.1. Si5383/84 Detailed Block Diagram

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Rev. 1.0 | 40

Si5383/84 Rev D Data Sheet

Typical Operating Characteristics (Jitter and Phase Noise)

8. Typical Operating Characteristics (Jitter and Phase Noise)

Figure 8.1. F_IN= 19.44 MHz; F_OUT= 156.25 MHz, 3.3 V LVPECL with Rakon 12.8 MHz Reference, 48 MHz Crystal

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Rev. 1.0 | 41

Si5383/84 Rev D Data Sheet

Pin Descriptions

9. Pin Descriptions

Si5383 56LGA

Top View

Si5384 56LGA

Top View

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

2

42

IN1

IN1b

RSVD

IN3

IN4

X1

LOL_REFb

2

41

IN1b

LOL_Ab

VDD

RSVD

VDD

3

4

3

40

39

38

37

36

35

34

33

32

31

30

29

LOL_Cb

IN3

IN4

X1

4

OUT4

OUT4b

VDDO4

OUT3

5

OUT4b

VDDO4

OUT3

6

7

GND

Pad

GND

Pad

XA

8

XB

OUT3b

VDDO3

OUT2

OUT3b

VDDO3

OUT2

9

X2

10

11

12

13

14

10

11

12

13

14

INTRb

VDDA

IN2

INTRb

VDDA

IN2

OUT2b

VDDO2

A0

OUT2b

VDDO2

A0

IN2b

FINC

IN2b

FINC

RSTb

Figure 9.1. Si5383 Pins

Figure 9.2. Si5384 Pins

Table 9.1. Si5383/84 Pin Descriptions ¹

Pin Name¹

Inputs

Pin Type ²

Pin Number

Function

XA

XB

X1

X2

7

8

6

9

I

Crystal Input. Input pin for external crystal (XTAL).

XTAL Shield. Connect these pins directly to the XTAL ground pins. The

XTAL ground pins should be separated from the PCB ground plane. Re-

fer to the Si5383/84 Reference Manual for layout guidelines.

IN0

IN0b

IN1

55

56

1

I

Clock Inputs. IN0-IN2 accept an input clock for synchronizing the device.

They support both differential and single-ended clock signals. Refer to In-

put Configuration and Terminations input termination options. These pins

are high-impedance and must be terminated externally. The negative side

of the differential input must be grounded through a capacitor when ac-

cepting a single-ended clock. IN3 and IN4 only support single ended

LVCMOS signals.These pins are high-impedance and must be termina-

ted externally. IN0-IN2 can be disabled by register configuration and the

pins left unconnected if unused. IN3 and IN4 must be externally pulled

low when unused.

IN1b

IN2

2

12

13

4

IN2b

IN3

IN4

5

REF

REFb

53

54

Reference Input. This input accepts a reference clock from a stable

source (eg. TCXO or OCXO) that is used to determine free-run frequency

accuracy and stability during free-run or holdover of the DSPLL or DCO.

These inputs can accept differential or single-ended connections. Refer to

the Si5383/84 Reference Manual for recommended TCXOs and OCXOs.

Outputs

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Rev. 1.0 | 42

Si5383/84 Rev D Data Sheet

Pin Descriptions

Pin Name¹

OUT0

Pin Type ²

Pin Number

Function

24

23

27

26

33

32

36

35

39

38

45

44

48

47

O

Output Clocks. These output clocks support a programmable signal am-

plitude and common-mode voltage. Desired output signal format is con-

figurable using register control.Termination recommendations are provi-

ded in Differential Output Terminations. Unused outputs should be left un-

connected.

OUT0b

OUT1

OUT1b

OUT2

OUT2b

OUT3

OUT3b

OUT4

OUT4b

OUT5

OUT5b

OUT6

OUT6b

Serial Interface

SDA

Serial Data Interface. This is the bidirectional data pin (SDA) for the I²C

interface. This pin must be pulled high to V_DDAusing an external resistor

of at least 1 kΩ.

51

50

I/O

Serial Clock Input Interface. This is the bidirectional I²C clock pin. Clock

stretching (i.e., driving SCL low to insert wait-states) will be utilized when

operating at rates greater than 100 kHz. This pin must be pulled up to

V_DDAusing an external resistor of at least 1 kΩ.

SCL

A1

I²C Address Select 1. This pin functions as the optional A1 I²C address

input pin. Attach a 4.7 kΩ pull-up resistor to V_DDA, or a 4.7 kΩ pull-down

resistor to ground to select the I²C slave address. This pin can be left

floating if unused.

17

30

I/O

I²C Address Select 0. This pin functions as the optional A0 I²C address

A0

input pin. Attach a 4.7 kΩ pull-up resistor to V_DDA, or a 4.7 kΩ pull-down

resistor to ground to select the I²C slave address. This pin can be left

floating if unused.

Control/Status

INTRb

10

29

O

Interrupt. This pin is asserted low when a change in device status has

occurred. It should be left unconnected when not in use.

RSTb

I/O

Device Reset. This pin functions as an active-low reset input/output. As

an input, the pin is used to generate a device reset when held low for

more than 15 us. This resets all internal logic to a known state and forces

device registers to their default values. Clock outputs are disabled during

reset. As an open-drain output, the pin will be driven low during POR. Ex-

ternal devices must be configured as open-drain to avoid contention.

OEb

15

I

Output Enable. This output enable pin has a programmable register

mask which allows it to control any of the output clocks. By default the

OEb pin enables all output clocks. This pin must be externally pulled low

when not in use.

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Rev. 1.0 | 43

Si5383/84 Rev D Data Sheet

Pin Descriptions

Pin Name¹

LOL_Ab

Pin Type ²

Pin Number

Function

41

O

Loss of Lock_A/C/D/REF. These output pins indicate when DSPLL A, C,

D and the REF input is out-of-lock (low) or locked (high). They can be left

unconnected when not in use.

(Si5383 only)

LOL_Cb

3

O

(Si5383 only)

LOL_Db

21

42

16

O

I

LOL_REF

FDEC

Frequency Decrement Pin. This pin is used to step-down the output fre-

quency of a selected DSPLL. The frequency change step size is register

configurable. This pin must be externally pulled low when not in use.

FINC

14

19

I

Frequency Increment Pin . This pin is used to step-up the output fre-

quency of a selected DSPLL. The frequency change step size is register

configurable. This pin must be externally pulled low when not in use.

BLMDb

Bootloader Enable. This pin should be driven low on reset negation to

enable bootloader mode. Under normal operation, this pin should be

pulled up to V_DDAwith a 4.7K resistor.

RSVD

41

3

—

Reserved. Leave disconnected.

(Si5384 only)

Power

VDD

28

40

52

11

18

49

20

22

25

31

34

37

43

46

—

P

Core Supply Voltage. The device core operates from a 1.8 V supply.

See the Si5383/84 Reference Manual for power supply filtering recom-

mendations. A 0402 1 μF capacitor should be placed very near each of

these pins.

VDDA

Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V power

source. See the Si5383/84 Reference Manual for power supply filtering

recommendations. A 0402 1 μF capacitor should be placed very near

each of these pins.

VDDO0

VDDO1

VDDO2

VDDO3

VDDO4

VDDO5

VDDO6

GND PAD

P

Output Clock Supply Voltage 0-6. Supply voltage (3.3 V, 2.5 V, 1.8 V)

for OUTn outputs. Leave VDDO pins of unused output drivers unconnec-

ted. An alternate option is to connect the VDDO pin to a power supply

and disable the output driver to minimize current consumption. A 0402 1

μF capacitor should be placed very near each of these pins.

Ground Pad. This pad provides connection to ground and must be con-

nected for proper operation. Use as many vias as practical and keep the

via length to an internal ground plane as short as possible.

Note:

1. Refer to the Si5383/84 Reference Manual for more information on register setting names.

2. I = Input, O = Output, P = Power.

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Rev. 1.0 | 44

Si5383/84 Rev D Data Sheet

Package Outline

10. Package Outline

The figure below illustrates the package details for the Si5383/84. The table below lists the values for the dimensions shown in the

illustration.

Figure 10.1. Si5383/84 8x8 mm 56-Pin LGA

Table 10.1. Package Dimensions

Dimension

Min

0.90

0.22

0.20

Nom

0.95

Max

1.00

0.30

A

A1

b

0.26

0.25

D

8.00 BSC

4.90

D2

e

4.80

5.00

0.50 BSC

8.00 BSC

4.90

E

E2

L

0.363 BSC

0.12

L1

aaa

bbb

ccc

ddd

eee

0.00

—

0.18

0.10

0.15

0.10

0.15

0.05

—

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Rev. 1.0 | 45

Si5383/84 Rev D Data Sheet

Package Outline

Dimension

Min

Nom

Max

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Rev. 1.0 | 46

Si5383/84 Rev D Data Sheet

PCB Land Pattern

11. PCB Land Pattern

The figure below illustrates the PCB land pattern details for the devices. The table below lists the values for the dimensions shown in

the illustration. Refer to the Si5383/84 Reference Manual for information about thermal via recommendations.

Figure 11.1. Si5383/84 PCB Land Pattern

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Rev. 1.0 | 47

Si5383/84 Rev D Data Sheet

PCB Land Pattern

Table 11.1. PCB Land Pattern Dimensions

Dimension

Si5383/84 IPC-7351

(Max)

Si5383/84 Alternative Dimensions with

Larger Pads

(Max)¹

7.90

0.50

0.30

0.85

4.95

C1

C2

E

7.50

0.50

0.30

0.45

4.95

X1

Y1

X2

Y2

Note:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted. Least Material Condition (LMC) is calculated based on a

Fabrication Allowance of 0.05 mm.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

4. A 3x3 array of 1.45 mm square openings on 2.0 mm pitch should be used for the center ground pad to achieve a target of ~50%

solder coverage.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Alternative Land Pattern

1. This alternative land pattern may be used if desired to facilitate easier rework and/or manual soldering

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Rev. 1.0 | 48

Si5383/84 Rev D Data Sheet

Top Marking

12. Top Marking

Figure 12.1. Si5383 Top Marking

Figure 12.2. Si5384 Top Marking

Table 12.1. Top Marking

Line

Characters

Si5383g-

Description

1

Base part number and Device Grade.

Si5384g-

Si5383: 3-PLL Packet Network Synchronizer for SyncE/1588

Si5384: 1-PLL Packet Network Synchronizer for SyncE/1588

g = Device Grade. See Chapter 2. Ordering Guide for more information.

– = Dash character.

2

Rxxxxx-GM

R = Product revision. (See Chapter 2. Ordering Guide for current revision.)

xxxxx = Customer specific NVM sequence number or firmware revision number.

-GM = Package (LGA) and temperature range (–40 to +85 °C).

3

4

YYWWTTTTTT

YYWW = Characters correspond to the year (YY) and work week (WW) of package as-

sembly.

TTTTTT = Manufacturing trace code.

Pin 1 indicator; left-justified

Circle w/ 1.6 mm diameter

e4

Pb-free symbol; Center-Justified

TW

TW = Taiwan; Country of Origin (ISO Abbreviation)

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Rev. 1.0 | 49

Si5383/84 Rev D Data Sheet

Device Errata

13. Device Errata

Please log in or register at www.silabs.com to access the device errata document.

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Rev. 1.0 | 50

Si5383/84 Rev D Data Sheet

Revision History

14. Revision History

14.1 Revision 0.8

• Added Si5384 part number and related specifications to all tables and figures.

• Updated description on front page.

• Updated values in Table 2.1.

• Updated text and corrected typographical errors in Section 3.

• Updated Figure 3.1 and Figure 3.4.

• Updated resistor values in Figure 3.8.

• Added Section 3.8.6 and 3.10.15.

• Updated Figures 3.14, 3.15, and 3.16.

• Removed a figure that incorrectly described OEb functionality.

• Added Section 3.12

• Updated values in Table 5.1, Table 5.2, Table 5.3, Table 5.4, Table 5.5, Table 5.6, Table 5.7, Table 5.8, Table 5.9, Table 5.10, Table

5.11, and Table 5.12.

• Updated Figure 6.1

• Added Figure 6.2

• Updated Figure 7.1

• Added Figure 8.1

• Updated Figure 9.1

• Added Figure 9.2

• Updated pin descriptions in Table 9.1

• Updated Figure 10.1

• Updated Table 10.1

• Updated Table 11.1.

• Updated Figure 12.1

• Added Figure 12.2

• Updated Table 12.1

14.2 Revision 1.0

April 27, 2017

• Updated 1. Feature List.

• Updated OPN information in section 2. Ordering Guide and 2.1 Ordering Part Number Fields.

• Added text about device reset recommendations in section 3.5.1 Initialization and Reset.

• Updated sections 3.10.9 Output Enable/Disable and 3.10.13 Synchronous/Asynchronous Output Disable.

• Updated values and added new test conditions to Table 5.2 DC Characteristics on page 26.

• Updated values in Table 5.5 Differential Clock Output Specifications on page 30.

• Update values and added new test conditions and footnotes 7-9 in Table 5.8 Performance Characteristics on page 33.

• Updated values in Table 5.11 Thermal Characteristics on page 36.

Removed t_VD:DATfrom Figure 5.1 I²C Serial Port Timing Standard and Fast Modes on page 35.

•

• Updated and added new diagrams in section 6. Typical Application Diagrams.

• Updated Figure 7.1 Si5383/84 Detailed Block Diagram on page 40.

• Updated Figure 8.1 F_IN= 19.44 MHz; F_OUT= 156.25 MHz, 3.3 V LVPECL with Rakon 12.8 MHz Reference, 48 MHz Crystal on page

41.

• Corrected the name of pin 19 in Figure 9.1 Si5383 Pins on page 42 and Figure 9.2 Si5384 Pins on page 42.

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Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

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型号：	SI5383A-D07172-GMR
厂家：	SILICON
描述：	Telecom Circuit, 电信电信集成电路
文件：	总55页 (文件大小：919K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI5383A-D07172-GMR [SILICON]

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