SI8055CA-B-IU [SILICON]
1 KV THREE TO SIX-CHANNEL DIGITAL ISOLATORS;
| 型号： | SI8055CA-B-IU |
| 厂家： | 
SILICON |
| 描述： | 1 KV THREE TO SIX-CHANNEL DIGITAL ISOLATORS |
| 文件： | 总23页 (文件大小：1552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si80xx-1kV
1 KV THREE TO SIX-CHANNEL DIGITAL ISOLATORS
Features
High-speed operation
DC to 10 Mbps
Default high or low output
Precise timing (typical)
No start-up initialization required
Wide Operating Supply Voltage
3.15 – 5.5 V
40 ns propagation delay
20 ns pulse width distortion
100 ns minimum pulse width
Transient Immunity 50 kV/µs
Up to 1000 V
isolation
RMS
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
High electromagnetic immunity
Low power consumption (typical)
2.3 mA per channel at 10 Mbps
Tri-state outputs with ENABLE
Schmitt trigger inputs
Ordering Information:
RoHS-compliant packages
QSOP-16
See page 18.
Applications
Industrial automation systems
Medical electronics
Isolated ADC, DAC
Power inverters
Hybrid electric vehicles
Communication systems
Description
Silicon Lab's family of low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability,
and external BOM advantages over legacy isolation technologies. The
operating parameters of these products remain stable across wide
temperature ranges and throughout device service life for ease of
design and highly uniform performance. All device versions have
Schmitt trigger inputs for high noise immunity and only require VDD
bypass capacitors. Data rates up to 10 Mbps are supported, and all
devices achieve propagation delays of less than 65 ns. Enable inputs
provide a single point control for enabling and disabling output drive.
Ordering options include a choice of 1kV
isolation ratings.
RMS
Rev. 1.0 1/14
Copyright © 2014 by Silicon Laboratories
Si80xx-1kV
Si80xx
2
Rev. 1.0
Si80xx
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4. Pin Descriptions (Si8030/35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. Pin Descriptions (Si8040/45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6. Pin Descriptions (Si8050) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7. Pin Descriptions (Si8055) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8. Pin Descriptions (Si8065) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
10. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
11. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
12.1. Top Marking (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
12.2. Top Marking Explanation (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Rev. 1.0
3
Si80xx
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
Min
–40
Typ
25
—
Max
125
5.5
Unit
ºC
V
T
A
V
3.15
3.15
DD1
DD2
V
—
5.5
V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 3.15 to 5.5 V, VDD2 = 3.15 to 5.5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage
Threshold
VDDUV+
V
, V
rising
2.65
2.80
3.05
V
DD1
DD2
VDD Undervoltage
Threshold
VDDUV–
V
, V
falling
2.2
—
2.50
270
1.6
2.75
—
V
mV
V
DD1
DD2
VDD Undervoltage
Threshold Hysteresis
VDD
HYS
Positive-Going Input
Threshold
VT+
VT–
All inputs rising
1.4
1.0
1.9
1.4
Negative-Going
Input Threshold
All inputs falling
1.2
V
Input Hysteresis
V
—
2.0
—
0.40
—
—
—
V
V
V
V
HYS
High Level Input Voltage
Low Level input voltage
High Level Output Voltage
V
IH
V
—
0.8
—
IL
V
loh = –4 mA
lol = 4 mA
V
,V
–
4.8
OH
DD1 DD2
0.4
—
—
—
—
—
Low Level Output Voltage
Input Leakage Current
V
0.2
—
0.4
±10
—
V
OL
I
µA
L
1
Output Impedance
Z
50
2.0
16
O
Enable Input High Current
Enable Input Low Current
Supply Current (DC)
I
V
= V
IH
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
V
V
V = 0, 1
—
—
4.4
7.5
7.5
10
mA
mA
DD1
DD2
I
C = 15 pF
L
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.0
Si80xx
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.15 to 5.5 V, VDD2 = 3.15 to 5.5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current (10 Mbps)
V
V
V = 5 MHz
—
—
4.4
9.4
7.5
12
mA
mA
DD1
DD2
I
C = 15 pF
L
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
40
20
10
100
65
Mbps
ns
—
20
—
t
, t
See Figure 2
See Figure 2
ns
PHL PLH
Pulse Width Distortion
PWD
30
ns
|t
– t
|
PLH
PHL
2
Propagation Delay Skew
Channel-Channel Skew
Output Rise Time
t
—
—
—
20
20
30
30
ns
ns
ns
PSK(P-P)
t
PSK
t
C = 15 pF
See Figure 2
r
L
2.5
4.0
Output Fall Time
t
C = 15 pF
See Figure 2
—
ns
f
L
2.5
50
4.0
—
Common Mode
CMTI
V = V or 0 V
35
kV/µs
I
DD
Transient Immunity
V
= 1500 V (see Figure 3)
CM
Enable to Data Valid
t
t
See Figure 1
—
—
—
10
10
40
—
—
—
ns
ns
µs
en1
Enable to Data Tri-State
See Figure 1
en2
3
Start-up Time
t
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
Rev. 1.0
5
Si80xx
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 2. Propagation Delay Timing
3.15 to 5.5 V
Supply
Si80xx
VDD1
VDD2
Input
Signal
Switch
INPUT
OUTPUT
3.15 to 5.5 V
Isolated Supply
Oscilloscope
GND1
GND2
Isolated
Ground
High Voltage
Differential
Probe
Output
Input
Vcm Surge
Output
High Voltage
Surge Generator
Figure 3. Common Mode Transient Immunity Test Circuit
6
Rev. 1.0
Si80xx
Table 3. Thermal Characteristics
Parameter
Symbol
QSOP-16
Unit
IC Junction-to-Air Thermal Resistance
105
ºC/W
JA
Table 4. Absolute Maximum Ratings1
Parameter
Symbol
Min
Typ
—
—
—
—
—
—
—
—
—
Max
150
125
150
7.0
Unit
ºC
ºC
°C
V
2
Storage Temperature
T
–65
–40
—
STG
Ambient Temperature Under Bias
Junction Temperature
Supply Voltage
T
A
T
J
V
, V
–0.5
–0.5
–0.5
—
DD1
DD2
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
Output Current Drive Channel
I
22
mA
V/ns
ºC
O
3
Latchup Immunity
—
100
260
Lead Solder Temperature (10 s)
—
Maximum Isolation (Input to Output) (1 sec)
QSOP-16
—
—
1500
V
RMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. Latchup immunity specification is for slew rate applied across GND1 and GND2.
Rev. 1.0
7
Si80xx
2. Functional Description
2.1. Theory of Operation
The Si80xx comprises a transmitter and a receiver separated by a semiconductor-based isolation barrier. The
Si80xx uses a high-frequency internal oscillator on the transmitter to modulate digital input signals across the
capacitive isolation barrier. On the receiver side, these signals are demodulated back to the corresponding digital
output signals that are galvanically isolated from the input. This simple and elegant architecture provides a robust
data path and requires no special considerations or initialization at start-up. A simplified block diagram for an
Si80xx data channel is shown in Figure 4.
Si80xx
Transmitter
Receiver
Serializer
High
Demodulator
Deserializer
Frequency
Oscillator
Clock
Recovery and
Demodulator
Output
Latch
Packet
Decoder
Input
Latch
Input
Selector
B
A
Modulator/
Packet
Encoder
Figure 4. Simplified Channel Diagram
The transmitter consists of an input stage that latches in data from up to six asynchronous channels, followed by a
serializer stage where the data is compressed into serial data packets that are then coupled across the capacitive
isolation barrier. The receiver consists of a demodulator block that converts the modulated signal back into serial
data packets that are then deserialized and latched to the output.
8
Rev. 1.0
Si80xx
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 5, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 5 to determine outputs when
power supply (VDD) is not present. Additionally, refer to Table 6 for logic conditions when enable pins are used.
Table 5. Si80xx Logic Operation
1,2
V
EN
VDDI
VDDO
Comments
I
V Output
O
1,2,3,4
1,5,6
1,5,6
1,2
Input
State
State
Input
H
L
H or NC
H or NC
L
P
P
P
P
P
P
H
L
Enabled, normal operation.
7
8
X
P
Hi-Z
Disabled.
7
X
H or NC
UP
Upon transition of VDDI from unpowered to pow-
ered, V returns to the same state as V after Start-
9
L
9
O
I
H
up Time, t
SU
7
8
X
L
UP
P
P
Hi-Z
Disabled.
7
7
X
X
UP
Undetermined Upon transition of VDDO from unpowered to pow-
ered, V returns to the same state as V after Start-
O
I
up Time, t , if EN is in either the H or NC state.
SU
Upon transition of VDDO from unpowered to pow-
ered, V returns to Hi-Z after Start-up Time, t , if
O
SU
EN is L.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si80xx is
operating in noisy environments.
4. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 3.15 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
9. See "9. Ordering Guide" on page 18 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data
channels have pull-downs on inputs/outputs.
Rev. 1.0
9
Si80xx
Table 6. Enable Input Truth1
Operation
1,2
P/N
EN2
H
Si8030
Si8040
Si8050
Outputs B1, B2, B3, B4, B5, B6 are enabled and follow input state.
3
L
Outputs B1, B2, B3, B4, B5, B6 are disabled and Logic Low or in high impedance state.
Si8035
Si8045
Si8055
Si8065
—
Outputs B1, B2, B3, B4, B5, B6 are enabled and follow input state.
Notes:
1. Enable, EN, can be used for multiplexing, for clock sync, or other output control. EN is internally pulled-up to local VDD
by a 16 µA current source allowing it to be connected to an external logic level (high or low) or left floating. To minimize
noise coupling, do not connect circuit traces to EN if it is left floating. If EN is unused, it is recommended that it be
connected to an external logic level, especially if the Si80xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
10
Rev. 1.0
Si80xx
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when V
falls below V
and exits UVLO when V
rises above
DD1
DD1(UVLO–)
DD1
V
. Side B operates the same as Side A with respect to its V
supply. See Figure 5 for more details.
DD1(UVLO+)
DD2
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 5. Device Behavior during Normal Operation
Rev. 1.0
11
Si80xx
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Refer to the end-system specification (61010-1, 60950-1,
60601-1, etc.) requirements before starting any design that uses a digital isolator.
3.3.1. Supply Bypass
The Si80xx family requires a 0.1 µF bypass capacitor between V
and GND1 and V
and GND2. The
DD2
DD1
capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user
may also include resistors (50–300 ) in series with the inputs and outputs if the system is excessively noisy.
3.3.2. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3.4. Fail-Safe Operating Mode
Si80xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input
supply is not powered) can either be a logic high or logic low when the output supply is powered. See Table 5 on
page 9 and "9. Ordering Guide" on page 18 for more information.
12
Rev. 1.0
Si80xx
4. Pin Descriptions (Si8030/35)
VDD1
VDD2
GND2
B1
GND1
I
s
o
l
RF
XMITR
RF
RCVR
A1
A2
RF
XMITR
RF
RCVR
B2
a
t
i
o
n
RF
XMITR
RF
RCVR
A3
NC
B3
NC
EN2/NC
GND2
NC
GND1
Si8030/35
Name
Pin#
1
Type
Description
V
Supply
Ground
Digital Input
Digital Input
Digital Input
NA
Side 1 power supply.
Side 1 ground.
DD1
GND1
A1
2
3
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
No Connect.
A2
4
A3
5
NC*
6
NC*
7
NA
No Connect.
GND1
GND2
EN2/NC*
NC*
8
Ground
Ground
Digital Input
NA
Side 1 ground.
9
Side 2 ground.
10
11
12
13
14
15
16
Side 2 active high enable on Si8030. NC on Si8035.
No Connect.
B3
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B2
B1
GND2
Ground
Supply
Side 2 ground.
V
Side 2 power supply.
DD2
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
Rev. 1.0
13
Si80xx
5. Pin Descriptions (Si8040/45)
VDD1
VDD2
GND2
B1
GND1
I
s
o
l
RF
XMITR
RF
RCVR
A1
A2
RF
XMITR
RF
RCVR
B2
a
t
i
o
n
RF
XMITR
RF
RCVR
A3
A4
B3
RF
XMITR
RF
RCVR
B4
EN2/NC
GND2
NC
GND1
Si8040/45
Name
Pin#
1
Type
Supply
Description
V
Side 1 power supply.
Side 1 ground.
DD1
GND1
A1
2
Ground
3
Digital Input
Digital Input
Digital Input
Digital Input
NA
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
No Connect.
A2
4
A3
5
A4
6
NC*
GND1
GND2
EN2/NC*
B4
7
8
Ground
Side 1 ground.
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Input
Side 2 active high enable on Si8040. NC on Si8045.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B3
B2
B1
GND2
Ground
Supply
Side 2 ground.
V
Side 2 power supply.
DD2
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
14
Rev. 1.0
Si80xx
6. Pin Descriptions (Si8050)
VDD1
VDD2
B1
RF
XMITR
RF
RCVR
A1
A2
I
s
o
l
RF
XMITR
RF
RCVR
B2
RF
XMITR
RF
RCVR
B3
A3
a
t
RF
XMITR
RF
RCVR
A4
B4
i
o
n
RF
XMITR
RF
RCVR
A5
B5
EN2
NC
GND2
GND1
Si8050
Name
Pin#
1
Type
Description
V
Supply
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
NA
Side 1 power supply.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
No connect.
DD1
A1
A2
2
3
A3
4
A4
5
A5
6
NC*
GND1
GND2
EN2
B5
7
8
Ground
Side 1 ground.
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Input
Side 2 active high enable on Si8050.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B4
B3
B2
B1
V
Supply
Side 2 power supply.
DD2
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
Rev. 1.0
15
Si80xx
7. Pin Descriptions (Si8055)
VDD1
VDD2
GND2
B1
GND1
A1
I
s
o
l
RF
RCVR
RF
XMITR
RF
XMITR
RF
RCVR
A2
B2
a
t
i
o
n
RF
XMITR
RF
RCVR
B3
A3
A4
RF
XMITR
RF
RCVR
B4
RF
RCVR
RF
XMITR
A5
B5
GND2
GND1
Si8055
Name
Pin#
1
Type
Description
V
Supply
Ground
Side 1 power supply.
Side 1 ground.
DD1
GND1
A1
2
3
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Ground
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 ground.
A2
4
A3
5
A4
6
A5
7
GND1
GND2
B5
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B4
B3
B2
B1
GND2
Ground
Supply
Side 2 ground.
V
Side 2 power supply.
DD2
16
Rev. 1.0
Si80xx
8. Pin Descriptions (Si8065)
VDD1
VDD2
B1
RF
XMITR
RF
RCVR
A1
A2
I
s
o
l
RF
XMITR
RF
RCVR
B2
RF
XMITR
RF
RCVR
B3
A3
a
t
RF
XMITR
RF
RCVR
A4
B4
i
o
n
RF
XMITR
RF
RCVR
A5
B5
RF
XMITR
RF
B6
A6
RCVR
GND2
GND1
Si8065
Name
Pin#
1
Type
Description
V
Supply
Side 1 power supply.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 ground.
DD1
A1
A2
2
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Ground
3
A3
4
A4
5
A5
6
A6
7
GND1
GND2
B6
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B5
B4
B3
B2
B1
V
Supply
Side 2 power supply.
DD2
Rev. 1.0
17
Si80xx
9. Ordering Guide
Table 7. Ordering Guide for Valid OPNs1,2,3
Ordering Part
Number (OPN)
Number of
Inputs/Outputs
DefaultOutput
State
Output
Enable
Yes/No
Isolation
Rating
(kVrms)
Package
Si803x
Si8030AA-B-IU
Si8030CA-B-IU
Si8035AA-B-IU
Si8035CA-B-IU
3
3
3
3
Low
High
Low
High
Yes
Yes
No
1
1
1
1
QSOP-16
QSOP-16
QSOP-16
QSOP-16
No
Si804x
Si8040AA-B-IU
Si8040CA-B-IU
Si8045AA-B-IU
Si8045CA-B-IU
4
4
4
4
Low
High
Low
High
Yes
Yes
No
1
1
1
1
QSOP-16
QSOP-16
QSOP-16
QSOP-16
No
Si805x
Si8050AA-B-IU
Si8050CA-B-IU
Si8055AA-B-IU
Si8055CA-B-IU
5
5
5
5
Low
High
Low
High
Yes
Yes
No
1
1
1
1
QSOP-16
QSOP-16
QSOP-16
QSOP-16
No
Si806x
Si8065AA-B-IU
Si8065CA-B-IU
6
6
Low
No
No
1
1
QSOP-16
QSOP-16
High
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
Moisture sensitivity level is MSL3 for QSOP-16 packages.
2. All devices >1 kVRMS are AEC-Q100 qualified.
3. “Si” and “SI” are used interchangeably.
18
Rev. 1.0
Si80xx
10. Package Outline: 16-Pin QSOP
Figure 6 illustrates the package details for the Si80xx in a 16-pin QSOP package. Table 8 lists the values for the
dimensions shown in the illustration.
Figure 6. 16-pin QSOP Package
Rev. 1.0
19
Si80xx
Table 8. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.20
0.17
0.30
0.25
c
D
4.89 BSC
6.00 BSC
3.90 BSC
0.635 BSC
E
E1
e
L
0.40
1.27
L2
h
0.25 BSC
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
20
Rev. 1.0
Si80xx
11. Land Pattern: 16-Pin QSOP
Figure 7 illustrates the recommended land pattern details for the Si80xx in a 16-pin QSOP package. Table 9 lists
the values for the dimensions shown in the illustration.
Figure 7. 16-Pin QSOP PCB Land Pattern
Table 9. 16-Pin QSOP Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
C1
E
0.635
0.40
X1
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.0
21
Si80xx
12. Top Markings
12.1. Top Marking (16-Pin QSOP)
80XYSV
RTTTTT
YYWW
12.2. Top Marking Explanation (16-Pin QSOP)
Line 1 Marking:
Base Part Number
Ordering Options
80 = Isolator product series
XY = Channel Configuration
X = # of data channels (6, 5, 4, 3)
Y = # of reverse channels (0)*
S = operating mode:
(See Ordering Guide for more
information).
A = default output = low
C = default output = high
V = Insulation rating
A = 1 kV
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
*Note: Si8035/45/55/65 have 0 reverse channels.
22
Rev. 1.0
Smart.
Connected.
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Products
www.silabs.com/products
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
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thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
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