SI8250_技术文档

Si8250/1/2

DIGITAL POWER CONTROLLER

Features

Pin Assignments:

See page 23

ꢀ

Single-Chip, Flash-based digital ꢀ In-system Flash programmable

power controller

ꢁ Supports isolated and non-isolated

applications

ꢁ Enables new system capabilities

such as:

ꢁ Flash can also be used as NV

memory for data storage

Low cost, comprehensive

development tool kit includes:

ꢁ Graphical, easy-to-use system

design tools

ꢁ Integrated development

environment

ꢁ In-system, on-line debugger

ꢁ Turnkey isolated 35 W digital

half-bridge target board

Typical Applications

ꢁ Isolated and non-isolated DC/DC

converters

ꢁ AC/DC converters

Fully Pb-free and ROHS compliant

packages

ꢁ 32-pin LQFP

32-pin LQFP

ꢀ

- Adaptive dead-time control for

higher efficiency

RST/C2CK

IPK

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

VSENSE

- Nonlinear control for faster

transient response

Si8250/1/2

Top View

GNDA

VDDA

VREF

/

XCLK

- Self diagnostics for higher

reliability

P1.0/VIN/AIN0

P1.1/AIN1

ꢀ

- Full PMBus command set

implementation for system

connectivity

ꢀ

Highly integrated control solution:

ꢁ High-speed digital hardware

control loop

28-pin QFN

ꢁ In-system programmable

supervisory processor

ꢁ Programmable system protection

functions

ꢁ Hardware cycle-by-cycle current

limiting and OCP

ꢁ External clock and frame

synchronization inputs

ꢁ 28-pin 5 x 5 mm QFN

Temp Range: –40 to +125 ºC

GND

RST

/

C2CK

IPK

1

2

3

4

5

6

7

21

20

19

18

17

16

15

P0.1

P0.2

VSENSE

GND

P0.3/XCLK

P0.4

Si8250/1/2

Top View

VDD

P0.5

VREF

P0.6

GND

P1.0/VIN/AIN0

P0.7

ꢁ Performs system management

functions such as external power

supply sequencing and fan

control/monitoring

Description

Patents pending

Si8250/1/2 provides all control and protection functions necessary to implement

highly intelligent, fast response power delivery and management control systems

for isolated and non-isolated power supplies. On-board processing capability

enables intelligent control optimization for improved system performance and new

capabilities such as serial connectivity via the PMBus or on-board UART. The

Si8250/1/2 family is in-system Flash programmable enabling control and

protection parameters such as system regulation and protection settings, start-up

and shutdown modes, loop response, and modulation timing to be readily

modified. The built-in high-speed control path provides loop updates every 100nS

and provides pulse-by-pulse current limiting and over-current protection even

while the internal CPU is disabled.

The Si825x family is supported by the Si8250DK development kit, which contains

everything required to develop and program power supply applications with the

Si825x family of digital controllers.

Preliminary Rev. 0.8 3/06

Si8250/1/2

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si8250/1/2

2

Preliminary Rev. 0.8

Si8250/1/2

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Benefits of Digital Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.1. System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.2. Control Processor Functional Block Descriptions (Figure 1) . . . . . . . . . . . . . . . . . . .16

3.3. System Management Processor Functional Block Descriptions . . . . . . . . . . . . . . . .17

4. Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5. Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

7. Pin Descriptions—Si8250/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

9. Package Outline—32LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

10. Package Outline—28QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Preliminary Rev. 0.8

3

Si8250/1/2

1. Electrical Specifications

Table 1. Absolute Maximum Ratings*

Parameter

Conditions

Min.

–55

–65

–0.3

—

Typ.

—

Max.

+135

+150

5.5

Units

°C

V

Ambient Temperature under Bias

Storage Temperature

—

Voltage on any Port0 Pin with respect to GND

Voltage on all other pins with respect to GND

Voltage on VDD with respect to GND

Maximum total current through VDD or GND

—

4.0

V

—

4.0

V

—

400

80

mA

Maximum output current sunk by RST or any

Port pin

—

*Note: Stresses above those listed under "2.1 Absolute Maximum Ratings" may cause permanent damage to the device. This

is a stress rating only, and functional operation of the devices at those or any other conditions above those indicated in

the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods

may affect device reliability.

Table 2. DC Electrical Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Supply Voltage

Conditions

Min

2.25

—

Typ

—

Max

2.75

—

Units

V

Supply Current, all Peripherals

Enabled

Analog + digital supply current.

26

mA

Lockout mode supply current

Analog + digital supply current.

(See Table 1 on page 4)

—

300

—

TBD

—

µA

V

Digital Supply Current (shutdown)

Oscillator not running, VDD mon-

itor disabled

Digital Supply RAM Data Retention

Voltage

1.5

4

Preliminary Rev. 0.8

Si8250/1/2

Table 3. Reference DAC Electrical Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Conditions

Min

—

Typ

—

Max

9

Units

Bits

mV

Resolution

LSB Size

—

2.44

—

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling Time

–2

+2

LSB

µs

–1.0

—

+1.0

—

1/2 LSB change from 0 to

full scale

2

Turn-on Time

—

20

1

—

µs

Noise

2 MHz BW

mV

PP

Power Supply Rejection

Supply Current

70

db

220

0.1

µA

Shutdown Supply Current

Preliminary Rev. 0.8

5

Si8250/1/2

Table 4. ADC0 (12-Bit ADC) Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

DC Accuracy

Conditions

Min

Typ

Max

Units

Resolution

—

12

—

±2

±1

—

bits

LSB

Integral Nonlinearity

Differential Nonlinearity

Offset Error

Guaranteed Monotonic

Differential mode

—

LSB

±3

3

LSB

Full Scale Error

LSB

Offset Temperature Coefficient

TBD

ppm/°C

Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps)

Signal-to-Noise Plus Distortion

Total Harmonic Distortion

Spurious-Free Dynamic Range

Conversion Rate

—

64

83

—

dB

th

Up to the 5 harmonic

–73

Conversion Time in SAR Clocks

Track/Hold Acquisition Time

Throughput Rate

Note 1

Note 2

—

1

13

—

clocks

µs

—

200

ksps

Analog Inputs

Input Voltage Range

Input Capacitance

Temperature Sensor

Linearity

0

—

V

REF

—

15

—

pF

Notes 3, 4

—

±TBD

1353

488

—

°C

µV/°C

mV

Gain

Offset

Notes 3, 4 (Temp = 0 °C)

Power Specifications

Power Supply Current (V sup-

plied to ADC0)

Operating Mode, 200 ksps

—

780

5

—

µA

µs

DD

Power-On Time

After V

settle, before tracking

begins

REF

Power Supply Rejection

—

TBD

—

mV/V

Notes:

1. An additional 2 F

cycles are required to start and complete a conversion.

CLK

2. Additional tracking time may be required depending on the output impedance connected to the ADC input.

3. Represents one standard deviation from the mean.

4. Includes ADC offset, gain, and linearity variations.

6

Preliminary Rev. 0.8

Si8250/1/2

Table 5. ADC1 Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Sampling Frequency

Conditions

ADCSP = 0

ADCSP = 1

Min

—

Typ

10

5

Max

—

Units

Msps

—

Resolution

—

5

6

Bits

mV

LSB

V

LSB Size

4

20

+31

1.3

+2

+1

—

Differential Input Voltage Range

Common-mode input voltage range

Integral Nonlinearity

Differential Nonlinearity

Gain Error

Note 1

–32

0.8

–2

–1

—

LSB

%

Offset Error

—

3

—

mV

µA

Input Bias Current

Standby Mode Supply Current

Operating Mode Supply Current

Notes:

—

5

—

disabled

—

0.1

—

µA

—

3

mA

1. LSB size (mV) is programmable using the RES[3:0] bits in the ADC1CN register.

Table 6. DSP Filter Engine Electrical Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Conditions

Min

—

Typ

—

Max

9

Units

Bits

µA

1

Resolution

2

Dithering

—

6

Standby Mode Supply Current

disabled

—

0.1

—

Notes:

1. Internal word length = 22 bits.

2. Up to a total 15 bits of resolution when dithering is enabled.

Preliminary Rev. 0.8

7

Si8250/1/2

Table 7. Peak Current Limit Detector Electrical Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Conditions

10 mV Overdrive

VT[3:0] = 0000

VT[3:0] = 0001

VT[3:0] = 0010

VT[3:0] = 0011

VT[3:0] = 0100

VT[3:0] = 0101

VT[3:0] = 0110

VT[3:0] = 0111

VT[3:0] = 1000

VT[3:0] = 1001

VT[3:0] = 1010

VT[3:0] = 1011

VT[3:0] = 1100

VT[3:0] = 1101

VT[3:0] = 1110

VT[3:0] = 1111

HYST[1:0] = 00

HYST[1:0] = 01

HYST[1:0] = 10

HYST[1:0] = 11

Min

—

Typ

45

Max

—

Units

ns

IPK Input to DPWM Output Latency

Threshold Detector Voltage

35

50

65

mV

85

100

150

200

250

300

350

400

450

500

550

600

650

700

750

800

0

115

165

215

265

315

365

415

465

515

565

615

665

715

765

815

—

135

185

235

285

335

485

435

485

535

585

635

685

735

785

—

Hysteresis

mV

ns

—

5

—

10

—

20

—

Blanking Time

LEB[1:0] = 00, f

= 200 MHz

—

0

—

PLL

LEB[1:0] = 01, f

LEB[1:0] = 10, f

LEB[1:0] = 11, f

= 200 MHz

—

20

—

40

—

80

—

Input Capacitance

—

4.5

0.1

100

—

pF

µA

Input Bias Current

—

Shutdown Supply Current

Active Supply Current

Enable bit = 0

—

IIN = (Vt + 100 mVpp),

1.5 MHz sq. wave

—

8

Preliminary Rev. 0.8

Si8250/1/2

Table 8. DPWM Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Conditions

Min

—

5

Typ

—

Max

200

50

25

9

Units

Clock Frequency

DPWMSP[4:3] = 00

DPWMSP[4:3] = 01

DPWMSP[4:3] = 1x

No dithering

MHz

Resolution

Bits

ns

Dithering enabled

DPWMSP[4:3] = 00

DPWMSP[4:3] = 01

DPWMSP[4:3] = 1x

15

—

Time Resolution

20

40

3

—

SYNC Pulse set-up time

SYNC signal minimum LOW time

before positive transition

—

DPWM

clock cycles

PH Rise, Fall Time

50pF on pin

—

75

40

—

5

ns

Ω

Output Resistance High

Output Resistance Low

Shutdown Supply Current

I

= –5 mA

= 8 mA

—

0.1

OUT

I

Ω

OUT

µA

Table 9. Bandgap Voltage Reference Specs

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Output Voltage

Conditions

Min

—

–1

—

Typ

1.20

—

Max

—

Units

V

%

Temperature Stability

Turn-on Response

+1

—

(0.01%, 4.7 µF)

no load

6.5

2

ms

—

µs

Noise

4.7 µF

2

—

µV (RMS)

µA

Bandgap Current

Reference Buffer Current

Power supply rejection

60

30

50

—

µA

—

dB

Preliminary Rev. 0.8

9

Si8250/1/2

Table 10. Comparator0 Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Conditions

Min

0

Typ

—

8

Max

Units

V

Vin

V

DD

Low-Speed Supply Current

Full-speed Supply Current

Hysteresis

—

µA

225

0

—

µA

CP0HYP[1:0] = 00

CP0HYP[1:0] = 01

mV

7

CP0HYP[1:0] = 10

14

28

0

CP0HYP[1:0] = 11

CP0HYN[1:0] = 00

CP0HYN[1:0] = 01

–7

–14

–28

180

25

5

CP0HYN[1:0] = 10

CP0HYN[1:0] = 11

Response Time

Low Power Mode, 25 mV Overdrive

High-Speed Mode, 25 mV Overdrive

ns

Input Capacitance

CMRR

pF

db

50

5

Input offset

mV

10

Preliminary Rev. 0.8

Si8250/1/2

Table 11. Reset Electrical Characteristics

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

RST Output Low Voltage

RST Input High Voltage

RST Input Low Voltage

RST Input Pull-up Current

VDD POR Threshold

Conditions

Min

—

Typ

—

Max

0.7

Units

V

I

= 8.5mA, VDD = 2.5V

OL

0.7 x V

—

V

DD

—

0.3 x V

TBD

2.2

V

DD

RST = 0.0

—

25

µA

V

2.0

2.1

250

Missing clock detector timeout Time from last system clock ris-

ing edge to start of reset

—

650

µs

Reset time delay

Delay between release of any

reset source and code execu-

tion at location 0x0000

5.0

6.5

—

µs

Minimum RST Low time to gen-

erate a System Reset

VDD monitor turn-on time

VDD monitor supply current

100

—

µs

40

µA

Table 12. Flash Electrical Characteristics

TA = –40 to +125 °C, VDD = 2.25 V – 2.75 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Flash Size

Conditions

Si8250

Min

32768

16383

Typ

—

Max

—

Units

(1)

bytes

Si8251, Si8252

—

Endurance

10 K

TBD

32

100 K

—

Erase/Write

Read Cycle Time

Erase Cycle Time

Write Cycle Time

Notes:

—

ns

ms

µs

50 MHz System Clock

—

48

76

—

114

1. The last 512 bytes of memory are reserved.

Preliminary Rev. 0.8

11

Si8250/1/2

Table 13. Port I/O DC Electrical Characteristics

TA = –40 to +125 °C, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameters

Conditions

push-pull

Min

—

Typ

—

Max

+ 0.7

Units

Port0 Input Voltage Tolerance

V

DD

open-drain

—

5.5

+ 0.7

Port1 Input Voltage Tolerance

Output High Voltage

—

DD

I

= –3 mA,

V

– 0.4

—

V

OH

DD

Port I/O push-pull

I

= –10 µA,

– 0.1

—

OH

DD

Port I/O push-pull

I

= –10 mA,

—

V

– 0.8

DD

OH

Port I/O push-pull

Output Low Voltage

I

= 8.5 mA

= 10 µA

= 25 mA

—

0.6

0.1

—

OL

I

OL

I

1.25

—

OL

Input High Voltage

Input Low Voltage

Input Leakage Current

(0.7) V

—

V

DD

—

(0.3) V

±10

DD

Weak Pullup Off

Weak Pullup On, V = 0 V

—

µA

—

20

50

IN

Table 14. PLL Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Stabilization Time

Conditions

Min

—

Typ

30

Max

—

Units

µs

Input Frequency Range

PLL Frequency

15

—

25

—

MHz

ps

200

250

15

Cycle-to-cycle jitter

Supply current

—

mA

µA

Shutdown current

—

0.1

—

12

Preliminary Rev. 0.8

Si8250/1/2

Table 15. 25MHz Oscillator Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Conditions

Min

—

Typ

24.5

100

0.3

Max

—

Units

MHz

µs

Frequency

Start-up time

—

Power supply sensitivity

Temperature coefficient

Supply current

—

%/V

PPM/°C

µA

—

50

—

450

0.1

—

Shutdown current

—

µA

Table 16. Low Frequency Oscillator (LFO) Specifications

TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.

Parameter

Conditions

Min

—

Typ

80

Max

—

Units

kHz

Frequency

Start-up time

—

100

1.7

1000

4

—

µs

Power supply sensitivity

Temperature coefficient

Supply current

—

%/V

PPM/°C

µA

—

Shutdown current

—

0.1

—

µA

Preliminary Rev. 0.8

13

Si8250/1/2

ꢀ Higher operating precision: Switch timing, control

response and protection setting thresholds in analog

systems are typically determined by the values of

external passive components. These components

typically have a wide tolerance and vary with

temperature and time. Designers must allow for

these tolerances when considering worst case

operating conditions. Digital control offers tighter

parameter tolerances with greatly reduced

2. Benefits of Digital Power Control

Digitally controlled power systems have the following

key advantages over analog implementations:

ꢀ In-system programmability: Virtually all aspects of

digital controller behavior can be changed in

software locally or remotely, and without hardware

modification. This benefits the system in several

ways:

temperature/time variations resulting in improved

worst-case operating specifications.

ꢁ Hardware designs can be segregated into base

platforms (for example, by form factor or output power),

and optimized to the end application in software. This

lowers development costs by reducing the total number

of hardware designs required to address a given

application segment.

ꢁ The controller's ability to readily accept change makes

possible low-cost, custom power supply versions with

relatively short lead-time.

ꢀ Power management and power delivery functions in

a single package: Power management functions,

such as external supply sequencing, PMBus

communication support and fan control can be

performed by the digital controller, eliminating

dedicated external components.

ꢀ System connectivity: PMBus and other emerging

communication protocols enable system processors

to communicate with the power supply to obtain data

and command action. For example, the system

processor may request the power supply operating

history, perform self-diagnostics or change system

settings without taking the supply off-line.

ꢁ The cost and risk of field configuration and/or updating

is greatly reduced, lowering the overhead associated

with customer support.

ꢀ More advanced control algorithms: Power supply

design with fixed-function analog components leads

to many performance trade-offs. For example,

analog compensator design routinely trades stability

for higher loop bandwidth, and places the required

poles and zeros using passive components. The "if-

then-else" decision-making capability of digital

control can change loop bandwidth as needed for

optimum control response. For example the

controller can operate the compensator at a

relatively low bandwidth during steady-state

operation, but significantly extend bandwidth during

a transient. This adaptive response concept can be

applied to improve other operating parameters such

as efficiency.

Communications with the system controller enables

notification of a pending power supply failure,

enhancing system reliability. This attribute also

reduces the cost and complexity of field

configurations and upgrades.

ꢀ Higher integration/smaller size/lower cost: Many

discrete circuits can be transformed to lines of

software code, eliminating components and saving

cost. The digital controller can be used to execute

self-diagnostic routines during production test

thereby reducing test time and saving cost. The

small physical size of the Si8250 in particular

(5 x 5 mm) saves board space.

ꢀ Power Efficiency Optimization: In a switched mode

power supply, it is desirable to maintain high power

efficiency over a wide range of loads. Software

algorithms can optimize efficiency at every point of

line and load. For example, the software can adjust

dead time with changes load, disable synchronous

rectification at low loads, or take other measures to

maximize efficiency.

14

Preliminary Rev. 0.8

Si8250/1/2

3. Product Description

System Management Processor

4x 16-BIT

TIMERS

VDD

16/32 kB

Flash

2% 25 Mhz OSC,

and LFO

SMBus

SYSCLKIN

I/O (8)

3 CH PCA

RESET

CONTROL

I/O PORT

LATCHES

1280 Byte

RAM

HARDWARE

DEBUG

PORT

UART

INTERRUPT

CONTROL

I/O (8)

VSENSE

ADC

12-BIT

REGISTERS

& LIMIT

200 Ksps

ADC

8

DETECTORS

TEMP

SENSOR

AUTO

SCAN

LOGIC

VSENSE

DSP

FILTER ENGINE

10 MHz

ADC

u(n)

VREF

REFDAC

MULTIPHASE

DPWM

GATE CONTROL

(6)

VREF

IPK

ICYC

Pulse-by-Pulse

Current Limiter

and OCP

OCP

Control Processor

Si8250/1/2

Figure 1. Functional Block Diagram

System Management Processor

Digital Peripherals:

- UART

VDD

- SMBus Port

- 4 x 16-Bit Timers

- 3 Ch PCA (PWM)

50MIPS 8051 CPU

and Memory

SYSCLKIN

16 General-Purpose

Analog/Digital I/O Lines

- I/O Port Latches

DEBUG

PORT

VSENSE

ADC 0

12-Bit, 200Ksps

10-Channel

Analog Input (e.g. average current)

Digital Ouput (e.g. fan speed control)

TEMP

SENSOR

POWER STAGES

VSENSE

SUPPLY INPUT

VOLTAGE

DSP

FILTER ENGINE

ADC1

10Msps

u(n)

SWITCHES

AND

MAGNETICS

OUTPUT

FILTER

VREF

REFDAC

VOUT

MULTIPHASE

DPWM

VREF

IPK

GATE

DRIVERS

Up to 6 Gate

Pulse-by-Pulse

Current Limiter

and OCP

ICYC

OCP

Control Outputs

Control Processor

Si8250

Peak Current Signal (e.g. CT)

Figure 2. Si8250 Top-Level Block Diagram

Preliminary Rev. 0.8

15

Si8250/1/2

The System Management Processor serves several

purposes, among these are:

3.1. System Operation

Figure 2 shows the Si8250/1/2 controlling a non-

isolated DC/DC converter operating in digital voltage

mode control. The output voltage signal connects to the

1. Continuously optimizes Control Processor operation

(e.g. efficiently optimization)

VSENSE input through a resistive divider, limiting the 2. Executes user-specific algorithms (e.g. support for

common mode voltage range applied to ADC1 to a

maximum of VREF. The equivalent resistance of the

divider and the capacitor form an anti-aliasing filter with

a cutoff frequency equal to ADC1 sampling frequency of

divided by 2 (the amplitudes of frequencies above fS/2

must be minimized to prevent aliasing).

proprietary system interfaces)

3. Provides regulation for low-bandwidth system

variables (e.g. VIN feed-forward)

4. Performs system fault detection and recovery

5. Provides system housekeeping functions such as

PMBus communication support

Differential ADC1 and the DSP Filter Engine together

perform the same function as an analog error amplifier

and associated RC compensation network. ADC1

6. Manages external device functions (e.g. external

supply sequencing, fan control/monitoring)

digitizes the difference between the scaled output The Si8250/1/2 system development requires using the

voltage and a programmable reference voltage provided Si8250DK, a comprehensive development kit providing

by the REFDAC. The ADC1 output signal is frequency all required hardware and software for control system

compensated (in digital domain) by the DSP Filter design. It comes complete with pre-written and verified

Engine. The resulting output from the DSP Filter Engine application software, and a set of tools that enable the

is a digital code that represents the compensated duty user to adapt this software to the end application. It also

cycle ratio, u(n). The digital PWM generator (DPWM) includes a turnkey isolated half-bridge DC/DC converter

directly varies output timing to the external gate drivers based on the Si8250/1/2 for evaluation and

based on the value of u(n) until the difference between experimentation.

VSENSE and ADC1 reference level is driven to zero.

3.2. Control Processor Functional Block

Sensing circuitry within the power stages (current

Descriptions (Figure 1)

transformer, sense amp, etc.) provides a signal

ADC 1: Differential input, 10 Msps control loop analog-

to-digital converter. ADC1 digitizes the difference

between the Vsense input and the programmable

voltage reference level from the REFDAC. ADC1 can be

operated at either 5 Msps or 10 Msps and has a

programmable LSB size to prevent limit cycle oscillation

(Limit cycle oscillation can also be avoided using

dithering to increase DPWM resolution). ADC1 has

programmable conversion rates of 10 Msps and 5 Msps

to accommodate a wide loop gain range. ADC1 also

contains a hardware transient detector that interrupts

the CPU at the onset of an output load or unload

transient. The CPU responds by executing specific

algorithms to accelerate output recovery. These

algorithms may include increasing loop bandwidth or

other measures.

representative of inductor or transformer current. This

signal connects to the pulse-by-pulse current limiting

hardware in the Si8250/1/2 via the IPK input pin. This

current limiting circuitry is similar to that found in a

voltage mode analog PWM. It contains a fast analog

comparator and a programmable leading-edge blanking

circuit to prevent unwanted tripping of the current

sensing circuitry on the leading edge of the current

pulse. Current limiting occurs when the sensed current

exceeds the programmed threshold. When this occurs,

the on-going active portions of the PWM outputs are

terminated. A programmable OCP counter keeps track

of the number of consecutive current limit cycles, and

automatically shuts the supply down when the

accumulated number of limit cycles exceeds the

programmed maximum.

REFDAC: 9-bit digital-to-analog converter provides the

output voltage reference setting. The REFDAC uses the

on-board band gap as its voltage reference, or can be

referenced to an external voltage reference source.

REFDAC is used for output voltage calibration,

margining and positioning. The CPU continuously

manages the REFDAC during soft-start and soft-stop.

The System Management Processor is based on a 50

million instruction per second (MIPS) 8051 CPU and

dedicated A/D converter (ADC0). ADC0 digitizes key

analog parameters that are used by the MCU to provide

protection, as well as manage and control other aspects

of the power system. On-board digital peripherals

include: timers, an SMBus interface port (for PMBus or

other protocols); and

receiver/transmitter (UART) for serial communications,

useful for communicating across an isolation boundary.

a

universal asynchronous

DSP Filter Engine: This two-stage loop compensation

filter is the functional equivalent of an active RC

compensation in an analog control scheme. The first

filter stage is a PID filter providing one pole and two

16

Preliminary Rev. 0.8

Si8250/1/2

zeros. The second stage is selectable: a two-pole low- operation. The DPWM includes an external SYNC input

pass filter (LPF) for the fastest possible response, or and ENABLE input, both of which can be connected to

SINC (multiple zero) decimation filter for relatively the I/O pins. The Enable is a logic input used to turn the

quieter operation. The PID plus the LPF result in a three power supply on and off. It can be configured to be

pole, two zero composite filter, while the PID plus the active high or active low. The SYNC input allows the

SINC results in a single pole, multiple zero composite start of each switching cycle to be synchronized to an

filter. The SINC filter provides zeros at intervals equal to external clock source, including another Si8250/1/2.

f /(2*DEC) where DEC is the decimation ratio (i.e. ratio

S

3.3. System Management Processor Func-

tional Block Descriptions

of input to output sampling rate). DEC is a software-

programmable parameter, and can be programmed

such that zero placement occurs that the PWM

frequency and its harmonics. This creates more than

100 db attenuation at these frequencies providing lower

system noise levels.

ADC0: Self-sequencing, 10-input, 200 Ksps analog-to-

digital converter. This general-purpose ADC acquires

other analog system parameters for supplemental

control by the CPU (e.g. dead time control using

average input current as the control variable). ADC0

also converts the output of the on-board temperature

The end-to-end response of the filter is defined using

only six software parameters, and can be re-

programmed during converter operation to implement

nonlinear control response for improved transient

resolution.

sensor.

Eight of the ten analog inputs may be

connected to the I/O pins for external interface. The

remaining two analog inputs (Vsense and Temp Sensor)

are internally connected. When placed in Auto

Sequencing mode, ADC0 automatically converts, stores

and limit-checks each analog input, and interrupts the

CPU when a converted result is outside of its

programmed range. This feature greatly facilitates

protection functions because all measurement and

comparison operations are automated.

As described in the ADC1 section above, limit cycle

oscillation can be avoided by increasing ADC1 LSB size

to allow the DPWM LSB to fit within a single ADC1

output code (i.e. zero-error bin). However in some

applications, it may not be desirable to lower ADC1

sensitivity. For such applications, limit cycle oscillation

can be avoided by dithering the DPWM output. The

Temperature Sensor: This sensor measures the die

temperature of the Si8250/1/2. It can achieve 3 C

accuracy with a single-point calibration and 1 C with a

two-point calibration. The temperature output signal is

digitized by ADC0.

DSP Filter Engine contains

a

pseudo-random,

broadband noise generator - mixing this noise into the

filter output randomly moves the gate control output(s)

over a range of 1 LSB, such that the time-averaged

resolution of the DPWM is increased.

8051 CPU: 50MIPS CPU core with 1K of SRAM and up

to 32 kB of Flash memory. This processor has its own

on-board oscillator and PLL, reset sources and real-

time in-system hardware debug interface eliminating the

need for external processor supervisors, timebases,

and "emulators". The CPU has an external interrupt

(INT0/) that can be connected to an external device via

the I/O pins. When interrupted, the CPU suspends

execution of the current task, and immediately vectors

to an interrupt service routine specifically designed to

handle the interrupting device.

The filter response is programmed using S-domain

design tools included in the Si8250DK development kit,

greatly minimizing software writing tasks.

Pulse-by-pulse Current Limiter/OCP: High-speed

comparator with 4-bit DAC threshold generator and 2-bit

programmable leading-edge blanking delay generator.

The comparator output causes the DPWM to terminate

the on-going portions of the active outputs when the

peak current signal applied to the IPK input exceeds the

threshold setting. Hardware performs an OCP supply

shutdown when the number of consecutive current limit

events equals a programmed maximum.

Digital peripherals: Peripherals include: four 16-bit

timers, a three-channel programmable counter array

(PCA), each channel useful as a PWM, an SMBus port

useful as a PMBus interface, a UART (useful as a serial

data port for isolated applications, and two 8-bit I/O port

latches for logic control outputs.

DPWM: Output generator may be programmed for

pulse width (PWM) or phase-shift modulation using

design tools contained in the Si8250DK design kit. The

DPWM may be modulated by the front-end of the

Control Processor (ADC1 and DSP Filter Engine); or by

the CPU. The DPWM has individually programmable

stop states for supply off (disable) and OCP. Software

bypass mode allows the CPU to force selected outputs

high or low while the remaining outputs continue normal

Preliminary Rev. 0.8

17

Si8250/1/2

4. Design Tools

The Si8250DK development kit (Figure 3) contains

everything required to develop applications with the

Si825x family of digital power controllers. This kit

supports all phases of power supply development from

controller design through real-time system debugging. It

also includes a turnkey, 35 W isolated DC/DC target

board for evaluation and experimentation.

Figure 3. Si8250DK Development Kit

Figure 5. Timing Design Tool (Top) and Buck

Regulator Compensation Tool (Bottom)

The tool set enables the user to configure pre-written

application software included in the kit to his application

using a set of PC-based graphical user interface (GUIs).

These GUIs (Figure 5) allow the user to quickly and

easily specify and verify system timing, loop

compensation and protection settings, and compile and

download the resulting code into the Si8250/1/2

(Figure 4).

Figure 4. Software Download to Si8250

Mounted in Power Supply

18

Preliminary Rev. 0.8

Si8250/1/2

5. Example Applications

Isolated DC/DC Converter: A 35 W, 400 kHz Si8250-based half bridge converter is shown in Figure 6. This circuit

is the same as that of the target (evaluation) board shipped in the Si8250DK development kit.

P3

DRIVER

180nH

VOUT

1uH

VIN+

.0.001

IRLR8113

0.010

P4

6 x 100uF

Ceramic

DRIVER

2.2uF

200

6:1

0.01uF

200

4.7

33K

4.7

FDS3572

IRLR8113

DRIVER

180nH

IOUT Vsense

1K

DRIVER

120uF

~

+

-

IPK

3.9K

7.5

0.01uF

10K

3V3P

P3

P4

PH4

PH3

2.2uF

33K

VDD

AIN

DC BAL

VIN

FDS3572

PH2

PH1

P2

P1

AIN

IIN

Isolator

AIN

TX

RX

GND

1.2nF

3V3P

1K

C8051F300

Microcontroller

VDD

GND

VDDA

VDDB

GNDA GNDB

Si8250

Digital Controller

VIN-

Figure 6. Isolated Half-Bridge DC/DC Converter

The Si8250/1/2 is located on the secondary-side of the power supply for optimum transient response. DPWM

outputs PH3 and PH4 control gates of the synchronous rectifiers via a dual driver I.C. DPWM outputs PH1 and

PH2 control the gates of the primary-side switching transistors with isolation provided by a Silicon Laboratories

isolator. A current transformer circuit provides peak current sensing. Primary side analog parameters (input voltage

and current and the filter node voltage) are digitized by a Silicon Laboratories C8051F300 microcontroller and

passed to the Si8250/1/2 using the on-board UART through additional channels of the isolator I.C. to the

Si8250/1/2. The Si8250/1/2 is uses the application software included with the Si8250DK development kit after

being configured for the half-bridge application using the tools supplied in the kit.

When power is applied, the CPU executes an internal reset followed by initialization of all parameters. The

Si8250/1/2 remains in a low-power state, monitoring digitized VIN data from the primary-side MCU until VIN is

within specified limits. At this time, the controller is fully enabled and executes soft-start by monitoring Vout while

sequentially incrementing the loop voltage reference (REFDAC) until the supply output voltage is within specified

range, at which time steady-state operation begins.

During steady-state operation, the MCU operates in interrupt mode where hardware events divert program

execution to specific routines in priority order.

Preliminary Rev. 0.8

19

Si8250/1/2

Single Phase POL (point of load) converter: A 65 W, 400 KHz Si8252 based single phase POL converter block

diagram is shown in Figure 7. DPWM outputs PH1 and PH2 control the gates of the buck and synchronous

switching transistors. A lossless current sensing method that relies on the resistor and inductance of the inductor is

used to measure the current for over current protection. The input voltage is measured using resistor divider

network and analog input port AIN0 of 12bit, 200 kHz ADC0.

DIFFERENTIAL

Ipk

AMPLIFIER

VIN

CIN

Vout

L

C

+2.5 V

VDD

DRIVER

Ipk

Vsense

PH1

PH2

Ipk

VIN

AIN0

Si8252

GND

Figure 7. Single-phase POL Block Diagram

When power is applied, the CPU executes an internal reset followed by initialization of all parameters. The Si8252

remains in a low-power state, monitoring digitized VIN data until VIN is within specified limits. At this time, the

controller is fully enabled and executes soft-start by monitoring output voltage while sequentially incrementing the

loop voltage reference (REFDAC) until the supply output voltage is within specified range, at which time steady-

state operation begins.

As in the previous half-bridge example, transient response is improved by adjusting loop gain at the onset of a

transient (i.e. nonlinear control). The efficiency of the POL converter can be optimized over the complete load

range by dynamically adjusting the dead-times. Typical efficiency simulation results for the POL are shown in

Figure 8. In this case, the single-phase POL operates at a PWM frequency of 400 kHz with an output voltage of

3.3 V and an input voltage range of 10 to 15 V. The curve shows the efficiency with an input voltage of 12.0 V.

95

90

Eff(Io)

85

80

0

5

10

15

20

25

Io

Figure 8. POL Efficiency

20

Preliminary Rev. 0.8

Si8250/1/2

6. Layout Considerations

The mixed-signal nature of the Si8250/1/2 mandates clean bias supplies and ground returns. It is best to provide

separate ground planes for analog, digital and power switch returns. These planes should tie together at only one

point to eliminate the possibility of circulating ground currents.

For best performance, the VDD supply should be decoupled from the main supply. The LQFP-32 package provides

the best noise performance because it has separate analog and digital VDD and ground inputs (AVDD, AGND). As

shown in Figure 9, the AVDD is decoupled by a filter consisting of a 1 Ω resistor in series with a 500 mA, 40 Ω

ferrite bead and a parallel combination of a 10 uF with a 0.1 uF high-frequency bypass capacitor. All connections

should be kept as short as possible. The VDDA and GNDA should be connected into their respective ground

planes. The QFN-28 package shares analog and digital power with ground on the same pins. Power supply

decoupling is shown in Figure 10. Again, all connections should be kept as short as possible.

Ferrite bead

500 mA, 40 Ω

1 Ω

2.5 V

10 uF

0.1 uF

10 uF

0.1 uF

AVDD

DVDD

Si8250/1/2

AGND

DGND

Keep trace

lengths as short

as possible

AGND

Figure 9. Power Supply Connections for LQFP-32 Package

Ferrite bead

500 mA, 40 Ω

1 Ω

2.5 V

10 uF

0.1 uF

VDD

Si8250/1/2

GND

Keep trace

lengths as short

as possible

Figure 10. Power Supply Connections for QFN-28 Package

Preliminary Rev. 0.8

21

Si8250/1/2

In both cases, the bias supplies must be filtered using low ESR/ESL capacitors placed close to the IC pins.

Thick copper traces should be connected to the bias pins (VDD, VDDA) and the ground pins (GND, GNDA) to

reduce resistance and inductance. The copper routings from the drivers to the FETs should be kept short and wide,

especially in very high frequency applications, to reduce inductance of the traces so that the drive signals can be

kept clean.

Connections between VSENSE and the output voltage must be kept absolutely as short as possible to minimize

inductance and parasitic ringing effects. It is best to locate the Si8250/1/2 as close to the output voltage terminal as

possible and use a Kelvin connection to ensure to difference in ground potential between the Si8250/1/2 and the

output voltage ground return.

Most applications will require access to the debug pins. These pins are susceptible to damage from electrostatic

discharge (ESD). It is therefore recommended the debug circuit interface use the input protection circuitry shown in

Figure 11.

Si8250/1/2

10

Debug Pins

DEBUG

(C2D, C2CK)

CONNECTOR

Figure 11. Debug Interface Pin Protection Circuit

22

Preliminary Rev. 0.8

Si8250/1/2

7. Pin Descriptions—Si8250/1/2

32-pin LQFP

28-pin QFN

GND

RST/C2CK

IPK

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P0.0

RST / C2CK

IPK

1

2

3

4

5

6

7

21

20

19

18

17

16

15

P0.1

P0.2

VSENSE

P0.2

VSENSE

GND

P0.3/XCLK

P0.4

Si8250/1/2

Top View

GNDA

VDDA

VREF

P0.3 / XCLK

P0.4

Si8250/1/2

Top View

P0.5

VDD

P0.5

P0.6

P1.0/VIN/AIN0

P1.1/AIN1

VREF

P0.6

P0.7

GND

P1.0/VIN/AIN0

P0.7

Figure 12. Example Pin Configurations

Table 17. Pin Descriptions

Name

RST/C2CK

QFN-28 LQFP-32

Type

Description

Pin #

Pin#

1

2

1

D I/O

AIN

Reset input or bidirect debug clock

Inductor current input

Output voltage feedback input

Ground

2

IPK

3

AIN

VSENSE

GND

4

—

4

AIN

—

5

AIN

GNDA

Ground

—

5

AIN

VDD

Power supply input

—

6

AIN

VDDA

Power supply input

6

AIN

VREF

External voltage reference input

7

D I/O or AIN

P1.0/VIN or AIN0

Port 1 I/O or scaled power supply input voltage or

ADC input 0

8

D I/O or AIN

AIN

P1.1/AIN1

P1.2/AIN2

P1.3/AIN3

P1.4/AIN4

GND

Port 1 I/O or ADC input 1

Port 1 I/O or ADC input 2

Port 1 I/O or ADC input 3

Port 1 I/O or ADC input 4

Ground

9

10

11

—

12

13

14

10

11

12

13

14

15

16

AIN

VDD

Power supply input

D I/O or AIN

P1.5/AIN5

P1.6/AIN6

P1.7/ AIN7/C2D

Port 1 I/O or ADC input 5

Port 1 I/O or ADC input 6

Port 1 I/O or ADC input 7 or C2 Data

D I/O, DIN or

AIN

Preliminary Rev. 0.8

23

Si8250/1/2

Table 17. Pin Descriptions (Continued)

Name

QFN-28 LQFP-32

Type

Description

Pin #

15

16

17

18

19

20

21

22

23

24

25

—

Pin#

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

D I/O

DOUT

AIN

P0.7

P0.6

P0.5

P0.4

Port 0 I/O

P0.3/XCLK

P0.2

P0.1

P0.0

Port 0 I/O or bidirectional debug data

Phase 6 switch control output

Phase 5 switch control output

Phase 4 switch control output

Power supply input

PH6

PH5

PH4

VDD

GND

PH3

—

AIN

Ground

26

27

28

DOUT

Phase 3 switch control output

Phase 2 switch control output

Phase 1 switch control output

PH2

PH1

Pin Functions:

RST/C2CK: CPU reset or debug tool clock. Driving this pin low resets the CPU. This pin is also clocked by the USB

debug adaptor during debug.

IPK: Input to the peak current detector for pulse-by-pulse current limiting and over-current protection shutdown

control.

VSENSE: ADC1 inverting input. This is the voltage feedback input for the Si8250. The maximum allowable signal is

VREF.

GND: Digital ground for the 32LQFP package, and the main ground for the 28MLP package.

GNDA: Analog ground for 32LQFP only.

VDD: Digital supply voltage for the 32LQFP package, and main supply voltage for the 28MLP package.

VDDA: Analog supply for 32LQFP only.

P1.0/VIN or AIN0: Programmable multifunction I/O pin. This pin can be software configured to be either a Port 1

digital input or output, or an ADC0 input at AMUX address 0. If used in a non-isolated application, positive input

supply voltage must be tied to this input through a resistor divider and anti-aliasing capacitor to minimize the

frequencies above fS/2 (100Khz) to prevent aliasing. Isolated applications may use this input as general-purpose

digital I/O or analog input.

P1.1 or AIN1–P1.7 or AIN7: Programmable multifunction I/O pins. These pins can be software configured to be a

Port 1 digital input or output, or an ADC0 input. P1.7 also serves as the debug data input (C2D) and is used during

debug by the USB debug adaptor. P1.7 may be used as general-purpose digital I/O when not in debug mode. Any

of the digital peripherals may be programmed to connect to these pins.

P0.0–P0.7: Programmable multifunction I/O pins. These pins can be software configured to be either a Port 1

digital input or output, or an ADC0 input. Any of the digital peripherals (including the ENABLE input) may be

programmed to connect to these pins. P0.3 may be programmed to serve as an external (25MHz nominal) clock

input.

PH1–PH6: DPWM gate control (complementary drive) outputs. These signals connect to the MOSFET gates

through an external gate driver. The output levels swing between ground and Vdd.

24

Preliminary Rev. 0.8

Si8250/1/2

8. Ordering Guide

Ordering Number

Flash Memory Number of

UART

Package

PWM

Outputs

Si8250-IQ

Si8250-IM

Si8251-IQ

Si8251-IM

Si8252-IQ

Si8252-IM

32 kB

16 kB

6

3

Yes

No

LQFP-32

QFN-28

LQFP-32

QFN-28

LQFP-32

QFN-28

No

Preliminary Rev. 0.8

25

Si8250/1/2

9. Package Outline—32LQFP

Figure 13 illustrates the package details for the 32-pin LQFP version of the Si8250/1/2. Table 18 lists the values for

the dimensions shown in the illustration.

D

D1

A2

A

A1

E1

E

L

b

e

32

PIN 1

IDENTIFIER

1

Figure 13. 32-pin LQFP Package Diagram

Table 18. LQFP-32 Package Dimensions

MM

Min

—

Typ

—

Max

1.60

0.15

1.45

0.45

—

A

A1

A2

b

0.05

1.35

0.30

—

1.40

0.37

9.00

7.00

0.80

9.00

7.00

D

D1

e

—

E

—

E1

—

26

Preliminary Rev. 0.8

Si8250/1/2

10. Package Outline—28QFN

Figure 14 illustrates the package details for the 28-lead QFN version of the Si8250/1/2. Table 19 lists the values for

the dimensions shown in the illustration.

Bottom View

Side View

L

7

15

16

17

18

19

20

21

e

6

5

4

3

2

1

D2

DETAIL 1

D2

2

AA

CC

R

DETAIL 1

6 x e

D

Figure 14. 28-lead Quad Flat No-lead (QFN) Package Diagram

Table 19. QFN-28 Package Dimensions

MM

Typ

0.90

0.02

0.65

0.25

0.23

5.00

3.15

5.00

3.15

0.5

MM

Typ

0.55

28

Min

0.80

0

Max

1.00

0.05

1.00

—

Min

0.45

—

Max

0.65

—

A

A1

A2

A3

b

L

N

0

ND

NE

R

—

7

—

7

—

0.18

—

0.30

—

0.09

—

D

AA

BB

CC

DD

0.435

0.18

—

D2

E

2.90

—

3.35

—

E2

e

2.90

—

3.35

—

Preliminary Rev. 0.8

27

Si8250/1/2

DOCUMENT CHANGE LIST

Revision 0.7 to Revision 0.8

ꢀ Updated DPWM phase output drive-high and drive-

low resistance in Table 8, “DPWM Specifications,” on

page 9.

28

Preliminary Rev. 0.8

Si8250/1/2

NOTES:

Preliminary Rev. 0.8

29

Si8250/1/2

CONTACT INFORMATION

Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: productinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

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Preliminary Rev. 0.8


型号：	SI8250
厂家：	SILICON
描述：	DIGITAL POWER CONTROLLER 数字电源控制器功率控制控制器
文件：	总30页 (文件大小：1097K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI8250 [SILICON]

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