SI8405AB-A-IS1 [SILICON]
Interface Circuit, PDSO16, SOIC-16;
| 型号： | SI8405AB-A-IS1 |
| 厂家： | 
SILICON |
| 描述： | Interface Circuit, PDSO16, SOIC-16 光电二极管 接口集成电路 |
| 文件： | 总34页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si840x
BIDIRECTIONAL I2C ISOLATORS WITH UNIDIRECTIONAL
DIGITAL CHANNELS
Features
Independent, bidirectional SDA and 60-year life at rated working voltage
SCL isolation channels
Open drain outputs with 35 mA
sink current
High electromagnetic immunity
Wide operating supply voltage
3.0 to 5.5 V
Supports I2C clocks up to 1.7 MHz
Unidirectional isolation channels
support additional system signals
(Si8405)
Wide temperature range
–40 to +125 °C max
Transient immunity 25 kV/µs
RoHS-compliant packages
SOIC-8 narrow body
Up to 2500 VRMS isolation
UL, CSA, VDE recognition
SOIC-16 narrow body
Applications
2
Motor Control Systems
Hot-swap applications
Intelligent Power systems
Isolated I C, SMBus
Isolated digital power supply
communications
Power over Ethernet
Description
The Si840x series of isolators are single-package galvanic isolation
2
solutions for I C and SMBus serial port applications. These products are
Ordering Information:
based on Silicon Labs proprietary RF isolation technology and offer shorter
propagation delays, lower power consumption, smaller installed size, and
more stable operation with temperature and age versus opto couplers or
other digital isolators.
See page 25.
All devices in this family include hot-swap, bidirectional SDA and SCL
isolation channels with open-drain, 35 mA sink capability and operate to a
maximum frequency of 1.7 MHz. The 8-pin version (Si8400/01) supports
bidirectional SDA and SCL isolation; the Si8402 supports bidirectional SDA
and unidirectional SCL isolation, and the 16-pin version (Si8405) features
two unidirectional isolation channels to support additional system signals,
such as an interrupt or reset. All versions contain protection circuits to
guard against data errors if an unpowered device is inserted into a powered
system.
Small size, low installed cost, low power consumption, and short
propagation delays make the Si840x family the optimum solution for
2
isolating I C and SMBus serial ports.
Safety Regulatory Approval
UL 1577 recognized
Up to 2500 VRMS for 1 minute
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
CSA component notice 5A approval
IEC 60950-1, 61010-1
(reinforced insulation)
Rev. 1.6 10/13
Copyright © 2013 by Silicon Laboratories
Si840x
Si840x
2
Rev. 1.6
Si840x
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4. Input and Output Characteristics for Non-I2C Digital Channels . . . . . . . . . . . . . . . .15
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Typical Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1. I2C Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2. I2C Isolator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3. I2C Isolator Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.4. I2C Isolator Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.1. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . .22
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
8. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
9. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
10. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
11. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
12. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
12.1. 8-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
12.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
13. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
13.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.6
3
Si840x
1. Electrical Specifications
Table 1. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
150
125
5.75
6.0
Unit
°C
°C
V
2
Storage Temperature
T
STG
Ambient Temperature Under Bias
T
A
3
Supply Voltage (Revision A)
V
DD
DD
3
Supply Voltage (Revision B)
V
V
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
2
Output Current Drive (non-I C channels)
I
I
I
±10
mA
mA
mA
°C
O
2
Side A output current drive (I C channels)
—
±15
±75
O
O
2
Side B output current drive (I C channels)
—
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s)
Notes:
—
260
—
3600
V
RMS
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "7.Ordering Guide" on page 25 for more information.
Table 2. Si840x Power Characteristics*
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C (See Figures 2 and 16 for test diagrams.)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8400/01/02 Supply Current
AVDD current
BVDD current
Idda
Iddb
All channels = 0 dc
All channels = 1 dc
—
—
4.2
3.9
6.3
5.9
mA
mA
AVDD current
BVDD current
Idda
Iddb
—
—
2.3
1.9
3.5
2.9
mA
mA
AVDD current
BVDD current
Idda
Iddb
All channels = 1.7 MHz
—
—
3.2
2.9
4.8
4.4
mA
mA
Si8405 Supply Current
2
AVDD current
BVDD current
Idda
Iddb
All non-I C channels = 0
—
—
3.2
2.9
4.8
4.4
mA
mA
2
All I C channels = 1
2
AVDD current
BVDD current
Idda
Iddb
All non-I C channels = 1
—
—
6.2
6.0
9.3
9.0
mA
mA
2
All I C channels = 0
2
AVDD current
BVDD current
Idda
Iddb
All non-I C channels = 5 MHz
—
—
4.7
4.5
7.1
6.8
mA
mA
2
All I C channels = 1.7 MHz
*Note: All voltages are relative to respective ground.
4
Rev. 1.6
Si840x
Table 3. Si8400/01/02/05 Electrical Characteristics for Bidirectional I2C Channels1
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Logic Levels Side A
Logic Input Threshold
Logic Low Output Voltages
2
2
I CV (Side A)
450
—
—
—
—
780
910
825
—
mV
mV
mV
mV
T
3
2
I CV (Side A) ISDAA = ISCLA = 3.0 mA 650
OL
ISDAA = ISCLA = 0.5 mA 550
2
Input/Output Logic Low Level
Difference
I CV (Side A)
50
4
Logic Levels Side B
2
Logic Low Input Voltage
Logic High Input Voltage
Logic Low Output Voltage
I CV (Side B)
—
2.0
—
—
—
—
0.8
—
400
V
V
mV
IL
2
I CV (Side B)
IH
2
I CV (Side B)
ISCLB = 35 mA
OL
SCL and SDA Logic High
Leakage
Isdaa, Isdab
Iscla, Isclb
SDAA, SCLA = VSSA
SDAB, SCLB = VSSB
—
2.0
10
µA
Pin capacitance SDAA, SCLA,
SDAB, SDBB
CA
CB
—
—
10
10
—
—
pF
pF
Notes:
1. All voltages are relative to respective ground.
2. VIL < 0.450 V, VIH > 0.780 V.
3. Logic low output voltages are 910 mV max from –10 to 125 °C at 3.0 mA.
Logic low output voltages are 955 mV max from –40 to 125 °C at 3.0 mA.
Logic low output voltages are 825 mV max from –10 to 125 °C at 0.5 mA.
Logic low output voltages are 875 mV max from –40 to 125 °C at 0.5 mA.
See “AN375: Design Considerations for Isolating an I2C Bus or SMBus” for additional information.
4. I2CV (Side A) = I2CVOL (Side A) – I2CVT (Side A). To ensure no latch-up on a given bus, I2CV (Side A) is the
minimum difference between the output logic low level of the driving device and the input logic threshold.
5. Side A measured at 0.6 V.
Rev. 1.6
5
Si840x
Table 3. Si8400/01/02/05 Electrical Characteristics for Bidirectional I2C Channels1 (Continued)
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Specifications (Measured at 1.40 V Unless Otherwise Specified)
2
Maximum I C bus Frequency
Fmax
—
—
1.7
MHz
Propagation Delay
5 V Operation
Side A to side B rising
5
Tphab
Tplab
Tphba
Tplba
No bus capacitance,
R1 = 1400,
—
—
—
—
25
15
20
9.0
29
22
30
12
ns
ns
ns
ns
5
Side A to side B falling
Side B to side A rising
Side B to side A falling
3.3 V Operation
R2 = 499,
See Figure 2
5
Side A to side B rising
Side A to side B falling
Tphab
Tplab
Tphba
Tplba
—
—
—
—
28
13
20
10
35
18
40
15
ns
ns
ns
ns
5
R1 = 806
R2 = 499
Side B to side A rising
Side B to side A falling
Pulse width distortion
5 V
Side A low to Side B low
Side B low to Side A low
3.3 V
Side A low to Side B low
No bus capacitance,
R1 = 1400,
5
PWDAB
PWDBA
R2 = 499,
See Figure 2
—
—
9.0
11
15
20
ns
ns
5
PWDAB
PWDBA
R1 = 806,
R2 = 499
—
—
15
11
22
30
ns
ns
Side B low to Side A low
Notes:
1. All voltages are relative to respective ground.
2. VIL < 0.450 V, VIH > 0.780 V.
3. Logic low output voltages are 910 mV max from –10 to 125 °C at 3.0 mA.
Logic low output voltages are 955 mV max from –40 to 125 °C at 3.0 mA.
Logic low output voltages are 825 mV max from –10 to 125 °C at 0.5 mA.
Logic low output voltages are 875 mV max from –40 to 125 °C at 0.5 mA.
See “AN375: Design Considerations for Isolating an I2C Bus or SMBus” for additional information.
4. I2CV (Side A) = I2CVOL (Side A) – I2CVT (Side A). To ensure no latch-up on a given bus, I2CV (Side A) is the
minimum difference between the output logic low level of the driving device and the input logic threshold.
5. Side A measured at 0.6 V.
6
Rev. 1.6
Si840x
Table 4. Electrical Characteristics for Unidirectional Non-I2C Digital Channels (Si8402/05)
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
AVDD, BVDD
–0.4
4.8
V
OH
Low Level Output Voltage
Input Leakage Current
V
—
—
—
0.2
—
0.4
±10
—
V
µA
OL
I
L
1
Output Impedance
Z
85
O
Timing Characteristics
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
—
10
40
20
12
Mbps
ns
—
—
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Output Rise Time
t
—
—
—
—
—
20
10
ns
ns
ns
PSK(P-P)
t
PSK
t
C = 15 pF
4.0
6.0
r
3
See Figure 1 and
Figure 2
Output Fall Time
t
C = 15 pF
—
3.0
4.3
ns
f
3
See Figure 1 and
Figure 2
Notes:
1. The nominal output impedance of a non-I2C isolator driver channel is approximately 85 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET.
When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with
controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
Rev. 1.6
7
Si840x
Table 5. Electrical Characteristics for All I2C and Non-I2C Channels
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
VDDUV+
VDDH–
Test Condition
AVDD, BVDD rising
AVDD, BVDD falling
Min
2.15
45
Typ Max
Unit
V
VDD Undervoltage Threshold
2.3
75
2.5
95
VDD Negative-going Lockout
Hysteresis
mV
Common Mode Transient
Immunity
CMTI
V = V or 0 V
—
25
—
kV/µs
I
DD
Shut Down Time from UVLO
t
—
—
3.0
15
—
µs
µs
SD
*
Start-up Time
t
40
START
*Note: Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing (Non-I2C Channels)
1.1. Test Circuits
Figure 2 depicts the timing test diagram.
AVDD
NC
BVDD
NC
R2
R2
R1
R1
ASDA
ADIN
ADOUT
BSDA
BDOUT
BDIN
ASCL
NC
BSCL
NC
C2
C3
C2
C3
C1
C1
AGND
BGND
Si840x
Figure 2. Simplified Timing Test Diagram
8
Rev. 1.6
Si840x
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 V
60950-1: Up to 130 V
VDE
reinforced insulation working voltage; up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
basic insulation working voltage.
RMS
RMS
RMS
RMS
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 V
for basic insulation working voltage.
peak
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 V isolation voltage for basic insulation.
RMS
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "7.Ordering Guide" on page 25.
Table 7. Insulation and Safety-Related Specifications
Parameter
Symbol Test Condition
Value
Unit
NB SOIC-8 NB SOIC-16
1
Nominal Air Gap (Clearance)
L(1O1)
L(1O2)
4.9
4.01
0.008
4.9
4.01
0.008
mm
mm
mm
1
Nominal External Tracking (Creepage)
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
600
V
RMS
0.040
0.019
mm
Erosion Depth
2
12
12
Resistance (Input-Output)
R
10
10
IO
2
Capacitance (Input-Output)
C
1.0
4.0
2.0
4.0
pF
pF
IO
3
Input Capacitance
C
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “8. Package Outline:
8-Pin Narrow Body SOIC” and “10. Package Outline: 16-Pin Narrow Body SOIC”. VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-8 package and 4.7 mm minimum for the NB SOIC-16 package.
UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the
clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 package and 3.9 mm minimum for the NB
SOIC-16 package.
2. To determine resistance and capacitance, the Si840x, SO-16, is converted into a 2-terminal device. Pins 1–8 (1-4, SO-
8) are shorted together to form the first terminal and pins 9–16 (5–8, SO-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Rev. 1.6
9
Si840x
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Condition
Specification
Basic Isolation Group
Material Group
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
RMS
RMS
RMS
RMS
Installation Classification
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Symbol
Test Condition
Characteristic Unit
V
560
V peak
V peak
Maximum Working Insulation Voltage
Input to Output Test Voltage
IORM
Method b1
(V
x 1.875 = V , 100%
IORM
PR
V
1050
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
V
t = 60 sec
4000
2
V peak
Transient Overvoltage
IOTM
Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at T , V = 500 V
9
R
>10
S
S
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter
Symbol
Test Condition
NB
NB
Unit
SOIC-8 SOIC-16
Case Temperature
Safety Input Current
T
I
150
160
150
210
°C
S
= 105 °C/W (NB SOIC-16),
140 °C/W (NB SOIC-8)
AVDD, BVDD = 5.5 V,
mA
S
JA
T = 150 °C, T = 25 °C
J
A
2
Device Power Dissipation
P
220
275
W
D
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 3 and Figure 4.
2. The Si840x is tested with AVDD, BVDD = 5.5 V; TJ = 150 ºC; C1, C2 = 0.1 µF; C3 = 15 pF; R1, R2 = 3kinput 1 MHz
50% duty cycle square wave.
10
Rev. 1.6
Si840x
Table 11. Thermal Characteristics
Parameter
Symbol
Test Condition
NB
NB
Unit
SOIC-8 SOIC-16
IC Junction-to-Air Thermal Resistance
140 105
°C/W
JA
400
300
270
AVDD, BVDD = 3.6 V
200
160
AVDD, BVDD = 5.5 V
100
0
0
50
100
150
200
Case Temperature (ºC)
Figure 3. NB SOIC-8 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
500
400
350
300
AVDD , BVDD = 3.6 V
210
200
AVDD , BVDD = 5.5 V
100
0
0
50
100
150
200
Temperature (ºC)
Figure 4. NB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 1.6
11
Si840x
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single unidirectional Si84xx channel is
shown in Figure 5.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 5. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 6 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 6. Modulation Scheme
12
Rev. 1.6
Si840x
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO–
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own under
voltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally
enters UVLO when AVDD falls below AVDD
and exits UVLO when AVDD rises above AVDD
. Side B
UVLO–
UVLO+
operates the same as Side A with respect to its BVDD supply.
UVLO+
UVLO-
AVDD
UVLO+
UVLO-
BVDD
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 7. Device Behavior during Normal Operation
Rev. 1.6
13
Si840x
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 9 and Table 7 on page 9 detail the working
voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component standards
(UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system
specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.) requirements before
starting any design that uses a digital isolator.
The following sections detail the recommended bypass and decoupling components necessary to ensure robust
overall performance and reliability for systems using the Si84xx digital isolators.
3.3.1. Supply Bypass
Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically
quiet environments. However, digital isolators are commonly used in hazardous environments with excessively
noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass
capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as
close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is
recommended that the designer add 50 to 100 resistors in series with the VDD supply voltage source and 50 to
300 resistors in series with the digital inputs/outputs (see Figure 8). For more details, see "5.Errata and Design
Migration Guidelines" on page 22.
All components upstream or downstream of the isolator should be properly decoupled as well. If these components
are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing
damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300 resistors protect
the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are
exceeded). Functional operation should be restricted to the conditions specified in Table 3, “Si8400/01/02/05
1
Electrical Characteristics for Bidirectional I2C Channels ,” on page 5. and Table 4, “Electrical Characteristics for
Unidirectional Non-I2C Digital Channels (Si8402/05),” on page 7
3.3.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
3.3.3. Output Pin Termination
2
The nominal output impedance of an non-I C isolator driver channel is approximately 85 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET.
When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated
with controlled impedance PCB traces. The series termination resistor values should be scaled appropriately while
keeping in mind the recommendations described in “3.3.1. Supply Bypass” above.
V Source 2
R2 (50 – 100 )
V Source 1
R1 (50 – 100 )
C1
AVDD
Ax
BVDD
Bx
C4
50 – 300
50 – 300
0.1 F
0.1 F
C2
C3
Input/Output
Input/Output
1 F
1 F
Ax
Bx
50 – 300
50 – 300
AGND
BGND
Figure 8. Recommended Bypass Components for the Si84xx Digital Isolator Family
14
Rev. 1.6
Si840x
2
3.4. Input and Output Characteristics for Non-I C Digital Channels
The Si84xx inputs and outputs for unidirectional channels are standard CMOS drivers/receivers. The nominal
output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where
transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance
2
PCB traces. Table 12 details powered and unpowered operation of the Si84xx’s non-I C digital channels.
Table 12. Si84xx Operation Table
1,2
1,2
1,3,4
1,3,4
Comments
V Input
V Output
VDDI State
VDDO State
I
O
H
L
P
P
P
P
H
L
Normal operation.
Upon transition of VDDI from unpowered to pow-
5
6
X
UP
P
P
L
ered, V returns to the same state as V in less
O
I
than 1 µs.
Upon transition of VDDO from unpowered to pow-
5
X
UP
Undetermined
ered, V returns to the same state as V within
O
I
1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low.
3. Powered (P) state is defined as 3.0 V < VDD < 5.5 V.
4. Unpowered (UP) state is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. For I2C channels, the outputs for a given side go to Hi-Z when power is lost on the opposite side.
Rev. 1.6
15
Si840x
3.5. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 2, 3, 4, and 5 for actual specification limits.
Side A
Side B
Side B
Side A
Figure 12. I2C Side A Pulling Up, Side B
Following
Figure 9. I2C Side A Pulling Down
(1100 Pull-Up)
10
Falling Edge
9
8
7
6
5
Side B
Side A
Rising Edge
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 13. Non I2C Channel Propagation Delay
vs. Temperature
Figure 10. I2C Side B Pulling Down
Side B
Side A
Figure 11. I2C Side B Pulling Up, Side A
Following
16
Rev. 1.6
Si840x
Figure 14. Si84xx Time-Dependent Dielectric Breakdown
Rev. 1.6
17
Si840x
4. Typical Application Overview
2
4.1. I C Background
2
In many applications, I C, SMBus, and other digital power supply communications, including those for bus power
management, the interfaces require galvanic isolation for safety or ground loop elimination. For example, Power
2
over Ethernet (PoE) applications typically use an I C interface for communication between the PoE power sourcing
device (PSE), and the earth ground referenced system controller. Galvanic isolation is required both by standard
and also as a practical matter to prevent ground loops in Ethernet connected equipment.
The physical interface consists of two wires: serial data (SDA) and serial clock (SCL). These wires are connected
to open collector drivers that serve as both inputs and outputs. At first glance, it appears that SDA and SCL can be
isolated simply by placing two unidirectional isolators in parallel, and in opposite directions. However, this
technique creates feedback that latches the bus line low when a logic low asserted by either master or slave. This
problem can be remedied by adding anti-latch circuits, but results in a larger and more expensive solution. The
2
Si840x products offer a single-chip, anti-latch solution to the problem of isolating I C/SMBus applications and
2
require no external components except the I C/SMBus pull-up resistors. In addition, they provide isolation to a
2
2
maximum of 2.5 kV
, support I C clock stretching, and operate to a maximum I C bus speed of 1.7 Mbps.
RMS
2
4.2. I C Isolator Operation
2
Without anti-latch protection, bidirectional I C isolators latch when an isolator output logic low propagates back
through an adjacent isolator channel creating a stable latched low condition on both sides. Anti-latch protection is
typically added to one side of the isolator to avoid this condition (the “A” side for the Si8400/01/02/05).
The following examples illustrate typical circuit configurations using the Si8400/01/02/05.
Si8400/01/02/05
I2C/SMBus
Unit 1
+
-
VIL
VOL
I2C/SMBus
Unit 2
ISO1
VIL
VOL
ISO2
Figure 15. Isolated Bus Overview (Bidirectional Channels)
The “A side” output low (V ) and input low (V ) levels are designed such that the isolator V is greater than the
OL
IL
OL
isolator V to prevent the latch condition.
IL
18
Rev. 1.6
Si840x
2
4.3. I C Isolator Design Constraints
Table 13 lists the design constraints.
Table 13. Design Constraints
Effect of Bus Pull-up Strength
and Temperature
Design Constraint
Data Sheet Values
Isolator V 0.8 V typical
OL
This is normally guaranteed by the
isolator data sheet. However, if the
pull up strength is too weak, the out-
put low voltage will fall and can get
too close to the input low logic level.
These track over temperature.
Isolator V 0.6 V typical
To prevent the latch condition, the
isolator output low level must be
greater than the isolator input low
level.
IL
Input/Output Logic Low Level
Difference
∆VSDA1, ∆VSCL1 = 50 mV minimum
If the pull up strength is too large,
the devices on the bus might not pull
the voltage below the input low
range. These have opposite tem-
perature coefficients. Worst case is
hot temperature.
Bus V = 0.4 V maximum
The bus output low must be less
than the isolator input low logic
level.
OL
Isolator V = 0.45 V minimum
IL
If the pull up strength is too large,
the isolator might not pull below the
bus input low voltage.
Si8400/01/05 Vol: –1.8 mV/C
CMOS buffer: –0.6 mV/C
This provides some temperature
tracking, but worst case is cold tem-
perature.
Bus V 0.3 x V = 1.0 V minimum for
IL
DD
V
= 3.3 V
DD
The isolator output low must be
less than the bus input low.
Isolator V = 0.825 V maximum,
OL
(0.5 mA pullup, –10 to 125 °C)
2
4.4. I C Isolator Design Considerations
2
The first step in applying an I C isolator is to choose which side of the bus will be connected to the isolator A side.
Ideally, it should be the side which:
1. Is compatible with the range of bus pull up specified by the manufacturer. For example, the Si8400/01/02/05
isolators are normally used with a pull up of 0.5 mA to 3 mA.
2. Has the highest input low level for devices on the bus. Some devices may specify an input low of 0.9 V and
other devices might require an input low of 0.3 x Vdd. Assuming a 3.3 V minimum power supply, the side with
an input low of 0.3 x Vdd is the better side because this side has an input low level of 1.0 V.
3. Have devices on the bus that can pull down below the isolator input low level. For example, the Si840x input
level is 0.45 V. As most CMOS devices can pull to within 0.4 V of GND this is generally not an issue.
4. Has the lowest noise. Due to the special logic levels, noise margins can be as low as 50 mV.
The Si840x isolators are not compatible with devices that have a logic low of 0.8 V. For this situation, a discrete
2
circuit can be used. See “AN352: Low-Cost, High-Speed I C Isolation with Digital Isolators” for additional
information.
Rev. 1.6
19
Si840x
Figures 16, 17, 18, and 19 illustrate typical circuit configurations using the Si8400, Si8401, Si8402 and Si8405.
BVDD
8
7
1
2
AVDD
ASDA
0.1 µF
3k
3k
0.1 µF
3k
3k
BSDA
I2C
Bus
BSCL
3
4
6
5
ASCL
BGND
AGND
Si8400
Figure 16. Typical Si8400 Application Diagram
BVDD
8
7
1
2
AVDD
ASDA
0.1 µF
3k
3k
0.1 µF
3k
3k
BSDA
I2C
Bus
BSCL
3
4
6
5
ASCL
BGND
AGND
Si8401
Figure 17. Typical Si8401 Application Diagram
BVDD
8
7
1
2
AVDD
ASDA
0.1 µF
3k
0.1 µF
3k
BSDA
I2C
Bus
BSCL
3
4
6
5
ASCL
BGND
AGND
Si8402
Figure 18. Typical Si8402 Application Diagram
20
Rev. 1.6
Si840x
BVDD
16
15
1
2
AVDD
0.1 µF
0.1 µF
3k
3k
3k
3k
BSDA
3
14
13
12
11
10
9
ASDA
Micro-
controller
RESET
4
5
6
7
8
I2C
Bus
Micro-
controller
INT
BSCL
ASCL
BGND
AGND
Si8405
Figure 19. Typical Si8405 Application Diagram
Rev. 1.6
21
Si840x
5. Errata and Design Migration Guidelines
The following errata apply to Revision A devices only. See "7.Ordering Guide" on page 25 for more details. No
errata exist for Revision B devices.
5.1. Power Supply Bypass Capacitors (Revision A and Revision B)
When using the Si840x isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on
both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V
supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins
(VDD1, VDD2) of the isolator device.
5.1.1. Resolution
For recommendations on resolving this issue, see "3.3.1.Supply Bypass" on page 14. Additionally, refer to
"7.Ordering Guide" on page 25 for current ordering information.
22
Rev. 1.6
Si840x
6. Pin Descriptions
1
2
3
4
8
7
6
5
AVDD
ASDA
ASCL
AGND
BVDD
BSDA
BSCL
BGND
1
2
3
4
8
7
6
5
AVDD
ASDA
ASCL
AGND
BVDD
BSDA
BSCL
BGND
Bidirectional
Isolator Channel
Bidirectional
Isolator Channel
Bidirectional
Isolator Channel
Unidirectional
Isolator Channel
Si8402
Si8400/01
Table 14. Si8400/01/02 in SO-8 Package
Description
Pin
1
Name
AVDD Side A power supply terminal; connect to a source of 3.0 to 5.5 V.
ASDA Side A data (open drain) input or output.
2
3
ASCL Side A clock input or output.
Open drain I/O for Si8400/01. Standard CMOS input for Si8402.
4
5
6
AGND Side A ground terminal.
BGND Side B ground terminal.
BSCL Side B clock input or output.
Open drain I/O for Si8400/01. Push-pull output for Si8402.
7
8
BSDA Side B data (open drain) input or output.
BVDD Side B power supply terminal; connect to a source of 3.0 to 5.5 V.
Rev. 1.6
23
Si840x
BVDD
NC
16
15
14
13
12
11
10
9
AVDD
NC
1
2
Bidirectional
Isolator Channel
3
4
5
6
7
8
ASDA
ADIN
BSDA
BDOUT
BDIN
BSCL
NC
Unidirectional
Isolator Channel
Unidirectional
Isolator Channel
ADOUT
ASCL
Bidirectional
Isolator Channel
NC
AGND
BGND
Si8405
Table 15. Si8405 in Narrow-Body SO-16 Package
Description
Pin
Name
1
2
3
4
AVDD
NC
Side A Power Supply Terminal. Connect to a source of 3.0 to 5.5 V.
No connection.
ASDA
ADIN
Side A Data (open drain) Input or Output.
Side A Standard CMOS Digital Input (non I2C).
Side A Digital Push-Pull Output (non I2C).
Side A Clock (open drain) Input or Output.
No connection.
5
6
ADOUT
ASCL
NC
7
8
AGND
BGND
NC
Side A Ground Terminal.
9
Side B Ground Terminal.
10
11
12
No connection.
BSCL
BDIN
Side B Clock (open drain) Input or Output.
Side B Standard CMOS Digital Input (non I2C).
Side B Digital Push-Pull Output (non I2C).
Side B Data (open drain) Input or Output.
No connection.
13
BDOUT
14
15
16
BSDA
NC
BVDD
Side B Power Supply Terminal. Connect to a source of 3.0 to 5.5 V.
24
Rev. 1.6
Si840x
7. Ordering Guide
These devices are not recommended for new designs. Please see the Si860x datasheet for replacement options.
Table 16. Ordering Guide1
MaxI2C
Bus
Speed
(MHz)
Ordering Part
Number
Alternative Part
Number
Number of
Bidirectional
I2C
Channels
Number of
Unidirectional
Channels
Max Data Rate Isolation
Package
of Non-I2C
Ratings
(OPN)
(APN)
Unidirectional
Channels
(Mbps)
Revision B Devices2
Si8400AA-B-IS
Si8400AB-B-IS
Si8401AA-B-IS
Si8401AB-B-IS
Si8402AB-B-IS
Si8600AB-B-IS
2
2
1
1
1
1.7
1.7
1.7
1.7
1.7
0
0
1
1
1
—
—
—
—
10
1 kVRMS
2.5 kVRMS
1 kVRMS
NB SOIC-8
NB SOIC-8
NB SOIC-8
NB SOIC-8
NB SOIC-8
Si8600AB-B-IS
Si8602AB-B-IS
Si8602AB-B-IS
Si8602AB-B-IS
2.5 kVRMS
2.5 kVRMS
1 forward
1 reverse
Si8405AA-B-IS1 Si8605AB-B-IS1
2
2
1.7
1.7
10
10
1 kVRMS
NB SOIC-16
1 forward
1 reverse
Si8405AB-B-IS1 Si8605AB-B-IS1
2.5 kVRMS NB SOIC-16
Revision A Devices2
Si8400AA-A-IS
Si8400AB-A-IS
Si8600AB-B-IS
Si8600AB-B-IS
2
2
1.7
1.7
0
0
—
—
1 kVRMS
NB SOIC-8
NB SOIC-8
2.5 kVRMS
1 forward
1 reverse
Si8405AA-A-IS1 Si8605AB-B-IS1
2
2
1.7
1.7
10
10
1 kVRMS
NB SOIC-16
1 forward
1 reverse
Si8405AB-A-IS1 Si8605AB-B-IS1
2.5 kVRMS NB SOIC-16
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C
according to the JEDEC industry standard classifications and peak solder temperature.
2. Revision A and Revision B devices are supported for existing designs.
Rev. 1.6
25
Si840x
8. Package Outline: 8-Pin Narrow Body SOIC
Figure 20 illustrates the package details for the Si840x in an 8-pin SOIC (SO-8). Table 17 lists the values for the
dimensions shown in the illustration.
Figure 20. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 17. Package Diagram Dimensions
Millimeters
Symbol
Min
Max
A
A1
A2
B
1.35
1.75
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0
6.20
0.50
1.27
8
L
26
Rev. 1.6
Si840x
9. Land Pattern: 8-Pin Narrow Body SOIC
Figure 21 illustrates the recommended land pattern details for the Si840x in an 8-pin narrow-body SOIC. Table 18
lists the values for the dimensions shown in the illustration.
Figure 21. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 18. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.6
27
Si840x
10. Package Outline: 16-Pin Narrow Body SOIC
Figure 22 illustrates the package details for the Si840x in a 16-pin narrow-body SOIC (SO-16). Table 19 lists the
values for the dimensions shown in the illustration.
Figure 22. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 19. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
0.25 BSC
28
Rev. 1.6
Si840x
Table 19. Package Diagram Dimensions (Continued)
Dimension
Min
0.25
0°
Max
0.50
8°
h
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012,
Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.6
29
Si840x
11. Land Pattern: 16-Pin Narrow Body SOIC
Figure 23 illustrates the recommended land pattern details for the Si840x in a 16-pin narrow-body SOIC. Table 20
lists the values for the dimensions shown in the illustration.
Figure 23. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 20. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
30
Rev. 1.6
Si840x
12. Top Marking: 8-Pin Narrow Body SOIC
12.1. 8-Pin Narrow Body SOIC Top Marking
Si84XYSV
YYWWRF
e3
AIXX
12.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator I2C Product Series:
XY = Channel Configuration
00 = Bidirectional SCL and SDA channels
01/02 = Bidirectional SDA channel;
Unidirectional SCL channel
(See Ordering Guide for more
information).
S = Speed Grade
A = 1.7 Mbps
V = Isolation rating
A = 1 kV; B = 2.5 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Work week
Assigned by assembly contractor. Corresponds to the
year and work week of the mold date.
R = Product Rev
F = Wafer Fab
First two characters of the manufacturing code from
Assembly.
Circle = 1.1 mm Diameter
Left-Justified
“e3” Pb-Free Symbol
A = Assembly Site
I = Internal Code
Last four characters of the manufacturing code from
assembly.
XX = Serial Lot Number
Rev. 1.6
31
Si840x
13. Top Marking: 16-Pin Narrow Body SOIC
13.1. 16-Pin Narrow Body SOIC Top Marking
Si84XYSV
YYWWTTTTTT
e3
13.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator product series
XY = Channel Configuration
05 = Bidirectional SCL, SDA; 1- forward and 1-reverse
unidirectional channel
S = Speed Grade
A = 1.7 Mbps
V = Isolation rating
A = 1 kV; B = 2.5 kV
Line 2 Marking:
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
TTTTTT = Mfg code
Manufacturing Code from Assembly Purchase Order
form.
Circle = 1.2 mm diameter
“e3” Pb-Free Symbol.
32
Rev. 1.6
Si840x
Revision 1.3 to Revision 1.4
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
Updated "3.3.1.Supply Bypass" on page 14.
Added Figure 8, “Recommended Bypass
Components for the Si84xx Digital Isolator Family,”
on page 14.
Updated document to reflect availability of Revision
B silicon.
Updated Tables 2, 3, 4, and 5.
Updated "5.1.Power Supply Bypass Capacitors
(Revision A and Revision B)" on page 22.
Updated all supply currents and timing parameters.
Revised logic low output voltage specifications in
Table 3.
Revision 1.4 to Revision 1.5
Updated Table 1.
Updated absolute maximum supply voltage.
Updated Table 7.
Updated "7.Ordering Guide" on page 25 to include
new title note and “ Alternative Part Number (APN)”
column.
Updated clearance and creepage dimensions.
Updated "5.Errata and Design Migration Guidelines"
on page 22.
Revision 1.5 to Revision 1.6
Updated part numbers on page 1 and in pin
descriptions images.
Updated "7.Ordering Guide" on page 25.
Revision 1.0 to Revision 1.1
Updated Table 4.
Updated Note 1 to reflect output impedance of 85 .
Updated rise and fall time specifications.
Updated Table 5.
Updated CMTI value.
Updated “7. Ordering Guide”.
Added Si8401 device configuration throughout
document.
Revision 1.1 to Revision 1.2
Updated document throughout to include MSL
improvements to MSL2A.
Updated "7.Ordering Guide" on page 25.
Updated Note 1 in ordering guide table to reflect
improvement and compliance to MSL2A moisture
sensitivity level.
Revision 1.2 to Revision 1.3
Added Si8402 throughout document. Clarified
description of Si8401’s BSCL pin to indicate pin type
is an open output, whereas the Si8402’s BSCL pin is
a push-pull CMOS pin.
Updated "7.Ordering Guide" on page 25 to include
Si8402.
Moved Table 1 to page 4.
Updated Tables 6, 7, 8, and 9.
Updated Table 12 footnotes.
Added Figure 14, “Si84xx Time-Dependent
Dielectric Breakdown,” on page 17.
Added Figure 18, “Typical Si8402 Application
Diagram,” on page 20.
Rev. 1.6
33
Si840x
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
http://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-
intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-
ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-
ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
34
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