SI8410-A-IS [SILICON]
SINGLE & DUAL-CHANNEL DIGITAL ISOLATORS; 单，双通道数字隔离器
| 型号： | SI8410-A-IS |
| 厂家： | 
SILICON |
| 描述： | SINGLE & DUAL-CHANNEL DIGITAL ISOLATORS |
| 文件： | 总26页 (文件大小：574K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8410/20/21
SINGLE & DUAL-CHANNEL DIGITAL ISOLATORS
Features
Pin Assignments
ꢀ High-speed operation
ꢁ DC – 150 Mbps
ꢀ 2500 V
isolation
RMS
ꢀ Transient Immunity
ꢁ >25 kV/µs
Narrow Body SOIC
ꢀ Low propagation delay
ꢁ <10 ns
Si841x
ꢀ DC correct
ꢀ Wide Operating Supply Voltage:
2.375–5.5 V
ꢀ No start-up initialization required
ꢀ <10 µs Startup Time
ꢀ High temperature operation
VDD1
VDD2
8
7
6
5
1
2
3
4
A1
VDD1
GND2
B1
ꢀ Low power
ꢁ I1 + I2 < 12 mA/channel at
ꢁ 125 °C at 100 Mbps
ꢁ 100 °C at 150 Mbps
100 Mbps
GND1
GND2
ꢀ Precise timing
ꢀ Narrow body SOIC-8 package
Top View
ꢁ 2 ns pulse width distortion
ꢁ 1 ns channel-channel matching
ꢁ 2 ns pulse width skew
Si842x
VDD1
A1
VDD2
B1
8
7
6
5
1
2
3
4
Applications
ꢀ Isolated switch mode supplies ꢀ Motor control
A2
B2
ꢀ Isolated ADC, DAC
ꢀ Power factor correction systems
GND1
GND2
Top View
Safety Regulatory Approvals
ꢀ UL recognition:2500 Vrms for 1 ꢀ IEC certification conformity
Minute per UL1577
ꢁ IEC 60747-5-2
(VDE0884 Part 2)
ꢀ CSA component acceptance
notice
Description
The Silicon Laboratories family of digital isolators are CMOS devices that
employ an RF coupler to transmit digital information across an isolation
barrier. Very high speed operation at low power levels is achieved. These
parts are available in an 8-pin narrow-body SOIC package. Three speed
grade options (1, 10, and 150 Mbps) are available and achieve typical
propagation delays of less than 10 ns.
Block Diagram
Si8410
Si8420
Si8421
B1
B2
B1
B2
A1
A2
A1
A2
A1
B1
Preliminary Rev. 0.1 5/07
Copyright © 2007 by Silicon Laboratories
Si8410/20/21
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si8410/20/21
2
Preliminary Rev. 0.1
Si8410/20/21
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . .22
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
7. Package Outline: 8-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Preliminary Rev. 0.1
3
Si8410/20/21
1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
V
OL
I
—
µA
L
DC Supply Current (All inputs 0 V or at Supply)
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
—
—
—
—
7
3
10
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
9
14
5
3
7
10
7
4
11
4
15
6
9
12
12
14
14
9
10
10
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410-B,-C, V
Si8410-B,-C, V
Si8420-B,-C, V
Si8420-B,-C, V
Si8421-B,-C, V
Si8421-B,-C, V
—
—
—
—
—
—
8
5
12
7
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
9
13
12
16
16
9
12
12
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410-C, V
Si8410-C, V
Si8420-C, V
Si8420-C, V
Si8421-C, V
Si8421-C, V
—
—
—
—
—
—
8
12
22
13
39
27
27
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
15
9
30
21
21
4
Preliminary Rev. 0.1
Si8410/20/21
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Timing Characteristics
Si841x/2x-A
Min
Typ
Max
Unit
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
40
—
1
1000
75
Mbps
ns
—
25
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
30
ns
|t
- t
|
PLH PHL
1
1
1
Propagation Delay Skew
Channel-Channel Skew
Si841x/2x-B
t
—
—
—
—
50
40
ns
ns
PSK(P-P)
t
PSK
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
20
—
10
100
35
Mbps
ns
—
10
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
7.5
ns
|t
- t
|
PLH PHL
Propagation Delay Skew
Channel-Channel Skew
Si841x/2x-C
t
—
—
—
—
25
5
ns
ns
PSK(P-P)
t
PSK
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
4
—
—
150
6.6
9.5
3.5
Mbps
ns
t
, t
See Figure 1
See Figure 1
6.5
—
ns
PHL PLH
Pulse Width Distortion
PWD
—
ns
|t
- t
|
PLH PHL
Propagation Delay Skew
Channel-Channel Skew
t
—
—
—
—
5.5
3
ns
ns
PSK(P-P)
t
PSK
Preliminary Rev. 0.1
5
Si8410/20/21
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
For All Models
Min
Typ
Max
Unit
Output Rise Time
t
C = 15 pF
—
—
25
2
2
—
—
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
L
f
Common Mode Transient
Immunity
CTMI
V = V or 0 V
30
kV/µs
I
DD
2
Start-up Time
t
—
3
—
µs
SU
Notes:
1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
2. Start-up time is the time period from the application of power to valid data at the output.
50%
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
50%
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing
6
Preliminary Rev. 0.1
Si8410/20/21
Table 2. Electrical Characteristics
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
V
OL
I
—
µA
L
DC Supply Current (All inputs 0 V or at supply)
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
—
—
—
—
6
2
9
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
8
13
4
2
7
9
4
6
10
4
14
6
8
11
11
13
13
8
9
9
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410-B,-C, V
Si8410-B,-C, V
Si8420-B,-C, V
Si8420-B,-C, V
Si8421-B,-C, V
Si8421-B,-C, V
—
—
—
—
—
—
7
4
11
6
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
8
12
12
14
14
8
10
10
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410-C, V
Si8410-C, V
Si8420-C, V
Si8420-C, V
Si8421-C, V
Si8421-C, V
—
—
—
—
—
—
7
11
16
12
26
21
21
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
10
8
20
17
17
Preliminary Rev. 0.1
7
Si8410/20/21
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si841x/2x-A
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
40
—
1
1000
75
Mbps
ns
—
25
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
30
ns
|t
– t
|
PLH
PHL
1
1
1
Propagation Delay Skew
Channel-Channel Skew
Si841x/2x-B
t
—
—
—
—
50
40
ns
ns
PSK(P-P)
t
PSK
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
20
—
10
100
35
Mbps
ns
—
10
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
7.5
ns
|t
– t
|
PLH
PHL
Propagation Delay Skew
Channel-Channel Skew
Si841x/2x-C
t
—
—
—
—
25
5
ns
ns
PSK(P-P)
t
PSK
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
4
—
—
150
6.6
10
Mbps
ns
t
, t
See Figure 1
See Figure 1
7.5
—
ns
PHL PLH
Pulse Width Distortion
PWD
—
3.5
ns
|t
– t
|
PLH
PHL
Propagation Delay Skew
Channel-Channel Skew
t
—
—
—
—
5.5
3
ns
ns
PSK(P-P)
t
PSK
8
Preliminary Rev. 0.1
Si8410/20/21
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
For All Models
Min
Typ
Max
Unit
Output Rise Time
t
C = 15 pF
—
—
25
2
2
—
—
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
L
f
Common Mode Transient
Immunity
CTMI
V = V or 0 V
30
kV/µs
I
DD
2
Start-up Time
t
—
3
—
µs
SU
Notes:
1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
2. Start-up time is the time period from the application of power to valid data at the output.
Preliminary Rev. 0.1
9
Si8410/20/21
Table 3. Electrical Characteristics
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
2.3
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
V
OL
I
—
µA
L
DC Supply Current (All inputs 0 V or at supply)
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8410-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8420-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
Si8421-A,-B,-C, V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
—
—
—
—
5
2
7
2
6
4
9
3
7
7
8
8
7
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
9
3
7
5
11
5
9
9
10
10
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410-B,-C, V
Si8410-B,-C, V
Si8420-B,-C, V
Si8420-B,-C, V
Si8421-B,-C, V
Si8421-B,-C, V
—
—
—
—
—
—
6
3
7
6
8
8
8
5
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
9
8
11
11
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410-C, V
Si8410-C, V
Si8420-C, V
Si8420-C, V
Si8421-C, V
Si8421-C, V
—
—
—
—
—
—
6
7
8
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
10
9
7
12
12
12
15
15
15
10
Preliminary Rev. 0.1
Si8410/20/21
Table 3. Electrical Characteristics (Continued)
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 °C)
Parameter
Symbol
Test Condition
Timing Characteristics
Si841x/2x-A
Min
Typ
Max
Unit
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
40
1
Mbps
ns
—
25
1000
75
ns
t
, t
See Figure 1
See Figure 1
PHL PLH
Pulse Width Distortion
—
—
30
ns
PWD
|t
- t
|
PLH PHL
1
1
1
Propagation Delay Skew
Channel-Channel Skew
—
—
—
—
50
40
ns
ns
t
PSK(P-P)
t
PSK
Si841x/2x-B
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
20
10
100
35
Mbps
ns
—
10
ns
t
, t
See Figure 1
See Figure 1
PHL PLH
Pulse Width Distortion
—
—
7.5
ns
PWD
|t
- t
|
PLH PHL
Propagation Delay Skew
Channel-Channel Skew
—
—
—
—
25
5
ns
ns
t
PSK(P-P)
t
PSK
Si841x/2x-C
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
5
—
—
10
100
10
Mbps
ns
17
ns
t
, t
See Figure 1
See Figure 1
PHL PLH
Pulse Width Distortion
—
—
7
ns
PWD
|t
- t
|
PLH PHL
Propagation Delay Skew
Channel-Channel Skew
—
—
—
—
12
4
ns
ns
t
PSK(P-P)
t
PSK
Preliminary Rev. 0.1
11
Si8410/20/21
Table 3. Electrical Characteristics (Continued)
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 °C)
Parameter
Symbol
Test Condition
For All Models
Min
Typ
Max
Unit
Output Rise Time
t
C = 15 pF
—
—
25
2
2
—
—
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
L
f
Common Mode Transient
Immunity
CTMI
V = V or 0 V
30
kV/µs
I
DD
2
Start-up Time
t
—
3
—
µs
SU
Notes:
1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
2. Start-up time is the time period from the application of power to valid data at the output.
12
Preliminary Rev. 0.1
Si8410/20/21
Table 4. Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Supply Voltage
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
Max
150
125
6
Unit
C°
C°
V
T
STG
T
A
V
, V
DD2
DD1
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
O
Output Current Drive Channel
Lead Solder Temperature (10s)
Maximum Isolation Voltage
L
10
mA
C°
—
260
—
4000
V
DC
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet.
Table 5. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
–40
Typ
25
25
—
Max
125
100
5.5
Unit
C°
C°
V
Ambient Operating Tempera-
ture*
T
100 Mbps, 15 pF, 5 V
150 Mbps, 15 pF, 5 V
A
0
Supply Voltage
V
2.375
2.375
DD1
V
—
5.5
V
DD2
*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating
channels, and supply voltage.
Preliminary Rev. 0.1
13
Si8410/20/21
Table 6. Regulatory Information
CSA
The Si84xx is certified under CSA Component Acceptance Notice. For more details, see File 232873.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si84xx is certified under UL1577 component recognition program to provide basic insulation to 2500 V
RMS
(1 minute). It is production tested > 3000 V
for 1 second. For more details, see File E257455.
RMS
Table 7. Insulation and Safety-related Specifications
Parameter
Symbol
L(IO1)
L(IO2)
Test Condition
Value
5.0 min
4.60
Unit
mm
mm
mm
Minimum Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
0.008
min
Tracking Resistance (Comparative Tracking
Index)
CTI
DIN IEC 60112/VDE 0303 Part 1
f = 1 MHz
>175
V
1
12
Resistance (Input-Output)
R
10
Ω
IO
1
Capacitance (Input-Output)
C
1.4
4.0
pF
pF
IO
2
Input Capacitance
C
I
Notes:
1. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–4 are shorted
together to form the first terminal and pins 5–8 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
2. Measured from input pin to ground.
14
Preliminary Rev. 0.1
Si8410/20/21
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Conditions
Specification
Basic isolation group
Material Group
IIIa
I-IV
I-III
I-II
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
RMS
RMS
RMS
Installation Classification
Table 9. IEC 60747-5-2 Insulation Characteristics*
Parameter
Symbol
Test Condition
Characteristic
Unit
Maximum Working Insulation Voltage
VIORM
560
V peak
Method a
After Environmental Tests
Subgroup 1
896
(VIORM x 1.6 = VPR, tm = 60 sec,
Partial Discharge < 5 pC)
Method b1
VPR
V peak
Input to Output Test Voltage
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
1050
After Input and/or Safety Test
Subgroup 2/3
(VIORM x 1.2 = VPR, tm = 60 sec,
Partial Discharge < 5 pC)
672
Highest Allowable Overvoltage (Transient
Overvoltage, tTR = 10 sec)
4000
V peak
VTR
Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO = 500 V
2
RS
>109
Ω
*Note: The Si84xx is suitable for basic electrical isolation a climate classification of 40/125/21.
Table 10. IEC Safety Limiting Values
Parameter
Case Temperature
Safety input, output, or supply current
Symbol
Test Condition
Min
—
Typ
Max Unit
—
T
I
150
105
°C
S
θ
= 210 °C/W,
JA
—
—
mA
S
V = 5.5 V,
I
T = 150 °C,
J
T = 25 °C
A
*Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2.
Preliminary Rev. 0.1
15
Si8410/20/21
Table 11. Thermal Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
IC Junction-to-Case Thermal Resistance
θ
Thermocouple
located at center of
package
—
100
—
°C/W
JC
IC Junction-to-Air Thermal Resistance
Device Power Dissipation*
θ
—
—
210
—
—
°C/W
mW
JA
P
250
D
*Note: The Si8420-C-IS is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 °C, CL = 15 pF, input a 150 Mbps 50% duty cycle
square wave.
100
78
75
2.75 V
5.5 V
50
3.6 V
25
0
0
50
100
150
200
Case Temperature (ºC)
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Preliminary Rev. 0.1
Si8410/20/21
2. Typical Performance Characteristics
10
9
20
15
10
5
5V
5V
3.3V
8
3.3V
7
2.5V
2.5V
6
5
0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Data Rate (Mbps)
Data Rate (Mbps)
Figure 6. Si8420 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 3. Si8410 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
12
5V
10
19
3.3V
5V
8
17
6
15
3.3V
2.5V
13
4
11
2.5V
2
0
9
7
5
0
10
20
30
40
50
60
70
80
90
100
Data Rate (Mbps)
0
10
20
30
40
50
60
70
80
90
100
Data Rate (Mbps)
Figure 4. Si8410 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 7. Si8421 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.5 V
Operation (15 pF Load)
15
13
11
5V
9
7
5
3.3V
2.5V
0
10
20
30
40
50
60
70
80
90
100
Data Rate (Mbps)
Figure 5. Si8420 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
Preliminary Rev. 0.1
17
Si8410/20/21
10
9
8
Falling Edge
7
6
5
Rising Edge
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 8. Propagation Delay
vs. Temperature 5 V Operation
10
9
Rising Edge
8
Falling Edge
7
6
5
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 9. Propagation Delay
vs. Temperature 3.3 V Operation
15
13
11
9
Rising Edge
Falling Edge
7
5
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 10. Propagation Delay
vs. Temperature 2.5 V Operation
18
Preliminary Rev. 0.1
Si8410/20/21
3. Application Information
3.1. Theory of Operation
The operation of an Si841x or Si842x channel is analogous to that of an opto coupler, except that an RF carrier is
modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at startup. A simplified block diagram for a single Si8410 channel is shown in
Figure 11. A channel consists of an RF transmitter and receiver separated by a transformer.
Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying and
applies the resulting waveform to the primary of the transformer. The receiver contains a demodulator that decodes
the input state according to its RF energy content and applies the result to output B via the output driver.
TRANSMITTER
RF
OSCILLATOR
RECEIVER
MODULATOR
DEMODULATOR
A
B
Figure 11. Simplified Channel Diagram
3.2. Eye Diagram
Figure 12 illustrates an eye-diagram taken on an Si8410. The test used an Anritsu (MP1763C) Pulse Pattern
Generator for the data source. The output of the generator's clock and data from an Si8410 were captured on an
oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The
results also show that very low pulse width distortion and very little jitter were exhibited.
Figure 12. Eye Diagram
Preliminary Rev. 0.1
19
Si8410/20/21
4. Layout Recommendations
Dielectric isolation is a set of specifications produced by safety regulatory agencies from around the world, which
describes the physical construction of electrical equipment that derives power from high-voltage power systems,
such as 100–240 V
systems or industrial power. The dielectric test (or HIPOT test) given in the safety
AC
specifications places a very high voltage between the input power pins of a product and the user circuits and the
user-touchable surfaces of the product. For the IEC relating to products deriving their power from the 220–240 V
power grids, the test voltage is 2500 V (or 3750 V , the peak equivalent voltage).
AC
DC
There are two terms described in the safety specifications:
ꢀ Creepage—the distance along the insulating surface an arc may travel.
ꢀ Clearance—the shortest distance through air that an arc may travel.
Figure 13 illustrates the accepted method of providing the proper creepage distance along the surface. For a
220–240 V application, this distance is 8 mm, and the wide-body SOIC package must be used. There must be no
copper traces within this 8 mm exclusion area, and the surface should have a conformal coating, such as solder
resist. The digital isolator chip must straddle this exclusion area.
Figure 13. Creepage Distance
4.1. Supply Bypass
The Si841x and Si842x families require a 0.1 µF bypass capacitor between V
The capacitor should be placed as close as possible to the package.
and GND1 and V
and GND2.
DD2
DD1
20
Preliminary Rev. 0.1
Si8410/20/21
4.2. Input and Output Characteristics
The Si841x and Si842x inputs and outputs are standard CMOS drivers/receivers. Table 12 details powered and
unpowered operation of the Si84xx.
Table 12. Si84xx Operation Table
1,4
1,2,3
1,2,3
1,4
Comments
V Input
VDDI State
VDDO State
V Output
I
O
H
L
P
P
P
P
P
H
L
L
Normal operation.
X
UP
Upon the transition of VDDI from unpowered to
powered, V returns to the same state as V in less
O
I
than 1 µs.
Upon the transition of VDDI from unpowered to
powered, V returns to the same state as V in less
X
P
UP
L
O
I
than 1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.375 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
4.3. RF Radiated Emissions
The Si841x and Si842x families use an RF carrier frequency of approximately 2.1 GHz. This will result in a small
amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but, rather,
is due to a small amount of RF energy driving the isolated ground planes, which can act as a dipole antenna.
The unshielded Si8410 evaluation board passes FCC requirements. Table 13 shows measured emissions
compared to FCC requirements.
Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less
efficient antenna.
Table 13. Radiated Emissions
Frequency Measured FCC Spec Compared to
(GHz)
2.094
2.168
4.210
4.337
6.315
6.505
8.672
(dBµV/m) (dBµV/m)
Spec (dB)
70.0
68.3
61.9
60.7
58.3
60.7
45.6
74.0
74.0
74.0
74.0
74.0
74.0
74.0
–4.0
–5.7
–12.1
–13.3
–15.7
–13.3
–28.4
Preliminary Rev. 0.1
21
Si8410/20/21
4.4. RF Immunity and Common Mode Transient Immunity
The Si841x and Si842x families have very high common mode transient immunity while transmitting data. This is
typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds.
Measurements show no failures up to 30 kV/µs. During a high surge event, the output may glitch low for up to
20–30 ns, but the output corrects immediately after the surge event.
The Si841x and Si842x families pass the industrial requirements of CISPR24 for RF immunity of 3 V/m using an
unshielded evaluation board. As shown in Figure 14, the isolated ground planes form a parasitic dipole antenna,
while Figure 15 shows the RMS common mode voltage versus frequency above which the Si841x becomes
susceptible to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage
below the envelope specified in Figure 15. The PCB should be laid-out to not act as an efficient antenna for the RF
frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal
enclosure, or otherwise shielded.
GND1
GND2
Isolator
Dipole
Antenna
Figure 14. Dipole Antenna
5
4
3
2
1
0
500
1000
Frequency (MHz)
1500
2000
Figure 15. RMS Common Mode Voltage vs. Frequency
22
Preliminary Rev. 0.1
Si8410/20/21
5. Pin Descriptions
Si841x
Si842x
VDD1
A1
VDD2
GND2
B1
VDD1
A1
8
7
6
5
1
2
3
4
VDD2
8
1
2
3
4
B1
7
6
5
VDD1
A2
B2
GND1
GND2
GND1
GND2
Top View
Top View
Narrow Body SOIC
Name
SOIC-8 Pin#
Si8410
SOIC-8 Pin#
Type
Description
Si8420/21
V
1,3
4
1
4
2
3
7
6
8
5
Supply
Ground
Side 1 power supply.
DD1
GND1
A1
Side 1 ground.
2
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Side 1 digital input or output.
Side 1 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
A2
NA
6
B1
B2
NA
8
V
DD2
GND2
5,7
Ground
Side 2 ground.
Preliminary Rev. 0.1
23
Si8410/20/21
6. Ordering Guide
Ordering Part
Number
Number of Inputs Number of Inputs
Side Side
Maximum
Data Rate
Temperature
Package Type
V
V
DD2
DD1
Si8410-A-IS
Si8410-B-IS
Si8410-C-IS
Si8420-A-IS
Si8420-B-IS
Si8420-C-IS
Si8421-A-IS
Si8421-B-IS
Si8421-C-IS
1
0
1
10
150
1
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
1
1
2
2
2
1
1
1
0
0
0
0
0
1
1
1
10
150
1
10
150
Note: All packages are Pb-free and RoHS Compliant. Moisture sensitivity level is MSL2 with peak reflow temperature of
260 °C according to the JEDEC industry standard classifications and peak solder temperature.
24
Preliminary Rev. 0.1
Si8410/20/21
7. Package Outline: 8-Pin SOIC
Figure 16 illustrates the package details for the Si84xx. Table 14 lists the values for the dimensions shown in the
illustration.
α
Figure 16. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 14. Package Diagram Dimensions
Millimeters
Symbol
Min
Max
A
A1
A2
B
1.35
1.75
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
∝
Preliminary Rev. 0.1
25
Si8410/20/21
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: PowerProducts@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
26
Preliminary Rev. 0.1
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