SI8410AA-C-IS [SILICON]
Interface Circuit,;
| 型号： | SI8410AA-C-IS |
| 厂家： | 
SILICON |
| 描述： | Interface Circuit, |
| 文件： | 总28页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8410/20/21
ULTRA LOW POWER SINGLE & DUAL-CHANNEL DIGITAL ISOLATORS
Features
Pin Assignments
High-speed operation
DC – 150 Mbps
Precise timing
2 ns pulse width distortion
1 ns channel-channel matching
2 ns pulse width skew
Narrow Body SOIC
Low propagation delay
<10 ns typical
Si841x
Up to 2500 V
isolation
Wide Operating Supply Voltage:
2.75–5.5 V
RMS
VDD1
VDD2
8
7
6
5
1
2
3
4
Transient Immunity
25 kV/µs
A1
VDD1
GND2
B1
Ultra low power
5 V Operation:
DC correct
GND1
GND2
I< 1.25 mA per channel at 1 Mbps
I< 2 mA per channel at 10 Mbps
I< 6 mA per channel at 100 Mbps
2.75 V Operation:
I< 1.25 mA per channel at 1 Mbps
I< 2 mA per channel at 10 Mbps
I< 4 mA per channel at 100 Mbps
No start-up initialization required
<30 µs startup time
Top View
High temperature operation
125 °C at 150 Mbps
Si842x
Narrow body SOIC-8 package
VDD1
A1
VDD2
B1
8
7
6
5
1
2
3
4
A2
B2
Applications
GND1
GND2
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Top View
Power factor correction systems
Safety Regulatory Approvals*
UL recognition: 2500 Vrms for 1 IEC certification conformity
Minute per UL1577
IEC 60747-5-2
(VDE0884 Part 2)
CSA component acceptance
notice
Description
The Silicon Laboratories family of ultra low power digital isolators are
CMOS devices that employ an RF coupler to transmit digital information
across an isolation barrier. Very high speed operation at low power levels
is achieved. These parts are available in an 8-pin narrow-body SOIC
package. Two speed grade options (1 and 150 Mbps) are available and
achieve typical propagation delays of less than 10 ns.
Block Diagram
Si8410
Si8420
Si8421
B1
B2
B1
B2
A1
A2
A1
A2
A1
B1
*Note: Pending.
Preliminary Rev. 0.22 1/09
Copyright © 2009 by Silicon Laboratories
Si8410/20/21
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si8410/20/21
2
Preliminary Rev. 0.22
Si8410/20/21
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . .21
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Package Outline: 8-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Preliminary Rev. 0.22
3
Si8410/20/21
1. Electrical Specifications
Table 1. Electrical Characteristics1
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
V
OL
I
—
µA
L
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1
1
2
1
2
2
4
2
mA
mA
mA
DD1
DD2
DD1
DD2
Si8420Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1
2
3
2
2
4
6
4
DD1
DD2
DD1
DD2
Si8421Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
2
3
3
4
4
6
6
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
V
V
—
—
2
1
3
2
mA
mA
mA
DD1
DD2
Si8420Ax, Bx
V
V
—
—
2
2
4
4
DD1
DD2
Si8421Ax, Bx
V
V
—
—
3
3
5
5
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
V
V
—
—
2
6
4
12
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
3
12
5
18
DD1
DD2
Si8421Bx
V
V
—
—
8
8
12
12
DD1
DD2
4
Preliminary Rev. 0.22
Si8410/20/21
Table 1. Electrical Characteristics1 (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate
0
—
—
—
—
1
Mbps
ns
Minimum Pulse Width
Propagation Delay
—
—
—
250
35
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate
0
—
5
—
—
8
150
6
Mbps
ns
Minimum Pulse Width
Propagation Delay
t
, t
See Figure 1
See Figure 1
15
3
ns
PHL PLH
Pulse Width Distortion
PWD
—
—
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
t
—
—
—
—
10
3
ns
ns
PSK(P-P)
t
PSK
For All Models
Output Rise Time
Output Fall Time
t
C = 15 pF
—
—
20
2
2
—
—
—
ns
ns
r
L
t
C = 15 pF
L
f
Common Mode Transient
Immunity
CMTI
V = V or 0 V
25
kV/µs
I
DD
3
Start-up Time
t
—
30
—
µs
SU
Notes:
1. Electrical specification values are preliminary. Various specifications will be adjusted to reflect actual performance as
final product characterization data becomes available.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Preliminary Rev. 0.22
5
Si8410/20/21
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing
6
Preliminary Rev. 0.22
Si8410/20/21
Table 2. Electrical Characteristics1
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
V
OL
I
—
µA
L
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1
1
2
1
2
2
4
2
mA
mA
mA
DD1
DD2
DD1
DD2
Si8420Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1
2
3
2
2
4
6
4
DD1
DD2
DD1
DD2
Si8421Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
2
3
3
4
4
6
6
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
V
V
—
—
2
1
3
2
mA
mA
mA
DD1
DD2
Si8420Ax, Bx
V
V
—
—
2
2
4
4
DD1
DD2
Si8421Ax, Bx
V
V
—
—
2
2
4
4
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
V
V
—
—
2
4
4
6
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
3
8
5
12
DD1
DD2
Si8421Bx
V
V
—
—
6
6
9
9
DD1
DD2
Preliminary Rev. 0.22
7
Si8410/20/21
Table 2. Electrical Characteristics1 (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate
0
—
—
—
—
1
Mbps
ns
Minimum Pulse Width
Propagation Delay
—
—
—
250
35
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
25
ns
|t
– t
|
PLH
PHL
2
Propagation Delay Skew
Channel-Channel Skew
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate
0
—
5
—
—
8
150
6
Mbps
ns
Minimum Pulse Width
Propagation Delay
t
, t
See Figure 1
See Figure 1
15
3
ns
PHL PLH
Pulse Width Distortion
PWD
—
—
ns
|t
– t
|
PLH
PHL
2
Propagation Delay Skew
Channel-Channel Skew
t
—
—
—
—
10
3
ns
ns
PSK(P-P)
t
PSK
For All Models
Output Rise Time
Output Fall Time
t
C = 15 pF
—
—
20
2
2
—
—
—
ns
ns
r
L
t
C = 15 pF
L
f
Common Mode Transient
Immunity
CMTI
V = V or 0 V
25
kV/µs
I
DD
3
Start-up Time
t
—
30
—
µs
SU
Notes:
1. Electrical specification values are preliminary. Various specifications will be adjusted to reflect actual performance as
final product characterization data becomes available.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Preliminary Rev. 0.22
Si8410/20/21
Table 3. Electrical Characteristics1
(VDD1 = 2.75 V, VDD2 = 2.75 V, TA = –40 to 125 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
2.3
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
V
OL
I
—
µA
L
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1
1
2
1
2
2
4
2
mA
mA
mA
V
V
V
V
DD1
DD2
DD1
DD2
Si8420Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1
2
3
2
2
4
6
4
V
V
V
V
DD1
DD2
DD1
DD2
Si8421Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
2
3
3
4
4
6
6
V
V
V
V
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
—
—
2
1
3
2
mA
mA
mA
V
V
DD1
DD2
Si8420Ax, Bx
—
—
2
2
4
4
V
V
DD1
DD2
Si8421Ax, Bx
—
—
2
2
4
4
V
V
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
—
—
2
4
4
6
mA
mA
mA
V
V
DD1
DD2
Si8420Bx
—
—
3
7
5
12
V
V
DD1
DD2
Si8421Bx
—
—
5
5
9
9
V
V
DD1
DD2
Preliminary Rev. 0.22
9
Si8410/20/21
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.75 V, VDD2 = 2.75 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate
0
—
—
—
1
Mbps
ns
Minimum Pulse Width
Propagation Delay
—
—
250
35
ns
t
, t
See Figure 1
See Figure 1
PHL PLH
Pulse Width Distortion
—
—
25
ns
PWD
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
—
—
—
—
40
35
ns
ns
t
PSK(P-P)
t
PSK
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate
0
—
5
—
—
8
150
6
Mbps
ns
Minimum Pulse Width
Propagation Delay
15
ns
t
, t
See Figure 1
See Figure 1
PHL PLH
Pulse Width Distortion
—
—
3
ns
PWD
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
—
—
—
—
10
3
ns
ns
t
PSK(P-P)
t
PSK
For All Models
Output Rise Time
Output Fall Time
t
C = 15 pF
—
—
20
2
2
—
—
—
ns
ns
r
L
t
C = 15 pF
L
f
Common Mode Transient
Immunity
CMTI
V = V or 0 V
25
kV/µs
I
DD
3
Start-up Time
t
—
30
—
µs
SU
Notes:
1. Electrical specification values are preliminary. Various specifications will be adjusted to reflect actual performance as
final product characterization data becomes available.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Preliminary Rev. 0.22
Si8410/20/21
Table 4. Absolute Maximum Ratings
Parameter
Storage Temperature
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
Max
150
125
6
Unit
C°
C°
V
T
STG
Operating Temperature
Supply Voltage
T
A
V
, V
DD2
DD1
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
O
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s)
L
10
mA
C°
—
260
—
3600
V
RMS
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet.
Table 5. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Ambient Operating Tempera-
ture*
T
150 Mbps, 15 pF, 5 V
–40
25
125
C°
A
Supply Voltage
V
2.75
2.75
—
—
5.5
5.5
V
V
DD1
V
DD2
*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating
channels, and supply voltage.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice. For more details, see File 232873.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
*Note: Pending. All 2.5 kVRMS rated devices are production tested to >3.6 kVRMS for 1 sec. For more information, see
"6. Ordering Guide" on page 23.
Preliminary Rev. 0.22
11
Si8410/20/21
Table 7. Insulation and Safety-related Specifications
Parameter
Symbol
L(IO1)
L(IO2)
Test Condition
Value
5.0 min
4.60
Unit
mm
mm
mm
Minimum Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
0.008
min
Tracking Resistance (Comparative Tracking
Index)
CTI
DIN IEC 60112/VDE 0303 Part 1
f = 1 MHz
>175
V
1
12
Resistance (Input-Output)
R
10
IO
1
Capacitance (Input-Output)
C
1
pF
pF
IO
2
Input Capacitance
C
4.0
I
Notes:
1. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–4 are shorted
together to form the first terminal and pins 5–8 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
2. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Conditions
Material Group
Specification
Basic isolation group
IIIa
I-IV
I-III
I-II
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
RMS
RMS
RMS
Installation Classification
12
Preliminary Rev. 0.22
Si8410/20/21
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Symbol
Test Condition
Characteristic
Unit
Maximum Working Insulation Voltage
VIORM
560
V peak
Method a
After Environmental Tests
Subgroup 1
896
(VIORM x 1.6 = VPR, tm = 60 sec,
Partial Discharge < 5 pC)
Method b1
VPR
V peak
Input to Output Test Voltage
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
1050
After Input and/or Safety Test
Subgroup 2/3
(VIORM x 1.2 = VPR, tm = 60 sec,
672
Partial Discharge < 5 pC)
Highest Allowable Overvoltage (Transient
Overvoltage, tTR = 10 sec)
4000
V peak
VTR
Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO = 500 V
2
RS
>109
*Note: The Si84xx is suitable for basic electrical isolation with a climate classification of 40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter
Case Temperature
Symbol
Test Condition
Min
—
Typ
Max Unit
—
T
I
150
160
°C
S
Safety input, output, or supply current
= 140 °C/W,
JA
V = 5.5 V,
—
—
mA
S
I
T = 150 °C,
J
T = 25 °C
A
2
Device Power Dissipation
P
—
—
150
mW
D
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2.
2. The Si8420 is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 °C, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Preliminary Rev. 0.22
13
Si8410/20/21
Table 11. Thermal Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
IC Junction-to-Case Thermal Resistance
Thermocouple
located at center of
package
—
70
—
°C/W
JC
IC Junction-to-Air Thermal Resistance
—
140
—
°C/W
JA
400
320
VDD1, VDD2 = 2.75 V
300
270
VDD1, VDD2 = 3.3 V
200
160
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
200
Case Temperature (ºC)
Figure 2. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
14
Preliminary Rev. 0.22
Si8410/20/21
2. Typical Performance Characteristics*
20
15
10
5
2
5V
5V
1.8
1.6
3.3V
3.3V
1.4
1.2
1
2.75V
2.75V
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 6. Si8420 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.75 V Operation
(15 pF Load)
Figure 3. Si8410 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.75 V Operation
10
12
5V
10
5V
8
6
4
2
0
8
3.3V
3.3V
6
2.75V
4
2.75V
2
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 7. Si8421 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.75 V Operation
(15 pF Load)
Figure 4. Si8410 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.75 V Operation
(15 pF Load)
12
3.5
5V
10
5V
3
2.5
2
8
6
4
2
0
3.3V
2.75V
3.3V
2.75V
1.5
1
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 5. Si8420 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.75 V Operation
Figure 8. Si8421 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.75 V Operation
(15 pF Load)
Preliminary Rev. 0.22
15
Si8410/20/21
11
10.5
10
9.5
9
Falling Edge
8.5
8
Rising Edge
7.5
7
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 9. Propagation Delay
vs. Temperature 5 V Operation
11
10.5
10
Falling Edge
9.5
9
8.5
8
Rising Edge
7.5
7
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 10. Propagation Delay
vs. Temperature 3.3 V Operation
11
10.5
10
Falling Edge
9.5
9
Rising Edge
8.5
8
7.5
7
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 11. Propagation Delay
vs. Temperature 2.75 V Operation
16
Preliminary Rev. 0.22
Si8410/20/21
3. Application Information
3.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 12.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 12. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 13 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 13. Modulation Scheme
Preliminary Rev. 0.22
17
Si8410/20/21
3.2. Eye Diagram
Figure 14 illustrates an eye-diagram taken on an Si8410. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8410 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 14. Eye Diagram
18
Preliminary Rev. 0.22
Si8410/20/21
4. Layout Recommendations
Dielectric isolation is a set of specifications produced by safety regulatory agencies from around the world, which
describes the physical construction of electrical equipment that derives power from high-voltage power systems,
such as 100–240 V
systems or industrial power. The dielectric test (or HIPOT test) given in the safety
AC
specifications places a very high voltage between the input power pins of a product and the user circuits and the
user-touchable surfaces of the product. For the IEC relating to products deriving their power from the 220–240 V
power grids, the test voltage is 2500 V (or 3750 V , the peak equivalent voltage).
AC
DC
There are two terms described in the safety specifications:
Creepage—the distance along the insulating surface an arc may travel.
Clearance—the shortest distance through air that an arc may travel.
Figure 15 illustrates the accepted method of providing the proper creepage distance along the surface. For a
220–240 V application, this distance is 8 mm, and the wide-body SOIC package must be used. There must be
AC
no copper traces within this 8 mm exclusion area, and the surface should have a conformal coating, such as solder
resist. The digital isolator chip must straddle this exclusion area.
IEC Specified
Creepage
Distance
Figure 15. Creepage Distance
4.1. Supply Bypass
The Si841x and Si842x families require a 1 µF bypass capacitor between V
The capacitor should be placed as close as possible to the package.
and GND1 and V
and GND2.
DD1
DD2
Preliminary Rev. 0.22
19
Si8410/20/21
4.2. Input and Output Characteristics
The Si841x and Si842x inputs and outputs are standard CMOS drivers/receivers. Table 12 details powered and
unpowered operation of the Si84xx.
Table 12. Si84xx Operation Table
1,4
1,2,3
1,2,3
1,4
Comments
V Input
VDDI State
VDDO State
V Output
I
O
H
L
P
P
P
P
P
H
L
L
Normal operation.
X
UP
Upon the transition of VDDI from unpowered to
powered, V returns to the same state as V in less
O
I
than 1 µs.
X
P
UP
L
Upon the transition of VDDI from unpowered to
powered, V returns to the same state as V in less
O
I
than 1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.75 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
4.3. RF Radiated Emissions
The Si841x and Si842x families use an RF carrier frequency of approximately 700 MHz. This results in a small
amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but, rather,
is due to a small amount of RF energy driving the isolated ground planes, which can act as a dipole antenna.
The unshielded Si8410 evaluation board passes FCC requirements. Table 13 shows measured emissions
compared to FCC requirements.
Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less
efficient antenna.
Table 13. Radiated Emissions*
Frequency Measured
FCC Spec Compared to
(GHz)
2.094
2.168
4.210
4.337
6.315
6.505
8.672
(dBµV/m)
(dBµV/m)
Spec (dB)
70.0
74.0
–4.0
68.3
74.0
–5.7
61.9
74.0
–12.1
–13.3
–15.7
–13.3
–28.4
60.7
74.0
58.3
74.0
60.7
74.0
45.6
74.0
*Note: Data table to be updated pending final characterization.
20
Preliminary Rev. 0.22
Si8410/20/21
4.4. RF Immunity and Common Mode Transient Immunity
The Si841x and Si842x families have very high common mode transient immunity while transmitting data. This is
typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds.
Measurements show no failures up to 25 kV/µs. During a high surge event, the output may glitch low for up to
20–30 ns, but the output corrects immediately after the surge event.
The Si841x and Si842x families pass the industrial requirements of CISPR24 for RF immunity of 3 V/m using an
unshielded evaluation board. As shown in Figure 16, the isolated ground planes form a parasitic dipole antenna,
while Figure 17 shows the RMS common mode voltage versus frequency above which the Si841x becomes
susceptible to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage
below the envelope specified in Figure 17. The PCB should be laid-out to not act as an efficient antenna for the RF
frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal
enclosure, or otherwise shielded.
GND1
GND2
Isolator
Dipole
Antenna
Figure 16. Dipole Antenna
5
4
3
2
1
0
500
1000
Frequency (MHz)
1500
2000
Figure 17. RMS Common Mode Voltage vs. Frequency
(Data to be Updated Pending Final Characterization)
Preliminary Rev. 0.22
21
Si8410/20/21
5. Pin Descriptions
Si841x
Si842x
VDD1
A1
VDD2
GND2
B1
VDD1
A1
8
7
6
5
1
2
3
4
VDD2
B1
8
7
6
5
1
2
3
4
VDD1
A2
B2
GND1
GND2
GND1
GND2
Top View
Top View
Narrow Body SOIC
Name
SOIC-8 Pin#
Si8410
SOIC-8 Pin#
Type
Description
Si8420/21
V
1,3
4
1
4
2
3
7
6
8
5
Supply
Ground
Side 1 power supply.
DD1
GND1
A1
Side 1 ground.
2
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Side 1 digital input or output.
Side 1 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
A2
NA
6
B1
B2
NA
8
V
DD2
GND2
5,7
Ground
Side 2 ground.
22
Preliminary Rev. 0.22
Si8410/20/21
6. Ordering Guide
Si84XYSV-R-TPn
Isolator Product
Data channel count
Reverse channel count
Max Data Rate (A = 1 Mbps, B = 150 Mbps)
Insulation Rating (A = 1 kV, B = 2.5 kV)
Product Revision
Temp Range (I = –40 to +125 ºC)
Package Type (S = SOIC)
Package Extension (1 = Narrow Body)
Figure 18. Ordering Part Number (OPN) Convention
Table 14. Ordering Guide
Ordering Part Number of Number of Maximum Isolation Temp Range Package
Legacy Part
Equivalent
Number (OPN)
Inputs
Inputs
Data Rate
Rating
Type
VDD1 Side VDD2 Side (Mbps)
Si8410AA-C-IS
Si8410BA-C-IS
Si8420AA-C-IS
Si8420BA-C-IS
Si8421AA-C-IS
Si8421BA-C-IS
Si8410AB-C-IS
Si8410BB-C-IS
1
1
2
2
1
1
1
1
0
0
0
0
1
1
0
0
1
150
1
—
—
—
1 kVrms –40 to 125 °C NB SOIC-8
150
1
—
—
—
150
1
Si8410-A-IS
150
Si8410-B-IS,
Si8410-C-IS
Si8420AB-C-IS
Si8420BB-C-IS
2
2
0
0
1
Si8420-A-IS
2.5 kVrms –40 to 125 °C NB SOIC-8
150
Si8420-B-IS,
Si8420-C-IS
Si8421AB-C-IS
Si8421BB-C-IS
1
1
1
1
1
Si8421-A-IS
150
Si8421-B-IS,
Si8421-C-IS
*Note: All packages are Pb-free and RoHS compliant. Moisture sensitivity level is MSL3 with peak reflow temperature of 260
°C according to the JEDEC industry standard classifications, and peak solder temperature.
Preliminary Rev. 0.22
23
Si8410/20/21
7. Package Outline: 8-Pin SOIC
Figure 19 illustrates the package details for the Si84xx. Table 15 lists the values for the dimensions shown in the
illustration.
Figure 19. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 15. Package Diagram Dimensions
Millimeters
Symbol
Min
Max
A
A1
A2
B
1.35
1.75
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0
6.20
0.50
1.27
8
L
24
Preliminary Rev. 0.22
Si8410/20/21
8. Top Marking
Si84XYSV
YYWWRF
e3
AIXX
Figure 20. Isolator Top Marking
Table 16. Top Marking Explanations
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
(See Ordering Guide for more
information).
A = 1 kV; B = 2.5 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by Assembly Contractor. Corresponds to the
year and workweek of the mold date.
R = Product (OPN) Revision
F = Wafer Fab
Circle = 1.1 mm Diameter
Left-Justified
“e3” Pb-Free Symbol
First Two Characters of the Manufacturing Code
A = Assembly Site
I = Internal Code
Last Four Characters of the Manufacturing Code
XX = Serial Lot Number
Preliminary Rev. 0.22
25
Si8410/20/21
DOCUMENT CHANGE LIST
Revision 0.11 to Revision 0.21
Rev 0.21 is the first revision of this document that
applies to the new series of ultra low power isolators
featuring pinout and functional compatibility with
previous isolator products.
Updated “1. Electrical Specifications”.
Updated “6. Ordering Guide”.
Added “8. Top Marking”.
Revision 0.21 to Revision 0.22
Updated all specs to reflect latest silicon.
26
Preliminary Rev. 0.22
Si8410/20/21
NOTES:
Preliminary Rev. 0.22
27
Si8410/20/21
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: PowerProducts@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
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Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
28
Preliminary Rev. 0.22
相关型号：
SI8411DB-T1-E3
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