SI8410AB-D-IS [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO8, SOIC-8;
| 型号： | SI8410AB-D-IS |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO8, SOIC-8 光电二极管 接口集成电路 |
| 文件： | 总30页 (文件大小：1657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8410/20/21
LOW-POWER SINGLE AND DUAL-CHANNEL
DIGITAL ISOLATORS
Features
High-speed operation
DC to 150 Mbps
Up to 2500 V
isolation
RMS
60-year life at rated working
voltage
No start-up initialization required
Wide Operating Supply Voltage:
2.70–5.5 V
Precise timing (typical)
<10 ns worst case
Ultra low power (typical)
5 V Operation:
< 2.1 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
2.70 V Operation:
< 1.8 mA per channel at 1 Mbps
< 4 mA per channel at 100 Mbps
High electromagnetic immunity
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
Transient Immunity 25 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS-compliant packages
SOIC-8 narrow body
Ordering Information:
See page 25.
Applications
Industrial automation systems
Hybrid electric vehicles
Isolated ADC, DAC
Motor control
Isolated switch mode supplies
Power inverters
Communications systems
Safety Regulatory Approvals
UL 1577 recognized
VDE certification conformity
Up to 2500 VRMS for 1 minute
IEC 60747-5-2
(VDE0884 Part 2)
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability,
and external BOM advantages when compared to legacy isolation
technologies. The operating parameters of these products remain stable
across wide temperature ranges throughout their service life. For ease of
design, only VDD bypass capacitors are required.
Data rates up to 150 Mbps are supported, and all devices achieve worst-
case propagation delays of less than 10 ns. All products are safety
certified by UL, CSA, and VDE and support withstand voltages of up to
2.5 kVrms. These devices are available in an 8-pin narrow-body SOIC
package.
Rev. 1.5 9/13
Copyright © 2013 by Silicon Laboratories
Si8410/20/21
Si8410/20/21
2
Rev. 1.5
Si8410/20/21
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.1. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . .23
3.2. Latch Up Immunity (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.1. 8-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 1.5
3
Si8410/20/21
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
Test Condition
Min
–40
Typ
25
—
Max
125
5.5
Unit
°C
V
T
150 Mbps, 15 pF, 5 V
A
V
2.70
2.70
DD1
DD2
V
—
5.5
V
*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating
channels, and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
—
Max
150
125
5.75
6.0
Unit
°C
°C
V
2
Storage Temperature
T
STG
Operating Temperature
Supply Voltage (Revision C)
Supply Voltage (Revision D)
Input Voltage
T
A
3
3
V
V
, V
, V
DD1
DD1
DD2
DD2
V
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s)
Notes:
I
10
mA
°C
O
—
260
—
3600
V
RMS
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "5. Ordering Guide" on page 25 for more information.
4
Rev. 1.5
Si8410/20/21
Table 3. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
1
Output Impedance
Z
85
O
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
DD1
DD2
DD1
DD2
mA
mA
mA
Si8420Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
DD1
DD2
DD1
DD2
Si8421Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
V
V
—
—
1.3
0.9
2.0
1.4
mA
mA
mA
DD1
DD2
Si8420Ax, Bx
V
V
—
—
2.0
1.6
3.0
2.4
DD1
DD2
Si8421Ax, Bx
V
V
—
—
1.9
1.9
2.9
2.9
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
5
Si8410/20/21
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
V
V
—
—
1.3
1.2
2.0
1.8
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
2.0
2.1
3.0
3.2
DD1
DD2
Si8421Bx
V
V
—
—
2.2
2.2
3.3
3.3
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
V
V
—
—
1.4
4.6
2.1
5.8
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
2.2
9.2
3.3
11.5
DD1
DD2
Si8421Bx
V
V
—
—
5.8
5.8
7.3
7.3
DD1
DD2
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate
0
—
—
—
1.0
250
35
Mbps
ns
Minimum Pulse Width
Propagation Delay
—
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
—
—
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.5
Si8410/20/21
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate
Symbol
Test Condition
Min
Typ
Max
Unit
0
—
—
150
6.0
9.5
Mbps
ns
Minimum Pulse Width
Propagation Delay
—
t
, t
See Figure 1
See Figure 1
3.0
6.0
ns
PHL PLH
Pulse Width Distortion
PWD
—
1.5
2.5
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
Output Fall Time
t
C = 15 pF
—
—
3.8
2.8
5.0
3.7
ns
ns
r
L
t
C = 15 pF
L
f
Common Mode Transient
Immunity
CMTI
V = V or 0 V
—
—
25
15
—
kV/µs
µs
I
DD
3
Start-up Time
t
40
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing
Rev. 1.5
7
Si8410/20/21
Table 4. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
1
Output Impedance
Z
85
O
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
V
V
V
V
DD1
DD2
DD1
DD2
mA
mA
mA
Si8420Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
V
V
V
V
DD1
DD2
DD1
DD2
Si8421Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
V
V
V
V
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
—
—
1.3
0.9
2.0
1.4
mA
mA
mA
V
V
DD1
DD2
Si8420Ax, Bx
—
—
2.0
1.6
3.0
2.4
V
V
DD1
DD2
Si8421Ax, Bx
—
—
1.9
1.9
2.9
2.9
V
V
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.5
Si8410/20/21
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
—
—
1.3
1.2
2.0
1.8
mA
mA
mA
V
V
DD1
DD2
Si8420Bx
—
—
2.0
2.1
3.0
3.2
V
V
DD1
DD2
Si8421Bx
—
—
2.2
2.2
3.3
3.3
V
V
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
—
—
1.3
3.3
2.0
4.9
mA
mA
mA
V
V
DD1
DD2
Si8420Bx
—
—
2.0
6.5
3.0
8.1
V
V
DD1
DD2
Si8421Bx
—
—
4.4
4.4
5.5
5.5
V
V
DD1
DD2
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate
0
—
—
—
1.0
250
35
Mbps
ns
—
—
Minimum Pulse Width
Propagation Delay
t
, t
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
See Figure 1
—
—
25
ns
|t
– t
|
PLH
PHL
2
t
—
—
—
—
40
35
ns
ns
Propagation Delay Skew
PSK(P-P)
t
Channel-Channel Skew
PSK
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
9
Si8410/20/21
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate
Symbol
Test Condition
Min
Typ
Max
Unit
0
—
—
150
6.0
9.5
Mbps
ns
—
Minimum Pulse Width
Propagation Delay
t
, t
See Figure 1
See Figure 1
3.0
6.0
ns
PHL PLH
Pulse Width Distortion
PWD
—
1.5
2.5
ns
|t
– t
|
PLH
PHL
2
t
—
—
2.0
0.5
3.0
1.8
ns
ns
Propagation Delay Skew
Channel-Channel Skew
All Models
PSK(P-P)
t
PSK
t
C = 15 pF
—
—
4.3
3.0
6.1
4.3
ns
ns
Output Rise Time
Output Fall Time
r
L
t
C = 15 pF
f
L
Common Mode Transient
Immunity
CMTI
V = V or 0 V
—
—
25
15
—
kV/µs
µs
I
DD
3
t
40
Start-up Time
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.5
Si8410/20/21
Table 5. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
2.3
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
2
Output Impedance
Z
85
O
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
V
V
V
V
DD1
DD2
DD1
DD2
mA
mA
mA
Si8420Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
V
V
V
V
DD1
DD2
DD1
DD2
Si8421Ax, Bx
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
V
V
V
V
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
—
—
1.3
0.9
2.0
1.4
V
V
DD1
DD2
mA
mA
mA
Si8420Ax, Bx
—
—
2.0
1.6
3.0
2.4
V
V
DD1
DD2
Si8421Ax, Bx
—
—
1.9
1.9
2.9
2.9
V
V
DD1
DD2
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.5
11
Si8410/20/21
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
—
—
1.3
1.2
2.0
1.8
V
V
DD1
DD2
mA
mA
mA
Si8420Bx
—
—
2.0
2.1
3.0
3.2
V
V
DD1
DD2
Si8421Bx
—
—
2.2
2.2
3.3
3.3
V
V
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
—
—
1.3
2.7
2.0
4.0
V
V
DD1
DD2
mA
mA
mA
Si8420Bx
—
—
2.0
5.2
3.0
6.5
V
V
DD1
DD2
Si8421Bx
—
—
3.7
3.7
4.6
4.6
V
V
DD1
DD2
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate
0
—
—
—
1.0
250
35
Mbps
ns
Minimum Pulse Width
Propagation Delay
—
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
—
—
25
ns
|t
- t
|
PLH PHL
3
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.5
Si8410/20/21
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate
0
—
—
150
6.0
9.5
Mbps
ns
Minimum Pulse Width
Propagation Delay
—
t
, t
See Figure 1
See Figure 1
3.0
6.0
ns
PHL PLH
Pulse Width Distortion
PWD
—
1.5
2.5
ns
|t
- t
|
PLH PHL
3
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
t
C = 15 pF
—
—
4.8
3.2
6.5
4.6
ns
ns
Output Rise Time
Output Fall Time
r
L
t
C = 15 pF
f
L
Common Mode Transient
Immunity
CMTI
V = V or 0 V
—
—
25
15
—
kV/µs
µs
I
DD
4
t
40
Start-up Time
SU
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 V
60950-1: Up to 130 V
VDE
reinforced insulation working voltage; up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
basic insulation working voltage.
RMS
RMS
RMS
RMS
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 V
for basic insulation working voltage.
peak
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 V isolation voltage for basic insulation.
RMS
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 25.
Rev. 1.5
13
Si8410/20/21
Table 7. Insulation and Safety-Related Specifications
Parameter
Symbol
L(IO1)
L(IO2)
Test Condition
Value
4.9
Unit
mm
mm
mm
1
Nominal Air Gap (Clearance)
1
Nominal External Tracking (Creepage)
4.01
0.008
Minimum Internal Gap (Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
V
RMS
0.040
mm
Erosion Depth
2
12
Resistance (Input-Output)
R
10
IO
2
Capacitance (Input-Output)
C
1.0
4.0
pF
pF
IO
3
Input Capacitance
C
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in "6. Package Outline:
8-Pin Narrow Body SOIC" on page 26. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB
SOIC-8 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–4 are shorted
together to form the first terminal and pins 5–8 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Basic Isolation Group
Test Condition
Specification
Material Group
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
RMS
RMS
RMS
RMS
Installation Classification
14
Rev. 1.5
Si8410/20/21
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Symbol
Test Condition
Characteristic Unit
V
560
V peak
V peak
Maximum Working Insulation Voltage
Input to Output Test Voltage
IORM
Method b1
(V
x 1.875 = V , 100%
IORM
PR
V
1050
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
V
t = 60 sec
4000
2
V peak
Transient Overvoltage
IOTM
Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at T , V = 500 V
9
R
>10
S
S
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter
Case Temperature
Symbol
Test Condition
Min
Typ
Max Unit
—
T
—
150
160
150
°C
mA
mW
S
= 140 °C/W,
JA
V = 5.5 V,
I
Safety input, output, or supply current
I
—
—
—
—
S
T = 150 °C,
J
T = 25 °C
A
2
Device Power Dissipation
P
D
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2.
2. The Si841x/2x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 °C, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.5
15
Si8410/20/21
Table 11. Thermal Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
°C/W
IC Junction-to-Air Thermal Resistance
—
140
—
JA
400
320
VDD1, VDD2 = 2.70 V
300
270
VDD1, VDD2 = 3.3 V
200
160
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
200
Case Temperature (ºC)
Figure 2. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Rev. 1.5
Si8410/20/21
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 3.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 3. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 4 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 4. Modulation Scheme
Rev. 1.5
17
Si8410/20/21
2.2. Eye Diagram
Figure 5 illustrates an eye-diagram taken on an Si8410. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8410 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 5. Eye Diagram
18
Rev. 1.5
Si8410/20/21
2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12.
Table 12. Si84xx Logic Operation Table
1,4
1,4
1,2,3
1,2,3
Comments
V Input
V Output
VDDI State
VDDO State
I
O
H
L
P
P
P
P
H
L
Normal operation.
Upon transition of VDDI from unpowered to pow-
5
X
UP
P
P
L
ered, V returns to the same state as V in less
O
I
than 1 µs.
Upon transition of VDDO from unpowered to pow-
5
X
UP
Undetermined
ered, V returns to the same state as V within
O
I
1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.70 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
Rev. 1.5
19
Si8410/20/21
2.4. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 13 and Table 7 on page 14 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.)
requirements before starting any design that uses a digital isolator.
The following sections detail the recommended bypass and decoupling components necessary to ensure robust
overall performance and reliability for systems using the Si84xx digital isolators.
2.4.1. Supply Bypass
Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically
quiet environments. However, digital isolators are commonly used in hazardous environments with excessively
noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass
capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as
close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is
recommended that the designer add 50 to 100 resistors in series with the VDD supply voltage source and 50 to
300 resistors in series with the digital inputs/outputs (see Figure 6). For more details, see "3. Errata and Design
Migration Guidelines" on page 23.
All components upstream or downstream of the isolator should be properly decoupled as well. If these components
are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing
damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300 resistors protect
the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are
exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended
Operating Conditions,” on page 4.
2.4.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
2.4.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in
mind the recommendations described in “2.4.1. Supply Bypass” above.
V Source 2
R2 (50 – 100 )
V Source 1
R1 (50 – 100 )
C1
VDD1
A1
VDD2
B1
C4
50 – 300
50 – 300
0.1 F
0.1 F
C2
C3
Input/Output
Input/Output
1 F
1 F
Ax
Bx
50 – 300
50 – 300
GND1
GND2
Figure 6. Recommended Bypass Components for the Si84xx Digital Isolator Family
20
Rev. 1.5
Si8410/20/21
2.5. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 3, 4, and 5 for actual specification limits.
30
25
20
15
10
5
30
25
20
15
10
5
5V
5V
3.3V
3.3V
2.70V
2.70V
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 10. Si8410 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 7. Si8410 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
30
25
30
25
20
20
5V
5V
15
15
3.3V
3.3V
10
10
2.70V
2.70V
5
5
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 8. Si8420 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 11. Si8420 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
30
25
10
Falling Edge
9
8
7
6
5
5V
20
15
10
5
3.3V
Rising Edge
2.70V
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
-40
-20
0
20
40
60
80
100
120
Data Rate (Mbps)
Temperature (Degrees C)
Figure 9. Si8421 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Figure 12. Propagation Delay
vs. Temperature
Rev. 1.5
21
Si8410/20/21
Figure 13. Si84xx Time-Dependent Dielectric Breakdown
22
Rev. 1.5
Si8410/20/21
3. Errata and Design Migration Guidelines
The following errata apply to Revision C devices only. See "5. Ordering Guide" on page 25 for more details. No
errata exist for Revision D devices.
3.1. Power Supply Bypass Capacitors (Revision C and Revision D)
When using the Si84xx isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on
both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V
supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins
(VDD1, VDD2) of the isolator device.
3.1.1. Resolution
For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 20. Additionally, refer to "5.
Ordering Guide" on page 25 for current ordering information.
3.2. Latch Up Immunity (Revision C Only)
Si84xx latch up immunity generally exceeds ± 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latch-
up immunity. To increase latch-up immunity on these pins, 100 of equivalent resistance must be included in
series with all of the pins listed in Table 13. The 100 equivalent resistance can be comprised of the source
driver's output resistance and a series termination resistor. The Si8410 is not affected by the latch up immunity
issue described above.
3.2.1. Resolution
This issue has been corrected with Revision D of the device. Refer to “5. Ordering Guide” for current ordering
information.
Table 13. Affected Ordering Part Numbers (Revision C Only)
Device
Affected Ordering Part Numbers*
Pin#
Name
Pin Type
Revision
3
7
A2
B1
Input or Output
Output
SI8420SV-C-IS, SI8421SV-C-IS
C
*Note: SV = Speed Grade/Isolation Rating (AA, AB, BA, BB).
Rev. 1.5
23
Si8410/20/21
4. Pin Descriptions
VDD1
VDD2
B1
VDD1
VDD1
VDD2
VDD2
B1
I
s
o
l
a
t
I
s
o
l
a
t
i
I
s
o
l
a
t
RF
XMITR
RF
RCVR
RF
XMITR
RF
XMITR
RF
RCVR
A1
A2
A1
GND2/NC
B1
A1
A2
RF
XMITR
RF
RCVR
RF
RCVR
RF
RCVR
RF
XMITR
B2
VDD1/NC
B2
i
i
o
n
o
n
o
n
GND1
GND2
GND2
GND2
GND1
GND1
Si8410 NB SOIC-8
Si8420 NB SOIC-8
Si8421 NB SOIC-8
Name
SOIC-8 Pin#
Si8410
SOIC-8 Pin#
Type
Description
Si8420/21
V
/NC*
1,3
4
1
4
2
3
7
6
8
5
Supply
Ground
Side 1 power supply.
DD1
GND1
Side 1 ground.
A1
A2
B1
B2
2
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Side 1 digital input or output.
Side 1 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
NA
6
NA
8
V
DD2
GND2/NC*
5,7
Ground
Side 2 ground.
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
24
Rev. 1.5
Si8410/20/21
5. Ordering Guide
These devices are not recommended for new designs. Please see the Si861x datasheet for replacement options.
Table 14. Ordering Guide for Valid OPNs1
Ordering Part
Number
Alternative
Number of
Number of
Maximum
Isolation
Rating
Package
Type
Part Number Inputs VDD1 Inputs VDD2 Data Rate
(OPN)
(APN)
Side
Side
(Mbps)
2
Revision D Devices
Si8410AB-D-IS
Si8410BB-D-IS
Si8420AB-D-IS
Si8420BB-D-IS
Si8421AB-D-IS
Si8421BB-D-IS
1
1
2
2
1
1
0
0
0
0
1
1
1
150
1
Si8610AB-B-IS
Si8610BB-B-IS
Si8620AB-B-IS
Si8620BB-B-IS
Si8621AB-B-IS
Si8621BB-B-IS
2.5 kVrms
NB SOIC-8
150
1
150
2
Revision C Devices
Si8410AB-C-IS
Si8410BB-C-IS
Si8420AB-C-IS
Si8420BB-C-IS
Si8421AB-C-IS
Si8421BB-C-IS
Notes:
1
1
2
2
1
1
0
0
0
0
1
1
1
150
1
Si8610AB-B-IS
Si8610BB-B-IS
Si8620AB-B-IS
Si8620BB-B-IS
Si8621AB-B-IS
Si8621BB-B-IS
2.5 kVrms
NB SOIC-8
150
1
150
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C
according to the JEDEC industry standard classifications and peak solder temperature.
2. Revision C and Revision D devices are supported for existing designs.
Rev. 1.5
25
Si8410/20/21
6. Package Outline: 8-Pin Narrow Body SOIC
Figure 14 illustrates the package details for the Si841x. Table 15 lists the values for the dimensions shown in the
illustration.
Figure 14. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 15. Package Diagram Dimensions
Millimeters
Symbol
Min
Max
A
A1
A2
B
1.35
1.75
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0
6.20
0.50
1.27
8
L
26
Rev. 1.5
Si8410/20/21
7. Land Pattern: 8-Pin Narrow Body SOIC
Figure 15 illustrates the recommended land pattern details for the Si841x in an 8-pin narrow-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 15. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 16. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.5
27
Si8410/20/21
8. Top Marking: 8-Pin Narrow Body SOIC
8.1. 8-Pin Narrow Body SOIC Top Marking
Si84XYSV
YYWWRF
e3
AIXX
8.2. Top Marking Explanation
Table 17. Top Marking Explanations
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)
S = Speed Grade
(See Ordering Guide for more
information).
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by Assembly Contractor. Corresponds to the
year and workweek of the mold date.
R = Product (OPN) Revision
F = Wafer Fab
Circle = 1.1 mm Diameter
Left-Justified
“e3” Pb-Free Symbol
First Two Characters of the Manufacturing Code
A = Assembly Site
I = Internal Code
Last Four Characters of the Manufacturing Code
XX = Serial Lot Number
28
Rev. 1.5
Si8410/20/21
Revision 1.2 to Revision 1.3
DOCUMENT CHANGE LIST
Revision 0.11 to Revision 0.21
Updated " Features" on page 1.
Moved Tables 1 and 2 to page 4.
Updated Tables 6, 7, 8, and 9.
Updated Table 12 footnotes.
Rev 0.21 is the first revision of this document that
applies to the new series of ultra low power isolators
featuring pinout and functional compatibility with
previous isolator products.
Added Figure 13, “Si84xx Time-Dependent
Dielectric Breakdown,” on page 22.
Updated “1. Electrical Specifications”.
Updated “5. Ordering Guide”.
Revision 1.3 to Revision 1.4
Added “8. Top Marking: 8-Pin Narrow Body SOIC”.
Updated "2.4.1. Supply Bypass" on page 20.
Added Figure 6, “Recommended Bypass
Components for the Si84xx Digital Isolator Family,”
on page 20.
Revision 0.21 to Revision 0.22
Updated all specs to reflect latest silicon.
Updated "3.1. Power Supply Bypass Capacitors
(Revision C and Revision D)" on page 23.
Revision 0.22 to Revision 0.23
Updated all specs to reflect latest silicon.
Revision 1.4 to Revision 1.5
Added "3. Errata and Design Migration Guidelines"
on page 23.
Updated "5. Ordering Guide" on page 25 to include
new title note and “ Alternative Part Number (APN)”
column.
Revision 0.23 to Revision 1.0
Updated document to reflect availability of Revision
D silicon.
Updated Tables 3,4, and 5.
Updated all supply currents and channel-channel skew.
Updated Table 2.
Updated absolute maximum supply voltage.
Updated Table 7.
Updated clearance and creepage dimensions.
Updated "3. Errata and Design Migration Guidelines"
on page 23.
Updated "5. Ordering Guide" on page 25.
Revision 1.0 to Revision 1.1
Updated Tables 3, 4, and 5.
Updated notes in tables to reflect output impedance of
85 .
Updated rise and fall time specifications.
Updated CMTI value.
Revision 1.1 to Revision 1.2
Updated document throughout to include MSL
improvements to MSL2A.
Updated "5. Ordering Guide" on page 25.
Updated Note 1 in ordering guide table to reflect
improvement and compliance to MSL2A moisture
sensitivity level.
Rev. 1.5
29
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