SI8413DB-T1-E1 [VISHAY]
MOSFET P-CH 20V 4.8A 2X2 4-MFP;
| 型号： | SI8413DB-T1-E1 |
| 厂家： | 
VISHAY |
| 描述： | MOSFET P-CH 20V 4.8A 2X2 4-MFP 开关 晶体管 |
| 文件： | 总10页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8413DB
Vishay Siliconix
P-Channel 20 V (D-S) MOSFET
FEATURES
TrenchFET® Power MOSFET
PRODUCT SUMMARY
•
MICRO FOOT® Chipscale Packaging
VDS (V)
RDS(on) ()
ID (A)
- 6.5
- 5.7
Qg (Typ.)
•
0.048 at VGS = - 4.5 V
0.063 at VGS = - 2.5 V
Reduces Footprint Area Profile (0.62 mm) and
On-Resistance Per Footprint Area
Material categorization:
- 20
14
•
For definitions of compliance please see
www.vishay.com/doc?99912
MICRO FOOT
Bump Side View
Backside View
APPLICATIONS
3
4
2
S
•
•
•
•
Load Switch
Battery Switch
Charger Switch
PA Switch
D
S
D
G
8413
xxx
G
1
Device Marking: 8413
xxx = Date/Lot Traceability Code
D
Ordering Information: Si8413DB-T1-E1 (Lead (Pb)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted)
A
Parameter
Symbol
5 s
Steady State
- 20
Unit
VDS
Drain-Source Voltage
Gate-Source Voltage
V
VGS
12
TA = 25 °C
TA = 70 °C
- 6.5
- 5.2
- 4.8
- 3.8
Continuous Drain Current (TJ = 150 °C)a
ID
A
IDM
IS
Pulsed Drain Current
- 25
Continuous Source Current (Diode Conduction)a
- 2.5
2.77
1.77
- 1.3
1.47
0.94
TA = 25 °C
TA = 70 °C
Maximum Power Dissipationa
PD
W
TJ, Tstg
Operating Junction and Storage Temperature Range
Package Reflow Conditionsb
- 55 to 150
260
°C
IR/Convection
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
35
Maximum
Unit
t 5 s
45
85
20
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
RthJA
Steady State
Steady State
72
°C/W
RthJF
16
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. Refer to IPC/JEDEC (J-STD-020), no manual or hand soldering.
c. In this document, any reference to case represents the body of the MICRO FOOT device and foot is the bump
Document Number: 72947
S13-1847-Rev. E, 19-Aug-13
For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
1
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8413DB
Vishay Siliconix
SPECIFICATIONS (T = 25 °C, unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VGS(th)
IGSS
VDS = VGS, ID = - 250 µA
Gate Threshold Voltage
- 0.6
- 1.4
100
- 1
V
VDS = 0 V, VGS
=
12 V
Gate-Body Leakage
nA
VDS = - 20 V, VGS = 0 V
DS = - 20 V, VGS = 0 V, TJ = 70 °C
VDS - 5 V, VGS = - 4.5 V
VGS = - 4.5 V, ID = - 1 A
IDSS
ID(on)
Zero Gate Voltage Drain Current
µA
A
V
- 5
On-State Drain Currenta
- 5
0.0393
0.052
7.4
0.048
0.063
Drain-Source On-State Resistancea
RDS(on)
V
GS = - 2.5 V, ID = - 1 A
Forward Transconductancea
Diode Forward Voltagea
Dynamicb
gfs
VDS = - 10 V, ID = - 1 A
IS = - 1 A, VGS = 0 V
S
V
VSD
- 0.8
- 1.1
21
Qg
Qgs
Qgd
Rg
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
14
1.7
5.1
18
V
DS = - 10 V, VGS = - 4.5 V, ID = - 1 A
nC
td(on)
tr
td(off)
tf
31
50
75
50
V
DD = - 10 V, RL = 10
ID - 1 A, VGEN = - 4.5 V, Rg = 6
Turn-Off Delay Time
Fall Time
105
90
160
135
130
ns
trr
IF = - 1 A, dI/dt = 100 A/µs
Source-Drain Reverse Recovery Time
85
Notes:
a. Pulse test; pulse width 300 µs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
25
20
15
10
5
25
20
15
10
5
V
GS
= 5 thru 3 V
2.5 V
2 V
T
= 125 °C
C
25 °C
1.5 V
- 55 °C
2.0
0
0
0
1
2
3
4
5
0.0
0.5
1.0
1.5
2.5
3.0
V
DS
- Drain-to-Source Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
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For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
Document Number: 72947
S13-1847-Rev. E, 19-Aug-13
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8413DB
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2000
1600
1200
800
400
0
0.20
0.16
0.12
0.08
0.04
0.00
C
iss
V
GS
= 2.5 V
V
GS
= 4.5 V
C
oss
C
rss
0
4
8
12
16
20
0
5
10
15
20
25
V
DS
- Drain-to-Source Voltage (V)
I
D
- Drain Current (A)
On-Resistance vs. Drain Current
Capacitance
5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
V
D
= 10 V
V
D
= 4.5 V
DS
= 1 A
GS
= 1 A
I
I
4
3
2
1
0
0
3
6
9
12
15
- 50 - 25
0
25
50
75
100 125 150
Q
- Total Gate Charge (nC)
T - Junction Temperature (°C)
J
g
Gate Charge
On-Resistance vs. Junction Temperature
0.20
0.16
0.12
0.08
0.04
0.00
30
10
T
= 150 °C
J
I
D
= 1 A
T
= 25 °C
J
1
0.0
0
1
2
3
4
5
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
SD
- S o urce-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Document Number: 72947
S13-1847-Rev. E, 19-Aug-13
For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
3
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8413DB
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.4
80
I
D
= 250 µA
0.3
0.2
60
40
20
0.1
0.0
- 0.1
- 0.2
0
- 50 - 25
0
25
50
75
100 125 150
0.001
0.01
0.1
1
10
100
600
T
- Temperature (°C)
Time (s)
J
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
I
Limited
DM
Limited by R
DS(on)*
10
1
P(t) = 0.001
P(t) = 0.01
I
D(on)
Limited
P(t) = 0.1
P(t) = 1
P(t) = 10
DC
T
= 25 °C
A
0.1
Single Pulse
BVDSS Limited
0.01
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V
GS
minimum V at which R
is specified
DS(on)
GS
Safe Operating Area
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
P
DM
0.1
0.05
t
1
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
= 72 °C/W
thJA
(t)
3. T - T = P
JM
Z
A
DM thJA
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
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For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
Document Number: 72947
S13-1847-Rev. E, 19-Aug-13
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8413DB
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 72947
S13-1847-Rev. E, 19-Aug-13
For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
5
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8413DB
Vishay Siliconix
PACKAGE OUTLINE
MICRO FOOT: 4-BUMP (0.8 mm PITCH)
4 x φ 0.30 ∼ 0.31
Note 3
Solder Mask φ
∼
0.40
e
A
A
2
Silicon
A
1
Bump Note 2
b Diamerter
e
S
e
Recommended Land
E
8413
XXX
e
S
D
Mark on Backside of Die
Notes (unless otherwise specified):
1. Laser mark on the silicon die back, coated with a thin metal.
2. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
3. Non-solder mask defined copper landing pad.
4. The flat side of wafers is oriented at the bottom.
Millimetersa
Inches
DIMENSIONS
MIN.
MAX.
0.650
0.290
MIN.
MAX.
0.0256
0.0114
A
0.600
0.260
0.0236
0.0102
A1
A2
0.340
0.370
1.520
1.520
0.360
0.410
1.600
1.600
0.0134
0.0146
0.0598
0.0598
0.0142
0.0161
0.0630
0.0630
b
D
E
e
0.800
0.0315
S
0.360
0.400
0.0142
0.0157
Notes:
a. Use millimeters as the primary measurement.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72947.
www.vishay.com
6
For technical questions, contact: pmostechsupport@vishay.com
This document is subject to change without notice.
Document Number: 72947
S13-1847-Rev. E, 19-Aug-13
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN824
Vishay Siliconix
PCB Design and Assembly Guidelines
For MICRO FOOTr Products
Johnson Zhao
INTRODUCTION
Vishay Siliconix’s MICRO FOOT product family is based on a
wafer-level chip-scale packaging (WL-CSP) technology that
implements a solder bump process to eliminate the need for an
outer package to encase the silicon die. MICRO FOOT
products include power MOSFETs, analog switches, and
power ICs.
For battery powered compact devices, this new packaging
technology reduces board space requirements, improves
thermal performance, and mitigates the parasitic effect typical
of leaded packaged products. For example, the 6−bump
MICRO FOOT Si8902EDB common drain power MOSFET,
which measures just 1.6 mm x 2.4 mm, achieves the same
performance as TSSOP−8 devices in a footprint that is 80%
smaller and with a 50% lower height profile (Figure 1). A
MICRO FOOT analog switch, the 6−bump DG3000DB, offers
low charge injection and 1.4 W on−resistance in a footprint
measuring just 1.08 mm x 1.58 mm (Figure 2).
FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and
Vishay Siliconix MICRO FOOT products can be handled with
the same process techniques used for high-volume assembly
of packaged surface-mount devices. With proper attention to
PCB and stencil design, the device will achieve reliable
performance without underfill. The advantage of the device’s
small footprint and short thermal path make it an ideal option
for space-constrained applications in portable devices such as
battery packs, PDAs, cellular phones, and notebook
computers.
Si8900EDB
3
2
1
0.18 ~ 0.25
A
B
1.08
0.5
This application note discusses the mechanical design and
reliability of MICRO FOOT, and then provides guidelines for
board layout, the assembly process, and the PCB rework
process.
0.285
0.5
0.285
1.58
FIGURE 2. Outline of MICRO FOOT CSP & Analog
Switch DG3000DB
Document Number: 71990
06-Jan-03
www.vishay.com
1
AN824
Vishay Siliconix
TABLE 1
Main Parameters of Solder Bumps in MICRO FOOT Designs
MICRO FOOT CSP
Bump Material
Bump Pitch*
Bump Diameter*
Bump Height*
MICRO FOOT CSP MOSFET
0.8
0.5
0.5
0.37-0.41
0.18-0.25
0.32-0.34
0.26-0.29
0.14-0.19
0.21-0.24
Eutectic Solder:
63Sm/37Pb
MICRO FOOT CSP Analog Switch
MICRO FOOT UCSP Analog Switch
* All measurements in millimeters
MICRO FOOT’S DESIGN AND RELIABILITY
BOARD LAYOUT GUIDELINES
Board materials. Vishay Siliconix MICRO FOOT products are
designed to be reliable on most board types, including organic
boards such as FR-4 or polyamide boards. The package
qualification information is based on the test on 0.5-oz. FR-4
and polyamide boards with NSMD pad design.
As a mechanical, electrical, and thermal connection between
the device and PCB, the solder bumps of MICRO FOOT
products are mounted on the top active surface of the die.
Table 1 shows the main parameters for solder bumps used in
MICRO FOOT products. A silicon nitride passivation layer is
applied to the active area as the last masking process in
fabrication,ensuring that the device passes the pressure pot
test. A green laser is used to mark the backside of the die
without damaging it. Reliability results for MICRO FOOT
products mounted on a FR-4 board without underfill are shown
in Table 2.
Land patterns. Two types of land patterns are used for
surface-mount packages. Solder mask defined (SMD) pads
have a solder mask opening smaller than the metal pad
(Figure 3), whereas on-solder mask defined (NSMD) pads
have a metal pad smaller than the solder-mask opening
(Figure 4).
TABLE 2
MICRO FOOT Reliability Results
NSMD is recommended for copper etch processes, since it
provides a higher level of control compared to SMD etch
processes. A small-size NSMD pad definition provides more
area (both lateral and vertical) for soldering and more room for
escape routing on the PCB. By contrast, SMD pad definition
introduces a stress concentration point near the solder mask
on the PCB side that may result in solder joint cracking under
extreme fatigue conditions.
Test Condition C: −65_ to 150_C
Test condition B: −40_ to 125_C
121_C @ 15PSI 100% Humidity Test
>500 Cycles
>1000 Cycles
96 Hours
The main failure mechanism associated with wafer-level
chip-scale packaging is fatigue of the solder joint. The results
shown in Table 2 demonstrate that a high level of reliability can
be achieved with proper board design and assembly
techniques.
Copper pads should be finished with an organic solderability
preservative
(OSP)
coating.
For
electroplated
nickel-immersion gold finish pads, the gold thickness must be
less than 0.5 mm to avoid solder joint embrittlement.
Solder Mask
Copper
Solder Mask
Copper
FIGURE 3. SMD
FIGURE 4. NSMD
Document Number: 71990
06-Jan-03
www.vishay.com
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AN824
Vishay Siliconix
Board pad design. The landing-pad size for MICRO FOOT
products is determined by the bump pitch as shown in Table 3.
The pad pattern is circular to ensure a symmetric,
barrel-shaped solder bump.
Chip pick-and-placement. MICRO FOOT products can be
picked and placed with standard pick-and-place equipment.
The recommended pick-and-place force is 150 g. Though the
part will self-center during solder reflow, the maximum
placement offset is 0.02 mm.
Reflow Process. MICRO FOOT products can be assembled
using standard SMT reflow processes. Similar to any other
package, the thermal profile at specific board locations must
be determined. Nitrogen purge is recommended during reflow
operation. Figure 6 shows a typical reflow profile.
TABLE 3
Dimensions of Copper Pad and Solder Mask
Opening in PCB and Stencil Aperture
Solder Mask
Opening
Stencil
Aperture
Pitch Copper Pad
0.33 " 0.01 mm
Thermal Profile
0.80 mm 0.30 " 0.01 mm 0.41 " 0.01 mm
0.50 mm 0.17 " 0.01 mm 0.27 " 0.01 mm
in ciircle aperture
250
0.30 " 0.01 mm
in square aperture
200
150
100
50
ASSEMBLY PROCESS
MICRO FOOT products’ surface-mount-assembly operations
include solder paste printing, component placement, and
solder reflow as shown in the process flow chart (Figure 5).
Stencil Design
IIncoming Tape and Reel Inspection
Solder Paste Printing
Chip Placement
0
0
100
200
300
400
Time (Seconds
FIGURE 6. Reflow Profile
Reflow
Solder Joint Inspection
Pack and Ship
PCB REWORK
To replace MICRO FOOT products on PCB, the rework
procedure is much like the rework process for a standard BGA
or CSP, as long as the rework process duplicates the original
reflow profile. The key steps are as follows:
FIGURE 5. SMT Assembly Process Flow
1. Remove the MICRO FOOT device using a convection
nozzle to create localized heating similar to the original
reflow profile. Preheat from the bottom.
Stencil design. Stencil design is the key to ensuring
maximum solder paste deposition without compromising the
assembly yield from solder joint defects (such as bridging and
extraneous solder spheres). The stencil aperture is dependent
on the copper pad size, the solder mask opening, and the
quantity of solder paste.
2. Once the nozzle temperature is +190_C, use tweezers to
remove the part to be replaced.
3. Resurface the pads using a temperature-controlled
soldering iron.
In MICRO FOOT products, the stencil is 0.125-mm (5-mils)
thick. The recommended apertures are shown in Table 3 and
are fabricated by laser cut.
4. Apply gel flux to the pad.
5. Use a vacuum needle pick-up tip to pick up the
replacement part, and use a placement jig to placed it
accurately.
Solder-paste printing. The solder-paste printing process
involves transferring solder paste through pre-defined
apertures via application of pressure.
6. Reflow the part using the same convection nozzle, and
preheat from the bottom, matching the original reflow
profile.
In MICRO FOOT products, the solder paste used is UP78
No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.
Document Number: 71990
06-Jan-03
www.vishay.com
3
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Revision: 02-Oct-12
Document Number: 91000
1
相关型号：
SI8413DB-T1-E3
TRANSISTOR 4800 mA, 20 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, 2 X 2 MM, MICRO FOOT, CSP-4, FET General Purpose Small Signal
VISHAY
SI8417DB-T2-E1
Small Signal Field-Effect Transistor, 0.0097A I(D), 12V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, 2.40 X 2 MM, ROHS COMPLIANT, ULTRA SMALL, MICRO FOOT, 4 PIN
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