SI8441-A-IS_技术文档

Si8440/1/2

QUAD-CHANNEL DIGITAL ISOLATOR

Features

Pin Assignments

ꢀ High-speed operation:

ꢀ 2500 V

isolation

RMS

DC – 150 Mbps

ꢀ Transient Immunity: >25 kV/µs

Wide Body SOIC

ꢀ Low propagation delay:

ꢀ Tri-state outputs with ENABLE

<10 ns

V_DD1

V_DD2

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

control

ꢀ Wide Operating Supply Voltage:

GND2

B1

GND1

A1

ꢀ DC correct

2.375–5.5 V

ꢀ No start-up initialization required

ꢀ <10 µs Startup Time

A2

B2

ꢀ Low power: I1 + I2 <

12 mA/channel at 100 Mbps

B3

A3

A4

ꢀ High temperature operation:

125 °C at 100 Mbps

B4

ꢀ Precise timing:

EN1

EN2

GND2

2 ns pulse width distortion

1 ns channel-channel matching

2 ns pulse width skew

100 °C at 150 Mbps

GND1

ꢀ Wide body SOIC-16 package

Top View

Applications

ꢀ Isolated switch mode supplies ꢀ Motor control

ꢀ Isolated ADC, DAC

ꢀ Power factor correction systems

Safety Regulatory Approvals

ꢀ UL recognition:2500 V

for 1 ꢀ VDE certification conformity

RMS

ꢁ DIN EN 60747-5-2 (VDE0884

Minute per UL1577

Part 2):2003-01

ꢀ CSA component acceptance

ꢁ DIN EN60950(VDE0805):

2001-12;EN60950:2000

ꢁ V_IORM= 560 V_PEAK

notice #5A

ꢀ * All Pending

Description

Silicon Lab's family of digital isolators are CMOS devices that employ

an RF coupler to transmit digital information across an isolation

barrier. Very high speed operation at low power levels is achieved.

These parts are available in a 16-pin wide body SOIC package. Three

speed grade options (1, 10, 100 Mbps) are available and achieve

typical propagation delay of less than 10 ns.

Block Diagram

Si8440

Si8441

Si8442

A1

A2

A3

A4

NC

A1

A2

A1

A2

B1

B2

B1

B2

B1

B2

B3

B4

A3

B3

B4

A3

B3

A4

B4

EN2

EN1

EN2

EN1

EN2

Rev. 0.3 4/06

Si8440/1/2

2

Rev. 0.3

Si8440/1/2

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.3. Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . .17

4.5. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

7. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Rev. 0.3

3

Si8440/1/2

1. Electrical Specifications

Table 1. Electrical Characteristics

(V_DD1= 5 V, V_DD2= 5 V, T_A= –40 to 125 C°)

Parameter

Symbol

Test Condition

Min

2.0

—

Typ

—

Max

—

Unit

V

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Enable Input High Current

Enable Input Low Current

V

IH

V

—

0.8

—

V

IL

V

loh = –4 mA

lol = 4 mA

V

,V

– 0.4

4.8

0.2

—

V

OH

DD1 DD2

V

—

0.4

±10

—

V

OL

I

—

µA

L

I

V

= V

IH

4

ENH

ENx

I

V

= V

IL

20

—

ENL

ENx

DC Supply Current (All inputs 0 V or at Supply)

Si8440-A,-B,-C, V

Si8441-A,-B,-C, V

Si8442-A,-B,-C, V

All inputs 0 DC

All inputs 1 DC

All inputs 0 DC

All inputs 1 DC

All inputs 0 DC

All inputs 1 DC

—

7.5

7

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

15

6.5

8.7

11

14

12.5

10

13

10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)

Si8440-B,-C, V

Si8441-B,-C, V

Si8442-B,-C, V

—

11

9

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

12

13.5

12.5

100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)

Si8440-C, V

Si8441-C, V

Si8442-C, V

—

12

27

16

27

21

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

4

Rev. 0.3

Si8440/1/2

Table 1. Electrical Characteristics (Continued)

(V_DD1= 5 V, V_DD2= 5 V, T_A= –40 to 125 C°)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Timing Characteristics

Maximum Data Rate

Minimum Pulse Width

0

—

5

100

—

Mbps

ns

—

1

Propagation Delay

t

, t

7.5

1

—

ns

PHL PLH

Pulse Width Distortion

PWD

—

ns

1

|t

- t

|

PLH PHL

2

Propagation Delay Skew

t

—

25

6

0.5

2

—

ns

PSK

t

PSKCD/OD

3

Channel-Channel Skew

Output Rise Time

Output Fall Time

C1 = 15 pF

ns

2

ns

Common Mode Transient

Immunity at Logic Low Output

CM

30

kV/µs

L

4

Common Mode Transient

Immunity at Logic High Output

CM

25

30

—

kV/µs

H

4

Enable to Data Valid

t

—

5

3

—

ns

µs

en1

Enable to Data Tri-State

en2

5

Start-up Time

t

SU

Notes:

1. t_PHLpropagation delay is measured from the 50% level of the falling edge of the V_Ixsignal to the 50% level of the falling

edge of the V_Oxsignal. t_PLHpropagation delay is measured from the 50% level of the rising edge of the V_Ixsignal to the

50% level of the rising edge of the V_Oxsignal.

2. t_PSKis the magnitude of the worst-case difference in t_PHLor t_PLHthat is measured between units at the same operating

temperature, supply voltages, and output load within the recommended operating conditions.

3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any

two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is

the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of

the isolation barrier.

4. CM_His the maximum common-mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V_DD2. CM_Lis

the maximum common-mode voltage slew rate that can be sustained while maintaining V_O< 0.8 V. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range

over which the common mode is slewed.

5. Start-up time is the time period from the application of power to valid data at the output.

INPUT

(V_IX

50%

ENABLE

)

t_PLH

t_PHL

OUTPUTS

OUTPUT

(V_OX

50%

)

t_en1

t_en2

Figure 1. ENABLE Timing Diagram

Figure 2. Propagation Delay Timing

Rev. 0.3

5

Si8440/1/2

Table 2. Electrical Characteristics

(V_DD1= 3.3 V, V_DD2= 3.3 V, T_A= –40 to 125 C°)

Parameter

Symbol

Test Condition

Min

2.0

—

Typ

—

Max

—

Unit

V

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Enable Input High Current

Enable Input Low Current

V

IH

V

—

0.8

—

V

IL

V

loh = –4 mA

lol = 4 mA

V

,V

– 0.4

3.1

0.2

—

V

OH

DD1 DD2

V

—

0.4

±10

—

V

OL

I

—

µA

L

I

V

= V

IH

4

ENH

ENx

I

V

= V

IL

20

—

ENL

ENx

DC Supply Current (All inputs 0 V or at supply)

Si8440-A,-B,-C, V

Si8441-A,-B,-C, V

Si8442-A,-B,-C, V

All inputs 0 DC

All inputs 1 DC

All inputs 0 DC

All inputs 1 DC

All inputs 0 DC

All inputs 1 DC

—

7.3

6.5

14.3

6

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

8.3

10.8

13.3

11.8

9

12

10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)

Si8440-B,-C, V

Si8441-B,-C, V

Si8442-B,-C, V

—

11

8

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

11.4

14.5

11.5

100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)

Si8440-C, V

Si8441-C, V

Si8442-C, V

—

11.4

18

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

12.5

21

17.5

6

Rev. 0.3

Si8440/1/2

Table 2. Electrical Characteristics (Continued)

(V_DD1= 3.3 V, V_DD2= 3.3 V, T_A= –40 to 125 C°)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Timing Characteristics

Maximum Data Rate

Minimum Pulse Width

0

—

5

100

—

Mbps

ns

—

1

Propagation Delay

t

,t

7.5

1

—

ns

PHL PLH

Pulse Width Distortion

PWD

—

ns

1

|t

- t

|

PLH PHL

2

Propagation Delay Skew

t

—

25

8

1

—

ns

PSK

t

PSKCD/OD

3

Channel-Channel Skew

Output Rise Time

Output Fall Time

C1 = 15 pF

2

ns

2

ns

Common Mode Transient

Immunity at Logic Low Output

CM

30

kV/µs

L

4

Common Mode Transient

Immunity at Logic High Output

CM

25

30

—

kV/µs

H

4

Enable to Data Valid

t

—

5

3

—

ns

µs

en1

en2

Enable to Data Tri-State

5

Start-up Time

t

SU

Notes:

1. t_PHLpropagation delay is measured from the 50% level of the falling edge of the V_Ixsignal to the 50% level of the falling

edge of the V_Oxsignal. t_PLHpropagation delay is measured from the 50% level of the rising edge of the V_Ixsignal to the

50% level of the rising edge of the V_Oxsignal.

2. t_PSKis the magnitude of the worst-case difference in t_PHLor t_PLHthat is measured between units at the same operating

temperature, supply voltages, and output load within the recommended operating conditions.

3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any

two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is

the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of

the isolation barrier.

4. CM_His the maximum common-mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V_DD2. CM_Lis

the maximum common-mode voltage slew rate that can be sustained while maintaining V_O< 0.8 V. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range

over which the common mode is slewed.

5. Start-up time is the time period from the application of power to valid data at the output.

Rev. 0.3

7

Si8440/1/2

Table 3. Electrical Characteristics

(V_DD1= 2.5 V, V_DD2= 2.5 V, T_A= –40 to 100 C°)

Parameter

Symbol

Test Condition

Min

2.0

—

Typ

—

Max

—

Unit

V

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Enable Input High Current

Enable Input Low Current

V

IH

V

—

0.8

—

V

IL

V

loh = –4 mA

lol = 4 mA

V

,V

– 0.4

2.3

0.2

—

V

OH

DD1 DD2

V

—

0.4

±10

—

V

OL

I

—

µA

L

I

V

= V

IH

4

ENH

ENx

I

V

= V

IL

20

—

ENL

ENx

DC Supply Current (All inputs 0 V or at supply)

Si8440-A,-B,-C, V

Si8441-A,-B,-C, V

Si8442-A,-B,-C, V

All inputs 0 DC

All inputs 1 DC

All inputs 0 DC

All inputs 1 DC

All inputs 0 DC

All inputs 1 DC

—

6.8

6.3

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

DD1

DD2

12.5

5.8

7.8

9.8

12.5

11

8.8

8.5

11.5

10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)

Si8440-B,-C, V

Si8441-B,-C, V

Si8442-B,-C, V

—

10.2

7

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

10.5

11.5

11

100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)

Si8440-C, V

Si8441-C, V

Si8442-C, V

—

10.8

14.5

12.5

17

—

mA

DD1

DD2

DD1

DD2

DD1

DD2

15

8

Rev. 0.3

Si8440/1/2

Table 3. Electrical Characteristics (Continued)

(V_DD1= 2.5 V, V_DD2= 2.5 V, T_A= –40 to 100 C°)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Timing Characteristics

Maximum Data Rate

Minimum Pulse Width

0

—

5

100

—

Mbps

ns

—

1

Propagation Delay

t

,t

12

1.5

—

ns

PHL PLH

Pulse Width Distortion

PWD

—

ns

1

|t

- t

|

PLH PHL

2

Propagation Delay Skew

t

—

25

10

1

—

ns

PSK

t

PSKCD/OD

3

Channel-Channel Skew

Output Rise Time

Output Fall Time

C1 = 15 pF

2

ns

2

ns

Common Mode Transient

Immunity at Logic Low Output

CM

30

kV/µs

L

4

Common Mode Transient

Immunity at Logic High Output

CM

25

30

—

kV/µs

H

4

Enable to Data Valid

t

—

5

3

—

ns

µs

en1

Enable to Data Tri-State

en2

5

Start-up Time

t

SU

Notes:

1. t_PHLpropagation delay is measured from the 50% level of the falling edge of the V_Ixsignal to the 50% level of the falling

edge of the V_Oxsignal. t_PLHpropagation delay is measured from the 50% level of the rising edge of the V_Ixsignal to the

50% level of the rising edge of the V_Oxsignal.

2. t_PSKis the magnitude of the worst-case difference in t_PHLor t_PLHthat is measured between units at the same operating

temperature, supply voltages, and output load within the recommended operating conditions.

3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any

two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is

the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of

the isolation barrier.

4. CM_His the maximum common-mode voltage slew rate that can be sustained while maintaining V_O> 0.8 V_DD2. CM_Lis

the maximum common-mode voltage slew rate that can be sustained while maintaining V_O< 0.8 V. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range

over which the common mode is slewed.

5. Start-up time is the time period from the application of power to valid data at the output.

Rev. 0.3

9

Si8440/1/2

Table 4. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min

–40

Typ

25

—

Max

125

100

5.5

Unit

ºC

V

Ambient Operating Temperature*

T

100 Mbps, 15 pF, 5 V

150 Mbps, 15 pF, 5 V

A

0

Supply Voltage

V

2.375

DD1

DD2

V

—

5.5

V

*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,

and supply voltage.

Table 5. Absolute Maximum Ratings

Parameter

Symbol

Min

–65

–40

–0.5

—

Typ

—

Max

150

125

6

Unit

ºC

V

Storage Temperature

Ambient Temperature Under Bias

Supply Voltage

T

STG

T

A

V

, V

DD2

DD1

Input Voltage

V

+ 0.5

V

I

DD

Output Voltage

V

+ 0.5

V

O

Output Current Drive Channel

Lead Solder Temperature (10s)

Maximum Isolation Voltage

L

10

mA

ºC

—

260

—

4000

V

DC

Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Table 6. Package Characteristics

Parameter

Symbol

Test Condition

Min

—

Typ

Max Unit

1

12

Resistance (Input-Output)

R

10

—

Ω

pF

IO

1

Capacitance (Input-Output)

C

f = 1 MHz

—

1.4

4.0

33

IO

2

Input Capacitance

C

—

pF

I

IC Junction-to-Case Thermal Resistance,

Side 1

θ

Thermocouple

located at center of

package underside

—

ºC/W

JCI

IC Junction-to-Case Thermal Resistance,

Side 2

θ

—

28

—

ºC/W

JCO

Notes:

1. Device considered a 2-terminal device; Pins 1– 8 shorted together and pins 9–16 shorted together.

2. Input capacitance is from any input data pin to ground.

10

Rev. 0.3

Si8440/1/2

Table 7. Regulatory Information

The Si84xx have been approved by the organizations listed below.

1

2

CSA

UL

VDE

Recognized under 1577 component Approved under CSA Component

Certified according to DIN EN

1

recognition program

Acceptance Notice #5A

60747-5-2 (VDE 0884 Part 2): 2003-

2

01

Basic insulation, 2500 V RMS

isolation voltage

Reinforced insulation per CSA

60950-1-03 and IEC 60950-1, 400 V

RMS maximum working voltage

Basic insulation, 560 V peak

Complies with DIN EN 60747-5-2

(VDE 0884 Part 2): 2003-01, DIN EN

60950 (VDE 0805): 2001-12; EN

60950:2000 Reinforced insulation,

560 V peak

File E257455

File 2500035643

File 5006301-4880-0001

Notes:

1. In accordance with UL1577, each Si84xx is proof tested by applying an insulation test voltage > 3000 V RMS for 1

second (current leakage detection limit = 5 µA).

2. In accordance with DIN EN 60747-5-2, each Si84xx is proof tested by applying an insulation test voltage > 1050 V

peak for 1 second (partial discharge detection limit = 5 pC). A “*” mark branded on the component designates DIN EN

60747-5-2 approval.

Table 8. Insulation and Safety-related Specifications

Parameter

Symbol

Test Condition

Value

Unit

Rated Dielectric Insulation Voltage

Minimum External Air Gap (Clearance)

1 minute duration

2500

V

RMS

L(IO1) Measured from input terminals to out- 7.7 min

put terminals, shortest distance

through air

mm

Minimum External Tracking (Creepage)

Minimum Internal Gap (Internal Clearance)

L(IO2) Measured from input terminals to out-

put terminals, shortest distance path

along body

8.1

mm

Insulation distance through insulation

0.017

min

mm

V

Tracking Resistance (Comparative Tracking

Index)

CTI

DIN IEC 112/VDE 0303 Part 1

>175

Basic Isolation Group

Material Group

IIIa

(DIN VDE 0110, 1/89, Table 1)

Rev. 0.3

11

Si8440/1/2

Table 9. DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics^1,2

Description

Symbol

Characteristic

Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltages < 150 V

For Rated Mains Voltages < 300 V

For Rated Mains Voltages < 400 V

I-IV

I-III

I-II

RMS

Climatic Classification

40/125/21

2

Pollution Degree (DIN VDE 0110, Table 1)

Maximum Working Insulation Voltage

Input to Output Test Voltage, Method b1

V

560

V

IORM

PEAK

V

1050

V

PR

(V

x 1.875 = V , 100% Production Test, t = 1 sec, Partial Dis-

IORM

PR m

charge < 5 pC)

Input to Output Test Voltage, Method a

After Environmental Tests Subgroup 1

V

(V

x 1.6 = V , t = 60 sec, Partial Discharge < 5 pC)

896

V

PR

TR

IORM

PR

m

PEAK

After Input and/or Safety Test Subgroup 2/3

(V x 1.2 = V , t = 60 sec, Partial Discharge < 5 pC)

672

V

IORM

PR

m

PEAK

Highest Allowable Overvoltage (Transient Overvoltage, t = 10 sec)

V

4000

TR

Safety-Limiting Values (Maximum value allowed in the event of a failure;

also see the thermal derating curve, Figure 3)

Case Temperature

Side 1 Current

Side 2 Current

T

I

150

265

335

ºC

mA

S

S1

S2

9

Insulation Resistance at T , V = 500 V

R

S

>10

Ω

S

IO

Notes:

1. This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is

ensured by protective circuits.

2. The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage.

350

300

250

SIDE #2

200

150

SIDE #1

100

50

0

50

100

150

200

Case Temperature (ºC)

Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Temperature per DIN EN 60747-5-2

12

Rev. 0.3

Si8440/1/2

2. Typical Performance Characteristics

15

20

18

16

14

12

10

13

5V

11

3.3V

2.5V

3.3V

9

7

2.5V

5

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

Data Rate (Mbps)

Figure 4. Si8440 Typical V_DD1Supply Current

vs. Data Rate 5, 3.3, and 2.5 V Operation

Figure 6. Si8441 Typical V_DD1Supply Current

vs. Data Rate 5, 3.3, and 2.5 V Operation

30

5V

25

3.3V

20

15

2.5V

10

5

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

Data Rate (Mbps)

Figure 5. Si8440 Typical V_DD2Supply Current

vs. Data Rate 5, 3.3, and 2.5 V Operation

(15 pF Load)

Figure 7. Si8441 Typical V_DD2Supply Current

vs. Data Rate 5, 3.3, and 2.5 V Operation

(15 pF Load)

30

25

5V

20

3.3V

15

2.5V

10

5

0

10

20

30

40

50

60

70

80

90

100

Data Rate (Mbps)

Figure 8. Si8442 Typical V_DD1or V_DD2Supply

Current vs. Data Rate 5, 3.3, and 2.5 V

Operation (15 pF Load)

Rev. 0.3

13

Si8440/1/2

10

9

8

Falling Edge

7

6

5

Rising Edge

-40

-20

0

20

40

60

80

100

120

Temperature (Degrees C)

Figure 9. Propagation Delay

vs. Temperature 5 V Operation

10

9

Rising Edge

8

Falling Edge

7

6

5

-40

-20

0

20

40

60

80

100

120

Temperature (Degrees C)

Figure 10. Propagation Delay

vs. Temperature 3.3 V Operation

15

13

11

9

Rising Edge

Falling Edge

7

5

-40

-20

0

20

40

60

80

100

120

Temperature (Degrees C)

Figure 11. Propagation Delay

vs. Temperature 2.5 V Operation

14

Rev. 0.3

Si8440/1/2

3. Application Information

3.1. Theory of Operation

The operation of an Si8440 channel is analogous to that of an opto coupler, except an RF carrier is modulated

instead of light. This simple architecture provides a robust isolated data path and requires no special

considerations or initialization at start-up. A simplified block diagram for a single Si8440 channel is shown in

Figure 12. A channel consists of an RF transmitter and receiver separated by a transformer.

Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying and

applies the resulting waveform to the primary of the transformer. The receiver contains a demodulator that decodes

the input state according to its RF energy content and applies the result to output B via the output driver.

3.2. Eye Diagram

Figure 13 illustrates an eye-diagram taken on an Si8440-IS. The test used an Anritsu (MP1763C) Pulse Pattern

Generator for the data source. The output of the generator's clock and data from an Si8440-IS were captured on an

oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The

results also show that very low pulse width distortion and very little jitter were exhibited.

TRANSMITTER

RF

OSCILLATOR

RECEIVER

MODULATOR

DEMODULATOR

A

B

Figure 12. Simplified Channel Diagram

Figure 13. Eye Diagram

Rev. 0.3

15

Si8440/1/2

4.1. Supply Bypass

4. Layout Recommendations

The Si8440 requires a 0.1 µF bypass capacitor between

Dielectric isolation is a set of specifications produced by

the safety regulatory agencies from around the world

that describes the physical construction of electrical

equipment that derives power from a high-voltage

V

and GND1 and V

and GND2. The capacitor

DD1

DD2

should be placed as close as possible to the package.

4.2. Input and Output Characteristics

power system such as 100–240 V

systems or

AC

The Si8440 inputs and outputs are standard CMOS

drivers/receivers.

industrial power systems. The dielectric test (or HIPOT

test) given in the safety specifications places a very high

voltage between the input power pins of a product and

the user circuits and the user touchable surfaces of the

product. For the IEC relating to products deriving their

power from the 220–240 V power grids, the test voltage

4.3. Enable Inputs

The receiver output drivers are enabled when the

Enable input is high and the drivers remain in a high-

impedance state when Enable is low. The Enable input

can be used for multiplexing or as a clock sync input.

Supply currents remain at their nominal values when

Enable is low. The Enable inputs must be tied to a logic

level.

is 2500 V

(or 3750 V —the peak equivalent

AC

DC

voltage).

There are two terms described in the safety

specifications:

ꢀ Creepage—the distance along the insulating surface

an arc may travel.

ꢀ Clearance—the distance through the shortest path

through air that an arc may travel.

Figure 14 illustrates the accepted method of providing

the proper creepage distance along the surface. For a

220–240 V application, this distance is 8 mm and the

wide body SOIC package must be used. There must be

no copper traces within this 8 mm exclusion area, and

the surface should have a conformal coating such as

solder resist. The digital isolator chip must straddle this

exclusion area.

Figure 14. Creepage Distance

16

Rev. 0.3

Si8440/1/2

4.4. RF Immunity and Common Mode Transient Immunity

The Si8440 family has very high common mode transient immunity while transmitting data. This is typically

measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements

show no failures up to 30 kV/µs. During a high surge event the output may glitch low for up to 20–30 ns, but the

output corrects immediately after the surge event.

The Si844x family passes the industrial requirements of CISPR24 for RF immunity of 3 V/m using an unshielded

evaluation board. As shown in Figure 15, the isolated ground planes form a parasitic dipole antenna, while

Figure 16 shows the RMS common mode voltage versus frequency above which the Si844x becomes susceptible

to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage below the

envelope specified in Figure 16. The PCB should be laid-out to not act as an efficient antenna for the RF frequency

of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or

otherwise shielded.

GND1

GND2

Isolator

Dipole

Antenna

Figure 15. Dipole Antenna

5

4

3

2

1

0

500

1000

Frequency (MHz)

1500

2000

Figure 16. RMS Common Mode Voltage vs. Frequency

Rev. 0.3

17

Si8440/1/2

4.5. RF Radiated Emissions

The Si8440 family uses a RF carrier frequency of approximately 2.1 GHz. This will result in a small amount of

radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but due to a small

amount of RF energy driving the isolated ground planes which can act as a dipole antenna.

The unshielded Si8440 evaluation board passes FCC requirements. Table 10 shows measured emissions

compared to FCC requirements.

Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less

efficient antenna.

Table 10. Radiated Emissions

Compared

Frequency Measured

FCC Spec

(dBµV/m)

to Spec

(dB)

(GHz)

(dBµV/m)

2.094

2.168

4.210

4.337

6.315

6.505

8.672

70.0

68.3

61.9

60.7

58.3

60.7

45.6

74.0

–4.0

–5.7

–12.1

–13.3

–15.7

–13.3

–28.4

18

Rev. 0.3

Si8440/1/2

5. Pin Descriptions

V_DD1

V_DD2

GND2

B1

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

GND1

A1

A2

B2

B3

A3

A4

B4

EN1

EN2

GND2

GND1

Top View

Wide Body SOIC

Name

SOIC-16 Pin#

Type

Description

V

1

2

Supply

Ground

Side 1 power supply.

Side 1 ground.

DD1

GND1

A1

3

Digital Input

Digital I/O

Digital Input

Ground

Side 1 digital input.

Side 1 digital input or output.

A2

4

A3

5

A4

6

EN1

GND1

GND2

EN2

B4

7

Side 1 active high enable. NC on Si8440.

Side 1 ground.

8

9

Ground

Side 2 ground.

10

11

12

13

14

15

16

Digital Input

Digital I/O

Side 2 active high enable.

Side 2 digital input or output.

B3

B2

Digital Output Side 2 digital output.

B1

GND2

Ground

Supply

Side 2 ground.

V

Side 2 power supply.

DD2

Rev. 0.3

19

Si8440/1/2

6. Ordering Guide

Ordering Part

Number

Number of

Number of Inputs MaximumData

Temperature

Package

Type

Inputs V

V

Side

Rate

DD1

DD2

Side

Si8440-A-IS

Si8440-B-IS

Si8440-C-IS

Si8441-A-IS

Si8441-B-IS

Si8441-C-IS

Si8442-A-IS

Si8442-B-IS

Si8442-C-IS

4

3

2

0

1

10

100

1

–40 to 125 °C

SOIC-16

0

1

2

10

100

1

10

100

Note: All packages are Pb-free and RoHS compliant. Moisture sensitivity level is MSL2 with peak reflow temperature of

260 °C according to the JEDEC industry standard classifications, and peak solder temperature.

20

Rev. 0.3

Si8440/1/2

7. Package Outline: Wide Body SOIC

Figure 17 illustrates the package details for the Quad-Channel Digital Isolator. Table 14 lists the values for the

dimensions shown in the illustration.

Figure 17. 16-Pin Wide Body SOIC

Table 14. Package Diagram Dimensions

Millimeters

Symbol

Min

—

Max

2.65

0.3

A

A1

D

E

E1

b

0.1

10.3 BSC

7.5 BSC

0.31

0.51

0.33

c

0.20

e

1.27 BSC

h

0.25

0.4

0°

0.75

1.27

7°

L

θ

Rev. 0.3

21

Si8440/1/2

DOCUMENT CHANGE LIST

Revision 0.2 to Revision 0.3

ꢀ Added enable high and low typical current

specifications to Tables 1, 2, and 3.

ꢀ Added startup time specifications (with note 5) to

Tables 1, 2, and 3.

ꢀ Rewrote paragraph 1 in section "4.4. RF Immunity

and Common Mode Transient Immunity" on page 17

to reflect 30 kV/µs transient immunity capability.

22

Rev. 0.3

Si8440/1/2

NOTES:

Rev. 0.3

23

Si8440/1/2

CONTACT INFORMATION

Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: MCUinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

24

Rev. 0.3


型号：	SI8441-A-IS
厂家：	SILICON
描述：	QUAD-CHANNEL DIGITAL ISOLATOR 四通道数字隔离器
文件：	总24页 (文件大小：593K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI8441-A-IS [SILICON]

相关型号：

SI8441-A-ISR

SI8441-B-IS

SI8441-B-ISR

SI8441-C-IS

SI8441-C-ISR

SI8441AA-C-IS1

SI8441AA-C-IS1R

SI8441AA-D-IS1

SI8441AA-D-IS1R

SI8441AB-C-IS

SI8441AB-C-IS1

SI8441AB-C-ISR