SI8441AB-C-IS [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16;
| 型号： | SI8441AB-C-IS |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16 光电二极管 接口集成电路 |
| 文件： | 总36页 (文件大小：829K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8440/41/42/45
LOW-POWER QUAD-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
DC to 150 Mbps
Up to 2500 V
isolation
RMS
60-year life at rated working
No start-up initialization required
voltage
Wide Operating Supply Voltage:
Precise timing (typical)
2.70–5.5 V
<10 ns worst case
Wide Operating Supply Voltage:
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
Transient Immunity 25 kV/µs
2.70–5.5V
Ultra low power (typical)
5 V Operation:
< 1.6 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
2.70 V Operation:
AEC-Q100 qualified
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS-compliant packages
< 1.4 mA per channel at 1 Mbps
< 4 mA per channel at 100 Mbps
High electromagnetic immunity
SOIC-16 wide body
SOIC-16 narrow body
Applications
Industrial automation systems
Hybrid electric vehicles
Isolated ADC, DAC
Motor control
Ordering Information:
Isolated switch mode supplies
Power inverters
See page 26.
Communications systems
Safety Regulatory Approvals
UL 1577 recognized
VDE certification conformity
Up to 2500 VRMS for 1 minute
IEC 60747-5-2
(VDE0884 Part 2)
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in 16-pin wide- and
narrow-body SOIC packages.
Rev. 1.7 4/18
Copyright © 2018 by Silicon Laboratories
Si8440/41/42/45
Si8440/41/42/45
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1. Enable Pin Causes Outputs to Go Low (Revision C Only) . . . . . . . . . . . . . . . . . . . .24
3.2. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . .24
3.3. Latch Up Immunity (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.1. 16-Pin Wide Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Rev. 1.7
2
Si8440/41/42/45
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
Test Condition
Min
–40
Typ
25
—
Max
125
5.5
Unit
ºC
V
T
150 Mbps, 15 pF, 5 V
A
V
2.70
2.70
DD1
DD2
V
—
5.5
V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
—
Max
150
125
5.75
6.0
Unit
°C
°C
V
2
Storage Temperature
T
STG
Ambient Temperature Under Bias
T
A
3
Supply Voltage (Revision C)
V
V
, V
, V
DD1
DD1
DD2
DD2
3
Supply Voltage (Revision D)
V
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s)
Notes:
I
10
mA
°C
O
—
260
—
3600
V
RMS
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum ratings for extended periods may degrade performance.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "5. Ordering Guide" on page 26 for more information.
Rev. 1.7
3
Si8440/41/42/45
Table 3. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
—
µA
L
1
Output Impedance
Z
85
O
Enable Input High Current
Enable Input Low Current
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at Supply)
Si8440Ax, Bx and Si8445Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.5
2.5
5.7
2.6
2.3
3.8
8.6
3.9
mA
mA
mA
DD1
DD2
DD1
DD2
Si8441Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.8
2.5
4.9
3.6
2.7
3.8
7.4
5.4
DD1
DD2
DD1
DD2
Si8442Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.3
4.5
4.5
3.5
3.5
6.8
6.8
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8440Ax, Bx and Si8445Bx
V
V
—
—
3.6
3.0
5.4
3.9
mA
mA
mA
DD1
DD2
Si8441Ax, Bx
V
V
—
—
3.5
3.4
5.3
5.1
DD1
DD2
Si8442Ax, Bx
V
V
—
—
3.6
3.6
5.4
5.4
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.7
Si8440/41/42/45
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
3.6
4.0
5.4
5.6
mA
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
3.7
4.1
5.5
5.7
DD1
DD2
Si8442Bx
V
V
—
—
4.2
4.2
5.9
5.9
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
V
V
—
—
3.8
19.4
5.7
24.3
mA
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
8.0
15.8
10
19.8
DD1
DD2
Si8442Bx
V
V
—
—
11.8
11.8
14.8
14.8
DD1
DD2
Timing Characteristics
Si844xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1.0
250
35
Mbps
ns
—
—
—
t
, t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.7
5
Si8440/41/42/45
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si844xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
6.0
9.5
2.5
Mbps
ns
—
3.0
—
t
, t
See Figure 2
See Figure 2
6.0
1.5
ns
PHL PLH
Pulse Width Distortion
PWD
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
—
3.8
2.8
25
5.0
3.7
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
Immunity
CMTI
V = V or 0 V
kV/µs
I
DD
3
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
5.0
7.0
15
8.0
9.2
40
ns
ns
µs
en1
en2
3
Enable to Data Tri-State
3,4
Start-up Time
t
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.7
Si8440/41/42/45
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 2. Propagation Delay Timing
Rev. 1.7
7
Si8440/41/42/45
Table 4. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
—
µA
L
1
Output Impedance
Z
85
O
Enable Input High Current
Enable Input Low Current
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8440Ax, Bx and Si8445Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.5
2.5
5.7
2.6
2.3
3.8
8.6
3.9
mA
mA
mA
DD1
DD2
DD1
DD2
Si8441Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.8
2.5
4.9
3.6
2.7
3.8
7.4
5.4
DD1
DD2
DD1
DD2
Si8442Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.3
4.5
4.5
3.5
3.5
6.8
6.8
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8440Ax, Bx and Si8445Bx
V
V
—
—
3.6
3.0
5.4
3.9
mA
mA
mA
DD1
DD2
Si8441Ax, Bx
V
V
—
—
3.5
3.4
5.3
5.1
DD1
DD2
Si8442Ax, Bx
V
V
—
—
3.6
3.6
5.4
5.4
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.7
Si8440/41/42/45
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
3.6
4.0
5.4
5.6
mA
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
3.7
4.1
5.5
5.7
DD1
DD2
Si8442Bx
V
V
—
—
4.2
4.2
5.9
5.9
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
V
V
—
—
3.6
14
5.5
17.5
mA
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
6.4
11.4
8.0
14.5
DD1
DD2
Si8442Bx
V
V
—
—
8.6
8.6
10.8
10.8
DD1
DD2
Timing Characteristics
Si844xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1.0
250
35
Mbps
ns
—
—
—
t
,t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.7
9
Si8440/41/42/45
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si844xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
6.0
9.5
2.5
Mbps
ns
—
3.0
—
t
, t
See Figure 2
See Figure 2
6.0
1.5
ns
PHL PLH
Pulse Width Distortion
PWD
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
—
4.3
3.0
25
6.1
4.3
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
Immunity
CMTI
V = V or 0 V
kV/µs
I
DD
3
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
5.0
7.0
15
8.0
9.2
40
ns
ns
µs
en1
3
Enable to Data Tri-State
en2
3,4
Start-up Time
t
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.7
Si8440/41/42/45
Table 5. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.
2.3
V
OH
DD1 DD2
4
Low Level Output Voltage
Input Leakage Current
V
—
—
—
—
—
0.2
—
0.4
±10
—
V
OL
I
µA
L
2
Output Impedance
Z
85
O
Enable Input High Current
Enable Input Low Current
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8440Ax, Bx and Si8445Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.5
2.5
5.7
2.6
2.3
3.8
8.6
3.9
mA
mA
mA
DD1
DD2
DD1
DD2
Si8441Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.8
2.5
4.9
3.6
2.7
3.8
7.4
5.4
DD1
DD2
DD1
DD2
Si8442Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.3
4.5
4.5
3.5
3.5
6.8
6.8
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8440Ax, Bx and Si8445Bx
V
V
—
—
3.6
3.0
5.4
3.9
mA
mA
mA
DD1
DD2
Si8441Ax, Bx
V
V
—
—
3.5
3.4
5.3
5.1
DD1
DD2
Si8442Ax, Bx
V
V
—
—
3.6
3.6
5.4
5.4
DD1
DD2
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.7
11
Si8440/41/42/45
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
3.6
4.0
5.4
5.6
mA
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
3.7
4.1
5.5
5.7
DD1
DD2
Si8442Bx
V
V
—
—
4.2
4.2
5.9
5.9
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
V
V
—
—
3.6
10.8
5.5
13.5
mA
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
5.6
9.3
7.0
11.6
DD1
DD2
Si8442Bx
V
V
—
—
7.2
7.2
9.0
9.0
DD1
DD2
Timing Characteristics
Si844xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1.0
250
35
Mbps
ns
—
—
—
t
,t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
3
Propagation Delay Skew
Channel-Channel Skew
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.7
Si8440/41/42/45
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si844xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
6.0
9.5
2.5
Mbps
ns
—
3.0
—
t
, t
See Figure 2
See Figure 2
6.0
1.5
ns
PHL PLH
Pulse Width Distortion
PWD
ns
|t
- t
|
PLH PHL
3
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
—
4.8
3.2
25
6.5
4.6
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
Immunity
CMTI
V = V or 0 V
kV/µs
I
DD
4
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
5.0
7.0
15
8.0
9.2
40
ns
ns
µs
en1
en2
4
Enable to Data Tri-State
4,5
Start-up Time
t
SU
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 24 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.7
13
Si8440/41/42/45
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
RMS
RMS
RMS
60950-1: Up to 130 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 V
for basic insulation working voltage.
peak
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 V isolation voltage for basic insulation.
RMS
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 26.
Table 7. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
Unit
WB
NB
SOIC-16 SOIC-16
1
L(IO1)
L(IO2)
8.0
8.0
4.9
4.01
0.008
mm
mm
mm
Nominal Air Gap (Clearance)
1
Nominal External Tracking (Creepage)
0.008
Minimum Internal Gap (Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
600
V
RMS
0.040
0.019
mm
Erosion Depth
12
12
2
R
10
10
Resistance (Input-Output)
IO
2
C
2.0
4.0
2.0
4.0
pF
pF
Capacitance (Input-Output)
IO
3
C
Input Capacitance
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “6. Package Outline:
16-Pin Wide Body SOIC” and “8. Package Outline: 16-Pin Narrow Body SOIC”. VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-16 package and 8.5 mm minimum for the WB SOIC-16 package.
UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance
and creepage limits as 3.9 mm minimum for the NB SOIC-16 package and 7.6 mm minimum for the WB SOIC-16
package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
14
Rev. 1.7
Si8440/41/42/45
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Condition
Specification
Basic Isolation Group
Material Group
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
RMS
RMS
RMS
RMS
Installation Classification
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Symbol
Test Condition
Characteristic Unit
V
560
V peak
V peak
Maximum Working Insulation Voltage
Input to Output Test Voltage
IORM
Method b1
(V
x 1.875 = V , 100%
IORM
PR
V
1050
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
V
t = 60 sec
4000
2
V peak
Transient Overvoltage
IOTM
Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at T , V = 500 V
9
R
>10
S
S
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Max
Parameter
Symbol
Test Condition
Min Typ
Unit
WB
NB
SOIC-16 SOIC-16
T
—
—
—
—
150
220
150
210
°C
Case Temperature
S
= 100 °C/W (WB SOIC-16),
105 °C/W (NB SOIC-16),
JA
Safety input, output, or
supply current
I
mA
S
V = 5.5 V, T = 150 °C, T = 25 °C
I
J
A
Device Power Dissipa-
tion
P
—
—
275
275
mW
2
D
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3 and 4.
2. The Si844x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.7
15
Si8440/41/42/45
Table 11. Thermal Characteristics
Typ
Parameter
Symbol
Test Condition
Min
Max
Unit
WB
NB
SOIC-16 SOIC-16
IC Junction-to-Air Thermal
Resistance
—
100 105
—
ºC/W
JA
500
450
V
DD1, VDD2 = 2.70 V
400
300
200
100
0
370
220
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
500
430
V
DD1, VDD2 = 2.70 V
400
300
200
100
0
360
VDD1, VDD2 = 3.6 V
210
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 4. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Rev. 1.7
Si8440/41/42/45
2. Functional Description
2.1. Theory of Operation
The operation of an Si844x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si844x channel is shown in
Figure 5.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 5. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 6 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 6. Modulation Scheme
Rev. 1.7
17
Si8440/41/42/45
2.2. Eye Diagram
Figure 7 illustrates an eye-diagram taken on an Si8440. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8440 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 7. Eye Diagram
18
Rev. 1.7
Si8440/41/42/45
2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an
overview of the output states when the Enable pins are active.
Table 12. Si84xx Logic Operation Table
V
EN
VDDI
VDDO
I
1,2
Comments
V Output
O
1,2,3,4
1,5,6
1,5,6
1,2
Input
State
State
Input
H
L
H or NC
H or NC
L
P
P
P
P
P
P
H
L
Enabled, normal operation.
7
8
X
Hi-Z or L
Disabled.
Upon transition of VDDI from unpowered to pow-
7
X
H or NC
L
UP
UP
P
P
L
ered, V returns to the same state as V in less
O
I
than 1 µs.
7
8
X
Hi-Z or L
Disabled.
Upon transition of VDDO from unpowered to pow-
ered, V returns to the same state as V within
1 µs, if EN is in either the H or NC state. Upon
transition of VDDO from unpowered to powered,
O
I
7
7
X
X
P
UP
Undetermined
V returns to Hi-Z within 1 µs if EN is L.
O
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si84xx is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on Si8440/45. No Connect replaces EN2 on the Si8445. No Connects are not internally
connected and can be left floating, tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V.
6. "Unpowered" state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
(EN = 0) in Revision C. Revision D outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 24 for more details.
Rev. 1.7
19
Si8440/41/42/45
Table 13. Enable Input Truth Table1
Operation
1,2
1,2
P/N
EN1
EN2
H
L
Si8440
—
—
H
L
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Outputs B1, B2, B3, B4 are disabled and Logic Low or in high impedance state.
Output A4 enabled and follows the input state.
3
Si8441
Si8442
Si8445
X
3
X
Output A4 disabled and Logic Low or in high impedance state.
X
H
L
Outputs B1, B2, B3 are enabled and follow the input state.
3
X
Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state.
H
L
X
Outputs A3 and A4 are enabled and follow the input state.
3
X
Outputs A3 and A4 are disabled and Logic Low or in high impedance state.
X
H
L
Outputs B1 and B2 are enabled and follow the input state.
3
X
Outputs B1 and B2 are disabled and Logic Low or in high impedance state.
—
—
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic
operation is summarized for each isolator product in Table 13. These inputs are internally pulled-up to local VDD by a
3 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize
noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is
recommended they be connected to an external logic level, especially if the Si84xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
(EN = 0) in Revision C. Revision D outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 24 for more details.
20
Rev. 1.7
Si8440/41/42/45
2.4. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 14 and Table 7 on page 14 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.)
requirements before starting any design that uses a digital isolator.
The following sections detail the recommended bypass and decoupling components necessary to ensure robust
overall performance and reliability for systems using the Si84xx digital isolators.
2.4.1. Supply Bypass
Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically
quiet environments. However, digital isolators are commonly used in hazardous environments with excessively
noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass
capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as
close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is
recommended that the designer add 50 to 100 resistors in series with the VDD supply voltage source and 50 to
300 resistors in series with the digital inputs/outputs (see Figure 8). For more details, see "3. Errata and Design
Migration Guidelines" on page 24.
All components upstream or downstream of the isolator should be properly decoupled as well. If these components
are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing
damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300 resistors protect
the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are
exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended
Operating Conditions,” on page 3.
2.4.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
2.4.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in
mind the recommendations described in “2.4.1. Supply Bypass” above.
V Source 2
R2 (50 – 100 )
V Source 1
R1 (50 – 100 )
C1
VDD1
A1
VDD2
B1
C4
50 – 300
50 – 300
0.1 F
0.1 F
C2
C3
Input/Output
Input/Output
1 F
1 F
Ax
Bx
50 – 300
50 – 300
GND1
GND2
Figure 8. Recommended Bypass Components for the Si84xx Digital Isolator Family
Rev. 1.7
21
Si8440/41/42/45
2.5. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 3, 4, and 5 for actual specification limits.
30
25
20
15
10
5
30
25
20
15
10
5
5V
3.3V
5V
3.3V
2.70V
2.70V
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 12. Si8440/45 Typical VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Figure 9. Si8440/45 Typical VDD1 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation
30
30
25
5V
25
20
15
10
5
5V
20
3.3V
15
3.3V
10
2.70V
5
0
2.70V
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 13. Si8441 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 10. Si8441 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
30
25
10
Falling Edge
9
8
7
6
5
20
15
10
5
5V
3.3V
Rising Edge
2.70V
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
-40
-20
0
20
40
60
80
100
120
Data Rate (Mbps)
Temperature (Degrees C)
Figure 14. Propagation Delay vs. Temperature
Figure 11. Si8442 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Rev. 1.7
22
Si8440/41/42/45
Figure 15. Si84xx Time-Dependent Dielectric Breakdown
Rev. 1.7
23
Si8440/41/42/45
3. Errata and Design Migration Guidelines
The following errata apply to Revision C devices only. See "5. Ordering Guide" on page 26 for more details. No
errata exist for Revision D devices.
3.1. Enable Pin Causes Outputs to Go Low (Revision C Only)
When using the enable pin (EN1, EN2) function on the 4-channel (Si8440/1/2) isolators, the corresponding output
pin states (pin = An, Bn, where n can be 1…4) are driven to a logic low (to ground) when the enable pin is disabled
(EN1 or EN2 = 0). This functionality is different from the legacy 4-channel (Si8440/1/2) isolators. On those devices,
the isolator outputs go into a high-impedance state (Hi-Z) when the enable pin is disabled (EN1 = 0 or EN2 = 0).
3.1.1. Resolution
The enable pin functionality causing the outputs to go low is supported in production for Revision C of the Si844x
devices. Revision D corrects the enable pin functionality (i.e., the outputs will go into the high-impedance state to
match the legacy isolator products). Refer to the Ordering Guide sections of the data sheet(s) for current ordering
information.
3.2. Power Supply Bypass Capacitors (Revision C and Revision D)
When using the Si844x isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on
both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V
supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins
(VDD1, VDD2) of the isolator device.
3.2.1. Resolution
For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 21. Additionally, refer to "5.
Ordering Guide" on page 26 for current ordering information.
3.3. Latch Up Immunity (Revision C Only)
Latch up immunity generally exceeds ± 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latch-up
immunity. To increase latch-up immunity on these pins, 100 of equivalent resistance must be included in series
with all of the pins listed in Table 14. The 100 equivalent resistance can be comprised of the source driver's
output resistance and a series termination resistor. The Si8441 is not affected when using power supply voltages
(VDD1 and VDD2) < 3.5 V.
3.3.1. Resolution
This issue has been corrected with Revision D of the device. Refer to “5. Ordering Guide” for current ordering
information.
Table 14. Affected Ordering Part Numbers (Revision C Only)
Device
Affected Ordering Part Numbers*
Pin#
Name
Pin Type
Revision
6
A4
EN2
B1
Input or Output
Input
SI8440SV-C-IS/IS1, SI8441SV-C-IS/IS1,
SI8442SV-C-IS/IS1
C
10
14
6
Output
A4
Input
SI8445SV-C-IS/IS1
C
14
B1
Output
*Note: SV = Speed Grade/Isolation Rating (AA, AB, BA, BB).
24
Rev. 1.7
Si8440/41/42/45
4. Pin Descriptions
VDD1
VDD1
VDD2
GND2
B1
VDD1
VDD2
GND2
B1
VDD2
GND2
B1
GND1
GND1
GND1
I
I
s
o
l
I
s
o
l
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
s
o
l
A1
A2
A1
A2
A1
A2
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B2
B2
B2
a
t
i
o
n
a
t
i
o
n
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
RCVR
RF
RCVR
RF
RF
XMITR
A3
A4
B3
A3
A4
B3
A3
A4
B3
XMITR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B4
B4
B4
EN2/NC
EN2
EN2
NC
EN1
GND1
EN1
GND1
GND2
GND2
GND1
GND2
Si8440/45
Si8441
Si8442
1
Name
SOIC-16 Pin#
Type
Description
V
1
2
Supply
Side 1 power supply.
Side 1 ground.
DD1
GND1
A1
Ground
3
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital Input
Ground
Side 1 digital input.
A2
4
Side 1 digital input.
A3
5
Side 1 digital input or output.
Side 1 digital input or output.
A4
6
2
2
EN1/NC
GND1
GND2
EN2/NC
B4
7
Side 1 active high enable. NC on Si8440/45.
Side 1 ground.
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Input
Digital I/O
Digital I/O
Side 2 active high enable. NC on Si8445.
Side 2 digital input or output.
Side 2 digital input or output.
B3
B2
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B1
GND2
Ground
Supply
Side 2 ground.
V
Side 2 power supply.
DD2
Notes:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15
must also be connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
Rev. 1.7
25
Si8440/41/42/45
5. Ordering Guide
These devices are not recommended for new designs. Please see the Si864x datasheet for replacement options.
Table 15. Ordering Guide for Valid OPNs1
Ordering Part
Number
Alternative Part Number of
Number of
Maximum
Isolation Package Type
Rating
Number
(APN)
Inputs VDD1 Inputs VDD2 Data Rate
(OPN)
Side
Side
(Mbps)
2
Revision D Devices
Si8440AA-D-IS1 Si8640AB-B-IS1
Si8440BA-D-IS1 Si8640BB-B-IS1
Si8441AA-D-IS1 Si8641AB-B-IS1
Si8441BA-D-IS1 Si8641BB-B-IS1
Si8442AA-D-IS1 Si8642AB-B-IS1
Si8442BA-D-IS1 Si8642BB-B-IS1
Si8445BA-D-IS1 Si8645BB-B-IS1
4
4
3
3
2
2
4
4
4
3
3
2
2
4
4
4
3
3
2
2
4
0
0
1
1
2
2
0
0
0
1
1
2
2
0
0
0
1
1
2
2
0
1
150
1
1
150
1
1 kVrms
NB SOIC-16
150
150
1
Si8440AB-D-IS
Si8440BB-D-IS
Si8441AB-D-IS
Si8441BB-D-IS
Si8442AB-D-IS
Si8442BB-D-IS
Si8445BB-D-IS
Si8640AB-B-IS
Si8640BB-B-IS
Si8641AB-B-IS
Si8641BB-B-IS
Si8642AB-B-IS
Si8642BB-B-IS
Si8645BB-B-IS
150
1
1,3
150
1
2.5 kVrms WB SOIC-16
150
150
1
Si8440AB-D-IS1 Si8640AB-B-IS1
Si8440BB-D-IS1 Si8640BB-B-IS1
Si8441AB-D-IS1 Si8641AB-B-IS1
Si8441BB-D-IS1 Si8641BB-B-IS1
Si8442AB-D-IS1 Si8642AB-B-IS1
Si8442BB-D-IS1 Si8642BB-B-IS1
Si8445BB-D-IS1 Si8645BB-B-IS1
150
1
1
150
1
2.5 kVrms NB SOIC-16
150
150
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
2. Revision C and Revision D devices are supported for existing designs.
3. AEC-Q100 qualified.
26
Rev. 1.7
Si8440/41/42/45
Table 15. Ordering Guide for Valid OPNs1 (Continued)
Ordering Part
Number
Alternative Part Number of
Number of
Maximum
Isolation Package Type
Rating
Number
(APN)
Inputs VDD1 Inputs VDD2 Data Rate
(OPN)
Side
Side
(Mbps)
2
Revision C Devices
Si8440AA-C-IS1 Si8640AB-B-IS1
Si8440BA-C-IS1 Si8640BB-B-IS1
Si8441AA-C-IS1 Si8641AB-B-IS1
Si8441BA-C-IS1 Si8641BB-B-IS1
Si8442AA-C-IS1 Si8642AB-B-IS1
Si8442BA-C-IS1 Si8642BB-B-IS1
Si8445BA-C-IS1 Si8645BB-B-IS1
4
4
3
3
2
2
4
4
4
3
3
2
2
4
4
4
3
3
2
2
4
0
0
1
1
2
2
0
0
0
1
1
2
2
0
0
0
1
1
2
2
0
1
150
1
1
150
1
1 kVrms
NB SOIC-16
150
150
1
Si8440AB-C-IS
Si8440BB-C-IS
Si8441AB-C-IS
Si8441BB-C-IS
Si8442AB-C-IS
Si8442BB-C-IS
Si8445BB-C-IS
Si8640AB-B-IS
Si8640BB-B-IS
Si8641AB-B-IS
Si8641BB-B-IS
Si8642AB-B-IS
Si8642BB-B-IS
Si8645BB-B-IS
150
1
1
150
1
2.5 kVrms WB SOIC-16
150
150
1
Si8440AB-C-IS1 Si8640AB-B-IS1
Si8440BB-C-IS1 Si8640BB-B-IS1
Si8441AB-C-IS1 Si8641AB-B-IS1
Si8441BB-C-IS1 Si8641BB-B-IS1
Si8442AB-C-IS1 Si8642AB-B-IS1
Si8442BB-C-IS1 Si8642BB-B-IS1
Si8445BB-C-IS1 Si8645BB-B-IS1
150
1
1
150
1
2.5 kVrms NB SOIC-16
150
150
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
2. Revision C and Revision D devices are supported for existing designs.
3. AEC-Q100 qualified.
Rev. 1.7
27
Si8440/41/42/45
6. Package Outline: 16-Pin Wide Body SOIC
Figure 16 illustrates the package details for the Si844x Digital Isolator. Table 16 lists the values for the dimensions
shown in the illustration.
Figure 16. 16-Pin Wide Body SOIC
Table 16. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.51
0.33
c
0.20
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
28
Rev. 1.7
Si8440/41/42/45
7. Land Pattern: 16-Pin Wide-Body SOIC
Figure 17 illustrates the recommended land pattern details for the Si844x in a 16-pin wide-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 17. 16-Pin SOIC Land Pattern
Table 17. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.7
29
Si8440/41/42/45
8. Package Outline: 16-Pin Narrow Body SOIC
Figure 18 illustrates the package details for the Si844x in a 16-pin narrow-body SOIC (SO-16). Table 18 lists the
values for the dimensions shown in the illustration.
Figure 18. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 18. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
0.25 BSC
30
Rev. 1.7
Si8440/41/42/45
Table 18. Package Diagram Dimensions (Continued)
Dimension
Min
0.25
0°
Max
0.50
8°
h
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation
AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.7
31
Si8440/41/42/45
9. Land Pattern: 16-Pin Narrow Body SOIC
Figure 19 illustrates the recommended land pattern details for the Si844x in a 16-pin narrow-body SOIC. Table 19
lists the values for the dimensions shown in the illustration.
Figure 19. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 19. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
32
Rev. 1.7
Si8440/41/42/45
10. Top Marking: 16-Pin Wide Body SOIC
10.1. 16-Pin Wide Body SOIC Top Marking
Si84XYSV
YYWWTTTTTT
e3
TW
10.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)*
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
(See Ordering Guide for more
information).
A = 1 kV; B = 2.5 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by Assembly House. Corresponds to the year
and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing Code from Assembly House
“e3” Pb-Free Symbol
Circle = 1.5 mm Diameter
(Center-Justified)
Country of Origin ISO Code
Abbreviation
TW = Taiwan
*Note: Si8445 has 0 reverse channels.
Rev. 1.7
33
Si8440/41/42/45
11. Top Marking: 16-Pin Narrow Body SOIC
11.1. 16-Pin Narrow Body SOIC Top Marking
Si84XYSV
YYWWTTTTTT
e3
11.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)*
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV
(See Ordering Guide for more
information).
Line 2 Marking:
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
TTTTTT = Mfg code
Manufacturing Code from Assembly Purchase Order
form.
Circle = 1.2 mm diameter
“e3” Pb-Free Symbol.
*Note: Si8445 has 0 reverse channels.
34
Rev. 1.7
Si8440/41/42/45
Revision 1.0 to Revision 1.1
DOCUMENT CHANGE LIST
Revision 0.62 to Revision 0.63
Updated Tables 3, 4, and 5.
Updated notes in both tables to reflect output
impedance of 85 .
Updated rise and fall time specifications.
Rev 0.63 is the first revision of this document that
applies to the new series of ultra low power isolators
featuring pinout and functional compatibility with
previous isolator products.
Updated CMTI value.
Revision 1.1 to Revision 1.2
Updated “1. Electrical Specifications”.
Updated “5. Ordering Guide”.
Updated document throughout to include MSL
improvements to MSL2A.
Added “10. Top Marking: 16-Pin Wide Body SOIC”.
Updated "5. Ordering Guide" on page 26.
Revision 0.63 to Revision 0.64
Updated Note 1 in ordering guide table to reflect
improvement and compliance to MSL2A moisture
sensitivity level.
Updated all specs to reflect latest silicon.
Revision 0.64 to Revision 0.65
Revision 1.2 to Revision 1.3
Updated all specs to reflect latest silicon.
Updated " Features" on page 1.
Moved Tables 1 and 2 to page 3.
Updated Tables 6, 7, 8, and 9.
Updated Table 12 footnotes.
Added "3. Errata and Design Migration Guidelines"
on page 24.
Added "11. Top Marking: 16-Pin Narrow Body SOIC"
on page 34.
Added Figure 15, “Si84xx Time-Dependent
Revision 0.65 to Revision 1.0
Dielectric Breakdown,” on page 23.
Updated document to reflect availability of Revision
Revision 1.3 to Revision 1.4
D silicon.
Updated "2.4.1. Supply Bypass" on page 21.
Updated Tables 3,4, and 5.
Updated all supply currents and channel-channel skew.
Updated Table 2.
Updated absolute maximum supply voltage.
Updated Table 7.
Added Figure 8, “Recommended Bypass
Components for the Si84xx Digital Isolator Family,”
on page 21.
Updated "3.2. Power Supply Bypass Capacitors
(Revision C and Revision D)" on page 24.
Updated clearance and creepage dimensions.
Updated Table 12.
Revision 1.4 to Revision 1.5
Updated Note 7.
Updated "5. Ordering Guide" on page 26 to include
Updated Table 13.
MSL2A.
Updated Note 3.
Revision 1.5 to Revision 1.6
Updated "3. Errata and Design Migration Guidelines"
on page 24.
Updated "5. Ordering Guide" on page 26 to include
new title note and “ Alternative Part Number (APN)”
column.
Updated "5. Ordering Guide" on page 26.
Revision 1.6 to Revision 1.7
Deleted references to MSL ratings throughout
document to eliminate redundancy and maintain
compliance with corporate data sheet format
requirements. The MSL ratings are specified in the
Qualification Report for the product.
35
Rev. 1.7
Smart.
Connected.
Energy-Friendly.
Products
www.silabs.com/products
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
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