SI8512-C-IS [SILICON]
Analog Circuit, 1 Func, PDSO20, ROHS COMPLIANT, MS-013AC, SOIC-20;
| 型号： | SI8512-C-IS |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, PDSO20, ROHS COMPLIANT, MS-013AC, SOIC-20 光电二极管 |
| 文件： | 总36页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si85xx
Si85XX UNIDIRECTIONAL AC CURRENT SENSORS
Features
Single-chip ac current sensor
50 kHz to 1 MHz input frequency
range
FAULT output to safeguard operation
Low loss: <1.3 m primary series
resistance and <2 nH inductance
Leading-edge noise suppression
eliminates need for leading-edge
blanking
"Ping-Pong" output version allows
one Si85xx to replace two current
transformers in full-bridge designs
5, 10, and 20 A full-scale versions
±5% initial accuracy
Large 2 V min output at full scale
PP
High-side or low-side current sensing
Compact 4x4x1 mm QFN package
(1 kV
isolation)
RMS
20-pin wide-body SOIC
(5 kV isolation)
RMS
–40 to 125 °C operating range
UL/VDE/CSA approval
Applications
Power supplies
Motor controls
Lighting equipment
Industrial equipment
Ordering Information:
Description
See page 26.
The Si85xx products are unidirectional ac current sensors available in full-scale
ranges of 5, 10, and 20 A. Si85xx products are ideal upgrades for older current-
sensing technologies offering size, performance, and cost advantages over current
transformers, Hall effect devices, DCR circuits, and other approaches. The Si85xx
are extremely low-loss, adding less than 1.3 m of series resistance and less than
2 nH series inductance in the sensing path at 25 °C. Current-sensing terminals are
Pin Assignments:
See page 24
20-Pin SOIC
isolated from the other package pins, providing up to 5 kV
safety approval ratings.
isolation level per
RMS
VDD
IIN
MODE
R1
IIN
Safety Approval (20-Pin SOIC Only)
IIN
R2
IIN
UL 1577 recognized
5000 V for 1 minute
CSA component notice 5A approval
IEC 60950, 61010, 60601
approved
VDE certification conformity
IEC 60747-5-2 (VDE0884 Part 2)
R3
IIN
Si851x
RMS
R4
OUT1
IOUT
IOUT
IOUT
IOUT
IOUT
OUT2
TRST/FAULT
GND
Functional Block Diagram
12-Pin QFN
Si851x
R1
R2
R3
R4
IIN
VDD
Si851x
R1
R2
VIN
IIN
MODE
VDD1 TRST
R2
RESET LOGIC
MODE LOGIC
IIN
R3
Si850x
GND1
OUT
GND2
R4
OUT1
OUT2
INTEGRATOR
SIGNAL CONDITIONING
R1
IOUT
OUT1
OUT2
IOUT
Q1
L
PH1
VOUT
C
Q2
PH2
AUTO CALIBRATION
LOGIC
TEMP
SENSOR
ADC
Typical Application
IOUT
GND
TRST/FAULT
VDD
Patents pending
Preliminary Rev. 0.4 6/12
Copyright © 2012 by Silicon Laboratories
Si85xx
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si85xx
2
Preliminary Rev. 0.4
Si85xx
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.3. Integrator Reset and Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.4. Total Measurement Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.5. Effect of Temperature on Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.6. Leading Edge Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.7. FAULT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.8. Safe Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1. Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. Layout Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3. Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4. Single-Phase Buck Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5. Full-Bridge Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.6. Push-Pull Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Pin Descriptions—12-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Pin Descriptions—20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Package Outline—12-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Recommended PCB Land Pattern (12-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10. Recommended PCB Land Pattern (20-Pin SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11. Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
12. Top Marking (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Preliminary Rev. 0.4
3
Si85xx
1. Electrical Specifications
Table 1. Electrical Specifications
TA = –40 to +125 ºC (typical specified at 25 ºC), VDD = 3 V (±10%) to 5 V (±10%), f = 400 kHz, unless specified
Parameter
Conditions
Min
2.7
—
Typ
—
4
Max
5.5
7
Unit
V
Supply Voltage (V
)
DD
Supply Current
Fully enabled,
mA
input frequency = 1 MHz
Undervoltage Lockout (V
)
2.1
—
2.3
2.5
—
V
UVLO
Undervoltage Lockout Hysteresis
(V
100
mV
)
HYST
Logic Input HIGH Level
Logic Input LOW Level
MODE, R1, R2, R3, R4 inputs
(TTL compatible)
2.0
—
—
—
—
0.8
—
V
V
Reset Time (t )
Time for 5% initial accuracy
150
15
—
—
ns
k
ns
ns
µs
m
nH
ns
R
1
Reset Time Resistor Range
—
2500
30
R1, R2, R3, R4 Input Rise Time (t
)
—
RR
R1, R2, R3, R4 Input Fall Time (t
)
—
—
30
FR
Measurement Watchdog Timeout (t
Series Input Resistance
Series Inductance
)
30
—
50
1.3
2
80
WD
Measured from IIN to IOUT
Measured from IIN to IOUT
—
—
—
1
Input/Output Delay
OUT, OUT1, OUT2 delay relative to
input
—
150
200
1
Start-Up Self-Cal Delay (t
)
Time from VDD = V
+ V to
HYST
—
150
200
µs
CAL
UVLO
cal complete
4x4 mm QFN
SOIC-20
Input Common Mode Voltage Range
(dc)
1000
5000
50
—
—
—
—
V
RMS
RMS
1
V
1
Operating Input Frequency Range (f)
DC Power Supply Rejection Ratio
Sensitivity @ VDD = 3 V
—
1000
—
kHz
db
—
40
Si8501/11/17
Si8502/12/18
Si8503/13/19
Si8501/11/17
Si8502/12/18
Si8503/13/19
—
404
202
101
392
196
98
—
mV/A
mV/A
mV/A
mV/A
mV/A
mV/A
—
—
—
—
Sensitivity @ VDD = 5 V
—
—
—
—
—
—
Notes:
1. Guaranteed by design and/or characterization.
2. Maximum output load is not recommended to exceed 200 pF and 5 k.
3. Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.
4. See "2.4. Total Measurement Error" on page 11 for more information.
4
Preliminary Rev. 0.4
Si85xx
Table 1. Electrical Specifications (Continued)
TA = –40 to +125 ºC (typical specified at 25 ºC), VDD = 3 V (±10%) to 5 V (±10%), f = 400 kHz, unless specified
Parameter
Conditions
Current flow from I to I
Min
Typ
Max
Unit
OUT, OUT1, OUT2 Offset Voltage
= 0
OUT
—
50
—
mV
IN
(V
)
OUTMIN
1,2
V
Slew Rate
OUT, OUT1, OUT2 load = 5K || 50 pF
—
20
50
—
—
—
—
V/µs
OUT
OUT, OUT1, OUT2 Output Resistance
130
+30
+10
3,4
Total Measurement Error (%)
(–40 to 125 ºC Temp Range)
20% of full scale (all devices)
–30
–10
%
3,4
100% of full scale
%
Notes:
1. Guaranteed by design and/or characterization.
2. Maximum output load is not recommended to exceed 200 pF and 5 k.
3. Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.
4. See "2.4. Total Measurement Error" on page 11 for more information.
Table 2. Regulatory Information1 (SOIC-20 Only)
CSA
The Si85xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
2
VDE
The Si85xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si85xx is certified under UL1577 component recognition program. For more details, see File E257455.
Notes:
1. All 5.0 kVRMS rated devices are production tested to >6.0 kVRMS for 1 sec. For more information, see "6. Ordering
Guide" on page 26.
2. Pending.
Preliminary Rev. 0.4
5
Si85xx
Table 3. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
SOIC-20
7.6 min
7.6 min
0.2
Unit
Minimum Air Gap (Clearance)
L(1O1)
L(1O2)
mm
mm
mm
Minimum External Tracking (Creepage)
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
DIN IEC 60112/VDE 0303 Part 1
f = 1 MHz
>175
V
1
12
Resistance (Input-Output)
R
10
IO
1
Capacitance (Input-Output)
C
1.4
4.0
pF
pF
IO
2
Input Capacitance
C
I
Notes:
1. To determine resistance and capacitance, the Si85xx is converted into a 2-terminal device. Pins 1–10 are shorted
together to form the first terminal and pins 11–20 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
2. Measured from input pin to ground.
Table 4. IEC 60664-1 (VDE 0884 Part 2) Ratings
Parameter
Test Conditions
Specification
SOIC-20
IIIa
Basic Isolation Group
Material Group
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
RMS
RMS
RMS
RMS
I-IV
I-IV
Installation Classification
I-IV
Rated Mains Voltages < 1000 V
I-III
RMS
6
Preliminary Rev. 0.4
Si85xx
Table 5. IEC 60747-5-2 Insulation Characteristics*
Parameter
Symbol
Test Condition
Characteristic
Unit
SOIC-20
1414
Maximum Working Insulation Voltage
Input to Output Test Voltage
V
V peak
V peak
IORM
V
Method b1
2652
PR
(V
x 1.875 = V , 100%
IORM
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
Transient Overvoltage
V
t = 60 s
8000
2
V peak
W
IOTM
Pollution Degree
(DIN VDE 0110, Table 1)
9
Insulation Resistance at T , V = 500 V
R
S
>10
S
IO
Note: The Si85xx is suitable for basic and reinforced electrical isolation only within the safety limit data. Maintenance of the
safety data is ensured by protective circuits. The Si85xx provides a climate classification of 40/125/21. Note that the
Si85xx is compliant with the IEC60747-5-2 but neither certified nor inspected to IEC60747-5-2. The Si85xx is
compliant, certified, and factory-inspected to IEC60950.
Table 6. IEC Safety Limiting Values1
Parameter
Symbol
Test Condition
SOIC-20 Unit
Case Temperature
Safety Input Current
T
I
150
30
°C
A
S
= 85, V = 5.5 V,
S
JA
DD
IIN to IOUT = 20 A,
T = 150 °C, T = 25 °C
J
A
2
Device Power Dissipation
P
0.9
W
D
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 1.
2. The Si85xx is tested with VDD = 5.5 V, TJ = 150 ºC, CL = 15 pF, and with an input current from IIN to IOUT equal to
20 Amps at 500 kHz (duty cycle = 50%).
Preliminary Rev. 0.4
7
Si85xx
Table 7. Thermal Characteristics
Parameter
Symbol
Test Condition
SOIC-20 4x4 mm
QFN
Unit
IC Junction-to-Air Thermal Resistance
85
55
°C/W
JA
40
30
20
10
VDD = 5.5 V
IIN to IOUT = 20 Amps
0
0
50
100
150
200
Case Temperature (ºC)
Figure 1. SOIC-20 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 8. Absolute Maximum Ratings1
Parameter
Storage temperature
Symbol
Min
–65
–40
—
Typ
—
Max
+150
Units
°C
°C
°C
V
T
STG
Ambient temperature under bias
Junction Temperature
Supply voltage
T
—
+125
A
T
—
150
J
V
—
—
5.75
DD
Voltage on any pin with respect to ground
(not including IIN, IOUT)
V
–0.5
—
VDD + 0.5
V
IN
Output Current Drive
L
—
—
—
—
—
—
—
—
—
10
mA
ºC
O
Lead solder temperature (10 s)
Maximum Input Current Rate of Change
Maximum Peak AC Input Current Limit
260
—
1000
200
A/µs
A
—
2
Thermal Limit (DC Current)
—
30
A
Maximum Isolation Voltage (QFN)
—
1400
6000
+1.5
+2500
+ 250
V
V
RMS
Maximum Isolation Voltage (SOIC-20)
—
RMS
ESD (CDM)
ESD (HBM)
ESD (MM)
Notes:
JEDEC (JESD22-C101C)
JEDEC (JESD22-A114E)
JEDEC (JESD22-A115A)
–1.5
–2500
–250
kV
V
V
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Refer to “AN329: Extending the Full-Scale Range of the Si85xx” for more information.
8
Preliminary Rev. 0.4
Si85xx
2. Functional Overview
The Si85xx ac current sensor family of products mimics
the functionality of traditional current transformer (CT)
circuits with burden resistor, diode, and output filter, but
offers enhanced performance and added capabilities.
These devices use inductive current sensing and on-
board signal conditioning electronics to generate a 2 V
full-scale output signal proportional to the ac current
flowing from the IIN to the IOUT terminals. As shown in
Figures 2 and 3, current flowing through the metal
package slug induces a signal in the pickup coil on the
Si85xx die. This signal is applied to the input of an
integrator that reconstructs the ac current flowing from
IIN to IOUT. Onboard circuitry provides cycle-by-cycle
integrator reset and temperature and offset voltage
compensation to achieve initial measurement accuracy
to within ±5%.
R1
R2
R3
R4
IIN
Si851x
MODE
RESET LOGIC
MODE LOGIC
OUT1
OUT2
INTEGRATOR
SIGNAL CONDITIONING
PICKUP
COIL
AUTO CALIBRATION
LOGIC
TEMP
SENSOR
ADC
IOUT
GND
TRST/FAULT
VDD
Figure 3. Si851x (Ping Pong Output) Block
Diagram
The Si85xx is superior to other current sensing
approaches and benefits the system in a number of
ways:
R1
R2
IIN
Si850x
Small size: With its 4x4 mm footprint and 1 mm
height (QFN package option), the Si85xx is among
the smallest current sensors available.
VDD2
OUT
RESET LOGIC
INTEGRATOR
SIGNAL CONDITIONING
Large output signal: The nominal 2.0 V full-scale
output swing offers superior noise immunity versus
other current sensing technologies.
PICKUP
COIL
Low loss: The Si85xx adds only 1.3 m (at 25 °C)
to the sensing path, making it one of the lowest-loss
current sensors available. Low 2 nH primary series
inductance is 2,000 times lower compared to a CT
and results in significantly less ringing.
AUTO CALIBRATION
LOGIC
TEMP
SENSOR
ADC
NC
High precision: All versions are available with an
initial maximum error of ±5% of reading; one of the
most accurate current sensors available.
IOUT
GND1
GND2
GND3
TRST
VDD1
Figure 2. Si850x (Single Output) Block Diagram
Ping-Pong output mode (Si851x): Alternately
routes the current measurements from each side of
a full-bridge circuit to separate output pins for
comparison, which is very useful for transformer flux
balancing applications. Eliminates a second CT in a
full-bridge application.
Leading edge noise suppression: Filters out
reflected noise due to long reverse recovery time of
output rectifier. Eliminates the need for external
leading edge blanking circuit.
High common-mode voltage: The Si85xx offers a
minimum of 1,000 V
(for QFN package) or
RMS
5 kV
(for SOIC package) of common-mode
RMS
voltage range (or isolation), making it useful over a
very wide voltage range.
Preliminary Rev. 0.4
9
Si85xx
FAULT output (Si8517/8/9): Goes low when
2.3. Integrator Reset and
Current Measurement
external reset timing is in error.
Ease-of-use: Other than conventional power and
grounding techniques, no special board layout
considerations are required. Built-in timing interface
circuits allow already-available system switching
signals to be used for reset with no external circuits
required.
The Si85xx measures current flowing from the IIN to
IOUT terminals. Current is allowed to flow in the
opposite direction, but will not be measured (OUT1 and
OUT 2 remain at their minimum values during reverse
current flow. Reverse current flow will not damage the
Si85xx).
2.1. Under Voltage Lockout (UVLO)
To achieve the specified accuracy, the integrator
capacitor must be discharged (reset) for time period t
R
UVLO is provided to prevent erroneous operation during
device start-up and shutdown or when VDD is
significantly below the specified operating range. The
prior to the start of every measurement cycle. This
cycle-by-cycle reset is implemented by connecting
existing system gate control signals to the R1–R4 inputs
in a way that resets the integrator when no current is
flowing from IIN to IOUT. To achieve rated accuracy, the
reset cycle must be completed prior to the start of the
measurement cycle. For maximum flexibility, integrator
reset operation can be configured in one of two ways:
Si85xx is in UVLO state when VDD < V
(Figure 4).
UVLO
During UVLO, the output(s) are held at minimum value
regardless of the amount of current flowing from IIN to
IOUT, and signals on integrator reset inputs R1–R4 are
ignored. The Si85xx exits UVLO when VDD > (V
+
UVLO
V
).
HYST
Option 1: The start and duration of reset is
determined by the states of the timing
signals applied to R1–R4.
2.2. Device Startup
Upon exit from UVLO, the Si85xx performs a voltage
offset and temperature self-calibration cycle. During this Option 2: The timing signals applied to R1–R4 trigger
time, output(s) are held at minimum value and reset
inputs (R1-R4) are ignored. The reset inputs are
enabled at the end of the self-calibration cycle, and an
integrator reset cycle is initiated on the first occurrence
of active signals on R1–R4. A current measurement is
initiated immediately after the completion of the
integrator reset cycle, and the resulting current
waveforms appear on the output pins. This "reset-
measure-reset" pattern repeats throughout steady-state
operation.
the start of reset, and the duration of the
reset is determined by an onboard
programmable reset timer.
VUVLO + VHYST
VDD
First Positive Edge
Following End of Self-Cal
SUPPLY
INTEGRATOR
DON’T CARE
tRP
tRP
RESET
Si85xx
STATUS
UNDER VOLTAGE
LOCKOUT STATE
START-UP
SELF-CAL CYCLE
RESET
tR
MEASURE CURRENT
RESET
tR
tCAL
Si85xx
OUTPUT
VOUTMIN
OUT1, OUT2
VALID
Figure 4. Si85xx Startup and Control Timing
10
Preliminary Rev. 0.4
Si85xx
Integrator reset Option 1 is selected by connecting T
2.4. Total Measurement Error
RST
to VDD. In this mode, the Si85xx is held in reset as long
as the signals on R1–R4 satisfy the logic equations of
Table 11. It is typically used in applications where the
gate drivers are external to the system controller IC (the
gate driver delay ensures reset is completed prior to the
start of measurement).
The Si85xx’s absolute accuracy is affected by the
following factors:
Ambient operating temperature
VDD supply voltage
Time
Reset Option 2 is selected by connecting a timing Table 10 includes a composite of all environmental and
resistor (R in Figure 5) from the TRST input to operating conditions that can ultimately affect the
TRST
ground. It is typically used in applications where the absolute measurement accuracy of the Si85xx. The
gate drivers are on-board the controller. In this mode, total worst-case accuracy at full scale can be estimated
the on-chip reset timer is triggered when the signals on by the sum of the initial accuracy (up to ±5%) plus aging
R1–R4 satisfy the logic equations in Table 11. Once (up to ±1.5%) and supply variations (up to ±3.5%). For
triggered, the timer maintains integrator in reset for time example, the total measurement error expected for a
duration t as programmed by the value of resistor device operating at a given V supply of 5 V (±10%) is
R
DD
R
. The user must select the value of resistor R
10% if the device is operated over a temperature range
TRST
TRST
to terminate the reset cycle prior to the start of of –40 to 125 °C for up to 10 years. If the temperature
measurement under worst-case timing conditions. Note range is limited to 0 to 85 °C, the measurement error
that values of t below the specified value in "1. can be improved by up to 2%. See Figure 6 for details.
R
Electrical Specifications" on page 4 results in increased
Table 10. Total Measurement Error Contributors
integrator output offset error and increased output noise
on V . Moreover, t ’s time is summarized by the
OUT
R
Error Contributor
% Error Added
following equation (see Table 9):
t = 10 ns/k
Initial error
R
±5%
@ given V ±10%, 25 °C
where values of R
that produce a reset time less
DD
TRST
than 150 ns (R
< 15 k) should not be used.
TRST
Temperature variation
–40 to 125 °C
±3.5%
±1.5%
Si85xx
Aging (10 years)
2.5. Effect of Temperature on Accuracy
Offset voltage present at the Si85xx output terminals
(output offset voltage) is calibrated out each time VDD is
applied to the Si85xx; so, its error contribution is
minimized when the temperature at which calibration
occurred is at or near the steady-state operating
temperature of the Si85xx. For example, applying VDD
at 25 °C (offset cal is performed) and operating at 85 °C
will result in a larger offset error than operating at 50 °C.
The effect of this error is summarized in Figure 6. The
chart is referenced to 25 °C. If the Si85xx is powered up
at 25 °C and then operated at 125 °C with no auto-
calibration performed (i.e., the power is not cycled at
125 °C, which causes an auto-calibration), a 3%
measurement error can be expected.
TRST
RTRST
Figure 5. Programming Reset Time (tR)
Table 9. Typical Reset Time vs. RTRST
Resistance
R
Reset Time (t )
TRST
R
15 k
100 k
1 M
150 ns
1 µs
9 µs
2.2 M
20 µs
Preliminary Rev. 0.4
11
Si85xx
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
-2.5%
-3.0%
Current Sense
Transformer
Si8502
-3.5%
0
25
50
75
100
125
Temperature (Celcius)
Figure 6. Differential Temperature
Calibration Error
Figure 7 shows the Si85xx thermal characteristics of the
on-chip sense resistance over the temperature range of
–40 to +125 °C. Series inductance is constant at 2 nH
(max) across this same temperature range.
Figure 8. Leading-Edge Noise Suppression
Waveforms (200 kHz, 9.3 A Load)
2
1.8
1.6
1.4
1.2
1
2.7. FAULT Output
The FAULT output (Si8517/8/9) guards against Si85xx
output signal errors caused by missing reset cycles.
FAULT is asserted when a measurement cycle exceeds
the internal watchdog timer times limit of t . FAULT
WD
0.8
0.6
0.4
0.2
0
can be used to alert a local microcontroller or digital
power controller of a current sense failure or to initiate a
system shutdown. To detect faults, tie a 200 k resistor
from TRST/FAULT to VDD.
-20
0
20
40
60
80
100
120
2.8. Safe Operating Limits
Temperature (°C)
The Si85xx is a very robust current sensor. Its maximum
input current rate of change is limited to 1000 A/µs. The
maximum peak ac input current limit is 200 A. The
thermal limit or continuous dc current flow limit is 30 A.
Exceeding these limits may cause long-term reliability
issues. Refer to “AN329: Extending the Full-Scale
Range of the Si85xx” for more information.
Figure 7. Series Resistance Thermal
Characteristics
2.6. Leading Edge Noise Suppression
High-amplitude spikes on the leading edge of the
primary switching waveforms can cause the PWM latch
to be erroneously reset at the start of the switching cycle
when operating in current mode control. To prevent this
problem, leading edge blanking is commonly used to
disable the current comparator during the early portion
of the primary-side switching cycle. The Si85xx
eliminates leading-edge noise spikes by including them
in the signal integration. As shown in the output
waveform of Figure 8 (Si8502 waveform measured
directly on OUT pin with no external filter), noise present
in the input waveform is eliminated without the use of
blanking.
12
Preliminary Rev. 0.4
Si85xx
3. Application Information
Ground
Plane Edge
Ground
Plane Edge
3.1. Board Layout
Top View
The Si85xx is connected in the series path of the current
to be measured. The Si85xx must be located as far as
possible from transformer and other magnetic field
sources. Like other analog components, the Si85xx
should be powered from a low-noise dc source and,
preferably, to a low-noise analog ground plane.
Recommended bypass capacitors are 1 µF in parallel
with a 0.1 µF, positioned as close to the Si85xx as
possible. When using the Si850x (single output
versions), all three ground pins MUST be connected to
the same ground point, and both VDD1 and VDD2 pins
MUST be tied to the VDD system power supply.
VDD Pin
Mode Pin
(Non-Ping-Pong)
Current
Carrying Slug
VDD Fly Wire
3.5 mm
Current
Sensor Die
Bonding Wire
3.2. Layout Requirements
The Si85xx requires special layout techniques to ensure
proper operation (see Figures 9 and 10). Due to the
close proximity of the current-carrying slug and current
sensor silicon, magnetic coupling between the current-
carrying slug and the silicon can form a ground loop
causing the output voltage to be 0 V even though
current is flowing through the slug. To eliminate any
such coupling issues, a red fly-wire VDD trace (see
Figures 9 and 10) should be implemented in the layout.
For the SOIC package, the red fly-wire trace should be
approximately 3.5 mm from the center edge of the
package intersecting approximately in the center of the
package (see Figure 9). For the QFN package, the red
fly-wire should be approximately in the center of the
package (see Figure 10). Standard wire thicknesses for
10 mA current-carrying capabilities should be used.
Moreover, note that the fly-wire trace should be
completely under the ground plane since this will also
reduce coupling.
Gnd Pin
Bypass Capacitor
SOIC Package
5 V VDD Trace
Figure 9. SOIC Layout Requirements
Ground Plane Edge
Ground
Plane Edge
VDD Pin
Mode Pin
(Non-Ping-Pong)
Top View
Current
Carrying Slug
Current
Sensor Die
2 mm
Bonding
Wires
Regarding isolation voltage requirements, the trace
does not need to follow the lead frame and bonding
traces exactly, as long as the net magnetic flux is close
to zero. The goal here is to keep the magnetic coupling
small and, at the same time, keep the isolation distance
large. Moreover, to ensure that the layout meets the
VDD
Fly Wire
Gnd Pin
Bypass Capacitor
5V VDD Trace
design’s
required
creepage
and
clearance
QFN Package
requirements, the VDD trace should be placed on one
of the inner layers or even the back side of the board.
For example, one can lay out the return VDD trace on
the other side of the PCB so the PCB itself can help to
provide high isolation voltage.
Figure 10. QFN Layout Requirements
Preliminary Rev. 0.4
13
Si85xx
3.3. Device Configuration
Configuring the Si85xx involves the following steps:
1. Selecting an output mode
R1
R2
2. Configuring integrator reset timing
3. Setting integrator reset time t
R
3.3.1. Device Selection
MEASURE RESET
MEASURE RESET
Si85xx State
tR
tR
The Si85xx family offers three output modes: Single
output (Si850x), and 2 and 4-Wire Ping Pong (Si851x).
The Si851x products can be configured to operate in all
three of these output modes.
OUT1
OUT2
The Si850x products operate ONLY in Single output
mode. Most half-wave and single-phase applications
require only Single output mode and will typically use
the Si850x.
TIME
Figure 12. Full-Bridge Timing Example B
In Single output mode, output current always appears
on the OUT pin (Si850x) or the OUT1 pin (Si851x). A
single integrator reset signal is typically sufficient when
operating in this mode.
4-Wire Ping-Pong mode is recommended for full-bridge
applications over 2-wire because it uses all four inputs,
making the reset function tolerant to single-point signal
failures. In 4-Wire Ping-Pong mode, current appears on
OUT2 when R1 is high and R2 is low, and appears on
OUT1 when R3 is high and R4 is low as shown in the
full-bridge timing example of Figure 13. Table 11 shows
the states of the Mode and R4 inputs that select each
output, and the resulting reset logic functions and truth
tables.
Ping-Pong mode routes the current waveform to two
different output pins on alternate measurement cycles.
It is useful in full-wave and push-pull topologies where
external circuitry can be used to monitor and/or control
transformer flux balance. (Section "3. Application
Information" on page 13 shows design examples using
both output modes in various power topologies.)
2-wire Ping-Pong mode is useful mainly in non-
overlapping two-phase buck converters but may also be
used in full-bridge applications. In this output mode,
reset inputs R1 and R2 are used, and input R3 is
grounded. Measured current appears on OUT1 when
R1 is high and on OUT2 when R2 is high as shown in
the full-bridge timing example of Figures 11 and 12.
R1
R2
R1
R2
R3
R4
MEASURE RESET
MEASURE RESET
Si85xx State
tR
tR
MEASURE RESET
MEASURE RESET
OUT1
tR
tR
OUT1
OUT2
OUT2
TIME
Figure 11. Two-Phase Buck Timing Example A
Figure 13. Full-Bridge Timing Example C
14
Preliminary Rev. 0.4
Si85xx
3.3.2. Selecting Reset Timing Signals
Reset timing signals should be chosen to meet the
following conditions:
Satisfy reset time t
R
Not overlap integrator reset into the desired
measurement period
Not violate reset watchdog timeout period t
WD
3.3.3. Configuring Integrator Reset
Per Section “2. Functional Overview”, the integrator
must be reset (zeroed) prior to the start of each
measurement cycle to achieve specified measurement
accuracy. This reset must be synchronized with the
system switch timing signals to ensure that current is
measured during the appropriate time; so, the Si85xx
integrator reset circuitry uses system timing as its
reference. Timing signals connect to reset inputs R1
through R4 where built-in logic functions allow the user
to choose the conditions that cause an integrator reset
event. Important Note: reset inputs R1–R4 are rated to
a maximum input voltage of VDD. External resistor
dividers must be used when connecting driver output
signals to R1–R4 that swing beyond VDD.
As shown in Table 11, the Si850x integrator reset logic
is a simple XOR gate where reset is maintained (or
triggered, depending on use of the TRST input) when
states of reset inputs R1 and R2 are not equal.
Figure 14 shows the logic for the Si851x products,
where any one of three reset logic functions can cause
integrator reset. The output mode (Si851x) is
determined by the states of the Mode and R4 inputs, as
shown in Table 11.
Preliminary Rev. 0.4
15
Si85xx
Table 11. Si85xx Output and Reset Mode Summary
Output Mode
MODE
R4
R3
R2
R1
Reset
Reset Logic Expression
1
State
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
0
2
Single-Ended
1
0
RESET = XOR[R1, (R2|R3)]
1
0
0
1
0
1
2-Wire Ping Pong
1
1
RESET = XNOR[R1,(R2|R3)]
0
4-Wire Ping Pong
0
RESET = (R1&R2)|(R3&R4)
1
Notes:
1. Device is in reset when Reset State = 1.
2. For Si850x devices, RESET = XOR [R1, R2].
16
Preliminary Rev. 0.4
Si85xx
As explained in Section “2.3. Integrator Reset and Current Measurement”, the signals applied to R1–R4 can
control integrator reset in real time (Option 1), or they can trigger a reset event of programmable duration (Option
2). Referring to Figure 14, reset timing is exclusively a function of the signals applied to R1–R4 when TRST is tied
to VDD.
If not connected to VDD, the reset timer is enabled, and TRST must be connected through a resistor to ground to
set the reset duration (t ). Note that the reset timer is retriggerable and generates a timed integrator discharge
R
pulse whenever the reset logic output transitions from low to high.
MODE = 1
R4 = 0
TRST = R1 to GND
TRST = VDD
Output 1
Output 2
Reset triggered by inputs
R1–R4. Reset time (tR) set
Reset timing determined
only by inputs R1–R4.
R1
R2
R3
R4
by value of resistor RTRST
.
MODE = 1
R4 = 1
RESET
TIMER
TRST
PGM
OUT
CLK
1
0
+
VREF
MODE = 0
Output 3
Logic level gate
control signals
(to Rn inputs)
SYSTEM
CONTROLLER
INTEGRATOR
External
Driver
Internal
Driver
Logic level gate
control signals
(to Rn inputs)
Required if driver
output voltage > VDD
Figure 14. Si851x Integrator Reset Logic
Preliminary Rev. 0.4
17
Si85xx
3.3.4. Setting Reset Time t
R
The programmable reset timer is triggered when the states of the signals applied to R1–R4 cause the associated
logic expression in Table 11 to go high (transition to the TRUE state).
Because this timer is re-triggerable, R1–R4 must remain TRUE for the duration of the desired t as shown in
R
Figure 15. Should R1–R4 transition FALSE during t , integrator reset will be immediately halted, resulting in lower
R
measurement accuracy due to higher integrator offset error.
CURRENT
R1–R4 TRUE
for programmed
tR (minimum)
TRUE
R1–R4 STATE
FALSE
Programmed
0 ns (min)
value of tR
Si85xx STATUS
Si85xx OUTPUT
RESET
MEASURE
Figure 15. Correct tR Programming Using Resistor from TRST Input to Ground
18
Preliminary Rev. 0.4
Si85xx
3.3.5. Measurement Watchdog Timer and FAULT Output
A built-in watchdog timer disables measurement and holds OUT or OUT1 and OUT2 at their minimum values when
the time between integrator resets exceeds the FAULT Detect Time. The output signal from this watchdog is
available on the FAULT output pin (Si8517/8/9 only).
Figure 16 illustrates two means of entering a fault condition. Either fault condition 1 or 2 occurs when the reset
period exceeds the FAULT Detect Time, which ranges from 30 to 80 µs due process variations. The fault condition
ends when the next logic reset cycle begins.
Output
t Cycle Reset
Reset Logic
30-80 µs
FAULT Detect Time
FAULT Output
FAULT Condition 1
Output
Reset Logic
30-80 µs
FAULT Detect Time
FAULT Output
FAULT Condition 2
Figure 16. Measurement Watchdog Timer Operation
Preliminary Rev. 0.4
19
Si85xx
3.3.6. Output Over-Range
The Si85xx can be over-ranged by more than 100% with no adverse effects. For instance, if the Si8512 (a 10 A
nominal full-scale device) has a 15 A peak current applied, then the output voltage (OUT) will be 3 V (assuming
VDD = 5 V). If a 10 A peak current is applied, then the output returns to the nominal 2 V output. The head room of
OUT is VDD–1.4 V. Figure 17 illustrates the head room limitation of the Si85xx versus supply.
5
3.6 V
4
VDD = 5 V
3
OUT (V)
VDD = 2.7 V
2
1
0
50%
100%
150%
200%
250%
I (Amps) Percent Nominal Full-Scale Input
Figure 17. Headroom Limitation
20
Preliminary Rev. 0.4
Si85xx
3.4. Single-Phase Buck Converter Example
In this example, the Si850x is configured to operate in a single-phase synchronous buck converter (Figure 18).
This converter has a PWM frequency of 1 MHz and a maximum duty cycle of 80%.
This is an example of a half-wave application that can be addressed with Single-Ended output mode. The PWM
–6
–6
period is calculated to be 1/10 = 1.0 µs, and the worst-case value, t , is 0.2 x 1.0 x 10 = 200 ns at 80%
R
maximum duty cycle (R
= 20 k).
TRST
In this example, the current measurement is made when the buck switch is on; so, PH2 is chosen as the reset
signal by connecting PH2 to R1 and grounding R2. The PH2 signal can be obtained at the input of the driver
external to the PWM controller or the output of the controller's internal driver (through a resistor divider if the driver
output swings beyond the device VDD range).
VDD
VIN
C1
C2
0.1 µF
1 µF
VDD1 VDD2
R2
GND1
GND2
GND3
IIN
Si850x
IOUT
TRST
R1
RTRST
2 Vpp
OUT
Q1
L1
PH1
PWM
PH2
VOUT
Current
I = 0
I > 0
C3
Q2
Si850x State
RESET
100 ns
MEASURE
PH2
Figure 18. Si850x Single-Phase Buck Converter
Preliminary Rev. 0.4
21
Si85xx
3.5. Full-Bridge Converter Example
The full-bridge circuit of Figure 19 uses an Si851x configured in 4-Wire Ping-Pong output mode. The switching
frequency of this phase-shifted full-bridge is 150 kHz, and the maximum control phase overlap is 70%.
VIN
VDD
VDD
IIN
OUT1
OUT2
PH1
PH2
OUT1
OUT2
MODE
GND
C1
C2
Si851x
0.1 µF
1 µF
VDD
TRST
R1 R2 R3 R4
IOUT
PH3
PH4
Q1
1–4
1–2
2–3
3–4
Switches Turned ON
Si85xx State
PH1
PH2
Q2
Q4
MEASURE
RESET
MEASURE
RESET
TI
OUT1
OUT2
Q3
PH3
PH4
Figure 19. Full-Bridge Converter
3
Given the 150 kHz switching frequency (duty cycle fixed at 50%), the equivalent period is 1/150 x 10 = 6.6 µs. At
–6
70% maximum overlap, this equates to a worst-case t value of 0.3 x 6.6 x 10 = 1.98 µs. The default value for t
R
R
can, therefore, be used and is selected by connecting TRST to VDD. As shown in the timing diagram of Figure 19,
integrator reset occurs when current circulates between Q1 and Q2 and between Q3 and Q4 (i.e. when current is
not being sourced from VIN). The external driver delay ensures reset is complete prior to the start of measurement.
22
Preliminary Rev. 0.4
Si85xx
3.6. Push-Pull Converter Example
The Push-Pull converter of Figure 20 uses 2-Wire Ping Pong output mode. As shown in the timing diagram, the
integrator reset occurs when the inputs of both the PH1 and PH2 drivers are low. As shown, TRST is connected to
VDD, selecting the default value of t (250 ns). Assuming an 80% maximum duty cycle, this value of t would
R
R
deliver specified accuracy over a PWM frequency range of 50 to 400 kHz. Frequencies above 400 kHz would
require the selection of a lower t value by connecting a resistor from TRST to ground.
R
VDD
VIN
C1
C2
0.1 µF
1 µF
VDD MODE
IIN
OUT1
OUT2
R4
TRST
Si851x
R3
R2
GND
R1
IOUT
Q1
PH2
PH1
PH2
T1
MEASURE RESET MEASURE RESET MEASURE
Si85xx Status
OUT1
Q2
PH1
OUT2
Figure 20. Push-Pull Example Using Default tR Value
Preliminary Rev. 0.4
23
Si85xx
4. Pin Descriptions—12-Pin QFN
R1
R1
IIN
IIN
R2
R3
R4
R2
GND2
Si851x
Si850x
GND3
OUT1
OUT2
OUT
IOUT
IOUT
NC
Figure 21. Example Pin Configurations
Table 12. Si85xx Family Pin Descriptions
Pin#
Si850x
Description
Si851x
Description
Pin Name
Pin Name
1
2
3
4
5
R1
R2
Integrator reset input 1
Integrator reset input 2
Ground
R1
R2
Integrator reset input 1
Integrator reset input 2
Integrator reset input 3
Integrator reset input 4
GND2
GND3
OUT
R3
R4
Output
OUT1
Output in single-ended output mode, or
one of two outputs in Ping-Pong mode.
6
7
NC
No connect
OUT2
TRST
GND
IOUT
IIN
Second of two Ping-Pong mode outputs
Reset time control
TRST
GND1
IOUT
IIN
Reset time control
Ground
8
Ground
9
Current output terminal
Current input terminal
Power supply input
Current output terminal
Current input terminal
Power supply input
10
11
12
VDD1
VDD2
VDD
MODE
Mode control input
24
Preliminary Rev. 0.4
Si85xx
5. Pin Descriptions—20-Pin SOIC
20-Pin SOIC
Si851x
20-Pin SOIC
VDD
IIN
VDD1
IIN
MODE
R1
IIN
VDD2
R1
IIN
IIN
IIN
R2
R2
IIN
IIN
R3
IIN
GND2
GND3
OUT
IIN
Si850x
R4
OUT1
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
IOUT
OUT2
NC
TRST/FAULT
TRST
GND
GND1
Figure 22. Example Pin Configurations
Table 13. Si85xx Family Pin Descriptions
Pin#
Si850x
Description
Si851x
Description
Pin Name
Pin Name
1
2
3
4
5
6
7
VDD1
VDD2
R1
VDD
MODE
R1
Power supply input
Power supply input
Mode control input
Integrator reset input 1
Integrator reset input 2
Ground
Integrator reset input 1
Integrator reset input 2
Integrator reset input 3
Integrator reset input 4
R2
R2
GND2
GND3
OUT
R3
R4
Output
OUT1
Output in single-ended output mode, or
one of two outputs in Ping-Pong mode.
8
9
NC
TRST
GND1
IOUT
IIN
No connect
OUT2
TRST
GND
IOUT
IIN
Second of two Ping-Pong mode outputs
Reset time control
Reset time control
Ground
10
Ground
11–15
16–20
Current output terminal
Current input terminal
Current output terminal
Current input terminal
Preliminary Rev. 0.4
25
Si85xx
6. Ordering Guide
Package2
New
Full
Scale
Current
(A)
Initial
Accuracy %1
Temp
Range
Pin 7
Function
Isolation Output
Old Obsolete
Old Obsolete
OPNs3
(Previously
Specified with
±5% Accuracy
and
OPNs3
(Previously
Specified with
±20%
Rating
Mode
OPNs
Accuracy)
–40C to +85 °C)
Si8501-C-IM
Si8502-C-IM
Si8503-C-IM
Si8501-C-IS
Si8502-C-IS
Si8503-C-IS
Si8511-C-IM
Si8512-C-IM
Si8513-C-IM
Si8511-C-IS
Si8512-C-IS
Si8513-C-IS
Si8517-C-IM
Si8518-C-IM
Si8519-C-IM
Si8517-C-IS
Si8518-C-IS
Si8519-C-IS
Notes:
5
Si8501-C-GM
Si8502-C-GM
Si8503-C-GM
Si8504-C-IM
Si8505-C-IM
Si8506-C-IM
10
20
5
1 kVRMS
5 kVRMS
1 kVRMS
5 kVRMS
1 kVRMS
5 kVRMS
QFN-12
SOIC-20
QFN-12
SOIC-20
QFN-12
SOIC-20
Single
10
20
5
New package offering
Integrator
Reset Pro-
gramming
Time Input
Si8511-C-GM
Si8512-C-GM
Si8513-C-GM
Si8514-C-IM
Si8515-C-IM
Si8516-C-IM
10
20
5
–40 to
125 °C
5%
10
20
5
New package offering
Ping-
Pong
Si8517-C-GM
Si8518-C-GM
Si8519-C-GM
10
20
5
—
FAULT
Output
10
20
New Package Offering
1. See "2.4. Total Measurement Error" on page 11 for more information.
2. All packages are RoHS-compliant. Moisture Sensitivity level is MSL3 with peak reflow temperature of 260 °C according to the JEDEC
industry classification, and peak solder temperature.
3. Since the initial accuracy for all devices is now specified as ±5%, Si8504/5/6 and Si8514/15/16 OPNs have been replaced with
Si8501/2/3 and Si8511/12/13 OPNs, respectively.
26
Preliminary Rev. 0.4
Si85xx
7. Package Outline—12-Pin QFN
Figure 23 illustrates the package details for the Si85xx. Table 14 lists the values for the dimensions shown in the
illustration.
Figure 23. 12-Pin QFN Package Diagram
Table 14. QFN-12 Package Diagram Dimensions
Dimension
Min
0.80
0.00
0.20
0.95
Nom
0.85
Max
0.90
0.05
0.30
1.05
A
A1
b1
b2
D
0.03
0.25
1.00
4.00 BSC.
0.50 BSC.
4.00 BSC.
0.75 BSC.
2.45 BSC.
1.30 BSC.
0.40
e
E
f
g
h
L1
L2
aaa
bbb
ccc
ddd
eee
0.35
0.85
0.45
0.95
0.90
0.05
0.05
0.08
0.10
0.10
Notes:
1. All dimensions shown are in millimeters (mm).
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Preliminary Rev. 0.4
27
Si85xx
8. Recommended PCB Land Pattern (12-Pin QFN)
Figure 24 illustrates the PCB land pattern details for the 12-pin QFN package. Table 15 lists the values for the
dimensions shown in the illustration.
Figure 24. 12-Pin QFN PCB Land Pattern
Table 15. 12-Pin QFN PCB Land Pattern Dimensions
Dimension
mm
1.95
1.30
3.90
2.45
0.50
0.80
1.00
0.30
1.10
C1
C2
D1
D2
E
X1
X2
Y1
Y2
Notes:
1. This Land Pattern Design is based on IPC-7351 design guidelines for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a
card fabrication tolerance of 0.05 mm is assumed.
28
Preliminary Rev. 0.4
Si85xx
9. Package Outline: Wide Body SOIC
Figure 25 illustrates the package details for the wide-body SOIC package. Table 16 lists the values for the
dimensions shown in the illustration.
Figure 25. 20-Pin Wide Body SOIC
Preliminary Rev. 0.4
29
Si85xx
Table 16. 20-Pin Wide Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
12.80 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AC.
4. Recommended reflow profile per JEDEC J-STD-020C specification for small body,
lead-free components.
30
Preliminary Rev. 0.4
Si85xx
10. Recommended PCB Land Pattern (20-Pin SOIC)
Figure 26 illustrates the PCB land pattern details for the 20-pin SOIC package. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 26. 20-Pin SOIC PCB Land Pattern
Table 17. 20-Pin SOIC PCB Land Pattern Dimensions
Dimension
mm
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Notes:
1. This Land Pattern Design is based on IPC-7351 design guidelines for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a
card fabrication tolerance of 0.05 mm is assumed.
Preliminary Rev. 0.4
31
Si85xx
11. Top Marking (QFN)
Si85XX
RTTTTT
YYWW
Figure 27. QFN Top Marking
Table 18. Top Marking Explanation
Line 1 Marking:
Device Part Number
Si85XX:
Where XX = 01, 02, 03, 11, 12, 13, 17, 18, 19
Line 2 Marking:
Line 3 Marking:
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Circle Bottom-Left Justified
Pin 1 Identifier
YY = Year
WW = Work Week
Corresponds to the year and work week of the assembly
build date.
32
Preliminary Rev. 0.4
Si85xx
12. Top Marking (SOIC)
Si85XX-IS
YYWWRTTTTT
TW
e3
Figure 28. SOIC Top Marking
Table 19. Top Marking Explanation
Line 1 Marking:
Line 2 Marking:
Device Part Number
Si85XX-IS
Where XX = 01, 02, 03, 11, 12, 13, 17, 18, 19
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking:
Circle = 1.5 mm Diameter
(Center Justified)
“e3” Pb-Free Symbol
Country of Origin
TW = Taiwan
ISO Code Abbreviation
Preliminary Rev. 0.4
33
Si85xx
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated Table 1, “Electrical Specifications,” on
page 4.
Added 20-pin wide-body SOIC package option.
Updated "6. Ordering Guide" on page 26.
All devices are now specified to ±5% initial accuracy.
All devices are now specified for operation over –40 to
+125 °C temperature range. All ordering part numbers
have been updated to reflect this (i.e. previous “-GM”
and “-GS” part number suffixes have been replaced with
“-IM” and “-IS” suffixes).
Added sections “8. Recommended PCB Land
Pattern (12-Pin QFN)” and “10. Recommended PCB
Land Pattern (20-Pin SOIC)”.
Revision 0.2 to Revision 0.21
Added reference to IEC61010, IEC60601 on page 1.
Updated "6. Ordering Guide" on page 26.
Added Top Marking sections.
Revision 0.21 to Revision 0.3
Updated Table 2 on page 5.
Production test voltage is > 6.0 kVRMS
.
Added “2.5. Effect of Switching Frequency on
Accuracy” on page 11.
Added Figure 6, “Full-Scale Output Accuracy vs.
Frequency,” on page 11.
Updated "3.2. Layout Requirements" on page 13.
Added layout recommendations for QFN.
Added Figure 10, “QFN Layout Requirements,” on
page 13.
Revision 0.3 to Revision 0.4
Updated Table 8 on page 8.
Added junction temperature spec.
Removed Figure 6, “Full-Scale Output Accuracy vs.
Frequency,” on page 11.
Updated Figures 9 and 10 on page 13.
Updated Table 11 on page 16.
Updated notes.
Updated Top Marks.
Added revision description.
34
Preliminary Rev. 0.4
Si85xx
NOTES:
Preliminary Rev. 0.4
35
Si85xx
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
36
Preliminary Rev. 0.4
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