SI8642BD-B-IS2 [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16;
| 型号： | SI8642BD-B-IS2 |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16 光电二极管 |
| 文件： | 总44页 (文件大小：1051K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si864x Data Sheet
Low-Power Quad-Channel Digital Isolators
KEY FEATURES
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages over legacy isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges and throughout device service life for
ease of design and highly uniform performance. All device versions have Schmitt trigger
inputs for high noise immunity and only require VDD bypass capacitors.
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
• Up to 5000 V
isolation
RMS
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Enable inputs provide a single point control for enabling and disabling
output drive. Ordering options include a choice of isolation ratings (1.0, 2.5, 3.75 and 5
kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products >1 kV are safety certified by UL, CSA, VDE, and CQC, and
products in wide-body packages support reinforced insulation withstanding up to 5
• Reinforced VDE 0884-10, 10 kV surge-
capable (Si864xxT)
• 60-year life at rated working voltage
• High electromagnetic immunity
• Ultra low power (typical)
kVRMS
.
5 V Operation
• 1.6 mA per channel at 1 Mbps
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
• 5.5 mA per channel at 100 Mbps
2.5 V Operation
• 1.5 mA per channel at 1 Mbps
Automotive Applications
Industrial Applications
• On-board chargers
• Industrial automation systems
• 3.5 mA per channel at 100 Mbps
• Tri-state outputs with ENABLE
• Schmitt trigger inputs
• Battery management systems
• Medical electronics
• Charging stations
• Isolated switch mode supplies
• Traction inverters
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Isolated ADC, DAC
• Hybrid Electric Vehicles
• Motor control
• Battery Electric Vehicles
• Power inverters
• Precise timing (typical)
• 10 ns propagation delay
• Communications systems
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 62368-1, 60601-1 (re-
inforced insulation)
• Wide temperature range
• –40 to 125 °C
• VDE certification conformity
• Si864xxT options certified to rein-
forced VDE 0884-10
• RoHS-compliant packages
• SOIC-16 wide body
• All other options certified to basic
VDE 0884-10 and reinforced 60950-1
• SOIC-16 narrow body
• QSOP-16
• CQC certification approval
• GB4943.1
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• IMDS and CAMDS listing support
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Rev. 2.11
Si864x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs1, 2
Number of Number of
Max Data
Rate
(Mbps)
Default Isolation
Inputs
Inputs
Ordering Part Number (OPN)
Output
State
Rating
(kV)
Temp (°C)
Package
VDD1
Side
VDD2
Side
QSOP-16 Packages
Si8640BA-B-IU
Si8640BB-B-IU
Si8640EB-B-IU
Si8641BA-B-IU
Si8641BA-C-IU
Si8641BB-B-IU
Si8641EB-B-IU
Si8642BA-B-IU
Si8642BA-C-IU
Si8642BB-B-IU
Si8642EA-B-IU
Si8642EB-B-IU
Si8645BA-B-IU
Si8645BA-C-IU
Si8645BB-B-IU
SOIC-16 Packages
Si8640BB-B-IS1
Si8640BB-B-IS
Si8640BC-B-IS1
4
4
4
3
3
3
3
2
2
2
2
2
4
4
4
0
0
0
1
1
1
1
2
2
2
2
2
0
0
0
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
Low
Low
High
Low
Low
Low
High
Low
Low
Low
High
High
Low
Low
Low
1.0
2.5
2.5
1.0
1.0
2.5
2.5
1.0
1.0
2.5
1.0
2.5
1.0
1.0
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
4
4
4
0
0
0
150
150
150
Low
Low
Low
2.5
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
NB SOIC-16
WB SOIC-16
NB SOIC-16
3.75
WB SOIC-16
(8 mm creepage)4
Si8640BD-B-IS2
4
0
150
Low
5.0
–40 to 125 ˚C
Si8640BD-B-IS
Si8640EC-B-IS1
4
4
0
0
150
150
Low
5.0
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
NB SOIC-16
High
3.75
WB SOIC-16
(8 mm creepage)4
Si8640ED-B-IS2
4
0
150
High
5.0
–40 to 125 ˚C
Si8640ED-B-IS
Si8641BB-B-IS1
Si8641BB-B-IS
Si8641BC-B-IS1
4
3
3
3
0
1
1
1
150
150
150
150
High
Low
Low
Low
5.0
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
NB SOIC-16
WB SOIC-16
NB SOIC-16
2.5
3.75
WB SOIC-16
(8 mm creepage)4
Si8641BD-B-IS2
3
1
150
Low
5.0
–40 to 125 °C
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Rev. 2.11 | 2
Si864x Data Sheet
Ordering Guide
Number of Number of
Max Data
Rate
(Mbps)
Default Isolation
Inputs
Inputs
Ordering Part Number (OPN)
Output
State
Rating
(kV)
Temp (°C)
Package
VDD1
Side
VDD2
Side
Si8641BD-B-IS
Si8641EC-B-IS1
3
3
1
1
150
150
Low
5.0
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
NB SOIC-16
High
3.75
WB SOIC-16
(8 mm creepage)4
Si8641ED-B-IS2
3
1
150
High
5.0
–40 to 125 °C
Si8641ED-B-IS
Si8642BB-B-IS1
Si8642BB-B-IS
Si8642BC-B-IS1
3
2
2
2
1
2
2
2
150
150
150
150
High
Low
Low
Low
5.0
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
NB SOIC-16
WB SOIC-16
NB SOIC-16
2.5
3.75
WB SOIC-16
(8 mm creepage)4
Si8642BD-B-IS2
2
2
150
Low
5.0
–40 to 125 °C
Si8642BD-B-IS
Si8642EC-B-IS1
2
2
2
2
150
150
Low
5.0
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
NB SOIC-16
High
3.75
WB SOIC-16
(8 mm creepage)4
Si8642ED-B-IS2
2
2
150
High
5.0
–40 to 125 °C
Si8642ED-B-IS
Si8645BB-B-IS1
Si8645BB-B-IS
Si8645BC-B-IS1
Si8645BD-B-IS
2
4
4
4
4
2
0
0
0
0
150
150
150
150
150
High
Low
Low
Low
Low
5.0
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
NB SOIC-16
WB SOIC-16
NB SOIC-16
WB SOIC-16
2.5
3.75
5.0
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
Si8640BT-IS
Si8640ET-IS
Si8641BT-IS
Si8641ET-IS
Si8642BT-IS
Si8642ET-IS
Si8645BT-IS
Si8645ET-IS
4
4
3
3
2
2
4
4
0
0
1
1
2
2
0
0
150
150
150
150
150
150
150
150
Low
High
Low
High
Low
High
Low
Low
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. The package designated IS2 has a design that eliminates tie bars, thus allowing for extra creepage distance while maintaining
standard WB SOIC-16 package dimensions and land pattern.
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Rev. 2.11 | 3
Si864x Data Sheet
Ordering Guide
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part Number Number of Number of Max Data
Default
Output
State
Isolation
Rating
(kV)
Temp (°C)
Package
(OPN)
Inputs
Inputs
Rate
(Mbps)
VDD1
Side
VDD2
Side
QSOP-16 Packages
Si8642EA-AU
2
2
150
High
1.0
–40 to 125 °C
QSOP-16
SOIC-16 Packages
Si8640BD-AS
Si8640ED-AS
Si8641BB-AS1
Si8641ED-AS
Si8642BB-AS1
Si8642BD-AS
Si8642EC-AS1
4
4
3
3
2
2
2
0
0
1
1
2
2
2
150
150
150
150
150
150
150
Low
High
Low
High
Low
Low
High
5.0
5.0
2.5
5.0
2.5
5.0
3.75
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
WB
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
WB
NB
WB
NB
WB
NB
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
Si8642ET-AS 150 High 5.0
Note:
2
2
–40 to 125 °C
WB
SOIC-16
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
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Rev. 2.11 | 4
Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.1 Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . .10
3.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . .11
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. Package Outline (16-Pin Wide Body SOIC)
7. Land Pattern (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . 31
8. Package Outline (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . .32
. . . . . . . . . . . . . . . . . . . 29
9. Land Pattern (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . 34
10. Package Outline (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . 35
11. Land Pattern (16-Pin QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . 37
12. Top Marking (16-Pin Wide Body SOIC)
13. Top Marking (16-Pin Narrow Body SOIC)
. . . . . . . . . . . . . . . . . . . . 38
. . . . . . . . . . . . . . . . . . .39
14. Top Marking (16-Pin QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . 40
15. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Rev. 2.11 | 5
Si864x Data Sheet
Functional Description
2. Functional Description
2.1 Theory of Operation
The operation of an Si864x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si864x channel is shown in the figure below.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the trans-
mitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that de-
codes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity
to magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Rev. 2.11 | 6
Si864x Data Sheet
Functional Description
2.2 Eye Diagram
The figure below illustrates an eye diagram taken on an Si8640. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8640 were captured on an oscilloscope. The re-
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
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Rev. 2.11 | 7
Si864x Data Sheet
Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 10, where UVLO+ and UVLO– are the respective positive-going and negative-going thresholds. Refer to the following tables to
determine outputs when power supply (VDD) is not present and for logic conditions when enable pins are used.
Table 3.1. Si86xx Logic Operation
VI Input1, 2 EN Input1, 2, 3, 4 VDDI State1, 5, 6 VDDO State1, 5, 6 VO Output1, 2
Comments
H
L
H or NC
H or NC
L
P
P
P
P
P
P
H
L
Enabled, normal operation.
X7
X7
Hi-Z8
L9
Disabled.
H or NC
UP
P
Upon transition of VDDI from unpowered to
powered, VO returns to the same state as VI
in less than 1 µs.
H9
X7
X7
Hi-Z8
L
UP
P
P
Disabled.
X7
UP
Undetermined Upon transition of VDDO from unpowered to
powered, VO returns to the same state as VI
within 1 µs, if EN is in either the H or NC
state. Upon transition of VDDO from unpow-
ered to powered, VO returns to Hi-Z within 1
µs if EN is L.
Note:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the
enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is operating in noisy
environments.
4. No Connect (NC) replaces EN1 on Si8640/45. No Connect replaces EN2 on the Si8645. No Connects are not internally connec-
ted and can be left floating, tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
9. See 1. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default
output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devi-
ces, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/
outputs.
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Si864x Data Sheet
Device Operation
Table 3.2. Enable Input Truth
EN11, 2
—
EN21, 2
Part Number
Operation
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Si8640
H
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.3
Output A4 enabled and follows the input state.
—
Si8641
Si8642
Si8645
H
L
X
X
Output A4 disabled and in high impedance state.3
X
X
H
L
Outputs B1, B2, B3 are enabled and follow the input state.
Outputs B1, B2, B3 are disabled and in high impedance state.3
Outputs A3 and A4 are enabled and follow the input state.
H
L
X
X
Outputs A3 and A4 are disabled and in high impedance state.3
Outputs B1 and B2 are enabled and follow the input state.
X
X
H
L
Outputs B1 and B2 are disabled and in high impedance state.3
Outputs B1, B2, B3, B4 are enabled and follow the input state.
—
—
Note:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic operation is
summarized for each isolator product in Table 2. These inputs are internally pulled-up to local VDD allowing them to be connec-
ted to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2
if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the
Si86xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
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Rev. 2.11 | 9
Si864x Data Sheet
Device Operation
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end-user application, high-voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low-voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.6 Insulation and Safety-Related
Specifications on page 24 and Table 4.8 VDE 0884-10 Insulation Characteristics for Si86xxxx 1 on page 25 detail the working volt-
age and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA
5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-
system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
3.3.1 Supply Bypass
The Si864x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed
as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series
with the inputs and outputs if the system is excessively noisy.
3.3.2 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-
chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
3.4 Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)
can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si86xx Logic Operation on page 8 and
1. Ordering Guide for more information.
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Rev. 2.11 | 10
Si864x Data Sheet
Device Operation
3.5 Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to 4. Electrical
Specifications for actual specification limits.
Figure 3.2. Si8640/45 Typical VDD1 Supply Current vs. Data
Figure 3.3. Si8640/45 Typical VDD2 Supply Current vs. Data
Rate 5, 3.3, and 2.5 V Operation
Rate 5, 3.3, and 2.5 V
Figure 3.4. Si8641 Typical VDD1 Supply Current vs. Data
Figure 3.5. Si8641 Typical VDD2 Supply Current vs. Data Rate
Rate 5, 3.3, and 2.5 V Operation
5, 3.3, and 2.5 V Operation (15 pF Load)
Figure 3.7. Propagation Delay vs. Temperature (5.0 V Data)
Figure 3.6. Si8642 Typical VDD1 or VDD2 Supply Current vs.
Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
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Rev. 2.11 | 11
Si864x Data Sheet
Electrical Specifications
4. Electrical Specifications
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
TJ
Min
—
Typ
—
Max
150
125
5.5
Unit
°C
°C
V
Junction Operating Temperature
Ambient Operating Temperature 1
TA
–40
25
—
VDD1
VDD2
2.375
2.375
Supply Voltage
—
5.5
V
Note:
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply
voltage.
Table 4.2. Electrical Characteristics
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si864xxA/B/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
4.8
—
V
VOL
0.2
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si864xxT
Output Impedance 1
Enable Input Current
Si864xxA/B/C/D
Si864xxT
ZO
IENH, IENL
VENx = VIH or VIL
—
—
2.0
—
—
µA
10.0
DC Supply Current (All Inputs 0 V or at Supply)
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Si864x Data Sheet
Electrical Specifications
Parameter
Si8640Bx, Ex, Si8645Bx
VDD1
Symbol
Test Condition
Min
Typ
Max
Unit
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
VDD2
mA
VDD1
VDD2
Si8641Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
VDD2
mA
VDD1
VDD2
Si8642Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
mA
mA
—
—
3.6
2.9
5.0
4.0
VDD2
Si8641Bx, Ex
VDD1
—
—
3.4
3.3
4.8
4.6
VDD2
Si8642Bx, Ex
VDD1
—
—
3.3
3.3
4.6
4.6
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
mA
mA
—
—
3.6
4.0
5.0
5.6
VDD2
Si8641Bx, Ex
VDD1
—
—
3.7
4.1
5.2
5.8
VDD2
Si8642Bx, Ex
VDD1
—
—
3.9
3.9
5.4
5.4
VDD2
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Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
—
—
3.6
5.0
VDD2
17.5
22.8
Si8641Bx, Ex
VDD1
mA
mA
—
—
7.3
9.8
VDD2
14.3
18.5
Si8642Bx, Ex
VDD1
—
—
11
11
14.3
14.3
VDD2
Timing Characteristics
Si864xBx, Ex
Maximum Data Rate
Minimum Pulse Width
0
—
—
150
5.0
13
Mbps
ns
—
Propagation Delay
tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 16
5.0
8.0
ns
Pulse Width Distortion
|tPLH – tPHL|
See Figure 4.2 Propagation
Delay Timing on page 16
PWD
tPSK(P-P)
tPSK
—
0.2
4.5
ns
Propagation Delay Skew 2
Channel-Channel Skew
All Models
—
—
2.0
0.4
4.5
2.5
ns
ns
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
See Figure 4.2 Propagation
Delay Timing on page 16
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
See Figure 4.2 Propagation
Delay Timing on page 16
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Diagram
on page 7
350
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxA/B/C/D
CMTI
kV/µs
See Figure 4.3 Common-
Mode Transient Immunity Test
Circuit on page 16
35
60
—
50
100
6.0
—
—
11
Si86xxxT
Enable to Data Valid
ten1
See Figure 4.1 ENABLE Tim-
ing Diagram on page 16
ns
ns
Enable to Data Tri-State
ten2
See Figure 4.1 ENABLE Tim-
ing Diagram on page 16
—
8.0
12
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Rev. 2.11 | 14
Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input power loss to valid default output
tSD
See Figure 3.1 Device Behav-
ior during Normal Operation
on page 10
—
8.0
12
ns
Start-up Time 3
tSU
—
15
40
µs
Note:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Rev. 2.11 | 15
Si864x Data Sheet
Electrical Specifications
Figure 4.1. ENABLE Timing Diagram
Figure 4.2. Propagation Delay Timing
Figure 4.3. Common-Mode Transient Immunity Test Circuit
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Rev. 2.11 | 16
Si864x Data Sheet
Electrical Specifications
Table 4.3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si864xxA/B/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
3.1
—
V
VOL
0.2
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si864xxT
Output Impedance 1
Enable Input Current
Si864xxA/B/C/D
Si864xxT
ZO
IENH, IENL
VENx = VIH or VIL
—
—
2.0
—
—
µA
10.0
DC Supply Current (All Inputs 0 V or at Supply)
Si8640Bx, Ex, Si8645Bx
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
VDD2
mA
VDD1
VDD2
Si8641Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
VDD2
mA
VDD1
VDD2
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Rev. 2.11 | 17
Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8642Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
mA
mA
—
—
3.6
2.9
5.0
4.0
VDD2
Si8641Bx, Ex
VDD1
—
—
3.4
3.3
4.8
4.6
VDD2
Si8642Bx, Ex
VDD1
—
—
3.3
3.3
4.6
4.6
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
mA
mA
—
—
3.6
3.4
5.0
4.7
VDD2
Si8641Bx, Ex
VDD1
—
—
3.5
3.6
4.9
5.1
VDD2
Si8642Bx, Ex
VDD1
—
—
3.6
3.6
5.0
5.0
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
mA
mA
—
—
3.6
5.0
VDD2
12.3
15.9
Si8641Bx, Ex
VDD1
—
—
5.9
7.9
VDD2
10.3
13.4
Si8642Bx, Ex
VDD1
—
—
8.2
8.2
10.7
10.7
VDD2
silabs.com | Building a more connected world.
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Si864x Data Sheet
Electrical Specifications
Parameter
Timing Characteristics
Si864xBx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
5.0
13
Mbps
ns
—
tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 16
5.0
8.0
ns
Pulse Width Distortion
|tPLH – tPHL|
See Figure 4.2 Propagation
Delay Timing on page 16
PWD
tPSK(P-P)
tPSK
—
0.2
4.5
ns
Propagation Delay Skew 2
Channel-Channel Skew
All Models
—
—
2.0
0.4
4.5
2.5
ns
ns
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
See Figure 4.2 Propagation
Delay Timing on page 16
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
See Figure 4.2 Propagation
Delay Timing on page 16
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Diagram
on page 7
350
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxA/B/C/D
CMTI
kV/µs
See Figure 4.3 Common-
Mode Transient Immunity
Test Circuit on page 16
35
60
—
50
100
6.0
—
—
11
Si86xxxT
Enable to Data Valid
ten1
ten2
tSD
See Figure 4.1 ENABLE
Timing Diagram on page 16
ns
ns
ns
Enable to Data Tri-State
See Figure 4.1 ENABLE
Timing Diagram on page 16
—
—
8.0
8.0
12
12
Input power loss to valid default output
See Figure 3.1 Device Be-
havior during Normal Opera-
tion on page 10
Start-up Time 3
tSU
—
15
40
µs
Note:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Si864x Data Sheet
Electrical Specifications
Table 4.4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si864xxA/B/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
2.3
—
V
VOL
0.2
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si864xxT
Output Impedance1
Enable Input Current
Si864xxA/B/C/D
Si864xxT
ZO
IENH, IENL
VENx = VIH or VIL
—
—
2.0
—
—
µA
10.0
DC Supply Current (All Inputs 0 V or at Supply)
Si8640Bx, Ex, Si8645Bx
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
VDD2
mA
VDD1
VDD2
Si8641Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
VDD2
mA
VDD1
VDD2
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Rev. 2.11 | 20
Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8642Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
mA
mA
—
—
3.6
2.9
5.0
4.0
VDD2
Si8641Bx, Ex
VDD1
—
—
3.4
3.3
4.8
4.6
VDD2
Si8642Bx, Ex
VDD1
—
—
3.3
3.3
4.6
4.6
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
mA
mA
—
—
3.6
3.1
5.0
4.3
VDD2
Si8641Bx, Ex
VDD1
—
—
3.5
3.4
4.8
4.8
VDD2
Si8642Bx, Ex
VDD1
—
—
3.4
3.4
4.8
4.8
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
VDD1
mA
mA
mA
—
—
3.6
9.9
5.0
VDD2
12.8
Si8641Bx, Ex
VDD1
—
—
5.2
8.5
7.0
VDD2
11.1
Si8642Bx, Ex
VDD1
—
—
6.9
6.9
9.0
9.0
VDD2
silabs.com | Building a more connected world.
Rev. 2.11 | 21
Si864x Data Sheet
Electrical Specifications
Parameter
Timing Characteristics
Si864xBx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
5.0
14
Mbps
ns
—
tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 16
5.0
8.0
ns
Pulse Width Distortion
|tPLH -tPHL|
See Figure 4.2 Propagation
Delay Timing on page 16
PWD
tPSK(P-P)
tPSK
—
0.2
5.0
ns
Propagation Delay Skew 2
Channel-Channel Skew
All Models
—
—
2.0
0.4
5.0
2.5
ns
ns
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
See Figure 4.2 Propagation
Delay Timing on page 16
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
See Figure 4.2 Propagation
Delay Timing on page 16
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Diagram
on page 7
350
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxA/B/C/D
CMTI
kV/µs
See Figure 4.3 Common-
Mode Transient Immunity
Test Circuit on page 16
35
60
—
50
100
6.0
—
—
11
Si86xxxT
Enable to Data Valid
ten1
ten2
tSD
See Figure 4.1 ENABLE
Timing Diagram on page 16
ns
ns
ns
Enable to Data Tri-State
See Figure 4.1 ENABLE
Timing Diagram on page 16
—
—
8.0
8.0
12
12
Input power loss to valid default output
See Figure 3.1 Device Be-
havior during Normal Opera-
tion on page 10
Start-up Time 3
tSU
—
15
40
µs
Note:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to the appearance of valid data at the output.
silabs.com | Building a more connected world.
Rev. 2.11 | 22
Si864x Data Sheet
Electrical Specifications
Table 4.5. Regulatory Information1
CSA
The Si864x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.
60950-1, 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).
VDE
The Si864x is certified according to VDE 0884-10. For more details, see certificates 40018443, 40037519.
0884-10: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si864x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si864x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifi-
cations apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to
5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see 1. Ordering Guide.
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Si864x Data Sheet
Electrical Specifications
Table 4.6. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
NB SOIC-16
4.9
Unit
WB SOIC-16
QSOP-16
Nominal External Air Gap (Clearance) 1
CLR
CPG
DTI
8.0
3.6
3.6
mm
mm
mm
Nominal External Tracking (Creepage) 1
Minimum Internal Gap
(Internal Clearance)
8.0
4.01
0.014
0.014
0.014
Tracking Resistance
CTI or PTI
ED
IEC60112
f = 1 MHz
600
600
600
VRMS
mm
Ω
Erosion Depth
0.019
0.019
0.031
Resistance (Input-Output) 2
Capacitance (Input-Output) 2
1012
2.0
1012
2.0
1012
2.0
RIO
CIO
CI
pF
pF
Input Capacitance 3
4.0
4.0
4.0
Note:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as 4.7 mm minimum for the NB SOIC-16 package and QSOP-16 packages and 8.5 mm minimum for the WB SOIC-16
package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance
and creepage of the WB SOIC-16 package with designation "IS2" as 8 mm minimum. CSA certifies the clearance and creepage
limits as 3.9 mm minimum for the NB SOIC 16, 3.6 mm minimum for the QSOP-16, and 7.6 mm minimum for the WB SOIC-16
package with package designation "IS" as listed in the data sheet.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form
the first termina and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between
these two terminals.
3. Measured from input pin to ground.
Table 4.7. IEC 60664-1 Ratings
Parameter
Test Conditions
Specification
WB SOIC-16
NB SOIC-16
QSOP-16
Basic Isolation Group
Material Group
I
I
I
Installation Classification
Rated Mains Voltages < 150
VRMS
I-IV
I-IV
I-IV
Rated Mains Voltages < 300
VRMS
I-IV
I-III
I-III
I-III
I-II
I-II
I-III
I-II
I-II
Rated Mains Voltages < 400
VRMS
Rated Mains Voltages < 600
VRMS
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Si864x Data Sheet
Electrical Specifications
Table 4.8. VDE 0884-10 Insulation Characteristics for Si86xxxx 1
Characteristic
WB SOIC-16 NB SOIC-16 QSOP-16
Parameter
Symbol
Test Condition
Unit
Maximum Working Insulation
Voltage
VIORM
1200
630
630
Vpeak
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
t = 60 sec
VPR
Input to Output Test Voltage
Transient Overvoltage
Surge Voltage
2250
6000
1182
6000
1182
6000
Vpeak
Vpeak
Vpeak
VIOTM
Tested per IEC 60065 with surge
voltage of 1.2 µs/50 µs
VIOSM
Si864xxT tested with magnitude
6250 V x 1.6 = 10 kV
6250
3077
—
—
Si864xxB/C/D tested with 4000 V
3077
3077
Pollution Degree
2
2
2
(DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO
= 500 V
>109
>109
>109
RS
Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.
Table 4.9. VDE 0884-10 Safety Limiting Values 1
Max
WB SOIC-16 NB SOIC-16 QSOP-16
Parameter
Symbol
Test Condition
Unit
TS
Case Temperature
150
220
275
150
210
275
150
210
275
°C
θJA = 100 °C/W (WB SOIC-16)
105 °C/W (NB SOIC-16, QSOP-16)
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Safety Input, Output, or Supply
Current
IS
mA
Device Power Dissipation 2
PD
mW
Note:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.4 (WB SOIC-16) Thermal Derat-
ing Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on page 26 and Figure 4.5 (NB
SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10
on page 26.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Si864x Data Sheet
Electrical Specifications
Table 4.10. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-16/QSOP-16
105
Unit
IC Junction-to-Air Thermal Resistance
θJA
100
°C/W
Figure 4.4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE
0884-10
Figure 4.5. (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per VDE 0884-10
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Si864x Data Sheet
Electrical Specifications
Table 4.11. Absolute Maximum Ratings 1
Parameter
Storage Temperature 2
Symbol
Min
Max
Unit
TSTG
–65
150
°C
Operating Temperature
Junction Temperature
Supply Voltage
TA
–40
—
125
150
°C
°C
TJ
VDD1, VDD2
–0.5
–0.5
–0.5
—
7.0
V
Input Voltage
VI
VO
IO
VDD + 0.5
VDD + 0.5
10
V
Output Voltage
V
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16, QSOP-16
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
mA
°C
—
260
—
4500
VRMS
—
6500
VRMS
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum ratings for exteneded peri-
ods may degrade performance.
2. VDE certifies storage temperature from –40 to 150 °C.
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Si864x Data Sheet
Pin Descriptions
5. Pin Descriptions
VDD1
VDD1
VDD2
GND2
B1
VDD2
VDD1
VDD2
GND2
B1
GND2
GND1
GND1
GND1
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B1
A1
A1
A2
A1
A2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A2
A3
B2
B2
RF
XMITR
RF
RCVR
B2
RF
XMITR
RF
RCVR
RF
RCVR
RF
B3
A3
A4
B3
RF
XMITR
RF
RCVR
XMITR
RCVR
A3
A4
B3
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
B4
B4
A4
RF
RCVR
RF
XMITR
B4
EN2/NC
GND2
EN2
GND2
NC
EN1
EN2
GND2
EN1
GND1
GND1
Si8640/45
Si8642
GND1
Si8641
Name
SOIC-16 Pin#
Type
Supply
Ground
Description
VDD1
1
Side 1 power supply.
Side 1 ground.
21
3
GND1
A1
A2
A3
A4
Digital Input
Digital Input
Digital I/O
Side 1 digital input.
Side 1 digital input.
4
5
Side 1 digital input or output.
Side 1 digital input or output.
6
Digital I/O
EN1/NC2
GND1
7
Digital Input
Side 1 active high enable. NC on Si8640/45.
Side 1 ground.
81
Ground
Ground
91
GND2
Side 2 ground.
EN2/NC2
B4
10
Digital Input
Side 2 active high enable. NC on Si8645.
11
12
13
14
Digital I/O
Digital I/O
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 digital output.
B3
B2
Digital Output
Digital Output
Ground
B1
Side 2 digital output.
151
16
GND2
Side 2 ground.
VDD2
Supply
Side 2 power supply.
Note:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be
connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
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Rev. 2.11 | 28
Si864x Data Sheet
Package Outline (16-Pin Wide Body SOIC)
6. Package Outline (16-Pin Wide Body SOIC)
The figure below illustrates the package details for the the Si86xx digital isolator in a 16-pin wide-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
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Si864x Data Sheet
Package Outline (16-Pin Wide Body SOIC)
Table 6.1. 16-Pin Wide Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Si864x Data Sheet
Land Pattern (16-Pin Wide Body SOIC)
7. Land Pattern (16-Pin Wide Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin wide-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC PCB Land Pattern
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.11 | 31
Si864x Data Sheet
Package Outline (16-Pin Narrow Body SOIC)
8. Package Outline (16-Pin Narrow Body SOIC)
The figure below illustrates the package details for the Si86xx in a 16-pin narrow-body SOIC package. The table lists the values for the
dimensions shown in the illustration.
Figure 8.1. 16-Pin Narrow Body SOIC
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Si864x Data Sheet
Package Outline (16-Pin Narrow Body SOIC)
Table 8.1. 16-Pin Narrow Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
h
0.25 BSC
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si864x Data Sheet
Land Pattern (16-Pin Narrow Body SOIC)
9. Land Pattern (16-Pin Narrow Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin narrow-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 9.1. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 9.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.11 | 34
Si864x Data Sheet
Package Outline (16-Pin QSOP)
10. Package Outline (16-Pin QSOP)
The figure below illustrates the package details for the Si86xx in a 16-pin QSOP package. The table lists the values for the dimensions
shown in the illustration.
Figure 10.1. 16-Pin QSOP Package
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Rev. 2.11 | 35
Si864x Data Sheet
Package Outline (16-Pin QSOP)
Table 10.1. 16-Pin QSOP Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
Max
1.75
0.25
—
A
A1
A2
b
—
0.10
1.25
0.20
0.30
0.25
c
0.17
D
4.89 BSC
6.00 BSC
3.90 BSC
0.635 BSC
0.40
E
E1
e
L
1.27
L2
h
0.25 BSC
0.25
0.50
8°
θ
0°
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si864x Data Sheet
Land Pattern (16-Pin QSOP)
11. Land Pattern (16-Pin QSOP)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin QSOP package. The table lists the values
for the dimensions shown in the illustration.
Figure 11.1. 16-Pin QSOP PCB Land Pattern
Table 11.1. 16-Pin QSOP Land Pattern Dimensions1, 2
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
C1
E
0.635
0.40
X1
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si864x Data Sheet
Top Marking (16-Pin Wide Body SOIC)
12. Top Marking (16-Pin Wide Body SOIC)
Si86XYSV
YYWWRTTTTT
e4
TW
Figure 12.1. 16-Pin Wide Body SOIC Top Marking
Table 12.1. 16-Pin Wide Body SOIC Top Marking Explanation
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4)
Y = # of reverse channels (5, 2, 1, 0)1
Base Part Number
Line 1 Marking: Ordering Options
(See 1. Ordering Guide for more information).
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV; T = 5.0 kV with
10 kV surge capability.
YY = Year
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
WW = Workweek
Line 2 Marking:
Manufacturing code from assembly house.
“R” indicates revision.
RTTTTT = Mfg Code
Circle = 1.7 mm Diameter
“e4” Pb-Free Symbol.
Line 3Marking: (Center-Justified)
Country of Origin ISO Code Abbreviation
TW = Taiwan as shown, TH = Thailand
Note:
1. Si8645 has 0 reverse channels.
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Si864x Data Sheet
Top Marking (16-Pin Narrow Body SOIC)
13. Top Marking (16-Pin Narrow Body SOIC)
Si86XYSV
YYWWRTTTTT
e3
Figure 13.1. 16-Pin Narrow Body SOIC Top Marking
Table 13.1. 16-Pin Narrow Body SOIC Top Marking Explanation
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4)
Y = # of reverse channels (5, 2, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
Base Part Number
Line 1 Marking: Ordering Options
(See 1. Ordering Guide for more information).
A = 1 kV; B = 2.5 kV; C = 3.75 kV
“e3” Pb-Free Symbol
Circle = 1.2 mm Diameter
YY = Year
Assigned by the assembly subcontractor. Corresponds to the
year and work week of the mold date.
Line 2 Marking: WW = Work Week
Manufacturing code from assembly house.
“R” indicates revision.
RTTTTT = Mfg Code
Note:
1. Si8645 has 0 reverse channels.
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Rev. 2.11 | 39
Si864x Data Sheet
Top Marking (16-Pin QSOP)
14. Top Marking (16-Pin QSOP)
Figure 14.1. 16-Pin QSOP Top Marking
Table 14.1. 16-Pin QSOP Top Marking Explanation
86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4)
Base Part Number
Y = # of reverse channels (5, 2, 1, 0)1
Ordering Options
Line 1 Marking:
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating.
(See 1. Ordering Guide for more information.)
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Manufacturing code from assembly house.
“R” indicates revision.
Line 2 Marking: RTTTTT = Mfg Code
YY = Year
Line 3 Marking:
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
WW = Work Week
Note:
1. Si8645 has 0 reverse channels.
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Rev. 2.11 | 40
Si864x Data Sheet
Revision History
15. Revision History
Revision 2.11
November 2017
• Added new table to Ordering Guide for Automotive-Grade OPN options
Revision 2.1
October 18, 2017
• Added new OPNs in Ordering Guide for IU (QSOP) and IS2 (8 mm creepage WB SOIC) package options.
• Added 62368-1 references throughout.
• Removed 61010-1 references throughout.
Revision 2.0
November 30, 2016
Added note to Table 1.1 Ordering Guide for Valid OPNs1, 2 on page 2 for denoting tape and reel marking.
•
Revision 1.9
November 18, 2015
• Deleted duplicate Si8641BB-B-IU OPN listing and corrected Si8645BB-B-IU listing in 1. Ordering Guide.
• Added QSOP-16 information to Table 4.7 IEC 60664-1 Ratings on page 24.
Added QSOP-16 information to Table 4.8 VDE 0884-10 Insulation Characteristics for Si86xxxx 1 on page 25.
Added QSOP-16 information to Table 4.9 VDE 0884-10 Safety Limiting Values 1 on page 25.
•
•
• Added QSOP-16 reference to Figure 4.5 (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per VDE 0884-10 on page 26.
Revision 1.8
October 29, 2015
• Added product options Si8641BB-B-IU, Si8645BB-B-IU and Si864xxT in 1. Ordering Guide.
• Added spec line items for Input and Enable Leakage Currents pertaining to Si864xxT in Electrical Specifications.
• Added new spec for tSD in 4. Electrical Specifications.
• Updated IEC 60747-5-2 to IEC 60747-5-5 throughout document.
Revision 1.7
June 18, 2015
• Updated Table 5 on page 14.
• Added CQC certificate numbers.
• Updated "4. Ordering Guide" on page 10.
• Added Si8640BA OPN.
• Removed references to moisture sensitivity levels.
• Removed Note 2.
Revision 1.6
September 25, 2013
• Added Figure 3, “Common Mode Transient Immunity Test Circuit,” on page 7.
• Added references to CQC throughout.
• Added references to 2.5 kVRMS devices throughout.
• Updated "4. Ordering Guide" on page 10.
• Updated "11.1. Top Marking (16-Pin Wide Body SOIC)" on page 20.
Revision 1.5
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Rev. 2.11 | 41
Si864x Data Sheet
Revision History
October 3, 2012
• Updated "4. Ordering Guide" on page 10.
• Updated "11.5. Top Marking (16-Pin QSOP)" on page 22.
Revision 1.4
June 26, 2012
• Updated Table 11 on page 18.
• Added junction temperature spec.
• Updated "2.3.1. Supply Bypass" on page 7.
• Removed “3.3.2 Pin Connections” on page 23.
• Updated "3. Pin Descriptions" on page 9.
• Updated table notes.
• Updated "4. Ordering Guide" on page 10.
• Removed Rev A devices.
• Updated "5. Package Outline: 16-Pin Wide Body SOIC" on page 12.
• Updated Top Marks.
• Added revision description.
Revision 1.3
March 21, 2012
• Updated "4. Ordering Guide" on page 10 to include MSL2A.
Revision 1.2
February 15, 2012
• Updated Table 3, “Ordering Guide for Valid OPNs” on page 10.
• Updated Note 1 with MSL2A.
• Updated Current Revision Devices.
Revision 1.1
September 14, 2011
• Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 8.
• Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 11.
Revision 1.0
July 14, 2011
• Reordered spec tables to conform to new convention.
• Removed “pending” throughout document.
Revision 0.2
March 31, 2011
• Added chip graphics on page 1.
• Moved Tables 1 and 11 to page 18.
• Updated Table 6, “Insulation and Safety-Related Specifications,” on page 15.
• Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 16.
• Moved Table 1 to page 4.
• Moved Table 2 to page 5.
• Moved “Typical Performance Characteristics” to page 8.
• Updated "3. Pin Descriptions" on page 9.
• Updated "4. Ordering Guide" on page 10.
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Rev. 2.11 | 42
Si864x Data Sheet
Revision History
Revision 0.1
September 15, 2010
• Initial release.
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Rev. 2.11 | 43
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri and others are trademarks or registered
trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other
products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
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USA
http://www.silabs.com
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