SI8661BB-B-IUR [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, QSOP-16;
| 型号： | SI8661BB-B-IUR |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO16, QSOP-16 光电二极管 |
| 文件： | 总43页 (文件大小：991K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8660/61/62/63 Data Sheet
Low Power Six-Channel Digital Isolator
KEY FEATURES
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages over legacy isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges and throughout device service life for
ease of design and highly uniform performance. All device versions have Schmitt trigger
inputs for high noise immunity and only require VDD bypass capacitors.
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
• Up to 5000 V
isolation
RMS
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Ordering options include a choice of isolation ratings (1.0, 2.5, 3.75 and
5 kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products >1 kVRMS are safety certified by UL, CSA, VDE, and CQC, and
products in wide-body packages support reinforced insulation withstanding up to 5
• 60-year life at rated working voltage
• High electromagnetic immunity
• Ultra low power (typical)
• 5 V Operation
kVRMS
.
• 1.6 mA per channel at 1 Mbps
• 5.5 mA per channel at 100 Mbps
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
• 2.5 V Operation
• 1.5 mA per channel at 1 Mbps
• 3.5 mA per channel at 100 Mbps
• Schmitt trigger inputs
Automotive Applications
Industrial Applications
• On-board chargers
• Industrial automation systems
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Battery management systems
• Medical electronics
• Charging stations
• Isolated switch mode supplies
• Precise timing (typical)
• 10 ns propagation delay
• Traction inverters
• Isolated ADC, DAC
• Hybrid Electric Vehicles
• Motor control
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Battery Electric Vehicles
• Power inverters
• Communication systems
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• Wide temperature range
• –40 to 125 °C
• IEC 60950-1, 62368-1, 60601-1 (re-
inforced insulation)
• RoHS-compliant packages
• SOIC-16 wide body
• VDE certification conformity
• VDE 0884-10
• SOIC-16 narrow body
• QSOP-16
• EN60950-1 (reinforced insulation)
• CQC certification approval
• GB4943.1
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• IMDS and CAMDS listing support
silabs.com | Building a more connected world.
Rev. 1.71
Si8660/61/62/63 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs 1,2, 3
Ordering Part Num- Number of Number of
Max Data
Rate
(Mbps)
Default
Output
State
Isolation Rating
(kV)
Temp (°C)
Package
ber (OPN)
Inputs
Inputs
VDD1 Side VDD2 Side
QSOP-16 Packages
Si8660BB-B-IU
Si8660EB-B-IU
Si8661BB-B-IU
Si8661EB-B-IU
Si8662BB-B-IU
Si8662EB-B-IU
Si8663BB-B-IU
Si8663EB-B-IU
SOIC-16 Packages
Si8660BA-B-IS1
Si8660BB-B-IS1
Si8660BC-B-IS1
Si8660EC-B-IS1
Si8660BD-B-IS
Si8660ED-B-IS
Si8661BB-B-IS1
Si8661BC-B-IS1
Si8661EC-B-IS1
Si8661BD-B-IS
Si8661ED-B-IS
Si8661BD-B-IS2
6
6
5
5
4
4
3
3
0
0
1
1
2
2
3
3
150
150
150
150
150
150
150
150
Low
High
Low
High
Low
High
Low
High
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
QSOP-16
6
6
6
6
6
6
5
5
5
5
5
5
0
0
0
0
0
0
1
1
1
1
1
1
150
150
150
150
150
150
150
150
150
150
150
150
Low
Low
Low
High
Low
High
Low
Low
High
Low
High
Low
1.0
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
NB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
3.75
3.75
5.0
5.0
2.5
3.75
3.75
5.0
5.0
5.0
WB SOIC-16
(8 mm cree-
page)4
Si8662BB-B-IS1
Si8662BC-B-IS1
Si8662EC-B-IS1
Si8662BD-B-IS
Si8662ED-B-IS
Si8663BB-B-IS1
Si8663BC-B-IS1
Si8663EC-B-IS1
Si8663BD-B-IS
4
4
4
4
4
3
3
3
3
2
2
2
2
2
3
3
3
3
150
150
150
150
150
150
150
150
150
Low
Low
High
Low
High
Low
Low
High
Low
2.5
3.75
3.75
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
5.0
2.5
3.75
3.75
5.0
silabs.com | Building a more connected world.
Rev. 1.71 | 2
Si8660/61/62/63 Data Sheet
Ordering Guide
Ordering Part Num- Number of Number of
Max Data
Rate
(Mbps)
Default
Output
State
Isolation Rating
(kV)
Temp (°C)
Package
ber (OPN)
Inputs
Inputs
VDD1 Side VDD2 Side
Si8663ED-B-IS
3
3
150
High
5.0
–40 to 125 °C
WB SOIC-16
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. The package designated IS2 has a design that eliminates tie bars, thus allowing for extra creepage distance while maintaining
standard WB SOIC-16 package dimensions and land pattern.
silabs.com | Building a more connected world.
Rev. 1.71 | 3
Si8660/61/62/63 Data Sheet
Ordering Guide
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part
Number (OPN)
Number of Number of
Inputs Inputs
VDD1 Side VDD2 Side
Max Data
Rate
(Mbps)
Default
Output
State
Isolation rating
(kV)
Temp (°C)
Package
SOIC-16 Packages
Si8660BC-AS1
Si8661BB-AS1
Si8662BD-AS
Si8663BD-AS
Note:
6
5
4
3
0
1
2
3
150
150
150
150
Low
Low
Low
Low
3.75
2.5
5.0
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
silabs.com | Building a more connected world.
Rev. 1.71 | 4
Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.1 Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . .10
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. Package Outline (16-Pin Wide Body SOIC)
7. Land Pattern (16-Pin Wide-Body SOIC). . . . . . . . . . . . . . . . . . . . . 31
8. Package Outline (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . .32
. . . . . . . . . . . . . . . . . . . 29
9. Land Pattern (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . 34
10. Package Outline (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . 35
11. Land Pattern (16-Pin QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . 37
12. Top Marking (16-Pin Wide Body SOIC)
13. Top Marking (16-Pin Narrow Body SOIC)
. . . . . . . . . . . . . . . . . . . . 38
. . . . . . . . . . . . . . . . . . .39
14. Top Marking (16-Pin QSOP)
. . . . . . . . . . . . . . . . . . . . . . . . 40
15. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
silabs.com | Building a more connected world.
Rev. 1.71 | 5
Si8660/61/62/63 Data Sheet
Functional Description
2. Functional Description
2.1 Theory of Operation
The operation of an Si866x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si866x channel is shown in the figure below.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 2.2. Modulation Scheme
silabs.com | Building a more connected world.
Rev. 1.71 | 6
Si8660/61/62/63 Data Sheet
Functional Description
2.2 Eye Diagram
The figure below illustrates an eye-diagram taken on an Si8660. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8660 were captured on an oscilloscope. The re-
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
silabs.com | Building a more connected world.
Rev. 1.71 | 7
Si8660/61/62/63 Data Sheet
Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 9, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to
determine outputs when power supply (VDD) is not present.
Table 3.1. Si866x Logic Operation
VI Input 1,2
VDDI State1,3,4
VDDO State1,3,4
VO Output1,2
Comments
H
L
P
P
P
P
P
H
L
Normal operation.
X 5
L6
H6
UP
Upon transition of VDDI from unpowered to pow-
ered, VO returns to the same state as VI in less
than 1 µs.
X5
P
UP
Undetermined
Upon transition of VDDO from unpowered to pow-
ered, VO returns to the same state as VI within 1
µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See 1. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default
output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devi-
ces, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/
outputs.
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
silabs.com | Building a more connected world.
Rev. 1.71 | 8
Si8660/61/62/63 Data Sheet
Device Operation
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.5 Regulatory Information 1 on
page 23 and Table 4.6 Insulation and Safety-Related Specifications on page 23 detail the working voltage and creepage/clearance
capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted
by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1,
60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
3.3.1 Supply Bypass
The Si866x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed
as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series
with the inputs and outputs if the system is excessively noisy.
3.3.2 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-
chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
3.4 Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)
can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si866x Logic Operation on page 8 and
1. Ordering Guide for more information.
silabs.com | Building a more connected world.
Rev. 1.71 | 9
Si8660/61/62/63 Data Sheet
Device Operation
3.5 Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to the electrical
characteristics tables for actual specification limits.
Figure 3.2. Si8660 Typical VDD1 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
Figure 3.3. Si8661 Typical VDD1 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 3.4. Si8662 Typical VDD1 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
Figure 3.5. Si8660 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
(15 pF Load)
(15 pF Load)
silabs.com | Building a more connected world.
Rev. 1.71 | 10
Si8660/61/62/63 Data Sheet
Device Operation
Figure 3.7. Si8662 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
Figure 3.6. Si8661 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
(15 pF Load)
(15 pF Load)
Figure 3.9. Propagation Delay vs. Temperature
Figure 3.8. Si8663 Typical VDD1 or VDD2 Supply Current vs.
Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
silabs.com | Building a more connected world.
Rev. 1.71 | 11
Si8660/61/62/63 Data Sheet
Electrical Specifications
4. Electrical Specifications
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
TJ
Min
—
Typ
—
Max
150
125
5.5
Unit
°C
°C
V
Junction Operating Temperature
Ambient Operating Temperature 1
TA
–40
25
—
VDD1
VDD2
2.375
2.375
Supply Voltage
—
5.5
V
Note:
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply
voltage.
Table 4.2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
VDDUV+
VDDUV–
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
1.95
1.88
Typ
2.24
2.16
Max
2.375
2.325
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
V
VDD Undervoltage
Hysteresis
VDDHYS
VT+
50
1.4
1.0
70
95
1.9
1.4
mV
V
Positive-Going Input Threshold
All inputs rising
All inputs falling
1.67
1.23
Negative-Going
Input Threshold
VT–
V
VHYS
VIH
VIL
Input Hysteresis
0.38
0.44
—
0.50
—
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance 1
2.0
—
—
0.8
—
V
VOH
VOL
IL
VDD1,VDD2 – 0.4
loh = –4 mA
lol = 4 mA
4.8
0.2
—
V
—
—
—
0.4
±10
—
V
µA
Ω
ZO
50
DC Supply Current (All Inputs 0 V or at Supply)
Si8660Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
VDD2
VDD1
VDD2
mA
12.3
5.6
silabs.com | Building a more connected world.
Rev. 1.71 | 12
Si8660/61/62/63 Data Sheet
Electrical Specifications
Parameter
Si8661Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
VDD2
mA
VDD1
11.1
7.2
VDD2
Si8662Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
VDD2
mA
VDD1
10.5
8.4
VDD2
Si8663Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on all Outputs)
Si8660Bx, Ex
VDD1
mA
mA
mA
mA
—
—
5.0
4.2
7.0
5.9
VDD2
Si8661Bx, Ex
VDD1
—
—
4.9
4.6
6.9
6.4
VDD2
Si8662Bx, Ex
VDD1
—
—
5.1
4.7
7.1
6.6
VDD2
Si8663Bx, Ex
VDD1
—
—
4.9
4.9
6.8
6.8
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on all Outputs)
Si8660Bx, Ex
VDD1
mA
mA
—
—
5.0
5.9
7.0
8.3
VDD2
Si8661Bx, Ex
VDD1
—
—
5.2
6.1
7.3
8.5
VDD2
silabs.com | Building a more connected world.
Rev. 1.71 | 13
Si8660/61/62/63 Data Sheet
Electrical Specifications
Parameter
Si8662Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
mA
—
—
5.6
5.9
7.9
8.2
VDD2
Si8663Bx, Ex
VDD1
mA
—
—
5.7
5.7
8.0
8.0
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
mA
mA
mA
mA
—
5.0
7.0
VDD2
—
26.2
34.1
Si8661Bx, Ex
VDD1
—
—
8.8
23
11.8
29.8
VDD2
Si8662Bx, Ex
VDD1
—
—
12.8
19.4
16.6
25.2
VDD2
Si8663Bx, Ex
VDD1
—
—
16.4
16.4
21.3
21.3
VDD2
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate
Minimum Pulse Width
0
—
—
150
5.0
Mbps
ns
—
See Figure 4.1 Propagation
Delay Timing on page 15
tPHL, tPLH
Propagation Delay
5.0
—
8.0
0.2
13
ns
ns
Pulse Width Distortion
See Figure 4.1 Propagation
Delay Timing on page 15
PWD
tPSK(P-P)
tPSK
4.5
|tPLH - tPHL
|
Propagation Delay Skew 2
Channel-Channel Skew
All Models
—
—
2.0
0.4
4.5
2.5
ns
ns
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
(See Figure 4.1 Propagation
Delay Timing on page 15)
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
(See Figure 4.1 Propagation
Delay Timing on page 15)
tJIT(PK)
Peak Eye Diagram Jitter
See
350
silabs.com | Building a more connected world.
Rev. 1.71 | 14
Si8660/61/62/63 Data Sheet
Electrical Specifications
Parameter
Symbol
CMTI
tSU
Test Condition
Min
35
Typ
50
Max
—
Unit
kV/µs
µs
VI = VDD or 0 V
VCM = 1500 V
Common Mode
Transient Immunity
(See Figure 4.2 Common
Mode Transient Immunity
Test Circuit on page 16)
Startup Time 3
—
15
40
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 4.1. Propagation Delay Timing
silabs.com | Building a more connected world.
Rev. 1.71 | 15
Si8660/61/62/63 Data Sheet
Electrical Specifications
3 to 5 V
Supply
Si86xx
VDD1
VDD2
Input
Signal
Switch
INPUT
OUTPUT
3 to 5 V
Isolated
Supply
Oscilloscope
GND1
GND2
Isolated
Ground
High Voltage
Differential
Probe
Output
Input
Vcm Surge
Output
High Voltage
Surge Generator
Figure 4.2. Common Mode Transient Immunity Test Circuit
Table 4.3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
2.0
—
V
VIL
—
0.8
V
VOH
VDD1,VDD2 – 0.4
loh = –4 mA
lol = 4 mA
3.1
0.2
—
—
V
VOL
—
—
—
0.4
V
IL
±10
—
µA
Ω
ZO
50
Output Impedance
DC Supply Current (All Inputs 0 V or at Supply)
silabs.com | Building a more connected world.
Rev. 1.71 | 16
Si8660/61/62/63 Data Sheet
Electrical Specifications
Parameter
Si8660Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
VDD2
mA
VDD1
12.3
5.6
VDD2
Si8661Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
VDD2
mA
mA
mA
VDD1
11.1
7.2
VDD2
Si8662Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
VDD2
VDD1
10.5
8.4
VDD2
Si8663Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
VDD2
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
mA
mA
mA
mA
—
—
5.0
4.2
7.0
5.9
VDD2
Si8661Bx, Ex
VDD1
—
—
4.9
4.6
6.9
6.4
VDD2
Si8662Bx, Ex
VDD1
—
—
5.1
4.7
7.1
6.6
VDD2
Si8663Bx, Ex
VDD1
—
—
4.9
4.9
6.8
6.8
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
silabs.com | Building a more connected world.
Rev. 1.71 | 17
Si8660/61/62/63 Data Sheet
Electrical Specifications
Parameter
Si8660Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
mA
—
—
5.0
5.0
7.0
7.0
VDD2
Si8661Bx, Ex
VDD1
mA
mA
mA
—
—
5.0
5.3
7.0
7.4
VDD2
Si8662Bx, Ex
VDD1
—
—
5.3
5.2
7.4
7.3
VDD2
Si8663Bx, Ex
VDD1
—
—
5.2
5.2
7.3
7.3
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
mA
mA
mA
mA
—
5.0
7.0
VDD2
—
18.3
23.8
Si8661Bx, Ex
VDD1
—
—
7.4
9.9
VDD2
16.4
21.3
Si8662Bx, Ex
VDD1
—
—
10
13
VDD2
14.1
18.3
Si8663Bx, Ex
VDD1
—
—
12.3
12.3
15.9
15.9
VDD2
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate
Minimum Pulse Width
0
—
—
150
5.0
Mbps
ns
—
See Figure 4.1 Propagation
Delay Timing on page 15
tPHL, tPLH
Propagation Delay
5.0
—
8.0
0.2
13
ns
ns
Pulse Width Distortion
See Figure 4.1 Propagation
Delay Timing on page 15
PWD
tPSK(P-P)
tPSK
4.5
|tPLH - tPHL
|
Propagation Delay Skew 2
Channel-Channel Skew
All Models
—
—
2.0
0.4
4.5
2.5
ns
ns
silabs.com | Building a more connected world.
Rev. 1.71 | 18
Si8660/61/62/63 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
See Figure 4.1 Propagation
Delay Timing on page 15
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
See Figure 4.1 Propagation
Delay Timing on page 15
See Figure 2.3 Eye Diagram
on page 7
tJIT(PK)
Peak Eye Diagram Jitter
350
VI = VDD or 0 V
VCM = 1500 V (See Figure
4.2 Common Mode Transi-
ent Immunity Test Circuit on
page 16)
Common Mode Transient
Immunity
CMTI
tSU
35
—
50
15
—
kV/µs
µs
Startup Time 3
40
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
silabs.com | Building a more connected world.
Rev. 1.71 | 19
Si8660/61/62/63 Data Sheet
Electrical Specifications
Table 4.4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
Symbol
VDDUV+
VDDUV–
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
1.95
1.88
Typ
2.24
2.16
Max
2.375
2.325
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
V
VDD Undervoltage
Hysteresis
VDDHYS
50
70
95
mV
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
VHYS
VIH
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
1.4
0.50
—
V
V
1.0
0.38
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
2.0
—
V
VIL
—
0.8
—
V
VOH
VOL
IL
VDD1,VDD2 – 0.4
loh = –4 mA
lol = 4 mA
2.3
0.2
—
V
—
—
—
0.4
±10
—
V
µA
Ω
Output Impedance1
ZO
50
DC Supply Current (All Inputs 0 V or at Supply)
Si8660Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
VDD2
mA
mA
mA
VDD1
12.3
5.6
VDD2
Si8661Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
VDD2
VDD1
11.1
7.2
VDD2
Si8662Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
VDD2
VDD1
10.5
8.4
VDD2
silabs.com | Building a more connected world.
Rev. 1.71 | 20
Si8660/61/62/63 Data Sheet
Electrical Specifications
Parameter
Si8663Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
mA
mA
mA
mA
—
—
5.0
4.2
7.0
5.9
VDD2
Si8661Bx, Ex
VDD1
—
—
4.9
4.6
6.9
6.4
VDD2
Si8662Bx, Ex
VDD1
—
—
5.1
4.7
7.1
6.6
VDD2
Si8663Bx, Ex
VDD1
—
—
4.9
4.9
6.8
6.8
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
mA
mA
mA
mA
—
—
5.0
4.6
7.0
6.4
VDD2
Si8661Bx, Ex
VDD1
—
—
5.0
4.9
6.9
6.9
VDD2
Si8662Bx, Ex
VDD1
—
—
5.2
4.9
7.2
6.9
VDD2
Si8663Bx, Ex
VDD1
—
—
5.0
5.0
7.0
7.0
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
mA
—
5.0
7.0
VDD2
—
14.7
19.1
silabs.com | Building a more connected world.
Rev. 1.71 | 21
Si8660/61/62/63 Data Sheet
Electrical Specifications
Parameter
Si8661Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
mA
—
—
6.7
9.1
VDD2
13.4
17.4
Si8662Bx, Ex
VDD1
mA
mA
—
—
8.7
11.3
15.2
VDD2
11.7
Si8663Bx, Ex
VDD1
—
—
10.3
10.3
13.4
13.4
VDD2
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate
Minimum Pulse Width
0
—
—
150
5.0
Mbps
ns
—
See Figure 4.1 Propagation
Delay Timing on page 15
tPHL, tPLH
Propagation Delay
5.0
—
8.0
0.2
14
ns
ns
Pulse Width Distortion
See Figure 4.1 Propagation
Delay Timing on page 15
PWD
tPSK(P-P)
tPSK
5.0
|tPLH - tPHL
|
Propagation Delay Skew2
Channel-Channel Skew
All Models
—
—
2.0
0.4
5.0
2.5
ns
ns
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
See Figure 4.1 Propagation
Delay Timing on page 15
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
See Figure 4.1 Propagation
Delay Timing on page 15
See Figure 2.3 Eye Diagram
on page 7
tJIT(PK)
Peak Eye Diagram Jitter
350
VI = VDD or 0 V
VCM = 1500 V
Common Mode
Transient Immunity
CMTI
35
—
50
15
—
kV/µs
µs
(See Figure 4.2 Common
Mode Transient Immunity
Test Circuit on page 16)
Startup Time3
tSU
40
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
silabs.com | Building a more connected world.
Rev. 1.71 | 22
Si8660/61/62/63 Data Sheet
Electrical Specifications
Table 4.5. Regulatory Information 1
CSA
The Si866x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.
60950-1, 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).
VDE
The Si866x is certified according to VDE 0884-10. For more details, see certificate 40018443.
0884-10: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si866x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si866x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifi-
cations apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to
5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see 1. Ordering Guide.
Table 4.6. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
Unit
WB SOIC-16
NB SOIC-16
4.9
QSOP-16
3.6
Nominal External Air Gap (Clearance)1
CLR
CPG
8.0
8.0
mm
mm
Nominal External Tracking (Creepage) 1
Minimum Internal Gap
(Internal Clearance)
4.01
3.6
DTI
0.014
0.014
0.014
mm
VRMS
mm
Ω
Tracking Resistance
CTI or PTI
IEC60112
f = 1 MHz
600
0.019
1012
2.0
600
0.019
1012
2.0
600
0.031
1012
2.0
Erosion Depth
ED
RIO
CIO
CI
Resistance (Input-Output)2
Capacitance (Input-Output)2
Input Capacitance3
pF
4.0
4.0
4.0
pF
silabs.com | Building a more connected world.
Rev. 1.71 | 23
Si8660/61/62/63 Data Sheet
Electrical Specifications
Value
Parameter
Symbol
Test Condition
Unit
WB SOIC-16
NB SOIC-16
QSOP-16
Note:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as 4.7 mm minimum for the NB SOIC-16 package and QSOP-16 packages and 8.5 mm minimum for the WB SOIC-16
package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance
and creepage of the WB SOIC-16 package with designation "IS2" as 8 mm minimum. CSA certifies the clearance and creepage
limits as 3.9 mm minimum for the NB SOIC 16, 3.6 mm minimum for the QSOP-16, and 7.6 mm minimum for the WB SOIC-16
package with package designation "IS" as listed in the data sheet.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form
the first termina and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between
these two terminals.
3. Measured from input pin to ground.
Table 4.7. IEC 60664-1 Ratings
Specification
Parameter
Test Conditions
Material Group
WB SOIC-16
NB SOIC-16
QSOP-16
Basic Isolation Group
I
I
I
Rated Mains Voltages < 150
VRMS
I-IV
I-IV
I-III
I-III
I-IV
I-III
I-II
I-IV
I-III
I-II
Rated Mains Voltages < 300
VRMS
Installation Classification
Rated Mains Voltages < 400
VRMS
Rated Mains Voltages < 600
VRMS
I-II
I-II
silabs.com | Building a more connected world.
Rev. 1.71 | 24
Si8660/61/62/63 Data Sheet
Electrical Specifications
Table 4.8. VDE 0884-10 Insulation Characteristics for Si86xxxx1
Characteristic
WB SOIC-16 NB SOIC-16 QSOP-16
Parameter
Symbol
Test Condition
Unit
Maximum Working Insulation
Voltage
VIORM
1200
630
630
Vpeak
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
t = 60 sec
VPR
Input to Output Test Voltage
2250
6000
1182
6000
1182
6000
Vpeak
VIOTM
Transient Overvoltage
Surge Voltage
Vpeak
Vpeak
Tested per IEC 60065 with surge
voltage of 1.2 µs/50 µs
VIOSM
Si866xxB/C/D tested with 4000 V
3077
2
3077
2
3077
2
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO
= 500 V
>109
>109
>109
RS
Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.
Table 4.9. VDE 0884-10 Safety Limiting Values1
Max
WB SOIC-16 NB SOIC-16 QSOP-16
Parameter
Symbol
Test Condition
Unit
TS
Case Temperature
150
220
415
150
215
415
150
215
415
°C
θJA = 100 °C/W (WB SOIC-16)
105 °C/W (NB SOIC-16, QSOP-16)
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Safety Input, Output, or Supply
Current
IS
mA
Device Power Dissipation2
PD
mW
Note:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.3 (WB SOIC-16) Thermal Derat-
ing Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on page 26 and Figure 4.4 (NB
SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10
on page 26.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
Table 4.10. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-16/QSOP-16
Unit
θJA
IC Junction-to-Air Thermal Resistance
100
105
°C/W
silabs.com | Building a more connected world.
Rev. 1.71 | 25
Si8660/61/62/63 Data Sheet
Electrical Specifications
500
450
370
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
400
300
200
100
0
220
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 4.3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE
0884-10
500
430
VDD1, VDD2 = 2.70 V
400
360
VDD1, VDD2 = 3.6 V
300
215
200
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
200
Temperature (ºC)
Figure 4.4. (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per VDE 0884-10
silabs.com | Building a more connected world.
Rev. 1.71 | 26
Si8660/61/62/63 Data Sheet
Electrical Specifications
Table 4.11. Absolute Maximum Ratings 1
Parameter
Storage Temperature 2
Symbol
Min
Max
Unit
°C
°C
°C
V
TSTG
–65
–40
—
150
125
TA
Ambient Temperature Under Bias
Junction Temperature
Supply Voltage
TJ
150
VDD1, VDD2
–0.5
–0.5
–0.5
—
7.0
VI
VO
IO
VDD + 0.5
VDD + 0.5
10
Input Voltage
V
Output Voltage
V
Output Current Drive Channel
Lead Solder Temperature (10 s)
mA
°C
—
260
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16, QSOP-16
VRMS
—
—
4500
6500
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
silabs.com | Building a more connected world.
Rev. 1.71 | 27
Si8660/61/62/63 Data Sheet
Pin Descriptions
5. Pin Descriptions
VDD1
VDD1
A1
A2
A3
A4
A5
A6
VDD2
B1
B2
B3
B4
B5
B6
VDD2
B1
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A1
A2
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B2
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B3
A3
A4
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B4
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A5
B5
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
A6
B6
GND2 GND1
GND2
GND1
Si8660
Si8661
VDD1
VDD1
VDD2
B1
VDD2
B1
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
A1
A2
A1
A2
I
s
o
l
a
t
I
s
o
l
a
t
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B2
B2
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
A3
A4
B3
A3
A4
B3
RF
RCVR
RF
RCVR
RF
XMITR
RF
XMITR
B4
B4
i
o
n
i
o
n
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
A5
B5
A5
B5
RF
RCVR
RF
RF
RCVR
RF
A6
B6
A6
B6
XMITR
XMITR
GND2
GND1
GND2
GND1
Si8662
Si8663
Figure 5.1. Si866x Pinout
Table 5.1. Si866x Pin Descriptions
Name
VDD1
A1
SOIC-16 Pin#
Type
Description
1
2
Supply
Digital Input
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital I/O
Ground
Side 1 power supply.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
A2
3
A3
4
A4
5
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 ground.
A5
6
A6
7
GND1
GND2
B6
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital I/O
Digital I/O
Digital I/O
Digital Output
Digital Output
Digital Output
Supply
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 digital output.
B5
B4
B3
B2
Side 2 digital output.
B1
Side 2 digital output.
VDD2
Side 2 power supply.
silabs.com | Building a more connected world.
Rev. 1.71 | 28
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin Wide Body SOIC)
6. Package Outline (16-Pin Wide Body SOIC)
The figure below illustrates the package details for the Si86xx digital isolator in a 16-pin wide-body SOIC package. The table below lists
the values for the dimensions shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
silabs.com | Building a more connected world.
Rev. 1.71 | 29
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin Wide Body SOIC)
Table 6.1. 16-Pin Wide Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
ααα
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
silabs.com | Building a more connected world.
Rev. 1.71 | 30
Si8660/61/62/63 Data Sheet
Land Pattern (16-Pin Wide-Body SOIC)
7. Land Pattern (16-Pin Wide-Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin wide-body SOIC package. The table below
lists the values for the dimensions shown in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC PCB Land Pattern
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
silabs.com | Building a more connected world.
Rev. 1.71 | 31
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin Narrow Body SOIC)
8. Package Outline (16-Pin Narrow Body SOIC)
The figure below illustrates the package details for the Si86xx in a 16-pin narrow-body SOIC package. The table below lists the values
for the dimensions shown in the illustration.
Figure 8.1. 16-Pin Narrow Body SOIC
silabs.com | Building a more connected world.
Rev. 1.71 | 32
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin Narrow Body SOIC)
Table 8.1. 16-Pin Narrow Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
h
0.25 BSC
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.71 | 33
Si8660/61/62/63 Data Sheet
Land Pattern (16-Pin Narrow Body SOIC)
9. Land Pattern (16-Pin Narrow Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin narrow-body SOIC package. The table
below lists the values for the dimensions shown in the illustration.
Figure 9.1. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 9.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
silabs.com | Building a more connected world.
Rev. 1.71 | 34
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin QSOP)
10. Package Outline (16-Pin QSOP)
The figure below illustrates the package details for the Si86xx in a 16-pin QSOP package. The table lists the values for the dimensions
shown in the illustration.
Figure 10.1. 16-Pin QSOP Package
silabs.com | Building a more connected world.
Rev. 1.71 | 35
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin QSOP)
Table 10.1. 16-Pin QSOP Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
Max
1.75
0.25
—
A
A1
A2
b
—
0.10
1.25
0.20
0.30
0.25
c
0.17
D
4.89 BSC
6.00 BSC
3.90 BSC
0.635 BSC
0.40
E
E1
e
L
1.27
L2
h
0.25 BSC
0.25
0.50
8°
θ
0°
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.71 | 36
Si8660/61/62/63 Data Sheet
Land Pattern (16-Pin QSOP)
11. Land Pattern (16-Pin QSOP)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin QSOP package. The table lists the values
for the dimensions shown in the illustration.
Figure 11.1. 16-Pin QSOP PCB Land Pattern
Table 11.1. 16-Pin QSOP Land Pattern Dimensions1, 2
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
C1
E
0.635
0.40
X1
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
silabs.com | Building a more connected world.
Rev. 1.71 | 37
Si8660/61/62/63 Data Sheet
Top Marking (16-Pin Wide Body SOIC)
12. Top Marking (16-Pin Wide Body SOIC)
Si86XYSV
YYWWRTTTTT
TW
e4
Figure 12.1. 16-Pin Wide Body SOIC Top Marking
Table 12.1. 16-Pin Wide Body SOIC Top Marking Explanation
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (6)
Y = # of reverse channels (3, 2, 1, 0)
Base Part Number
S = Speed Grade
Ordering Options
Line 1 Marking:
A = 1 Mbps
(See 1. Ordering Guide for more information.)
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
YY = Year
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
WW = Workweek
Line 2 Marking:
Manufacturing code from assembly house
“R” indicates revision
RTTTTT = Mfg Code
Circle = 1.7 mm Diameter
“e4” Pb-Free Symbol
Line 3 Marking: (Center-Justified)
Country of Origin ISO Code Abbreviation
TW = Taiwan as shown, TH = Thailand
silabs.com | Building a more connected world.
Rev. 1.71 | 38
Si8660/61/62/63 Data Sheet
Top Marking (16-Pin Narrow Body SOIC)
13. Top Marking (16-Pin Narrow Body SOIC)
Si86XYSV
YYWWRTTTTT
e3
Figure 13.1. 16-Pin Narrow Body SOIC Top Marking
Table 13.1. 16-Pin Narrow Body SOIC Top Marking Explanation
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (6)
Y = # of reverse channels (3, 2, 1, 0)
Base Part Number
S = Speed Grade
Ordering Options
Line 1 Marking:
A = 1 Mbps
(See 1. Ordering Guide for more information.)
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
“e3” Pb-Free Symbol
Circle = 1.2 mm Diameter
YY = Year
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
WW = Work Week
Line 2 Marking:
Manufacturing code from assembly house.
“R” indicates revision.
RTTTTT = Mfg Code
Circle = 1.2 mm diameter
“e3” Pb-Free Symbol.
silabs.com | Building a more connected world.
Rev. 1.71 | 39
Si8660/61/62/63 Data Sheet
Top Marking (16-Pin QSOP)
14. Top Marking (16-Pin QSOP)
Figure 14.1. 16-Pin QSOP Top Marking
Table 14.1. 16-Pin QSOP Top Marking Explanation
86 = Isolator product series
XY = Channel Configuration
X = # of data channels (6)
Base Part Number
Y = # of reverse channels (3, 2, 1, 0)
Line 1 Marking: Ordering Options
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
(See 1. Ordering Guide for more information).
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Manufacturing code from assembly house
“R” indicates revision
Line 2 Marking: RTTTTT = Mfg Code
YY = Year
Line 3 Marking:
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
WW = Work Week
silabs.com | Building a more connected world.
Rev. 1.71 | 40
Si8660/61/62/63 Data Sheet
Revision History
15. Revision History
Revision 1.71
January 2018
• Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 1.7
October 18, 2017
• Added new OPNs in Ordering Guide for IU (QSOP) and IS2 (8 mm creepage WB SOIC) package options.
• Added 62368-1 references throughout.
• Removed 61010-1 references throughout.
• Added QSOP-16 package information.
Revision 1.6
June 18, 2015
Updated Table 4.5 Regulatory Information 1 on page 23.
• Added CQC certificate numbers.
•
• Updated 1. Ordering Guide.
• Removed references to moisture sensitivity levels.
• Removed Note 2.
Added note to Table 1.1 Ordering Guide for Valid OPNs 1,2, 3 on page 2 for denoting tape and reel marking.
•
Revision 1.5
September 25, 2013
• Added Figure 4.2 Common Mode Transient Immunity Test Circuit on page 16.
• Added references to CQC throughout.
• Added references to 2.5 kVRMS devices throughout.
• Updated 1. Ordering Guide.
• Updated 12. Top Marking (16-Pin Wide Body SOIC).
Revision 1.4
June 26, 2012
Updated Table 4.11 Absolute Maximum Ratings 1 on page 27.
• Added junction temperature spec.
•
• Updated 3.3.1 Supply Bypass.
• Removed “3.3.2. Pin Connections”.
• Updated 1. Ordering Guide.
• Removed Rev A devices.
• Updated 6. Package Outline (16-Pin Wide Body SOIC).
• Updated Top Marks.
• Added revision description.
Revision 1.3
March 21, 2012
• Updated 1. Ordering Guide to include MSL2A.
Revision 1.2
September 14, 2011
• Reordered spec tables to conform to new convention.
• Removed “pending” throughout document.
silabs.com | Building a more connected world.
Rev. 1.71 | 41
Si8660/61/62/63 Data Sheet
Revision History
Revision 1.1
July 14, 2011
• Reordered spec tables to conform to new convention.
• Removed “pending” throughout document.
Revision 1.0
March 31, 2011
• Added chip graphics on front page.
• Updated features list on front page.
Moved Table 4.1 Recommended Operating Conditions on page 12 and Table 4.11 Absolute Maximum Ratings 1 on page 27.
•
• Updated 4. Electrical Specifications.
• Moved Table 3.1 Si866x Logic Operation on page 8.
• Moved and updated 3.5 Typical Performance Characteristics.
• Updated Table 5.1 Si866x Pin Descriptions on page 28.
• Updated 1. Ordering Guide.
• Removed references to QSOP-16 package.
Revision 0.1
September 15, 2010
• Initial release.
silabs.com | Building a more connected world.
Rev. 1.71 | 42
Smart.
Connected.
Energy-Friendly.
Products
www.silabs.com/products
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri and others are trademarks or registered
trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other
products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
相关型号：
©2020 ICPDF网 联系我们和版权申明