SI88240ED-IS [SILICON]
QUAD DIGITAL ISOLATORS WITH DC-DC CONVERTER;
| 型号： | SI88240ED-IS |
| 厂家： | 
SILICON |
| 描述： | QUAD DIGITAL ISOLATORS WITH DC-DC CONVERTER DC-DC转换器 |
| 文件： | 总48页 (文件大小：929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si88x4x
QUAD DIGITAL ISOLATORS WITH DC-DC CONVERTER
Features
High-speed isolators with
integrated dc-dc converter
Fully-integrated secondary sensing
Highly-reliable: 100 year lifetime
High electromagnetic immunity and
ultra-low emissions
feedback-controlled converter with RoHS compliant packages
dithering for low EMI
SOIC-20 wide body
SOIC-24 wide body
Isolation of up to 5000 Vrms
High transient immunity of
100 kV/µs (typical)
dc-dc converter peak efficiency of
83% with external power switch
Up to 5 W isolated power with
external power switch
Ordering Information:
Options include dc-dc shutdown,
frequency control, and soft start
Standard Voltage Conversion
3/5 V to isolated 3/5 V
24 V to isolated 3/5 V supported
Precise timing on digital isolators
0–100 Mbps
AEC-Q100 qualified
Wide temp range
–40 to +125 °C
See page 38.
Pin Assignments
See page 33
18 ns typical prop delay
1
2
3
4
5
6
20
19
GNDP
VSW
VDDP
VDDA
GNDA
SH
GNDB
VDDB
Applications
18 DNC
17 NC
Industrial automation systems
Hybrid electric and electric
vehicles
Inverters
Data acquisition
Motor control
PLCs, distributed control systems
VSNS
16
15 COMP
B1
Isolated power supplies
HF
XMTR
HF
RCVR
A1
14
13 B2
7
8
HF
XMTR
HF
RCVR
A2
Safety Approval (Pending)
HF
XMTR
HF
RCVR
A3
B3
B4
9
12
11
UL 1577 recognized
VDE certification conformity
VDE 0884-10
CQC certification approval
GB4943.1
HF
XMTR
HF
RCVR
A4
10
Up to 5000 Vrms for 1 minute
CSA component notice 5A
approval
Si88240
Patents pending
Description
The Si88xx integrates Silicon Labs’ proven digital isolator technology with an
on-chip isolated dc-dc converter that provides regulated output voltages of
3.3 or 5.0 V (or >5 V with external components) at peak output power levels
of up to 5 W. These devices provide up to four digital channels. The dc-dc
converter has user-adjustable frequency for minimizing emissions, a soft-start
function for safety, a shut-down option and loop compensation. The device
requires only minimal passive components and a miniature transformer.
The ultra-low-power digital isolation channels offer substantial data rate,
propagation delay, size and reliability advantages over legacy isolation
technologies. Data rates up to 100 Mbps max are supported, and all devices
achieve propagation delays of only 23 ns max. Ordering options include a
choice of dc-dc converter features, isolation channel configurations and a fail-
safe mode. All products are certified by UL, CSA, VDE, and CQC.
Preliminary Rev. 0.6 7/15
Copyright © 2015 by Silicon Laboratories
Si88x4x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si88x4x
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.2. Digital Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.3. DC-DC Converter Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.4. Transformer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3. Digital Isolator Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6. Package Outline: 20-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7. Land Pattern: 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8. Package Outline: 24-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
9. Land Pattern: 24-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
10. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
10.1. Si88x4x Top Marking (20-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . .45
10.2. Top Marking Explanation (20-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .45
10.3. Si88x4x Top Marking (24-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . .46
10.4. Top Marking Explanation (24-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .46
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
2
Preliminary Rev. 0.6
Si88x4x
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Power Input Voltage
Symbol
Min
–40
3.0
3.0
3.0
Typ
25
—
Max
125
5.5
Unit
°C
V
T
A
VDDP
VDDA
VDDB
Supply Voltage
—
5.5
V
—
5.5
V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics1
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC/DC Converter
Switching Frequency
Si8824x, Si8844x
FSW
FSW
250
200
kHz
kHz
Switching Frequency
Si8834x, Si8864x
RFSW = 23.3 k
180
450
810
220
550
990
FSW = 1025.5/(RFSW x CSS)
CSS = 220 nF (see Figure 9)
(1% tolerance on BOM)
RFSW = 9.3 k
500
900
kHz
kHz
FSW = 1025.5/(RFSW x CSS)
CSS = 220 nF (see Figure 9)
(1% tolerance on BOM)
RFSW = 5.18 k,
CSS = 220 nF (see Figure 9)
VSNS voltage
VSNS
ILOAD = 0 A
1.002
–500
1.05
—
1.097
500
V
VSNS current offset
I
nA
offset
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
Preliminary Rev. 0.6
3
Si88x4x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
Output Voltage
Symbol
Test Condition
Min
Typ
Max
Unit
See Figure 2
ILOAD = 0 mA
–5
—
+5
%
2
Accuracy
Line Regulation
VOUT(line)/V
See Figure 2
ILOAD = 50 mA
1
mV/V
DDP
VDDP varies from 4.5 to 5.5 V
Load Regulation
VOUT(load)/V
See Figure 2
0.1
%
OUT
ILOAD = 50 to 400 mA
Output Voltage Ripple
Si8824x, Si8834x
Si8844x, Si8864x
ILOAD = 100 mA
See Figure 2
See Figure 3
100
mV p-p
Turn-on overshoot
VOUT(start)
See Figure 2
CIN = COUT = 0.1 μF in
parallel with 10 μF,
ILOAD = 0 A
2
%
Continuous Output Current
Si8824x, Si8834x
5.0 V to 5.0 V
3.3 V to 3.3 V
3.3 V to 5.0 V
ILOAD(max)
mA
See Figure 2
400
400
250
550
5.0 V to 3.3 V
Si8844x, Si8864x
24.0 to 5.0 V
24.0 to 3.0 V
See Figure 3
1000
1500
Cycle-by-cycle average
current limit
ILIM
See Figure 2
Output short circuited
3
A
Si8824x, Si8834x
3
No Load Supply Current
IDDP
Si8824x, Si8834x
IDDPQ_DCDC
See Figure 2
VDDP = VDDA = 5 V
30
5.7
mA
mA
4
No Load Supply Current
IDDA
IDDAQ_DCDC
See Figure 2
VDDP = VDDA = 5 V
Si8824x, Si8834x
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
4
Preliminary Rev. 0.6
Si88x4x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3
4
No Load Supply Current
IDDP
Si8844x, Si8864x
IDDPQ_DCDC
See Figure 3
VIN = 24 V
0.8
mA
No Load Supply Current
IDDA
Si8844x, Si8864x
IDDAQ_DCDC
See Figure 3
VIN = 24 V
5.8
mA
%
Peak Efficiency
Si8824x, Si8834x
Si8844x, Si8864x
See Figure 2, 3
78
83
Voltage Regulator Refer-
ence Voltage
Si8844x, Si8864x
I
= 600 µA
4.8
V
VREGA,
VREGB
REG
See Figure 30 for typical I–V
curve
VREG tempco
–0.43
—
mV/°C
µA
K
TVREG
VREG input current
350
950
I
REG
Soft Start Time, Full Load
Si8824x, Si8844x
Si8834x, Si8864x
t
See Figures 25 through 28 for
typical soft start times over
load conditions.
ms
SST
25
50
Restart Delay from fault
event
tOTP
21
s
Digital Isolator
VDD Undervoltage
Threshold
VDDUV+
VDDUV–
VDDA, VDDB rising
VDDA, VDDB falling
2.7
2.6
V
V
VDD Undervoltage
Threshold
VDD Undervoltage
Hysteresis
VDD
100
1.67
mV
V
HYS
Positive-Going Input
Threshold
VT+
All inputs rising
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
Preliminary Rev. 0.6
5
Si88x4x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Negative-Going Input
Threshold
VT–
All inputs falling
1.23
V
Input Hysteresis
V
0.44
—
V
V
V
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
2.0
—
—
0.8
—
IH
V
—
IL
V
loh = –4 mA
lol = 4 mA
V
,
–
—
OH
DDA
V
DDB
0.4
Low Level Output Voltage
Input Leakage Current
Output Impedance
V
—
—
—
—
—
50
0.4
±10
—
V
µA
OL
I
L
Z
O
Supply Current, C
= 15 pF
LOAD
DC, VDDx = 3.3 V ± 10%
Si88x40
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
12.9
5.4
5.1
5.3
mA
mA
mA
DDA
DDB
DDA
DDB
Si88x41
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
10.9
6.8
5.6
5.1
DDA
DDB
DDA
DDB
Si88x42
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
9.7
7.8
5.9
4.3
DDA
DDB
DDA
DDB
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
6
Preliminary Rev. 0.6
Si88x4x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si88x43
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
8.5
9.3
6.5
3.9
mA
DDA
DDB
DDA
DDB
Si88x44
mA
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
6.6
10.6
6.5
DDA
DDB
DDA
DDB
3.6
1 Mbps, VDDx = 3.3 V ± 10% (All Inputs = 500 kHz Square Wave, C
= 15 pF)
LOAD
Si88x40
mA
mA
mA
mA
mA
V
V
—
—
8.9
5.4
DDA
DDB
Si88x41
V
V
—
—
8.3
6.0
DDA
DDB
Si88x42
V
V
—
—
7.9
6.1
DDA
DDB
Si88x43
V
V
—
—
7.6
6.7
DDA
DDB
Si88x44
V
V
—
—
6.7
7.1
DDA
DDB
100 Mbps, VDDx = 3.3 V ± 10% (All Inputs = 50 MHz Square Wave, C
= 15 pF)
LOAD
Si88x40
mA
V
V
—
—
8.7
19.2
DDA
DDB
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
Preliminary Rev. 0.6
7
Si88x4x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si88x41
mA
V
V
—
—
12.7
16.6
DDA
DDB
Si88x42
mA
mA
mA
V
V
—
—
15.6
13.6
DDA
DDB
Si88x43
V
V
—
—
18.7
11.0
DDA
DDB
Si88x44
V
V
—
—
21.6
6.9
DDA
DDB
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
8
Preliminary Rev. 0.6
Si88x4x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
DC, VDDx = 5 V ± 10%
Si88x40
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
13.1
5.6
5.2
5.4
mA
DDA
DDB
DDA
DDB
Si88x41
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
11.1
6.9
5.7
5.2
mA
mA
mA
mA
DDA
DDB
DDA
DDB
Si88x42
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
10.1
7.9
6.2
4.4
DDA
DDB
DDA
DDB
Si88x43
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
8.6
9.2
6.6
3.9
DDA
DDB
DDA
DDB
Si88x44
V
V
V
V
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
—
—
—
—
6.8
11.0
6.7
DDA
DDB
DDA
DDB
3.8
1 Mbps, VDDx = 5 V ± 10% (All Inputs = 500 kHz Square Wave, C
= 15 pF)
LOAD
Si88x40
mA
V
V
—
—
9.1
5.8
DDA
DDB
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
Preliminary Rev. 0.6
9
Si88x4x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si88x41
mA
V
V
—
—
8.4
6.3
DDA
DDB
Si88x42
mA
mA
mA
V
V
—
—
8.2
6.2
DDA
DDB
Si88x43
V
V
—
—
7.8
6.7
DDA
DDB
Si88x44
V
V
—
—
6.9
7.4
DDA
DDB
100 Mbps, VDDx = 5 V ± 10% (All Inputs = 50 MHz Square Wave, C
= 15 pF)
LOAD
Si88x40
mA
mA
mA
mA
mA
V
V
—
—
8.2
26.2
DDA
DDB
Si88x41
V
V
—
—
14.7
22.0
DDA
DDB
Si88x42
V
V
—
—
18.9
16.5
DDA
DDB
Si88x43
V
V
—
—
24.0
11.7
DDA
DDB
Si88x44
V
V
28.1
6.6
DDA
DDB
Timing Characteristics
Data Rate
0
—
100
Mbps
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
10
Preliminary Rev. 0.6
Si88x4x
Table 2. Electrical Characteristics1 (Continued)
VIN = 24 V; VDDA = 4.3 V (see Figure 3) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
TA = –40 to 125 °C unless otherwise noted
Parameter
Minimum Pulse Width
Propagation Delay
Symbol
Test Condition
Min
10
Typ
—
Max
—
Unit
ns
t
t
t
t
See Figure 1
VDDx = 3.3 V
—
17.8
—
ns
PHL
PLH
PHL
PLH
Propagation Delay
Propagation Delay
Propagation Delay
Pulse Width Distortion
See Figure 1
VDDx = 3.3 V
—
—
—
—
—
14.5
17.5
12.6
3.4
—
—
—
—
—
ns
ns
ns
ns
ns
See Figure 1
VDDx = 5.0 V
See Figure 1
VDDx = 5.0 V
PWD
PWD
See Figure 1
VDDx = 3.3 V
|t
– t
|
PLH
PHL
Pulse Width Distortion
|t – t
See Figure 1
VDDx = 5.0 V
4.8
|
PHL
PLH
6
Propagation Delay Skew
Channel-Channel Skew
Output Rise Time
t
—
—
—
2.0
1.0
2.5
—
—
—
ns
ns
ns
PSK(P-P)
t
PSK
t
C
C
= 15 pF
= 15 pF
r
LOAD
LOAD
Output Fall Time
t
—
2.5
—
—
ns
f
Common Mode
CMTI
V = VDDx or 0 V
40
100
kV/µs
I
Transient Immunity
V
= 1500 V
CM
See Figure 4
7
Startup Time
t
—
55
—
µs
SU
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
Preliminary Rev. 0.6
11
Si88x4x
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing for Digital Channels
IIN
C1
D1
T1
DB2440100L
10 µF
R4
100
+
+
VOUT
_
C3
C2
VIN
10 µF
10 µF
C5
_
100 pF
UTB02185S
U1
VSW
IDDB
IDDP
VDDB
VDDP
VDDA
R1
49.9 k
IDDA
VSNS
COMP
R3
49.9 k
R2
13.3 k
SH
C4
GNDA
GNDP
1.5 nF
GNDB
Figure 2. Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx
12
Preliminary Rev. 0.6
Si88x4x
ILOAD
IIN
IDDP
IDDA
D1
T1
SBRT5A50SA
R8
27.4
R9
82
+
+
C3
C2
VIN
VOUT
22 µF
10 µF
C7
C6
_
_
100 pF
68 pF
UTB02205S
U2
IDDB
Q1
FDT3612
ESW
VDDB
RSNS
R1
49.9 k
R5
0.1
R7
19.6 k
VSNS
GNDP
VREG
COMP
Q2
R3
100 k
R2
13.3 k
MMBT2222LT1
C5
0.1 µF
C4
VDDA
1.5 nF
C8
GNDB
10 µF
SS
SH_FC
C1
R6
18 k
0.22 µF
GNDA
Figure 3. Measurement Circuit for Converter Efficiency and Regulation for Si884xx, Si886xx
DC-DC Output
Powers B-side
Referenced to
Earth Ground
Si8824x
VSW
VDDB
VDDP/VDDA
Oscilloscope
Forward
Channel
Input
Forward
Channel
Ouput
Reverse
Channel
Measured by
Forward
Channel in
Loopback
Isolated
Supply
+
_
Reverse
Channel
Output
Reverse
Channel
Input
GNDB
GNDA
High Voltage
Differential
Probe
High Voltage Transient Generator
Figure 4. Common-Mode Transient Immunity Test Circuit
Preliminary Rev. 0.6
13
Si88x4x
Table 3. Regulatory Information1,2
CSA
The Si88xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
VDE
The Si88xx is certified according to VDE 0884-10. For more details, see File 5006301-4880-0001.
VDE 0884-10: Up to 891 V
for basic insulation working voltage.
peak
UL
The Si88xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V
isolation voltage for basic protection.
RMS
CQC
The Si88xx is certified under GB4943.1-2011.
Rated up to 600 V
reinforced insulation working voltage; up to 1000 V
basic insulation working voltage.
RMS
RMS
Notes:
1. Regulatory Certifications apply to 5 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
2. All certifications are pending.
14
Preliminary Rev. 0.6
Si88x4x
Table 4. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WB SOIC-20
WB SOIC-24
1
Nominal Air Gap (Clearance)
L(1O1)
L(1O2)
8.0
mm
1
Nominal External Tracking (Creepage)
8.0
mm
mm
Minimum Internal Gap
(Internal Clearance)
0.014
Tracking Resistance (Proof Tracking Index)
Erosion Depth
PTI
ED
IEC60112
f = 1 MHz
600
V
mm
0.019
2
12
Resistance (Input-Output)
R
10
IO
2
Capacitance (Input-Output)
C
1.4
4.0
pF
pF
IO
3
Input Capacitance
C
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and
creepage limits as 8.5 mm minimum for the WB SOIC-20 and WB SOIC-24 packages. UL does not impose a clearance
and creepage minimum for component-level certifications. CSA certifies the clearance and creepage limits as 7.6 mm
minimum for the WB SOIC-20 and WB SOIC-24 packages.
2. To determine resistance and capacitance, the Si88xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input to ground.
Table 5. IEC 60664-1 (VDE 0884-10) Ratings
Parameter
Test Condition
Specification
WB SOIC-20
WB SOIC-24
Basic Isolation Group
Material Group
I
Installation Classification
Rate Mains Voltages <150 V
Rate Mains Voltages <300 V
Rate Mains Voltages <400 V
Rate Mains Voltages <600 V
I–IV
I–IV
I–III
I–III
RMS
RMS
RMS
RMS
Preliminary Rev. 0.6
15
Si88x4x
Table 6. VDE 0884-10 Insulation Characteristics*
Parameter
Symbol
Test Condition
Characteristic
WB SOIC-20
WB SOIC-24
Unit
Maximum Working
Insulation Voltage
V
891
V peak
IORM
Input to Output Test Voltage
V
1671
V peak
Method b1
PR
(V
x 1.875 = V , 100%
PR
IORM
Production Test,
= 1 sec,
t
m
Partial Discharge < 5 pC)
Transient Overvoltage
V
t = 60 sec
6000
2
V peak
IOTM
Pollution Degree
(DIN VDE 0110, Table 1)
9
Insulation Resistance at T ,
R
>10
S
S
V
= 500 V
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si88xx provides a climate classification of
40/125/21.
Table 7. IEC Safety Limiting Values*
Parameter
Case Temperature
Safety Input Current
Symbol
Test Condition
WB SOIC-20
150
Unit
°C
T
I
S
= 55 °C/W (WB SOIC-20),
JA
413
mA
S
V
= 5.5 V,
DDA
Device Power Dissipation
P
2.27
W
T = 150 °C, T = 25 °C
D
J
A
*Note: Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 3.
16
Preliminary Rev. 0.6
Si88x4x
Table 8. Thermal Characteristics
Parameter
Symbol
WB SOIC-20
Unit
IC Junction-to-Air Thermal Resistance
55
°C/W
JA
Figure 5. WB SOIC-20 Thermal Derating Curve*
*Note: Values are not final and are subject to change. Dependence of Safety Limiting Values with Case Temperature per VDE
0884-10.
Preliminary Rev. 0.6
17
Si88x4x
Table 9. Absolute Maximum Ratings1,2
Parameter
Storage Temperature
Symbol
Min
–65
—
Max
+150
+150
6.0
Unit
°C
°C
V
T
STG
Junction Temperature
T
J
Input-side Supply Voltage
VDDA
VDDP
–0.6
Output supply
VDDB
VIN
–0.6
–0.5
6.0
V
V
Voltage on any Pin with respect to Ground
Output Drive Current per Channel
Input Current for VREGA, VREGB
Lead Solder Temperature (10 s)
ESD per AEC-Q100
VDD + 0.5
I
10
1
mA
mA
°C
kV
kV
O
I
—
—
—
—
—
REG
260
4
HBM
CDM
2
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-20, WB SOIC-24
6500
V
RMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. VDE certifies storage temperature from –40 to 150 °C.
18
Preliminary Rev. 0.6
Si88x4x
2. Functional Description
2.1. Theory of Operation
The Si88xx family of products is capable of transmitting and receiving digital data signals from an isolated power
domain to a local system power domain with up to 5 kV of isolation. Each part has four unidirectional digital
isolation channels. In addition, Si88xx products include an integrated controller and switches for a dc-dc converter
which regulates output voltage by sensing it on the isolated side.
2.2. Digital Isolation
The operation of an Si88xx digital channel is analogous to that of a digital buffer, except an RF carrier transmits
data across the isolation barrier. This simple architecture provides a robust isolated data path and requires no
special considerations or initialization at start-up. A simplified block diagram for a single Si88xx channel is shown in
Figure 6.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 6. Simplified Si88xx Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a silicon dioxide capacitive isolation
barrier. In the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 7 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 7. Modulation Scheme
Preliminary Rev. 0.6
19
Si88x4x
2.3. DC-DC Converter Application Information
The Si88xx isolated dc-dc converter is based on a modified fly-back topology and uses an external transformer and
Schottky rectifying diode for low cost and high operating efficiency. The PWM controller operates in closed-loop,
peak current mode control and generates isolated output voltages with 2 W average output power at 5.0 V. Options
are available for 24 Vdc input or output operation and externally configured switching frequency.
The dc-dc controller modulates a pair of internal primary-side power switches (see Figure 8) to generate an
isolated voltage at external diode D1 cathode. Closed-loop feedback is provided by a compensated error amplifier,
which compares the voltage at the VSNS pin to an internal voltage reference. The resulting error voltage is fed
back through the isolation barrier via an internal feedback path to the controller, thus completing the control loop.
For higher input supply voltages than 5 V, an external FET Q2 is modulated by a driver pin ESW as shown in (see
Figure 9). A shunt resistor based voltage sense pin RSN provides current sensing capability to the controller.
Additional features include an externally-triggered shutdown of the converter functionality using the SH pin and a
programmable soft start configured by a capacitor connected to the SS pin. The Si88xx can be used in low- or high-
voltage configurations. These features and configurations are explained in more detail below.
2.3.1. Shutdown
This feature allows the operation of the dc-dc converter to be shut down when asserted high. This function is
provided by pin 6 (labeled “SH” on the Si882xx) and pin 7 (labeled “SH_FC” on the Si883xx and Si886xx). This
feature is not available on the Si884xx. Pin 6 or pin 7 provide the exact same functionality and shut down the dc-dc
converter when asserted high. For normal operation, pins 6 and 7 should be connected to ground.
2.3.2. Soft-Start
The dc-dc controller has an internal timer that controls the power conversion start-up to limit inrush current. There
is also the Soft Start option where users can program the soft start up by an external capacitor connected to the SS
pin. This feature is available on the Si883xx and the Si886xx.
2.3.3. Programmable Frequency
The frequency of the PWM modulator is set to a default of 250 kHz for Si882xx/4xx. Users can program their
desired frequency within a given band of 200 kHz to 800 kHz by controlling the time constant of an external RC
connected to the SH_FC and SS pins for Si883xx/6xx.
2.3.4. External Transformer Driver
The dc-dc controller has internal switches (VSW) for driving the transformer with up-to a 5.5 V voltage supply. For
higher voltages on the primary side, a driver output (ESW) is provided that can drive an external NMOS power
transistor for driving the transformer. When this configuration is used, a shunt resistor based voltage sense pin
(RSN) provides current sensing to the controller.
2.3.5. VREGA, VREGB
For supporting voltages greater than 5.5 V, an internal voltage regulator (VREGA, VREGB) needs to be used in
conjunction with an external NPN transistor, a resistor and a capacitor to provide regulated voltage to the IC.
2.3.6. Output Voltage Control
The isolated output voltage (VOUT) is sensed by a resistor divider that provides feedback to the controller through
the VSNS pin. The voltage error is encoded and transmitted back to the primary side controller across the isolation
barrier, which in turn changes the duty cycle of the transformer driver. The equation for VOUT is as follows:
R1
R2
VOUT = VSNS 1 + ------- + R1 IOFFSET
20
Preliminary Rev. 0.6
Si88x4x
2.3.7. Compensation
The dc-dc converter uses peak current mode control. The loop is compensated by connecting an external resistor
in series with a capacitor from the COMP pin to GNDB. The compensation resistance, RCOMP is fixed at 49.9 k
for Si882xx/3xx and 100 k for Si884xx/6xx to match internal resistance. Capacitance value is given by the
following equation, where f is crossover frequency:
C
6
CCOMP = ----------------------------------------------------------
2 fC RCOMP
For more details on the calculations involved, please see “AN892: Design Guide for Isolated DC/DC Using the
Si882xx/883xx”.
2.3.8. Thermal Protection
A thermal shutdown circuit is included to protect the system from over-temperature events. The thermal shutdown
is activated at a junction temperature that prevents permanent damage from occurring.
2.3.9. Cycle Skipping
Cycle skipping is included to reduce switching power losses at light loads. This feature is transparent to the user
and is activated automatically at light loads. The product options with integrated power switches (Si882xx/3xx) may
never experience cycle skipping during operation even at light loads while the external power switch options
(Si884xx/6xx) are likely to have cycle skipping start at light loads.
Preliminary Rev. 0.6
21
Si88x4x
2.3.10. Low-Voltage Configuration
The low-voltage configuration is used for converting 3.0 V to 5.5 V. All product options of the Si882xx and Si883xx
are intended for this configuration.
An advantage of Si88xx devices over other converters that use this same topology is that the output voltage is
sensed on the secondary side without requiring additional optocouplers and support circuitry to bias those
optocouplers. This allows the dc-dc to operate with superior line and load regulation while reducing external
components and increasing lifetime reliability.
In a typical digital signal isolation application, the dc-dc powers the Si882xx and Si883xx VDDB as shown in
Figure 8. In addition to powering the isolated side of the dc-dc can deliver up to 2 W of power to other loads. The
dc-dc requires an input capacitor, C2, blocking capacitor, C1, transformer, T1, rectifying diode, D1, and an output
capacitor, C3. Resistors R1 and R2 divide the output voltage to match the internal reference of the error amplifier.
Type 1 loop compensation made by RCOMP and CCOMP are required at the COMP pin. Though it is not
necessary for normal operation, we recommend that a snubber be used to minimize radiated emissions. More
details can be found in “AN892: Design Guide for Isolated DC-DC Using the Si882xx/883xx”.
Vin
Vout
C1
T1
D1
C3
C2
R1
Si8832x
R2
VDDB
VDDA
UVLO
UVLO
Power
FET
Used in applications
where converter
output is > 5.5 V
VREG
VSNS
VSW
HVREG
Reference
DC-DC
Controller
Power
FET
RFSW
CSS
SH_FC
SS
Error Amp
and
Compensation
Freq. Control
and Shutdown
CCOMP
COMP
Soft Start
Encoder
RCOMP
HF RX
HF TX
HF RX
Fwd. Digital
Channels
HF TX
HF TX
A1
A2
B1
B2
Rev. Digital
Channels
HF RX
Figure 8. Si88xx Block Diagram: 3 V–5 V Input to 3 V–5 V Output
22
Preliminary Rev. 0.6
Si88x4x
2.3.11. High-Voltage Configuration
The high-voltage configuration is used for converting up to 24 V to 3.3 V or 5.0 V. All product options of the
Si884xx and Si886xx are intended for this configuration.
Si884xx and Si886xx can be used for dc-dc applications that have primary side voltage greater than 5.5 V. The dc-
dc converter uses the isolated flyback topology. With this topology, the switch and sense resistor are external,
allowing higher switching voltages. Digital isolator supply VDDA of the Si884xx and Si886xx require a supply less
than or equal to 5.5 V. If a suitable supply is not available on the primary side, the VREGA voltage reference with
external NPN transistor can supply VDDA. This eliminates the need to design an additional linear regulator circuit.
Like the Si882xx and Si883xx, the output voltage is sensed on the secondary side without requiring additional
optocouplers and support circuitry to bias those optocouplers. This allows the dc-dc to operate with superior line
and load regulation.
Figure 9 shows the block diagram of an Si886xx with external components. Si886xx is different from the
Si882xx/883xx as it has externally-controlled switching frequency and soft start. The dc-dc requires input capacitor
C2, transformer T1, switch Q1, sense resistor R4, rectifying diode D1 and an output capacitor C3. To supply VDDA,
Q2 transistor is biased and filtered by R3 and C1. External frequency and soft start behavior is set by CSS and
RFSW. Resistors R1 and R2 divide the output voltage to match the internal reference of the error amplifier. Type 1
loop compensation made by RCOMP and CCOMP are required at the COMP pin. Though it is not necessary for
normal operation, we recommend to use a snubber, to minimize high-frequency emissions. For further details, see
“AN901: Design Guide for Isolated DC-DC Using the Si884xx/886xx”.
VOUT
Vin
T1
D1
C3
C2
Si8862x
R3
Used in applications
where converter
output is > 5.5 V
VREGA
VDDA
VREGB
VDDB
VREG
Reference
VREG
Reference
Q2
UVLO
UVLO
C1
ESW
RSN
Q1
FET
Driver
DC-DC Controller
Current
Sensing
R4
GNDP
R1
VSNS
R
2
RFSW
CSS
FC_SH
SS
Error Amp
and
Compensation
Freq. Control
and Shutdown
CCOMP
COMP
Soft Start
Encoder
RCOMP
HF RX
HF TX
Fwd. Digital
Channel
HF TX
HF RX
A1
A2
HF RX
HF TX
B1
B2
Rev. Digital
Channel
Figure 9. Si88xx Block Diagram: 24 V Input to 5 V Output
Preliminary Rev. 0.6
23
Si88x4x
2.4. Transformer Design
Table 10 provides a list of transformers and their parametric characteristics that have been validated to work with
Si882xx/3xx products (input voltage of 3 to 5 V) and Si884xx/Si886xx products (input voltage of 24 V). It is
recommended that users order the transformers from the vendors per the part numbers given below. Refer to
AN892 and AN901 for voltage translation applications not listed below.
To manufacture transformers from your preferred suppliers that may not be listed below, please specify to supplier
the parametric characteristics as specified in the table below for a given input voltage and isolation rating.
Table 10. Transformer Specifications
Transformer
Supplier
Ordering Part #
Input
Turns
Leakage
Primary
Primary
Isolation
Rating
Voltage Ratio Inductance Inductance Resistance
UMEC
TG-UTB02185s 3.0 – 5.5 V 4.0:1 105 nH max 2 µH ± 5% 0.05 max 2.5 kVrms
www.umec-usa.com
TG-UTB02205s
TA7608-AL
24 V
3.0:1 800 nH max 25 µH ± 5% 0.135 max 2.5 kVrms
60 nH max 2 µH ± 10% 0.036 max 2.5 kVrms
Coilcraft
3.0 – 5.5 V 4.0:1
www.coilcraft.com
24
Preliminary Rev. 0.6
Si88x4x
3. Digital Isolator Device Operation
Table 11. Si88xx Logic Operation
, ,
, ,
VDDI1,2 3 4
VDDO1,2 3 4
VI Input
VO Output
Comments
H
L
P
P
P
P
P
H
L
Normal operation.
X
UP
L4
H4
Upon transition of VDDI from unpow-
ered to powered, V returns to the
O
same state as V .
I
X
P
UP
Undetermined Upon transition of VDDO from
unpowered to powered, V returns
O
to the same state as V .
I
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. P = powered; UP = unpowered.
3. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. This
situation should be avoided. We recommend that I/O's not be driven high when primary side supply is turned off or
when in dc-dc shutdown mode.
4. See "5. Ordering Guide" on page 38 for details. This is the selectable fail-safe operating mode (ordering option). When
VDDB is powered via the primary side and the integrated dc-dc, the default outputs are undetermined as secondary
side power is not available when primary side power shuts off.
3.1. Device Startup
Outputs are held low during power up until VDDx is above the UVLO threshold for time period t . Following this,
SU
the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDDx is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when VDDA falls below V
and exits UVLO when VDDA rises above V
.
DDUV–
DDUV+
Side B operates the same as Side A with respect to its VDD supply.
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 4 and Table 6 detail the working voltage and
creepage/clearance capabilities of the Si88xx. These tables also detail the component standards (UL1577,
VDE0884-10, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system
specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements
before starting any design that uses a digital isolator.
Preliminary Rev. 0.6
25
Si88x4x
3.3.1. Supply Bypass
The Si88xx family requires a 0.1 µF bypass capacitor between all VDDx and their associated GNDx. The capacitor
should be placed as close as possible to the package. To enhance the robustness of a design, the user may also
include resistors (50–300 ) in series with the inputs and outputs if the system is excessively noisy.
3.3.2. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
high-impedance terminated PCB traces, output pins should be source-terminated to minimize reflections.
3.4. Fail-Safe Operating Mode
Si88xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input
supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 11 and
Table 13 for more information.
26
Preliminary Rev. 0.6
Si88x4x
3.5. Typical Performance Characteristics
The typical performance characteristics are for information only. Refer to Table 2 for specification limits. The data
below is for all channels switching.
Figure 10. Si88240 Typical VDDA Supply Current
vs. Data Rate (5 and 3.3 V Operation)
Figure 11. Si88240 Typical VDDB Supply Current
vs. Data Rate (5 and 3.3 V Operation)
Figure 12. Si88241 Typical VDDA Supply Current Figure 13. Si88241 Typical VDDB Supply Current
vs. Data Rate (5 and 3.3 V Operation)
vs. Data Rate (5 and 3.3 V Operation)
Figure 14. Si88242 Typical VDDA Supply Current
vs. Data Rate (5 and 3.3 V Operation)
Figure 15. Si88242 Typical VDDB Supply Current
vs. Data Rate (5 and 3.3 V Operation)
Preliminary Rev. 0.6
27
Si88x4x
Figure 17. Si88243 Typical VDDB Supply Current
vs. Data Rate (5 and 3.3 V Operation)
Figure 16. Si88243 Typical VDDA Supply Current
vs. Data Rate (5 and 3.3 V Operation)
Figure 19. Si88244 Typical VDDB Supply Current
vs. Data Rate (5 and 3.3 V Operation)
Figure 18. Si88244 Typical VDDA Supply Current
vs. Data Rate (5 and 3.3 V Operation)
28
Preliminary Rev. 0.6
Si88x4x
Figure 20. Propagation Delay vs. Temperature
Preliminary Rev. 0.6
29
Si88x4x
Figure 21. Efficiency vs. Load Current over
Temperature (3.3 to 3.3 V)
Figure 22. Efficiency vs. Load Current over
Temperature (3.3 to 5.0 V)
Figure 23. Efficiency vs. Load Current over
Temperature (5.0 to 3.3 V)
Figure 24. Efficiency vs. Load Current over
Temperature (5.0 to 5.0 V)
30
Preliminary Rev. 0.6
Si88x4x
V: 1V/div
H: 2ms/div
V: 1V/div
H: 2ms/div
Figure 25. 5 V–5 V VOUT Startup vs.Time
(No Load)
Figure 26. 5 V–5 V VOUT Startup vs.Time
(10 mA Load Current)
V: 1V/div
H: 2ms/div
V: 1V/div
H: 5ms/div
Figure 27. 5 V–5 V VOUT Startup vs.Time
(50 mA Load Current)
Figure 28. 5 V–5 V VOUT Startup vs.Time
(400 mA Load Current)
Preliminary Rev. 0.6
31
Si88x4x
Figure 29. 5 V–5 V VOUT Load Transient Response, 10% to 90% Load
Figure 30. Typical I-V Curve for VREGA/B
32
Preliminary Rev. 0.6
Si88x4x
4. Pin Descriptions
20
GNDP
VSW
VDDP
VDDA
GNDA
SH
1
2
3
4
5
6
GNDB
20
1
GNDP
GNDB
19
18
VDDB
DNC
19 VDDB
VSW
VDDP
VDDA
GNDA
SH
2
3
4
5
6
18
DNC
17 NC
17 NC
VSNS
16
VSNS
16
15 COMP
15 COMP
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
B1
14
7
8
A1
B1
14
7
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A2
13 B2
12 B3
A2
13 B2
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A3
9
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
B4
HF
XMTR
HF
RCVR
A4
11
10
A4
10
Si88241
Si88240
20
1
GNDP
VSW
VDDP
VDDA
GNDA
SH
GNDB
20
1
GNDP
VSW
VDDP
VDDA
GNDA
SH
GNDB
VDDB
19
18
2
3
4
5
6
VDDB
DNC
19
2
3
4
5
6
18 DNC
17 NC
17 NC
VSNS
16
VSNS
16
15 COMP
15 COMP
B1
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
B1
14
7
8
A1
14
13 B2
7
8
HF
RCVR
HF
XMTR
HF
XMTR
HF
RCVR
A2
13 B2
A2
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
A3
B3
B4
12
11
9
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
A4
10
A4
10
Si88243
Si88242
20
19
18
1
2
3
4
5
6
GNDP
VSW
VDDP
VDDA
GNDA
SH
GNDB
VDDB
DNC
17 NC
VSNS
16
15 COMP
HF
RCVR
HF
XMTR
A1
B1
14
7
8
HF
RCVR
HF
XMTR
A2
13 B2
HF
RCVR
HF
XMTR
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
A4
10
Si88244
Figure 31. Si8824x Pin Configurations
Preliminary Rev. 0.6
33
Si88x4x
24
23
22
24
23
22
1
2
3
4
5
6
7
1
2
3
4
5
6
7
GNDP
VSW
VDDP
VDDA
GNDA
NC
GNDB
VDDB
DNC
GNDP
VSW
VDDP
VDDA
GNDA
NC
GNDB
VDDB
DNC
21 NC
21 NC
VSNS
VSNS
20
20
19 COMP
19 COMP
SH_FC
SS
SH_FC
SS
18
18
NC
NC
8
8
17
16
17
16
NC
B1
NC
B1
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
A2
A3
A4
A1
A2
A3
A4
9
9
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
15 B2
14 B3
10
15 B2
14 B3
10
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
11
12
11
12
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
B4
13
B4
13
Si88340
Si88341
24
24
1
2
3
4
5
6
7
1
2
3
4
5
6
7
GNDP
VSW
VDDP
VDDA
GNDA
NC
GNDB
GNDP
VSW
VDDP
VDDA
GNDA
NC
GNDB
23
23
VDDB
DNC
VDDB
DNC
22
22
21 NC
21 NC
VSNS
VSNS
20
20
19 COMP
19 COMP
SH_FC
SS
SH_FC
SS
18
18
NC
NC
8
9
8
9
17
17
NC
NC
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
B1
A1
B1
16
15 B2
16
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
A2 10
A2 10
15 B2
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
A3
11
A3
11
B3
B4
B3
B4
14
13
14
13
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
A4
A4
12
12
Si88342
Si88343
24
1
2
3
4
5
6
7
GNDP
GNDB
23 VDDB
VSW
VDDP
VDDA
GNDA
NC
22
DNC
21 NC
VSNS
20
19 COMP
SH_FC
SS
18
17
NC
NC
B1
8
HF
RCVR
HF
XMTR
A1
A2
A3
A4
16
9
HF
RCVR
HF
XMTR
15 B2
14 B3
10
11
12
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
B4
13
Si88344
Figure 32. Si8834x Pinout Diagrams
34
Preliminary Rev. 0.6
Si88x4x
20
19
18
20
1
2
3
4
5
6
1
2
3
4
5
6
GNDP
RSN
GNDB
VDDB
VREGB
GNDP
RSN
GNDB
19
18
VDDB
ESW
VDDA
GNDA
VREGA
A1
ESW
VDDA
GNDA
VREGA
A1
VREGB
17 NC
17 NC
VSNS
VSNS
16
16
15 COMP
15 COMP
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
B1
B1
14
14
7
8
7
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A2
13 B2
A2
13 B2
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A3
A3
B3
B4
B3
B4
9
12
11
9
12
11
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
A4
A4
10
10
Si88440
Si88441
20
19
18
1
2
3
4
5
6
GNDP
RSN
GNDB
VDDB
VREGB
20
19
18
1
2
3
4
GNDP
RSN
GNDB
VDDB
VREGB
ESW
VDDA
GNDA
VREGA
A1
ESW
VDDA
GNDA
VREGA
A1
17 NC
17 NC
VSNS
16
VSNS
16
5
6
15 COMP
15 COMP
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
B1
14
7
8
B1
14
7
8
9
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
A2
13 B2
A2
13 B2
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
A3
B3
B4
12
11
9
A3
B3
B4
12
11
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
10
A4
A4 10
Si88442
Si88443
20
1
2
3
4
5
6
GNDP
RSN
GNDB
VDDB
VREGB
19
18
ESW
VDDA
GNDA
VREGA
A1
17 NC
VSNS
16
15 COMP
HF
RCVR
HF
XMTR
B1
14
7
8
HF
RCVR
HF
XMTR
A2
13 B2
HF
RCVR
HF
XMTR
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
A4
10
Si88444
Figure 33. Si8844x Pinout Diagrams
Preliminary Rev. 0.6
35
Si88x4x
24
24
1
2
3
4
1
2
3
4
GNDP
RSN
GNDB
VDDB
VREGB
GNDP
RSN
GNDB
VDDB
VREGB
23
23
22
22
ESW
ESW
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VSNS
VSNS
20
20
5
6
7
5
6
7
19 COMP
19 COMP
18
18
NC
NC
8
8
17
17
NC
NC
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
A2
A3
A4
B1
16
A1
A2
A3
A4
B1
9
16
15 B2
9
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
15 B2
14 B3
10
10
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
11
12
14
13
B3
B4
11
12
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
B4
13
Si88640
Si88641
24
24
23
22
1
2
3
4
1
2
3
4
GNDP
RSN
GNDB
GNDP
RSN
GNDB
VDDB
VREGB
23
VDDB
22
ESW
VREGB
ESW
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VSNS
VSNS
20
20
5
6
7
5
6
7
19 COMP
19 COMP
18
17
18
17
NC
NC
B1
NC
NC
B1
8
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
A2
A3
A1
A2
A3
16
9
16
9
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
15 B2
15 B2
14 B3
10
11
10
11
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
B3
B4
14
13
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
B4
A4 12
13
A4 12
Si88642
Si88643
24
1
2
3
4
GNDP
GNDB
23
22
RSN
ESW
VDDB
VREGB
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VSNS
20
5
6
7
19 COMP
18
NC
8
17
NC
HF
RCVR
HF
XMTR
A1
A2
A3
A4
B1
16
9
HF
RCVR
HF
XMTR
15 B2
14 B3
10
HF
RCVR
HF
XMTR
11
12
HF
RCVR
HF
XMTR
B4
13
Si88644
Figure 34. Si8864x Pinout Diagrams
36
Preliminary Rev. 0.6
Si88x4x
Table 12. Si88x4x Pin Descriptions
Pin Name
DC-DC Input Side
Description
VDDP
VREGA
GNDP
ESW
Power stage primary power supply.
Voltage reference output for external voltage regulator pin.
Power stage ground.
Power stage external switch driver output.
Power stage internal switch output.
Soft startup control.
VSW
SS
SH, SH_FC
RSN
Shutdown and Switch frequency control.
Power stage current sense input.
DC-DC Output Side
VSNS
Power stage feedback input.
Power stage compensation.
COMP
VREGB
Voltage reference output for external voltage regulator pin.
Do not connect; leave open.
DNC
NC
No connect; this pin is not connected to the silicon.
Digital Isolator VDDA Side
VDDA
Primary side signal power supply.
I/O signal channel 1–4.
A1–A4
GNDA
Primary side signal ground.
Digital Isolator VDDB Side
VDDB
B1–B4
GNDB
Secondary side signal power supply.
I/O signal channel 1–4.
Secondary side signal ground.
Preliminary Rev. 0.6
37
Si88x4x
5. Ordering Guide
Table 13. Si88x4x Ordering Guide1,2,3,4
Soft Start Frequency External Forward
Part #
DC-DC
Shutdown
Product Options Available Now
Reverse
Digital
Package
Control
Control
Switch
Digital
Si88240ED-IS
Si88241ED-IS
Si88242ED-IS
Si88243ED-IS
Si88244ED-IS
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
4
3
2
1
0
0
1
2
3
4
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
Contact Silicon Labs for Availability
Si88240BD-IS
Si88241BD-IS
Si88242BD-IS
Si88243BD-IS
Si88244BD-IS
Si88340ED-IS
Si88341ED-IS
Si88342ED-IS
Si88343ED-IS
Si88344ED-IS
Si88440ED-IS
Si88441ED-IS
Si88442ED-IS
Si88443ED-IS
Si88444ED-IS
Si88640ED-IS
Si88641ED-IS
Si88642ED-IS
Si88643ED-IS
Si88644ED-IS
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
4. All Si88xxxEx product options are default output high on input power loss. All Si88xxxBx product options are default low.
See "3. Digital Isolator Device Operation" on page 25 for more details about default output behavior.
38
Preliminary Rev. 0.6
Si88x4x
6. Package Outline: 20-Pin Wide Body SOIC
Figure 35 illustrates the package details for the 20-pin wide-body SOIC package. Table 14 lists the values for the
dimensions shown in the illustration.
Figure 35. 20-Pin Wide Body SOIC
Preliminary Rev. 0.6
39
Si88x4x
Table 14. 20-Pin Wide Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
12.80 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AC.
4. Recommended reflow profile per JEDEC J-STD-020C specification for small body,
lead-free components.
40
Preliminary Rev. 0.6
Si88x4x
7. Land Pattern: 20-Pin SOIC
Figure 36 illustrates the PCB land pattern details for the 20-pin SOIC package. Table 15 lists the values for the
dimensions shown in the illustration.
Figure 36. 20-Pin SOIC PCB Land Pattern
Table 15. 24-Pin SOIC PCB Land Pattern Dimensions
Dimension
mm
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Notes:
1. This Land Pattern Design is based on IPC-7351 design guidelines for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC), and a
card fabrication tolerance of 0.05 mm is assumed.
Preliminary Rev. 0.6
41
Si88x4x
8. Package Outline: 24-Pin Wide Body SOIC
Figure 37 illustrates the package details for the 24-pin wide-body SOIC package. Table 16 lists the values for the
dimensions shown in the illustration.
Figure 37. 24-Pin Wide Body SOIC
42
Preliminary Rev. 0.6
Si88x4x
Table 16. 24-Pin Wide Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
15.40 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AD.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body,
lead-free components.
Preliminary Rev. 0.6
43
Si88x4x
9. Land Pattern: 24-Pin SOIC
Figure 38 illustrates the PCB land pattern details for the 24-pin SOIC package. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 38. 24-Pin SOIC PCB Land Pattern
Table 17. 24-Pin SOIC PCB Land Pattern Dimensions
Dimension
mm
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Notes:
1. This Land Pattern Design is based on IPC-7351 design guidelines for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC), and a
card fabrication tolerance of 0.05 mm is assumed.
44
Preliminary Rev. 0.6
Si88x4x
10. Top Markings
10.1. Si88x4x Top Marking (20-Pin Wide Body SOIC)
10.2. Top Marking Explanation (20-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Si88x4 = 5 kV rated 4 channel digital isolator with dc-dc
converter
X = 2, 4
2 = dc-dc shutdown
4 = External FET
Y = Number of reverse channels
Z = E, B
See Ordering Guide for more
information.
E = default high
B = default low
R = D
D = 5 kVrms isolation rating
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order
form.
Circle = 1.5 mm Diameter
(Center Justified)
“e4” Pb-Free Symbol
Country of Origin
TW = Taiwan
ISO Code Abbreviation
Preliminary Rev. 0.6
45
Si88x4x
10.3. Si88x4x Top Marking (24-Pin Wide Body SOIC)
10.4. Top Marking Explanation (24-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Si88x4 = 5kV rated 4 channel digital isolator with dc-dc
converter
X = 3, 6
3 = Full-featured dc-dc with internal FET
6 = Full-featured dc-dc with external FET
Y = Number of reverse channels
Z = E, B
See Ordering Guide for more
information.
E = default high
B = default low
R = D
D = 5 kVrms isolation rating
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order
form.
Circle = 1.5 mm Diameter
(Center Justified)
“e4” Pb-Free Symbol
Country of Origin
TW = Taiwan
ISO Code Abbreviation
46
Preliminary Rev. 0.6
Si88x4x
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 0.6
Reformatted figures.
Corrected typos.
Added text for clarity.
Preliminary Rev. 0.6
47
Si88x4x
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-
intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-
ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-
ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
48
Preliminary Rev. 0.6
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