SI8901D-A02-GSR_技术文档

Si8900/1/2

ISOLATED MONITORING ADC

Features

 ADC

3 input channels

 Temperature range:

–40 to +85 °C

10-bit resolution

 >60-year life at rated working

2.5 µs conversion time

 Isolated serial I/O port

voltage

 CSA component notice 5A

UART (Si8900)

approval

I²C/SMbus (Si8901)

2 MHz SPI port (Si8902)

 Transient immunity:

45 kV/µs (typ)

 IEC 60950, 62368, 60601

 VDE 0884-10

 UL1577 recognized

Up to 5 kVrms for 1 minute

Ordering Information:

See page 27.

Applications

Pin Assignments

 I s o la t e d d a t a a c q u is it io n

 AC mains monitor

 Solar inverters

 Isolated temp/humidity sensing

 Switch mode power systems

 Telemetry

VDDA

VREF

AIN0

VDDB

NC

Description

NC

AIN1

Rx

Si8900

Si8901

Si8902

The Si8900/1/2 series of isolated monitoring ADCs are useful as linear

signal galvanic isolators, level shifters, and/or ground loop eliminators in

many applications including power-delivery systems and solar inverters.

These devices integrate a 10-bit SAR ADC subsystem, supervisory state

Tx

AIN2

NC

RST

VDDB

GNDB

GNDA

2

machine and isolated UART (Si8900), I C/SMbus port (Si8901), or SPI

Port (Si8902) in a single package. Based on Silicon Labs’ proprietary

CMOS isolation technology, ordering options include a choice of 2.5 or

5 kV isolation ratings. All products are safety certified by UL, CSA, and

VDE. The Si8900/1/2 devices offer a typical common-mode transient

immunity performance of 45 kV/µs for robust performance in noisy and

high-voltage environments. Devices in this family are available in 16-pin

SOIC wide-body packages.

VDDA

VREF

AIN0

VDDB

NC

AIN1

SCL

SDA

NC

AIN2

RST

RSDA

GNDA

VDDB

GNDB

Safety Approval

 UL 1577 recognized

U p t o 5 k V r m s f o r 1 m i n u t e

 CSA component notice 5A

approval

 VDE certification conformity

VDE 0884-10

VDDA

RST

VDDB

NC

SDO

SCLK

SDI

VREF

AIN0

AIN1

AIN2

GNDA

IEC 60950, 62368, 60601

EN

VDDB

GNDB

Rev. 1.2 4/19

Si8900/1/2

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4. ADC Data Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.1. Demand Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.2. Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.3. Multiple Channel Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.4. UART (Si8900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2

4.5. I C/SMBus (Si8901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.6. SPI Port (Si8902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.7. Master Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5. Si8900/1/2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.1. Isolated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.2. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6.3. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7. Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

10. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

11.1. Si8900/1/2 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Rev. 1.2

2

Si8900/1/2

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Condition

Min

2.7

—

Typ

—

Max

3.6

Unit

V

Input Side Supply Voltage

Input Side Supply Current

V

With respect to GNDA

DDA

I

V

= 3.3 V, Si890x active

10

13.3

11.4

5.5

mA

DDA

V

= 3.3 V, Si890x idle

—

8.6

—

DDA

Output Side Supply Voltage

Output Side Supply Current

V

With respect to GNDB

= 3.3 V to 5.5 V, Si890x active

2.7

—

V

DDB

I

V

4.4

3.3

—

5.8

mA

DDB

V

= 3.3 V to 5.5 V, Si890x idle

—

3.9

DDB

Operating Temperature

T

–40

+85

°C

A

Table 2. Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

ADC

Resolution

R

10

bits

LSB

Integral Nonlinearity

INL

DNL

VREF = 2.4 V

—

±0.5

±1

Differential Nonlinearity

VREF = 2.4 V,

Guaranteed Monotonic

Offset Error

OFS

FSE

–2

—

0

+2

—

LSB

ppm/°C

V

Full Scale Error

Offset Tempco

T

45

OS

Input Voltage Range

Sampling Capacitance

Input MUX Impedance

V

REF

IN

C

—

5

—

pF

IN

R

—

k

MUX

Power Supply

Rejection

PSRR

–70

dB

Reference Voltage

V

Default V

= V

0

—

12

V

REF

DDA

VREF Supply Current

ADC Conversion Time

I

—

µA

µs

VREF

t

2.5

CONV

Rev. 1.2

3

Si8900/1/2

Table 2. Electrical Specifications (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Reset and Undervoltage Lockout

Power-on RESET

Voltage Threshold High

VRSTH

—

1.7

—

1.8

—

1

V

Power-on RESET

Voltage Threshold Low

VRSTL

VDDA Power-On Reset Ramp

Time

tRAMP Time from VDDA = 0 V

to VDDA > VRST

ms

Power-On Reset

Delay Time

tPOR

tRAMP < 1 ms

0.3

ms

Output Side UVLO Threshold

UVLO

H

—

2.3

—

V

Output side UVLO

Hysteresis

100

mV

Digital Inputs

Logic High Level Input Voltage

Logic Low Level Input Voltage

Logic Input Current

V

0.7 x V

—

0.6

+10

—

V

IH

DDB

V

IL

I

VIN = 0 V or V

–10

—

µA

pF

IN

DD

Input Capacitance

C

15

IN

Digital Outputs

Logic High Level Output Voltage

V

= 5 V,

= –4 mA

V

– 0.4

4.8

3.1

0.2

50

—

V



OH

DDB

I

OH

V

= 3.3 V,

= –4 mA

– 0.4

DDB

I

OH

Logic Low Level Output Voltage

V

= 3.3 to 5 V,

= 4 mA

—

0.4

—

OL

DDB

I

OL

Digital Output Source

Impedance

R

—

OUT

Serial Ports

UART Bit Rate

60

—

500

240

kbps

2

SMBus/I C Bit Rate

Slave

Address = 1111000x

SPI Port Bit Rate

Mode 3: CPOL = 1,

CPHA = 1

—

2

Mbps

4

Rev. 1.2

Si8900/1/2

Table 2. Electrical Specifications (Continued)

Parameter

SPI Port Timing

Symbol

Test Condition

Min

Typ

Max

Unit

EN Falling Edge to SCLK Rising

Edge

t

80

—

ns

SE

Last Clock Edge to /EN Rising

EN Falling to SDO Valid

SCLK High Time

t

80

—

160

—

ns

SD

t

SEZ

t

200

80

CKH

SCLK Low Time

t

—

CKL

SDI Valid to SCLK Sample Edge

t

—

SIS

SCLK Sample Edge to SDI

Change

t

80

—

SIH

SCLK Shift Edge to SDO

Change

t

—

160

ns

SOH

EN

tSE

tCKL

tSD

SCLK

tCLKH

tSIS

tSIH

SDI

tSOH

tSEZ

tSDZ

SDO

Figure 1. SPI Port Timing Characteristics

Rev. 1.2

5

Si8900/1/2

Table 3. Thermal Characteristics

Parameter

Symbol

Test Condition

WB SOIC-16

Unit

IC Junction-to-Air Thermal Resistance



100

ºC/W

JA

500

450

V_DDA, V_DDB= 2.70 V

400

370

V

_DDA, V_DDB= 3.6 V

300

220

200

V_DDA, V_DDB= 5.5 V

100

0

50

100

Temperature (ºC)

150

200

Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values

with Ambient Temperature

6

Rev. 1.2

Si8900/1/2

Table 4. Absolute Maximum Ratings

Parameter

Storage Temperature

Symbol

Min

–65

–40

–0.5

—

Typ

—

Max

150

Unit

°C

V

T

STG

Ambient Temperature under Bias

Input-Side Supply Voltage

Output-Side Supply Voltage

Input/Output Voltage

T

85

A

V

6.0

DDA

DDB

V

6.0

V

VDD +0.5

10

V

I

Output Current Drive

I

mA

°C

O

Lead Solder Temperature (10 s)

Maximum Isolation Voltage

—

260

—

6500

V

RMS

*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Rev. 1.2

7

Si8900/1/2

2. Regulatory Information

The Si8900/1/2 family is certified by Underwriters Laboratories, CSA International, and VDE. Table 5 summarizes

the certification levels supported.

Table 5. Regulatory Information

CSA

The Si89xx is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.

62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.

60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.

60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.

VDE

The Si89xx is certified according to VDE 0884-10. For more details, see File 5006301-4880-0001.

0884-10: Up to 1200 Vpeak for basic insulation working voltage.

60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.

UL

The Si89xx is certified under UL1577 component recognition program. For more details, see File E257455.

Rated up to 5000 VRMS isolation voltage for basic protection.

8

Rev. 1.2

Si8900/1/2

3. Functional Description

The Si8900/1/2 (Figure 3) are isolated monitoring ADCs that convert input signals into digital format and transmit

the resulting data through an on-chip isolated serial port to an external master processor (typically a

microcontroller). The Si890x access protocol is simple: The master configures and controls the start of ADC

conversion by writing a configuration register (CNFG_0) Command Byte to the Si890x. The master then acquires

ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the type of serial port.

2

Options include a UART with on-chip baud rate generator that operates at 500 kbps max (Si8900), an SMBus/I C

port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2 MHz max (Si8902).

The integrated ADC subsystem consists of a three-channel analog input multiplexer (MUX) followed by a series

gain amplifier (selectable 1x or 0.5x gain) and 10-bit SAR ADC. Serial-port-accessible ADC options allow the user

to select VDDA or a different reference voltage applied to the VREF pin, set the programmable gain amplifier

(PGA), and select the ADC MUX address. The master can configure the Si890x to return ADC data on-demand

(Demand Mode) or continuously (Burst Mode). For more information, see " CNFG_0 Command Byte" on page 20.

The RST pin on the input side resets the state machine. For the Si8901, the RSDA pin connects to an external

pullup resistor to VDDA to allow operation of I2C/SMBus communication.

Rev. 1.2

9

Si8900/1/2

VDDA

VDDB

AIN0

AIN1

Tx

Rx

10‐Bit

ADC

Tx Data

MUX

PGA

UART

AIN2

VREF

All

Blocks

GNDB

ADC Subsystem

ISOLATION

State Machine/

User Registers

RST

GNDA

Si8900

VDDA

VDDB

AIN0

AIN1

SDA

SCL

10‐Bit

ADC

Tx Data SMBus/

I²C

MUX

PGA

All

Blocks

AIN2

VREF

GNDB

ADC Subsystem

VREF

RST

ISOLATION

State Machine/

User Registers

RSDA

GNDA

Si8901

VDDA

VDDB

SCK

SDI

AIN0

AIN1

10‐Bit

ADC

Tx Data

MUX

PGA

SPI Port

SDO

EN

AIN2

VREF

All

Blocks

ADC Subsystem

GNDB

ISOLATION

RST

State Machine/

User Registers

GNDA

Si8902

Figure 3. Si8900/1/2 Block Diagrams

10

Rev. 1.2

Si8900/1/2

4. ADC Data Transmission Modes

The Si890x ADC performs conversions by exercising the serial port. Each of the three channels can be in Demand

Mode (MODE=1) or Burst Mode (MODE=0). Upon power cycle or reset, all channels are initialized to Demand

Mode. The CNFG=0 command byte can be used to switch a channel between Demand and Burst modes. Demand

Mode ADC conversions are initiated by Demand Mode CNFG=0 commands. Once a channel is in Burst Mode,

ADC conversions are initiated by byte reads of the serial port. An advantage of Burst Mode is the conversion time

of each ADC sample is masked by the time it takes to read data bytes on the serial port. An advantage of Demand

Mode over multiple channels in Burst Mode is the master controller will dictate which ADC channel is sampled

immediately.

4.1. Demand Mode

Master to Slave

Slave to Master

Master writes CNFG_0

Command Byte to Si8900 Rx

CNFG_0

Command

Byte

t_CONV

MODE = 1

CNFG_0

Command

ADC_H

ADC_L

Byte

Master reads updated CNFG_0 and ADC

Data From Si8900 (Tx output)

B) Si8900 Demand Mode ADC Read

Master to Slave

Slave to Master

Master writes Slave Address and

CNFG_0 Command Byte to Si8901 SDA

CNFG_0

Command

Byte

Slave

Address

Slave Address

t_CONV

MODE = 1

CNFG_0

Command

ADC_H

ADC_L

Byte

Master reads Slave Address, updated CNFG_0

and ADC Data from Si 8901(SDA pin)

C) Si8901 Demand Mode ADC Read

Master writes CNFG_0

Command Byte to Si8902SDI

Master to Slave

Slave to Master

CNFG_0

Command

Byte

t_CONV

MODE = 1

CNFG_0

Command

Byte

ADC_H

ADC_L

The master must wait 8µS

(track‐and‐hold time) before

reading ADC data packet .

Master reads updated CNFG_0 and

ADC Data from Si8902 SDO

D) Si8902 Demand Mode ADC Read

Figure 4. ADC Demand Mode Operation

Rev. 1.2

11

Si8900/1/2

Referring to Figure 4A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the

Si8900. Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an

ADC conversion, at which time the master may immediately begin reading ADC conversion data from the Si8900

UART. The ADC conversion data packet contains an echo of the Command Byte for verification and two-bytes of

ADC conversion data. The Si8901 (Figure 4B) ADC read transaction is identical to that of the Si8900 with the

2

exception of the added I C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). For the slower UART and

2

I C, the required tconv delay is consumed by reading the echo command byte. Since SPI supports the fastest data

rate, the master controller may need to delay before reading the SPI port. If the SPI read request occurs before

valid data is available, the Si8902 will output 0xFF bytes until valid data is available. The Si8902 Demand Mode

ADC read transaction (Figure 4C) is the same as that of the Si8900, except the master must wait 8 µs after the

transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two

times shorter versus the Si8900/01.

4.2. Burst Mode

Figure 5 shows the byte sequence for a channel operating in Burst Mode. A channel is switched from Demand

Mode to Burst Mode by writing a command CNFG_0 byte with MODE=0. Placing a channel in Burst Mode negates

the need to write subsequent CNFG_0 commands to initiate ADC conversions. At all serial port communication

speeds, the tconv is masked by the data rate of the data byte reads. Like the Demand Mode example, the Si8901

has a Slave Address byte prior to the CNFG_0 Command Byte. When using the Si8901, the master must write the

2

I C port address prior to reading the serial port. The Si8902 Burst Mode (Figure 5C) is similar to that of the Si8900/

1, except the master must wait 8 µs before reading the first Burst Mode ADC data packet. After reading the first

Burst Mode ADC data packet, the master may read all ADC data packets that follow without delay.

12

Rev. 1.2

Si8900/1/2

Master writes CNFG_0

Command Byte to Si8900 Rx

CNFG_0

Command

Byte 0

MODE = 0

Master to Slave

Slave to Master

t_CONV

CNFG_0

Command

Byte

ADC_H

Data

ADC_H

Data

ADC_L

Data

ADC_L

Data

Master reads updated CNFG_0 Command Byte and ADC data from Si8900 Tx

A) Si8900 ADC Burst Mode (MODE = 0)

Master writes Slave Address & CNFG_0

Command Byte to Si8901 SDA

CNFG_0

Command

Byte 0

Slave Addrress

Write

MODE = 0

t_CONV

CNFG_0

Command

Byte

Master to Slave

ADC_H

Data

ADC_H

Data

Slave Address

Read

ADC_L

Data

ADC_L

Data

Slave to Master

Master reads Slave Address, updated CNFG_0 and ADC data from Si8901 SDA

B) Si8901 ADC Burst Mode (MODE = 0)

Master writes CNFG_0 Command

Byte to Si8902 SDI

CNFG_0

Command

Byte

Master to Slave

Slave to Master

t_CONV

MODE = 0

CNFG_0

Command

Byte

ADC_H

Data

ADC_H

Data

ADC_L

Data

ADC_L

Data

Master reads updated CNFG_0 and ADC data from Si8902 SDO

C) Si8902 ADC Burst Mode (MODE = 0)

Figure 5. ADC Burst Mode Operation

Rev. 1.2

13

Si8900/1/2

4.3. Multiple Channel Burst Mode

It is possible to set any channel from Demand to Burst Mode and any Burst Mode Channel back to Demand Mode.

However, CNFG_0 command byte can only write to one channel at a time. To operate two or more channels in

Burst Mode, first set one channel to Burst Mode. This will enable the first Burst Channel operation. The master

controller will then need to set additional channels to Burst Mode by writing another CNFG_0 command byte.

For the Si8901, communication is half duplex. Therefore, the data reads of a previously set burst channel must be

interrupted by writing a new CNFG_0 command to set the additional channel to Burst Mode.

For the Si8900 and Si8902, communication is full duplex, and a new CFNG_0 command byte can be written at the

same time as reading data from a previously set burst channel. Depending on where the new CNFG_0 command

is received during the burst read, the Si8902 may output data with MX0 = 1 and MX1 = 1 (see “5. Si8900/1/2

Configuration Registers” ), which does not point to a valid channel. Ignore that ADC_H byte and the following

ADC_L byte. This is a temporary artifact of having restarted the burst sequence with an additional burst-enabled

channel. See "4.7. Master Controller Firmware" on page 19.

To parse the data stream for multiple burst mode channels, the master controller must analyze the MX0 and MX1

bits of the ADC_H byte. For each ADC_H byte received, the next ADC_L byte received is the second part of that

channel's data. The Si890x will cycle through all Burst Mode channels sequentially. For example, if channels 0 and

1 are in Burst Mode, the data read back will have this order: ADC_H (MX1=0, MX0=0), ADC_L, ADC_H (MX1=0,

MX0=1), ADC_L, ADC_H (MX1=0, MX0=0), ADC_L, and so on.

14

Rev. 1.2

Si8900/1/2

4.4. UART (Si8900)

The UART is a two-wire interface (Tx, Rx) and operates as an asynchronous, full-duplex serial port with internal

auto baud rate generator that measures the period of incoming data stream and automatically adjusts the internal

baud rate generator to match. The auto baud rate detection and matching optimizes UART timing for minimum bit

error rate. For more information, see “AN635: Si8900 Automatic Baud Rate Detection”.

There are a total of 10 bits per data byte: One start bit, eight data bits (LSB first), and one stop bit with data

transmitted LSB first as shown in Figure 6. Figure 7A and Figure 7B show master/Si8900 ADC read transactions

for Demand Mode and Burst Mode, respectively.

MARK

SPACE

Start Bit

D5

D6

D7

D2

D4

D0

D1

D3

STOP BIT

BIT TIMES

BIT SAMPLING

Figure 6. UART Data Byte

Master to Slave

Slave to Master

CNFG_0 Write Command Byte

S

‐

1

P

D0 D1 D2 D3 D4 D5 D6 D7

ADC Data

S

1

P

S

0

1

P

S

0

0 S

‐

D0 D1 D2 D3 D4 D5 D6 D7

CNFG_0 Read Data

D0 D1 D2 D3 D4 D5 D6 D7

CNFG_0 Write Command Byte

A) Si8900 Demand Mode ADC Read

S

‐

1

1 P

D0 D1 D2 D3 D4 D5 D6 D7

Periodic ADC Data

1

S

P

S

0 1 P S 0

0 P S

0 1 P

S

0

0 P S

‐

D0 D1 D2 D3 D4 D5 D6 D7

CNFG_0 Read Data

D0 D1 D2 D3 D4 D5 D6 D7

B) Si8900 Burst Mode ADC Read

Figure 7. Si8900 ADC Read Operation

Rev. 1.2

15

Si8900/1/2

2

4.5. I C/SMBus (Si8901)

2

The I C/SMBus serial port is a two-wire serial bus where data line SDA is bidirectional and clock line SCL is

2

unidirectional. Reads and writes to this interface by the master are byte-oriented, with the I C/SMBus master

controlling the serial data rates up to 240 kbps. The SDA and SCL lines must be pulled high through pull-up

resistors of 5 k or less. An Si8901 ADC read transaction begins with a START condition (“S” or Repeated START

condition “SR”), which is defined as a high-to-low transition on SDA while SCL is high (Figure 8). The master

terminates a transmission with a STOP condition (P), defined as a low-to-high transition on SDA while SCL is high.

The data on SDA must remain stable during the high period of the SCL clock pulse because such changes in either

line will be interpreted as a control command (e.g., S, P SR). SDA and SCL idle in the high state when the bus is

not busy. Acknowledge bits (Figure 9) provide detection of successful data transfers, whereas unsuccessful

transfers conclude with a not-acknowledge bit (NACK). Both the master and the Si8901 generate ACK and NACK

bits. An ACK bit is generated when the receiving device pulls SDA low before the rising edge of the acknowledged

related (ninth) SCL pulse and maintains it low during the high period of the clock pulse. A NACK bit is generated

when the receiver allows SDA to be pulled high before the rising edge of the acknowledged related SCL pulse and

maintains it high during the high period of the clock pulse. An unsuccessful data transfer occurs if a receiving

device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master

2

attempts communication at a later time. Figure 10A shows the I C Slave Address Byte and CNFG_0 byte for the

Si8901. Figure 10B and Figure 10C show master/Si8901 ADC read transactions for Demand Mode and Burst

Mode, respectively.

S_R

P

S

SDA

SCL

Figure 8. Start and Stop Conditions

Not Acknowledge (NACK)

S

SDA

SCL

Acknowledge (ACK)

9

1

2

Figure 9. Acknowledge Cycle

16

Rev. 1.2

Si8900/1/2

Master to Slave

Slave to Master

D7 D6 D5 D4 D3 D2 D1 D0

S

1

‐

s6 s5 s4 s3 s2 s1 s0

A

A P

Si8901 CNFG_0 Write Data

Si8901 Slave Address

A) Si8901 CNFG_0 Write

D7 D6 D5 D4 D3 D2 D1 D0

S

s6 s5 s4 s3 s2 s1 s0

A

1

‐

A

P

Si8901 Write

Slave Address

Si8901 CNFG_0 Write Data

ADC Data

D7 D6 D5 D4 D3 D2 D1 D0

Si8901 Slave Address = 0xF0

S

s6 s5 s4 s3 s2 s1 s0

A

S

1

‐

1

0

A

P

D7 D6 D5 D4 D3 D2 D1 D0

Si8901 Read

Slave Address

Si8901 CNFG_0 Read Data

B) Si8901 Demand Mode ADC Read

D7 D6 D5 D4 D3 D2 D1 D0

s6 s5 s4 s3 s2 s1 s0

Si8901 Slave Address

S

1

‐

A

A P

Si8901 CNFG_0 Write Data

Periodic ADC Data

D7 D6 D5D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

S

A S

1

‐

1

0

A

s6 s5 s4 s3 s2 s1 s0

A

P

D7 D6 D5 D4 D3 D2 D1 D0

Si8901 Read

Slave Address

Si8901 CNFG_0

Read Data

C) Si8901 Burst Mode ADC Read

Figure 10. Si8901 ADC Read Operation

Rev. 1.2

17

Si8900/1/2

4.6. SPI Port (Si8902)

MASTER

Si8902

MOSI

MISO

SDI

SDO

EN

SPI Shift Register

7 6 5 4 3 2 1 0

SPI Shift Register

7 6 5 4 3 2 1 0

Receive Buffer

Baud Rate

Generator

SCLK

EN or Px.y

Figure 11. Master Connection to Si8902

EN

SCLK

SDI

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SDO

Figure 12. Si8902 Data/Clock Relationship

The Serial Peripheral Interface (SPI port) is a slave mode, full-duplex, synchronous, 4-wire serial bus that connects

to the master as shown in Figure 11. The master's clock and data timing must match the Si8902 timing shown

Figure 12 (for more information about clock and data timing, please see the “SPI Port” section of Table 2 on

page 5).

As shown in Figure 13, the Si8902 will update output data on SDO with falling SCLK edge and sample data on SDI

with rising SCLK edge. For idle condition between bytes, EN and SCLK should be held high by the master

controller. Also, during ADC_H and ADC_L byte reads, the master controller must hold SDI high. The master

transmits data from its master-out/slave-in terminal (MOSI) to the Si8902 serial read/write input terminal (SDI). The

Si8902 transmits data to the master from its serial data-out terminal (SDO) to the master-in/slave-out terminal

(MISO), and data transfer ends when the master returns EN to the high state. Figure 13A shows the Si8902

CNFG_0 Command Byte format, while Figures 13B and 13C show Si8902 Demand Mode and Burst Mode ADC

reads.

The Si8902 SDO pin will either drive low or drive high. It does not go into Hi-Z when EN is deasserted. Therefore,

a system with multiple SPI slaves should use separate MISO signals to avoid SPI bus contentions.

18

Rev. 1.2

Si8900/1/2

Master to Slave

Slave to Master

D7 D6 D5 D4 D3 D2 D1 D0

1

‐

A) Si8902 CNFG_0 Command Byte

D7

D0

D7

D0

8µS

Delay

8µS

Delay

1

‐

SDI High during Read

1

‐

CNFG_0 Write Byte

D7

D0 D7

D0

D7

Anew CNFG _0 WriteByte

and 8µS Delay are required

to re‐sample a Demand

Mode Channel

1

‐

1

0

1

CNFG_0 Read Byte

Demand Channel ADC Sample

B) Si8902 ADC Demand Mode

D7

D0

D7

D0

8µS

Delay

SDI High during Idle

1

‐

1

‐

Optional CNFG_0 WriteByteto Enable

Another Burst Channel or to Placean Existing

Burst Channel Back to Demand Mode

CNFG_0 Write Byte

D7

D0 D7

D0

1

‐

1

0

1

0

CNFG_0 Read Byte

Fisrt Burst Channel ADC Sample

Next Burst Channel ADC Sample

Periodic ADC Data

C) Si8902 ADC Burst Mode

Figure 13. Si8902 ADC Read Operation

4.7. Master Controller Firmware

The user's master controller must include firmware to manage the Si890x Demand and Burst operating modes and

serial port control. For more information on master controller firmware, see “AN637: Si890x Master Controller

Recommendations”, available for download at www.silabs.com/isolation.

Rev. 1.2

19

Si8900/1/2

5. Si8900/1/2 Configuration Registers

CNFG_0 Command Byte

Bit

D7

1

D6

1

D5

D4

D3

D2

—

D1

MODE

R/W

D0

Name

Type

MX1

R/W

MX0

R/W

VREF

R/W

PGA

R/W

Bit

7:6

5:4

Name

Function

1,1

Internal use. These bits are always set to 1.

MX1, MX0 ADC MUX Address.

ADC MUX address selection is controlled by MX1, MX0 as follows:

MX1

MX0

Selected ADC MUX Channel

1

0

1

0

1

0

Not Used

AIN2

AIN1

AIN0

3

VREF

ADC Voltage Reference Source

VDD is selected as the reference voltage when this bit is set to 1. An externally con-

nected voltage reference generator is selected when this bit is reset to 0.

2

1

—

Not used.

MODE

ADC Read Mode

ADC Demand Mode read is enabled when this bit is 1, and Burst Mode is enabled

when this bit is 0. For more information on Demand and Burst mode operation,

please see "4. ADC Data Transmission Modes" on page 11.

0

PGA

PGA Gain Set

PGA gain is 1 when this bit is set to 1. PGA gain is 0.5 when this bit is reset to 0.

ADC_H Byte

Bit

D7

1

D6

0

D5

MX1

R

D4

MX0

R

D3

D9

R

D2

D8

R

D1

D7

R

D0

D6

R

Name

Type

R

20

Rev. 1.2

Si8900/1/2

Bit

7:6

5:4

Name

Function

1,0

Internal use. These bits are always set to 1,0.

MX1, MX0 ADC MUX Address

ADC input MUX address for the converted data in ADC_H, ADC_L.

3:0

D9: D6

ADC conversion data bits D9:D6

Most significant 4 bits of ADC conversion data.

ADC_L Byte

Bit

D7

0

D6

D5

R

D5

D4

R

D4

D3

R

D3

D2

R

D2

D1

R

D1

D0

R

D0

0

Name

Type

R

Bit

7

Name

0

Function

Internal use. This bit is always set to 0.

6:1

D5:D0

ADC Conversion Data Bits D5:D0

Least significant 6 bits of ADC conversion data.

0

Internal use. This bit is always set to 0.

Rev. 1.2

21

Si8900/1/2

6. Applications

6.1. Isolated Outputs

The Si890x serial outputs are internally isolated from the device input side. To ensure safety in the end-user

application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low

voltage circuits (i.e., circuits with <30 VAC) by a certain distance (creepage/clearance). If a component straddles

this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large

high-voltage breakdown protection rating (commonly referred to as working voltage protection). Tables published in

the component standards (UL1577, VDE 0884-10, CSA 5A) are readily accepted by certification bodies to provide

proof for end-system specifications requirements. Refer to the end-system specification (62368-1, 60950-1, 60601-

1, etc.) requirements before starting any circuit design that uses galvanic isolation. The nominal output impedance

of a digital output is approximately 50   40%, which is a combination of the on-chip series termination resistor

and channel resistance of the output driver FET. When driving high-impedance terminated PCB traces, outputs can

be source terminated to minimize reflection.

The Si890x supply inputs must be bypassed with a parallel combination of 10 µF and 0.1 µF capacitors at VDDA

and VDDB as shown in Figure 14A. The 0.1 µF capacitors should be placed as close to the package as possible.

The Si890x uses the VDDA supply as its internal ADC voltage reference by default. A precision external reference

can be installed as shown in Figure 14A and must be bypassed with a parallel combination of 0.1 µF and 4.7 µF

capacitors. (Note that the CNFG_0 VREF bit must be set to 0 when using the external reference.) The Si890x has

an on-chip power-on-reset circuit (POR) that maintains the device in its reset state until VDDA has stabilized. A

2 k pull-up resistor and 10 nF capacitor on RST is strongly recommended to reduce the possibility of external

noise coupling into the reset input. The capacitor slows the rise of voltage on RST during power up. The delay

ensures a state machine resets on power up. A state machine reset with power on using the RC on RST will suffice

for most applications. For the master controller to have access to this pin, a single channel Si8610 digital isolator

can be placed in parallel with the Si890x and connected to the RST input. The Si8901 requires a 5 k pull-up

resistor to VDDA on the RSDA input.

Board Edge

2.7 V to 3.6 V

2.7 V to 5.5 V

Si890x

VDDA

VDDB

0.1 µF

10 µF

0.1 µF

10 µF

VDDA

Si890x

VREF

4.7 µF

0.1 µF

VREF

GNDA

GNDB

Optional External VREF

VDDA

8 mm

(min)

GNDA

GNDB

10 nF

5 KO

2 KO

RST

RSDA

GNDA

Required

for Si8901

GNDB

Board Edge

Keep‐out Area

(No metal in this area)

A

B

Figure 14. Si890x Installation

Figure 14B shows the required PCB ground configuration, where an 8 mm (min) “keep-out area” is provided to

ensure adequate creepage and clearance distances between the two grounds. PCB metal traces cannot be

present or cross through the keep-out area on the PCB top or bottom layer.

22

Rev. 1.2

Si8900/1/2

6.2. Device Reset

During power-up, the Si890x is held in the reset state by the internal power-on reset signal (POR) until VDDA

settles above VRST. When this condition is met, a delay is initiated that maintains the Si890x in the reset state for

time period tPOR, after which the reset signal is driven high allowing the Si890x to start-up. Note the maximum

allowable VDD ramp time (i.e. time from 0 V to VDDA settled above VRST) is 1 ms. Slower ramp times may cause

the Si890x to be released from reset before VDDA reaches the VRST level.

Figure 15 shows typical VDDA monitor reset timing where the internal reset is driven low (Si890x in reset) when

VDDA falls below VRST (e.g., during a power down or VDDA brownout). The internal reset is released to its high

state when VDDA again settles above VRST. External circuitry can also be used to force a reset event by driving

the external RST input low. A 2 k pull-up resistor on RST is recommended to avoid erroneous reset events from

external noise coupling to the RST input.

VDDA

VRSTH

VRSTL

VDDA(min)

Internal

RESET

tPOR

VDDA

Monitor

Reset

Power‐On Reset

Figure 15. Si890x Power-on and Monitor Reset

Rev. 1.2

23

Si8900/1/2

6.3. Application Example

Figure 16 shows the Si8900 operating as a single-phase ac line voltage and current monitor. The VDDA dc bias

circuit uses a low-cost 3.3 V linear regulator referenced to the neutral (white wire). The ac current is measured on

ADC input AIN0. The ac line voltage is scaled by resistors R17 and R18 and level-shifted by the 1.5 V VREF. AC

line current is measured using differential amplifier U1 connected across shunt resistor R1. Data is transferred to

the external controller or processor via the isolated UART.

Single‐Phase

AC Line

1.5 V

R2

R3

R4

Si8900

R1

AIN0

AIN1

R6

C2

U1

Low Cost

Dual OpAmp

R5

R7

R17

R11

C3

R18

R8

T_X

R_X

R9

R10

1.5 V

External

Master Controller

C1

R12

D1

U2

3.3 V

LDO

VDDA

GNDA

VDDB

GNDB

R14

C5

C4

R13

Output Side

Bias Supply

1.5 V

R15

Figure 16. AC Line Monitor Application Example

24

Rev. 1.2

Si8900/1/2

7. Device Pin Assignments

VDDA

VREF

AIN0

VDDA

VREF

AIN0

VDDA

RST

VDDB

NC

VDDB

NC

VDDB

NC

SDO

AIN1

VREF

AIN0

AIN1

AIN2

GNDA

AIN1

Rx

SCL

SDA

NC

SCLK

Si8900

Si8901

Si8902

Tx

AIN2

SDI

AIN2

NC

RST

NC

EN

RST

RSDA

GNDA

VDDB

GNDB

VDDB

GNDB

VDDB

GNDB

GNDA

Figure 17. Si8900/1/2 Pinout (SOIC-16 WB)

Table 6. Si8900/1/2 Pin Assignments

Si8900 Si8901 Si8902

Description

1

2

VDDA

Input side VDD bias voltage (typically 3.3 V)

VREF

RST Si8900/1: External voltage reference input.

Si8902: Active low reset.

3

4

5

6

7

AIN0

AIN1

AIN2

NC

AIN0

NC Si8900: ADC analog input channel 0.

Si8901: ADC analog input channel 0.

Si8902: No connection

AIN1 VREF Si8900: ADC analog input channel 1.

Si8901: ADC analog input channel 1.

Si8902: External VREF in.

AIN2

AIN0 Si8900: ADC analog input channel 2.

Si8901: ADC analog input channel 2.

Si8902: ADC analog input channel 0.

RST

AIN1 Si8900: No Connection.

Si8901: Active low reset.

Si8902: ADC analog input channel 1.

RST

RSDA AIN2 Si8900: Active low reset.

Si8901: RSDA bias resistor (typically 5 k).

Si8902: ADC analog input channel 2.

8

GNDA

GNDB

VDDB

Input side ground

9

Output side ground

10

11

12

Output side VDD bias voltage (2.7 V to 5.5 V)

EN Si8900/1: No connection. Si8902: SPI Port Enable.

SDI Si8900: UART unidirectional transmit output.

NC

Tx

SDA

2

Si8901: I C bidirectional data input/output.

Si8902: SPI port serial data in.

Rev. 1.2

25

Si8900/1/2

Table 6. Si8900/1/2 Pin Assignments (Continued)

Si8900 Si8901 Si8902

Description

13

Rx

SCL

SCLK Si8900: UART unidirectional receive input.

2

Si8901: I C port unidirectional serial clock input.

Si8902: SPI port unidirectional serial clock input.

14

NC

SDO Si8900/1: No connection.

Si8902: SPI port Serial data out (SDO)

15

16

NC

No connection

VDDB

Si8900/1/2: Output side VDD bias voltage (2.7 V to 5.5 V).

26

Rev. 1.2

Si8900/1/2

8. Ordering Guide

Table 7. Product Ordering Information^1,2

Part Number (OPN)

Serial Port

Package

Isolation Rating

Temp Range

Si8900B-A01-GS

Si8900D-A01-GS

Si8901B-A02-GS

Si8901D-A02-GS

Si8902B-A01-GS

Si8902D-A01-GS

Notes:

UART

WB SOIC

2.5 kV

5.0 kV

2.5 kV

5.0 kV

2.5 kV

5.0 kV

–40 to +85 °C

2

I C/SMBus

2

I C/SMBus

SPI Port

1. Add an “R” suffix to the part number to specify the tape and reel option. Example: “Si8900AB-A-ISR”.

2. All packages are RoHS-compliant.

Rev. 1.2

27

Si8900/1/2

9. Package Outline: 16-Pin Wide Body SOIC

Figure 18 illustrates the package details for the Si8900/1/2 Digital Isolator. Table 8 lists the values for the

dimensions shown in the illustration.

Figure 18. 16-Pin Wide Body SOIC

28

Rev. 1.2

Si8900/1/2

Table 8. Package Diagram Dimensions

Millimeters

Symbol

Min

—

Max

A

A1

A2

b

2.65

0.30

—

0.10

2.05

0.31

0.20

0.51

0.33

c

D

10.30 BSC

7.50 BSC

1.27 BSC

E

E1

e

L

0.40

0.25

0°

1.27

0.75

8°

h

θ

aaa

bbb

ccc

ddd

eee

fff

—

0.10

0.33

0.10

0.25

0.10

0.20

—

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise

noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC Outline MS-013, Variation AA.

4. Recommended reflow profile per JEDEC J-STD-020C specification

for small body, lead-free components.

29

Rev. 1.2

Si8900/1/2

10. Land Pattern: 16-Pin Wide-Body SOIC

Figure 19 illustrates the recommended land pattern details for the Si8900/1/2 in a 16-pin wide-body SOIC. Table 9

lists the values for the dimensions shown in the illustration.

Figure 19. 16-Pin SOIC Land Pattern

Table 9. 16-Pin Wide Body SOIC Land Pattern Dimensions

Dimension

Feature

Pad Column Spacing

Pad Row Pitch

Pad Width

(mm)

9.40

1.27

0.60

1.90

C1

E

X1

Y1

Pad Length

Notes:

1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN

for Density Level B (Median Land Protrusion).

2. All feature sizes shown are at Maximum Material Condition (MMC) and a card

fabrication tolerance of 0.05 mm is assumed.

30

Rev. 1.2

Si8900/1/2

11. Top Marking: 16-Pin Wide Body SOIC

11.1. Si8900/1/2 Top Marking

Si890XY

YYWWRTTTTT

e4

TW

11.2. Top Marking Explanation

Si890 = Isolator product series

X = Serial Port

Base Part Number

0 = UART

1 = I C

Ordering Options

2

Line 1 Marking:

2 = SPI

Y = Insulation rating

(See Ordering Guide for more

information).

B = 2.5 kV; D = 5.0 kV

YY = Year

WW = Workweek

Assigned by assembly subcontractor. Corresponds to the

year and workweek of the mold date.

Line 2 Marking:

Line 3 Marking:

Manufacturing code from assembly house

“R” indicates revision

RTTTTT = Mfg Code

Circle = 1.7 mm Diameter

(Center-Justified)

“e4” Pb-Free Symbol

TW = Taiwan

Country of Origin ISO Code

Abbreviation

Rev. 1.2

31

Si8900/1/2

DOCUMENT CHANGE LIST

Revision 0.5 to Revision 1.0

 No changes.

Revision 1.0 to Revision 1.1

 Removed “pending” throughout.

 Changed AN638 reference to AN637.

 Updated "11. Top Marking: 16-Pin Wide Body SOIC" on page 31.

Revision 1.1 to Revision 1.2

April, 2019

 Table 1, Changed GND1 to GNDA and GND2 to GNDB.

 Table 2, tconv changed from 2 µs to 2.5 µs.

 Table 2, Digital Outputs, changed min for Voh with VDDB=3.3 V to 3.1 V.

 Table 2, Digital Outputs, added typical for Voh with VDDB=3.3 V to 3.1 V.

 Table 2, Digital Outputs, changed specification name Digital Output Series Impedance to Digital Output Source

Resistance.

 Table 2, Digital Outputs, changed typical source resistance from 85  to 50  typical.

 Table 2, Serial Ports, changed maximum UART Bit Rate from 234 kbps to 500 kbps.

 Table 2, Serial Ports, changed specification name SPI port to SPI Bit Rate.

 Table 2, Serial Ports, added test condition for SPI Port, Mode 3: CPOL=1, CPHA=1.

 Table 2, Serial Ports, changed maximum SPI Bit Rate from 2 mbps to 2.5 mbps.

 Table 3, Removed data from NB SOIC 16.

 Figure 2, Changed VDD1 and VDD2 to VDDA and VDDB.

 Table 5, Updated certification nomenclature for CSA from 61010-1 to 62368-1, up to 1000 VRMS basic

insulation working voltage.

 Table 5, Updated certification nomenclature for VDE from IEC 60747-5-2 to VDE 0884-10.

 Removed Figure 3, NB SOIC 16 derating curve.

 Function Description, removed ADC option of internal voltage reference.

 Function Description, described RST and RSDA pin functions.

 Figure 4, Updated Si8902 GND pin names.

 ADC Data Transmission Modes, Updated description of Demand and Burst Modes.

 Figure 5, Showed tconv starting at the end of CNFG_0 byte for Si8901 Demand Mode.

 UART (Si8900), Changed name of AN635 from AC Line Monitoring to Si8900 Automatic Band Rate Detection.

 Figure 8A, Showed proper span of ADC data.

 Figure 11B and 11C, Added ACK bit between slave address and echo CNFG_0 byte.

 Figure 12, Removed EN signal from controlling SDO driver circuit.

 SPI Port (Si8902), Added requirement of SDI being held high during byte reads.

 SPI Port (Si8902), SDO does not enter Hi-Z state with EN function.

 Si8900/1/2 Configuration Registers, removed default setting from registers.

 Applications, Isolated Outputs, recommend a 10 nF capacitor from RST to GNDA for reliable reset on power

cycle.

 Table 7, updated OPN for Si8901 from revision A01 to A02.

 Table 7, removed Note 3.

32

Rev. 1.2

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Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without

further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior

notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance

of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to

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型号：	SI8901D-A02-GSR
厂家：	SILICON
描述：	ADC, Successive Approximation, 转换器
文件：	总33页 (文件大小：1548K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI8901D-A02-GSR [SILICON]

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