SL28504BZC-2T [SILICON]
Clock Generator for Intel®Eaglelake Chipset;型号: | SL28504BZC-2T |
厂家: | SILICON |
描述: | Clock Generator for Intel®Eaglelake Chipset |
文件: | 总28页 (文件大小:410K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SL28504-2
Clock Generator for Intel®Eaglelake Chipset
• 25MHz Free run for WOL
Features
• Selectable 25MHz/24.576MHz output
• Buffered Reference Clock 14.318 MHz
• Compliant to Intel® CK505
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Low-voltage frequency select input
• I2C support with readback capabilities
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Differential CPU clocks with selectable frequency
• 100 MHz Differential SRC clocks
• 96 MHz Differential DOT clock
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 56-pin TSSOP packages
CPU
SRC
PCI
x6
REF
x 2
DOT96 USB_48 24.576M 25M
• 48 MHz USB clocks
x2 / x3
x8/x11
x 1
x1
x1
x2
• 33 MHz PCI clock
Block Diagram
Pin Configuration
Xin
Xout
14.318MHz
Crystal
PCI_0/ CR#_A
VDD_PCI
1
56
SCLK
REF0
2
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SDATA
PLL Reference
Divider
PCI_1/ CR#_B
PCI_2
3
REF0/FSC/TEST_SEL
VDD_REF
4
CPU[1:0]
PCI_3
5
XTAL_IN
PLL1
PCI_4 / SRC5_EN
PCIF_0 / ITP_EN
VSS_PCI
6
XTAL_OUT
7
VSS_REF
SRC8/CPU2_ITP
8
FSB / TEST_MODE
VDD_48
9
CK_PWRGD / PWRDWN#
VDD_CPU
PCI[4:0]; PCIF0
SRC
USB_48 / FSA
VSS_48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PLL3
Divider
CPU0
VDD_IO
CPU0#
SRC0 / DOT96
SRC0# / DOT96#
VSS_IO
VSS_CPU
CPU1
SRC_SATA
25M0_F
CPU1#
VDD_PLL3
VDD_CPU_IO
*SEL_24.576M
SRC8 / CPU2_ITP
SRC8# / CPU2_ITP#
VDD_SRC_IO
SRC7/ CR#_F
SRC7#/ CR#_E
VSS_SRC
SL28504-2
SRC1/25M0_F
SRC1#/25M1_24.576M
VSS_PLL3
Divider
PLL4
PLL2
VDD_PLL3_IO
SRC2_SATA
SRC2#_SATA#
VSS_SRC
25M1_24.576M
SRC3/ CR#_C
SRC3#/ CR#_D
VDD_SRC_IO
SRC4
SRC6
DOT96/SRC0
USB_48
SRC6#
Divider
VDD_SRC
SRC5/ PCI_STOP#
SRC5#/ CPU_STOP#
SRC4#
PCI_STOP#
CPU_STOP#
FSC:A]
* Internal Pull-Down
SATA_SEL
Control Logic
CK_PWRGD/PD#
SDATA
SEL_24.576M
SCLK
........................ DOC #: SP-AP-0051 (Rev. AA) Page 1 of 27
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669
www.silabs.com
SL28504-2
56-TSSOP Pin Definitions
Pin No.
Name
Type
Description
1
PCI_0/ CR#_A
I/O, SE 33 MHz clock/3.3V CR# Input mappable via I2C to control either SRC 0 or
SRC 2. Default PCI_0
2
3
VDD_PCI
PWR 3.3V Power supply for PCI PLL.
PCI_1/ CR#_B
I/O, SE 33 MHz clock/3.3V CR# Input mappable via I2C to control either SRC 1 or
SRC 4. Default PCI_1.
4
5
6
PCI_2
O, SE 33 MHz clock.
PCI_3
O, SE, 33 MHz clock.
PCI4 /SRC5_EN
I/O, SE 33 MHz clock output/3.3V-tolerant input for SRC enable
(Sampled on CKPWRGD assertion)
1 = SRC5, 0 =CPU_STOP#/PCI_STOP#
7
PCIF_0/ITP_EN
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled
on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND Ground for outputs.
9
VDD_48
PWR 3.3V Power supply for outputs and PLL.
10
USB_48/FSA
I/O
3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output. Refer
to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
11
12
13
VSS_48
GND Ground for outputs.
VDD_IO
PWR 3.3V-1.05V Power supply for outputs.
SRC0/DOT96T
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected
via I2C default is SRC0.
14
SRC0#/DOT96#
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected
via I2C default is SRC0.
15
16
17
18
VSS_IO
GND Ground for PLL2.
VDD_PLL3
PWR 3.3V Power supply for PLL3
SRC1/25M0_F
SRC1#/25M1_24.576M
O, SE 100 MHz Differential serial reference clocks/ Free run 25MHz clock output
O, SE 100 MHz Differential serial reference clocks/ 25MHz clock output/24.576MHz clock
output
19
20
21
22
23
24
VSS_PLL3
GND Ground for PLL3.
VDD_PLL3_IO
SRC2_SATA
SRC2#_SATA#
VSS_SRC
PWR 3.3V-1.05V power supply for PLL3
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
GND Ground for outputs.
SRC3/ CR#_C
I/O, 100-MHz Differential serial reference clocks / 3.3V CR#_C, input, mappable via
Dif
I/O, 100-MHz Differential serial reference clocks / 3.3V CR#_D input, mappable via I2C
Dif to control either SRC 1 or SRC 4. Default SRC3
I2C to control either SRC 0 or SRC 2. Default SRC3
25
SRC3#/ CR#_D
26
27
28
29
VDD_SRC_IO
SRC4
PWR 3.3V-1.05V power supply for SRC outputs.
O, DIF 100 MHz Differential serial reference clocks.
SRC4#
O, DIF 100 MHz Differential serial reference clocks.
CPU_STOP#/SRC5#
I/O, 3.3V tolerant input for stopping CPU outputs./100 MHz Differential serial reference
Dif
I/O, 3.3V tolerant input for stopping PCI and SRC outputs./100 MHz Differential serial
Dif reference clocks.The option is selected by SRC5_EN
PWR 3.3V Power supply for SRC PLL.
clocks. The option is selected by SRC5_EN
30
31
PCI_STOP#/SRC5
VDD_SRC
........................ DOC #: SP-AP-0051 (Rev. AA) Page 2 of 27
SL28504-2
56-TSSOP Pin Definitions
Pin No.
32
Name
Type
Description
SRC6#
SRC6
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
GND Ground for outputs.
33
34
VSS_SRC
35
SRC7#/ CR#_E
I/O, 100 MHz Differential serial reference clocks/3.3V CR#_E Input controlling SRC6.
Dif Default SRC7.
36
SRC7/ CR#_F
I/O, 100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
Dif Default SRC7.
37
38
VDD_SRC_IO
PWR 3.3V-1.05V power supply for SRC outputs.
SRC8#/CPUC2_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
39
40
SRC8/CPUT2_ITP
SEL_24.576M
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
I, PD Select 25M1_24.576M output and SRC1
0 = 25M1, M= SRC1, 1 = 24.576M
41
42
VDD_CPU_IO
CPU1#
PWR 3.3V-1.05V power supply for CPU outputs.
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
43
CPU1
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
44
45
46
47
48
VSS_CPU
GND Ground for outputs.
CPU0#
O, DIF Differential CPU clock outputs.
O, DIF Differential CPU clock outputs.
PWR 3.3V Power supply for CPU PLL.
CPU0
VDD_CPU
CK_PWRGD/PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
49
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
50
51
52
53
VSS_REF
XTAL_OUT
XTAL_IN
GND Ground for outputs.
O, SE 14.318 MHz Crystal output.
I
14.318 MHz Crystal input.
VDD_REF
PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
54
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects
test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH. Refer to DC
Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
55
56
SMB_DATA
SMB_CLK
I/O
I
SMBus compatible SDATA.
SMBus compatible SCLOCK.
........................ DOC #: SP-AP-0051 (Rev. AA) Page 3 of 27
SL28504-2
Frequency Select Pin (FSA, FSB and FSC)
FSC
0
FSB
0
FSA
0
CPU
SRC
PCIF/PCI
REF
DOT96
USB
266 MHz
133 MHz
200 MHz
166 MHz
333 MHz
100 MHz
400 MHz
Reserved
0
0
1
0
1
0
0
1
1
100 MHz
33 MHz
14.318 MHz
Reserved
96 MHz
48 MHz
1
0
0
1
0
1
1
1
0
1
1
1
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
their default setting at power-up. The use of this interface is
.
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
18:11
19
18:11
19
27:20
Byte Count–8 bits
20
(Skip this step if I2C_EN bit set)
28
36:29
37
Acknowledge from slave
Data byte 1–8 bits
27:21
28
Slave address–7 bits
Read = 1
Acknowledge from slave
Data byte 2–8 bits
29
Acknowledge from slave
Byte Count from slave–8 bits
45:38
37:30
........................ DOC #: SP-AP-0051 (Rev. AA) Page 4 of 27
SL28504-2
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Description
Bit
46
....
....
....
....
Description
Acknowledge from slave
Bit
38
Acknowledge
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
46:39
47
Data byte 1 from slave–8 bits
Acknowledge
55:48
56
Data byte 2 from slave–8 bits
Acknowledge
....
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
....
....
....
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
........................ DOC #: SP-AP-0051 (Rev. AA) Page 5 of 27
SL28504-2
Control Registers
Byte 0: Control Register 0
Bit
7
@Pup
HW
HW
HW
0
Name
FS_C
Description
CPU Frequency Select Bit, set by HW
6
FS_B
CPU Frequency Select Bit, set by HW
CPU Frequency Select Bit, set by HW
5
FS_A
4
iAMT_EN
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled
3
2
1
0
0
0
Reserved
Reserved
SATA_SEL
Reserved
Reserved
Select source of SATA clock
0 =PLL3, 1= PLL4
0
1
PD_Restore
Save Config. In powerdown
0 = Config. Cleared, 1 = Config. Saved
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
0
SRC0_SEL
Select for SRC0 or DOT96
0 = SRC0, 1 = DOT96
6
5
0
0
PLL1_SS_DC
PLL3_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
Select for down or center SS
0 = Down spread, 1 = Center spread
4
3
2
1
0
0
0
0
1
1
Reserved
Reserved
Reserved
Reserved
PCI_SEL
Reserved
Reserved
Reserved
Reserved
Select source of PCI clocks
0=PLL1, 1=PLL3
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
REF0_OE
Output enable for REF0
0 = Output Disabled, 1 = Output Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
USB48_OE
PCIF0_OE
PCI4_OE
PCI3_OE
PCI2_OE
PCI1_OE
PCI0_OE
Output enable for USB48
0 = Output Disabled, 1 = Output Enabled
Output enable for PCIF5
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
........................ DOC #: SP-AP-0051 (Rev. AA) Page 6 of 27
SL28504-2
Byte 3: Control Register 3
Bit
7
@Pup
Name
Reserved
Description
1
1
1
1
Reserved
Reserved
Reserved
6
Reserved
5
Reserved
4
SRC8/CPU2_ITP_OE
Output enable for SRC8 or CPU2_ITP
0 = Output Disabled, 1 = Output Enabled
3
2
1
1
SRC7_OE
SRC6_OE
Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
1
0
1
1
RESERVED
SRC4_OE
RESERVED
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
1
SRC3_OE
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC2_SATA_OE
SRC1_OE
Output enable for SRC2_SATA
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
SRC0/DOT96_OE
CPU1_OE
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
CPU0_OE
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
PLL1_SS_EN
PLL3_SS_EN
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
CR#_A_EN
Enable CR#_A (clk req)
0 = Disabled, 1 = Enabled,
6
5
4
3
2
0
0
0
0
0
CR#_A_SEL
CR#_B_EN
CR#_B_SEL
CR#_C_EN
CR#_C_SEL
Set CR#_A SRC0 or SRC2
0 = CR#_ASRC0, 1 = CR#_ASRC2
Enable CR#_B(clk req)
0 = Disabled, 1 = Enabled,
Set CR#_B SRC1 or SRC4
0 = CR#_BSRC1, 1 = CR#_BSRC4
Enable CR#_C (clk req)
0 = Disabled, 1 = Enabled
Set CR#_C SRC0 or SRC2
0 = CR#_CSRC0, 1 = CR#_CSRC2
........................ DOC #: SP-AP-0051 (Rev. AA) Page 7 of 27
SL28504-2
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
1
0
CR#_D_EN
Enable CR#_D (clk req)
0 = Disabled, 1 = Enabled
0
0
CR#_D_EN
Enable CR#_D (clk req)
0 = Disabled, 1 = Enabled
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
CR#_E_EN
Enable CR#_E (clk req) SRC6
0 = Disabled, 1 = Enabled
6
0
CR#_F_EN
Enable CR#_F (clk req) SRC8
0 = Disabled, 1 = Enabled
5
4
3
2
1
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SRC_STP_CTRL
Allows control of SRC with assertion of PCI_STOP#
0 = Free running SRC 1 = Stopped with PCI_STOP#
Byte 7: Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
0
1
1
0
0
0
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
6
5
4
3
2
Vendor ID Bit 2
1
Vendor ID Bit 1
0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
7
@Pup
Name
Description
0
0
0
0
Device_ID3
Device_ID2
Device_ID1
Device_ID0
0000 = 56-TSSOP
0001 = 64-TSSOP
0010 = Reserved
0011 = 56-QFN
6
5
0100 = 64-QFN
0101 = Reserved
0110 = Reserved
0111 = 56-SSOP
1000 = Reserved
1001 = Reserved
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
4
3
0
Reserved
Reserved
........................ DOC #: SP-AP-0051 (Rev. AA) Page 8 of 27
SL28504-2
Byte 8: Control Register 8 (continued)
Bit
2
@Pup
Name
Description
0
1
Reserved
25M0_F_OE
Reserved
1
Output enable for 25M0_F
0 = Output Disabled, 1 = Output Enabled
0
1
25M1_24.576M_OE
Output enable for 25M1_24.576M
0 = Output Disabled, 1 = Output Enabled
Byte 9: Control Register 9
Bit
@Pup
Name
Description
7
0
PCIF5_STP_CTRL
Allows control of PCIF5 with assertion of PCI_STOP#
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
6
5
0
1
Reserved
REF Bit1
Reserved
REF drive strength Setting 1 of 3 (see Byte 13 and 14 for more settings)
0 = Low, 1 = High
4
3
0
0
Reserved
Reserved
TEST_MODE_ENTRY
Allows entry into test mode
0 = Normal Operation, 1 = Enter test mode(s)
2
1
0
1
0
1
I2C_VOUT<2>
I2C_VOUT<1>
I2C_VOUT<0>
I2C_VOUT[2:0]
000 = 0.30V
001 = 0.40V
010 = 0.50V
011 = 060V
100 = 0.70V
101 = 0.80V (default)
110 = 0.90V
111 = 1.00V
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
HW
SRC5_EN
SRC5_EN latche status
0= CPU_STP#/PCI_STP#; 1= SRC5
6
5
4
3
2
1
0
0
0
0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPU1_STP_CTRL
Enable CPU_STOP# control of CPU1
0 = Free running, 1= Stoppable
0
1
CPU0_STP_CTRL
Enable CPU_STOP# control of CPU0
0 = Free running, 1= Stoppable
Byte 11: Control Register 11
Bit
7
@Pup
Name
Description
0
0
1
Reserved
Reserved
25M0_F
Reserved
Reserved
6
5
25M0_F Output Enabled applies to Powerdown / M1
0 = 25MHz disabled in Powerdown / M1
1 = 25MHz enabled in Powerdown / M1; Sticky 1
4
0
Reserved
Reserved
........................ DOC #: SP-AP-0051 (Rev. AA) Page 9 of 27
SL28504-2
Byte 11: Control Register 11 (continued)
3
2
0
1
CPU2_iAMT_EN
CPU1_iAMT_EN
PCIF5/ITP_EN
AMT_EN
CPU2_AMT_EN CPU1_AMT_EN
Description
x
x
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Reserved
CPU1 = M1 Clock
CPU2 - M1 Clock
CPU1 and CPU2 = M1 Clock
1
0
0
1
Reserved
Reserved
CPU2_STP_CRTL
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
Byte 12: Byte Count
Bit
7
@Pup
Name
Reserved
Reserved
BC5
Description
0
0
0
1
0
0
1
1
Reserved
Reserved
Byte count
Byte count
Byte count
Byte count
Byte count
Byte count
6
5
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
Byte 13: Control Register 13
Bit
7
@Pup
Name
Description
0
1
0
0
1
0
0
0
PCIF/PCI Bit 2
PCIF/PCI Bit 1
PCIF/PCI Bit 0
USB Bit 2
Drive Strength Control - Bit[2:0]
Note: REF Bit 1 is located in Byte 9 Bit 5
6
5
Buffer
Strength
Bit 2
(Various Bytes)
Bit 1
Bit 0
(Various Bytes) (Various Bytes)
4
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Strongest
3
USB Bit 1
2
USB Bit 0
1
REF Bit 2
0
REF Bit 0
Default
Weakest
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
0
25M_24.576M Bit 2
25M_24.576M Bit 2 drive strength
0 = Low, 1 = High
6
5
1
0
25M_24.576M Bit 1
25M_24.576M Bit 0
25M_24.576M SE1/SE2 Bit 1 drive strength
0 = Low, 1 = High
25M_24.576M Bit 0 drive strength
0 = Low, 1 = High
4
3
2
0
0
1
RESERVED
RESERVED
SATA_SS_EN
RESERVED
RESERVED
Enable SATA spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
...................... DOC #: SP-AP-0051 (Rev. AA) Page 10 of 27
SL28504-2
Bit
@Pup
Name
Description
1
1
EN_CFG0_SET
By defalult CFG0 pin strap sets the SMBus initial values to select the HW
mode. When this bit is written0, subsequent SMBus accesses is the Lathes
Open state, can overwrite the CFG0 pin setting into the SMBus bits and set
the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5
0
1
SW_PCI
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are
resumed in a synchronous manner with no short pulses.
Byte 15: Control Register 15
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
CPU_DAF_N7
CPU_DAF_N6
CPU_DAF_N5
CPU_DAF_N4
CPU_DAF_N3
CPU_DAF_N2
CPU_DAF_N1
CPU_DAF_N0
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
6
5
4
3
2
1
0
Byte 16: Control Register 16
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
CPU_DAF_N8
CPU_DAF_M6
CPU_DAF_M5
CPU_DAF_M4
CPU_DAF_M3
CPU_DAF_M2
CPU_DAF_M1
CPU_DAF_M0
See Byte 14 for description
6
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
5
4
3
2
1
0
Byte 17: Control Register 17
Bit
7
@Pup
Name
Description
PCI-E Dial-A-Frequency® Bit N7
PCI-E Dial-A-Frequency Bit N6
PCI-E Dial-A-Frequency Bit N5
PCI-E Dial-A-Frequency Bit N4
PCI-E Dial-A-Frequency Bit N3
PCI-E Dial-A-Frequency Bit N2
PCI-E Dial-A-Frequency Bit N1
PCI-E Dial-A-Frequency Bit N0
0
0
0
0
0
0
0
0
PCI-E_N7
PCI-E_N6
PCI-E_N5
PCI-E_N4
PCI-E_N3
PCI-E_N2
PCI-E_N1
PCI-E_N0
6
5
4
3
2
1
0
Byte 18: Control Register 18
Bit @Pup
Name
Description
...................... DOC #: SP-AP-0051 (Rev. AA) Page 11 of 27
SL28504-2
Byte 18: Control Register 18 (continued)
7
6
5
4
0
0
0
0
SMSW_EN
Enable Smooth Switching
0 = Disabled, 1= Enabled
SMSW_SEL
Smooth switch select
0 = PLL1, 1 = PLL3
Prog_PCI-E_EN
Prog_CPU_EN
Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
Programmable CPU frequency enable
0 = Disabled, 1= Enabled
3
2
1
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Table 4. Crystal Recommendations
Frequency
Drive
(max.)
Shunt Cap Motional
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
(Fund)
Cut
Loading Load Cap
(max.)
(max.)
14.31818 MHz
AT
Parallel 20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
The SL28504-2 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal causes the SL28504-2 to
operate at the wrong frequency and violates the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading
C lo ck C h ip
C i2
C i1
P in
3 to 6 p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, use the total capac-
itance the crystal sees to calculate the appropriate capacitive
loading (CL).
X 2
X 1
C s2
C s1
T ra ce
2 .8 p F
X T A L
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
C e 1
C e 2
T rim
3 3 p F
Figure 2. Crystal Loading Example
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
1
CLe
=
1
1
(
)
+
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
Figure 1. Crystal Capacitive Clarification
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires, etc.)
...................... DOC #: SP-AP-0051 (Rev. AA) Page 12 of 27
SL28504-2
Dial-A-Frequency® (CPU and PCIEX)
switch circuit is less than 1 MHz/0.667 s. The frequency
overshoot and undershoot is less than 2%.
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
The Smooth Switch circuit assigns auto or manual. In Auto
mode, clock generator assigns smooth switch automatically
when the PLL does overclocking. For manual mode, assign
the smooth switch circuit to PLL via Smbus. By default the
smooth switch circuit is set to auto mode. PLL can be
over-clocked when it does not have control of the smooth
switch circuit but it is not guaranteed to transition to the new
frequency without large frequency glitches.
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
• “N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
Do not enable over-clocking and change the N values of both
PLLs in the same SMBUS block write and use smooth switch
mechanism on spread spectrum on/off.
• “G” stands for the PLL Gear Constant, which is determined
by the programmed value of FS[E:A]. See Table ,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
control of the N register, the M value is fixed and
documented in Table , Frequency Select Table.
PD_RESTORE
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the SL28504-2 initiates a full reset. The result of this is
that the clock chip emulates a cold power on start and goes to
the “Latches Open” state. If the PD_RESTORE bit is set to a
‘1’ then the configuration is stored upon PWRDWN# asserted
LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then
the PD_RESTORE bit must be ignored. In other words, in Intel
iAMT mode, PWRDWN# reset is not allowed.
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
Associated Register Bits
PWRDWN# (Power down) Clarification
• CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
The CKPWRGD/PWRDWN# pin is a dual-function pin. During
initial power up, the pin functions as CKPWRGD. Once
CKPWRGD has been sampled HIGH by the clock chip, the pin
assumes PD# functionality. The PD# pin is an asynchronous
active LOW input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD# is also an asynchronous input for powering
up the system. When PD# is asserted LOW, clocks are driven
to a LOW value and held before turning off the VCOs and the
crystal oscillator.
• CPU_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table , Frequency Select Table.
• CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default
= 0, the allowable values for M are detailed in Table ,
Frequency Select Table
PWRDWN# (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
• SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain
valid values before SRC_DAF is set. Default = 0, (No DAF).
PWRDWN# Deassertion
• SRC_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table , Frequency Select Table.
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 4 is an example showing the relationship of
clocks coming up.
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
...................... DOC #: SP-AP-0051 (Rev. AA) Page 13 of 27
SL28504-2
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power down Assertion Timing Waveform
Ts table
<1.8 ms
PD#
CP UT , 133MHz
CP UC, 133MHz
S RCT 100MHz
S RCC 100MHz
US B , 48MHz
DOT 96T
DOT 96C
P CI, 33MHz
REF
Tdriv e_PW R D N #
<300 s , >200m V
Figure 4. Power down Deassertion Timing Waveform
Figure 5. CK_PWRGD Timing Diagram
...................... DOC #: SP-AP-0051 (Rev. AA) Page 14 of 27
SL28504-2
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
1.8 ms
CPU_STOP#
PD#
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
...................... DOC #: SP-AP-0051 (Rev. AA) Page 15 of 27
SL28504-2
1.8 ms
CPU_STOP#
PD#
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
.
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks are affected by this pin if their
corresponding control bit in the SMBus register is set to allow
them to be free running.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
PCI_STP# Deassertion
.
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods, after PCI_STP# transi-
tions to a HIGH level.
Tdrive_SRC
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
...................... DOC #: SP-AP-0051 (Rev. AA) Page 16 of 27
SL28504-2
.
Table 5. Output Driver Status during PCI-STOP# and CPU-STOP#
PCI_STOP# Asserted
CPU_STOP# Asserted
Running
SMBus OE Disabled
Single-ended Clocks Stoppable
Non stoppable
Stoppable
Driven low
Driven low
Running
Running
Differential Clocks
Clock driven high
Clock# driven low
Running
Clock driven high
Clock# driven low
Running
Clock driven Low or 20K
pulldown
Non stoppable
Table 6. Output Driver Status
All Differential Clocks except
CPU1
All Single-ended Clocks
w/o Strap w/ Strap
Low Hi-z
CPU1
Clock
Clock#
Clock
Clock#
Latches Open State
Powerdown
M1
Low or 20K pulldown Low
Low or 20K pulldown Low
Low or 20K pulldown Low
Low or 20K pulldown Low
Low or 20K pulldown Low
Low
Low
Hi-z
Hi-z
Running
Running
.
Figure 12. Clock Generator Power up/Run State Diagram
...................... DOC #: SP-AP-0051 (Rev. AA) Page 17 of 27
SL28504-2
C l o c k O f f t o M1
3.3V
Vcc
2.0V
T_delay t
FSC
FSB
FSA
CPU_STOP#
PCI_STOP#
CKPWRGD/PWRDWN
CK505 SMBUS
CK505 State
Off
Latches Open
Off
M1
BSEL[0..2]
Off
CK505 Core Logic
PLL1
Locked
CPU1
PLL2 & PLL3
All Other Clocks
REF Oscillator
T_delay2
T_delay3
Figure 13. BSEL Serial Latching
...................... DOC #: SP-AP-0051 (Rev. AA) Page 18 of 27
SL28504-2
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Analog Supply Voltage
IO Supply Voltage
Input Voltage
Condition
Min.
Max.
4.6
4.6
1.5
4.6
150
85
Unit
V
–
–
VDD_A
VDD_IO
VIN
V
V
Relative to VSS
Non-functional
Functional
–0.5
–65
-40
VDC
°C
°C
TS
Temperature, Storage
TA
Temperature, Operating
Ambient
TJ
Temperature, Junction
Functional
–
–
150
20
°C
ØJC
Dissipation, Junction to Case Mil-STD-883E Method 1012.1
°C/
W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
–
°C/
W
ESDHBM
ESD Protection (Human Body MIL-STD-883, Method 3015
Model)
2000
V
UL-94
MSL
Flammability Rating
At 1/8 in.
V–0
1
Moisture Sensitivity Level
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
VDD core
Description
Condition
Min.
3.135
2.0
Max.
3.465
VDD + 0.3
0.8
Unit
3.3V Operating Voltage
3.3V Input High Voltage (SE)
3.3V Input Low Voltage (SE)
Input High Voltage
3.3 ± 5%
V
V
V
V
V
V
V
V
VIH
VIL
VSS – 0.3
2.2
VIHI2C
VILI2C
VIH_FS
VIL_FS
VIHFS_C_TEST
SDATA, SCLK
SDATA, SCLK
–
Input Low Voltage
–
1.0
FS_[A,B] Input High Voltage
FS_[A,B] Input Low Voltage
0.7
1.5
VSS – 0.3
2
0.35
FS_C, SEL_24.576M Input
High Voltage
VDD + 0.3
VIMFS_C_NORMAL FS_C, SEL_24.576M Input
Middle Voltage
0.7
2
V
V
VILFS_C_NORMAL FS_C, SEL_24.576M Input Low
Voltage
VSS – 0.3
0.35
IIH
SEL_24.576M_HI SEL_24.576M Input High
Voltage
SEL_24.576M_MI SEL_24.576M Input Mid
Voltage
SEL_24.576M_LO SEL_24.576M Input Low
Input High Leakage Current
Except internal pull-down resistors, 0 < VIN < VDD
Typ. 2.75V
–
5
A
2.40
VDD
V
GH
Typ. 1.65V
1.30
0
2.00
V
V
D
Typ. 0.550V
0.900
Voltage
W
IIL
Input Low Leakage Current
Except internal pull-up resistors, 0 < VIN < VDD
–5
2.4
–
–
–
A
V
VOH
VOL
3.3V Output High Voltage (SE) IOH = –1 mA
3.3V Output Low Voltage (SE) IOL = 1 mA
Low Voltage IO Supply Voltage
0.4
V
VDD IO
VOH
VOL
1
3.465
0.90
0.40
3.3V Input High Voltage (DIFF)
0.70
V
V
3.3V Input Low Voltage (DIFF)
...................... DOC #: SP-AP-0051 (Rev. AA) Page 19 of 27
SL28504-2
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
IOZ
High-impedance Output
Current
–10
10
A
CIN
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
1.5
5
6
pF
pF
nH
V
COUT
LIN
–
7
VXIH
VXIL
Xin High Voltage
0.7VDD
VDD
0.3VDD
250
Xin Low Voltage
0
–
V
IDD3.3V
Dynamic Supply Current
mA
...................... DOC #: SP-AP-0051 (Rev. AA) Page 20 of 27
SL28504-2
AC Electrical Specifications
Parameter
Crystal
TDC
Description
Condition
Min.
Max.
Unit
XIN Duty Cycle
XIN Period
The device operates reliably with input
dutycyclesup to 30/70 but theREF clock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
When XIN is driven from an external
clock source
69.841
71.0
ns
TR/TF
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Measured between 0.3VDD and 0.7VDD
–
–
10.0
500
ns
ps
TCCJ
As an average over 1-s duration
CPU at 0.7V
TDC
45
55
CPUT and CPUC Duty Cycle
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
10.0100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODAbs
100 MHz CPUT and CPUC Period
133 MHz CPUT and CPUC Period
166 MHz CPUT and CPUC Period
200 MHz CPUT and CPUC Period
266 MHz CPUT and CPUC Period
333 MHz CPUT and CPUC Period
400 MHz CPUT and CPUC Period
10.02406 10.02607
100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
166 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
200 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
266 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
333 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
400 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
7.51804
6.01444
5.01203
3.75902
3.00722
2.50601
9.91400
7.51955
6.01564
5.01303
3.75978
3.00782
2.50652
10.0860
100 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
7.41425
5.91440
4.91450
3.66463
2.91470
2.41475
9.91406
7.41430
5.91444
4.91453
3.66465
7.58575
6.08560
5.08550
3.83538
3.08530
2.58525
10.1362
7.62340
6.11572
5.11060
3.85420
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
133 MHz CPUT and CPUC Absolute
period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
166 MHz CPUT and CPUC Absolute
period
200 MHz CPUT and CPUC Absolute
period
266 MHz CPUT and CPUC Absolute
period
333 MHz CPUT and CPUC Absolute
period
400 MHz CPUT and CPUC Absolute
period
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 166 MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 200 MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 266 MHz CPUT and CPUC Absolute
period, SSC
...................... DOC #: SP-AP-0051 (Rev. AA) Page 21 of 27
SL28504-2
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
2.91472
3.10036
TPERIODSSAbs 333 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
ns
2.41477
2.59780
TPERIODSSAbs 400 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
ns
TCCJ
CPU Cycle to Cycle Jitter
CPU2_ITP Cycle to Cycle Jitter
Long-term Accuracy
Measured at 0V differential
–
–
85
125
100
100
150
8
ps
ps
TCCJ2
Measured at 0V differential
LACC
Measured at 0V differential
–
ppm
ps
TSKEW
TSKEW2
TR / TF
TRFM
CPU0 to CPU1 Clock Skew
CPU2_ITP to CPU0 Clock Skew
CPU Rising/Falling Slew rate
Rise/Fall Matching
Measured at 0V differential
–
Measured at 0V differential
–
ps
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
V/ns
%
20
VHIGH
Voltage High
1.15
–
V
VLOW
Voltage Low
–0.3
300
V
VOX
Crossing Point Voltage at 0.7V Swing
550
mV
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
ns
ns
ns
ns
ns
9.99900
10.0010
TPERIOD
TPERIODSS
TPERIODAbs
100 MHz SRC Period
Measured at 0V differential @ 0.1s
Measured at 0V differential @ 0.1s
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
10.02406 10.02607
100 MHz SRC Period, SSC
100 MHz SRC Absolute Period
9.87400
9.87406
–
10.1260
10.1762
3.0
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
TSKEW(window) Any SRC Clock Skew from the earliest Measured at 0V differential
bank to the latest bank
TCCJ
SRC Cycle to Cycle Jitter
SRC Long Term Accuracy
SRC Rising/Falling Slew Rate
Rise/Fall Matching
Measured at 0V differential
–
–
125
100
8
ps
ppm
V/ns
%
LACC
Measured at 0V differential
TR / TF
TRFM
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
20
VHIGH
VLOW
VOX
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
Crossing Point Voltage at 0.7V Swing
550
mV
DOT96 at 0.7V
TDC
DOT96 Duty Cycle
Measured at 0V differential
45
55
10.4177
10.6677
250
100
8
%
ns
ns
ps
ppm
V/ns
%
10.4156
TPERIOD
TPERIODAbs
TCCJ
DOT96 Period
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
10.1656
DOT96 Absolute Period
DOT96 Cycle to Cycle Jitter
DOT96 Long Term Accuracy
DOT96 Rising/Falling Slew Rate
Rise/Fall Matching
–
–
LACC
TR / TF
TRFM
2.5
–
20
VHIGH
VLOW
VOX
Voltage High
1.15
–
V
Voltage Low
–0.3
300
–
V
Crossing Point Voltage at 0.7V Swing
Rise/Fall Matching
550
20
mV
%
TRFM
Measured single-endedly from ±75 mV
VHIGH
VLOW
VOX
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
Crossing Point Voltage at 0.7V Swing
550
mV
PCI/PCIF at 3.3V
...................... DOC #: SP-AP-0051 (Rev. AA) Page 22 of 27
SL28504-2
AC Electrical Specifications (continued)
Parameter
TDC
Description
PCI Duty Cycle
Condition
Measurement at 1.5V
Min.
Max.
Unit
%
45
55
29.99700 30.00300
30.08421 30.23459
29.49700 30.50300
29.56617 30.58421
TPERIOD
Spread Disabled PCIF/PCI Period
Spread Enabled PCIF/PCI Period
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
ns
TPERIODSS
TPERIODAbs
ns
ns
TPERIODSSAbs Spread Enabled PCIF/PCI Period
ns
THIGH
TLOW
THIGH
Spread Enabled PCIF and PCI high time Measurement at 2V
Spread Enabled PCIF and PCI low time Measurement at 0.8V
12.27095 16.27995 ns
11.87095 16.07995 ns
12.27365 16.27665 ns
Spread Disabled PCIF and PCI high
time
Measurement at 2.V
TLOW
Spread Disabled PCIF and PCI low time Measurement at 0.8V
11.87365 16.07665 ns
TR / TF
TSKEW
TCCJ
PCIF/PCI Rising/Falling Slew Rate
Measured between 0.8V and 2.0V
1.0
–
4.0
1000
500
V/ns
ps
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
PCIF and PCI Cycle to Cycle Jitter
PCIF/PCI Long Term Accuracy
Measurement at 1.5V
Measurement at 1.5V
–
ps
LACC
–
100
ppm
48_M at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2V
45
55
%
ns
20.83125 20.83542
20.48125 21.18542
8.216563 11.15198
7.816563 10.95198
TPERIOD
TPERIODAbs
THIGH
TLOW
Period
Absolute Period
48_M High time
ns
ns
48_M Low time
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
ns
TR / TF
TCCJ
Rising and Falling Edge Rate
Cycle to Cycle Jitter
48M Long Term Accuracy
1.0
–
2.0
350
100
V/ns
ps
LACC
–
ppm
25_M
Measurement at 1.5V
45
39.996
1.0
55
40.004
4.0
%
ns
TDC
Duty Cycle
Measurement at 1.5V
TPERIOD
TR/TF
Period
Measured between 0.8V and 2.0V
Measurement at 1.5V
V/ns
ps
Rising and Falling Edge Rate
Cycle to Cycle Jitter
25M Long Term Accuracy
–
500
TCCJ
Measurement at 1.5V
–
50
ppm
LACC
1394A - 24.576M
Measurement at 1.5V
45
40.686
1.0
55
40.694
4.0
%
ns
TDC
Duty Cycle
Measurement at 1.5V
TPERIOD
TR/TF
TCCJ
Period
Measured between 0.8V and 2.0V
Measurement at 1.5V
V/ns
ps
Rising and Falling Edge Rate
Cycle to Cycle Jitter
24M Long Term Accuracy
–
200
Measurement at 1.5V
–30
30
ppm
LACC
REF
TDC
REF Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2V
45
55
%
ns
69.82033 69.86224
68.83429 70.84826
29.97543 38.46654
29.57543 38.26654
TPERIOD
TPERIODAbs
THIGH
TLOW
REF Period
ns
REF Absolute Period
REF High time
ns
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
ns
REF Low time
TR / TF
TSKEW
REF Rising and Falling Edge Rate
REF Clock to REF Clock
1.0
–
4.0
V/ns
ps
500
...................... DOC #: SP-AP-0051 (Rev. AA) Page 23 of 27
SL28504-2
AC Electrical Specifications (continued)
Parameter
TCCJ
LACC
Description
REF Cycle to Cycle Jitter
Long Term Accuracy
Condition
Measurement at 1.5V
Measurement at 1.5V
Min.
Max.
1000
100
Unit
ps
–
–
ppm
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS Stopclock Set-up Time
–
1.8
–
ms
ns
10.0
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
Measurement
Point
22
L1
L2
50
4 pF
4 pF
L1 = 0.5", L2 = 8"
22
PCI/USB
Measurement
Point
50
L2
L1
Figure 14. Single-ended PCI and USB Double Load Configuration
Measurement
15
L2
L1
Point
50
4 pF
Measurement
Point
4 pF
15
15
L1
L1
L2
REF
50
Measurement
Point
4 pF
L2
50
Figure 15. Single-ended REF Triple Load Configuration
Figure 16. Single-ended Output Signals (for AC Parameters Measurement)
For CPU, SRC, and DOT96 Signals and Reference
This diagram shows the test load configuration for the differential CPU and SRC outputs
...................... DOC #: SP-AP-0051 (Rev. AA) Page 24 of 27
SL28504-2
Figure 17. 0.7V Differential Load Configuration
Clock Period (Differential)
Positive Duty Cycle (Differential)
Negative Duty Cycle (Differential)
0.0V
0.0V
Clck-Clck#
Rise
Edge
Rate
Fall
Edge
Rate
VIH = +150V
VIH = +150V
0.0V
0.0V
VIL = -150V
VIL = -150V
Clock-Clock#
Figure 18. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
VM AX = 1.15V
VM AX = 1.15V
CLK#
VcrossM AX = 550m V
VcrossM IN = 300m V
VcrossM AX = 550m V
VcrossM IN = 300m V
CLK
VM IN = 0.30V
VM IN = 0.30V
CLK#
Vcross delta = 140m V
Vcross delta = 140m V
CLK#
CLK#
Vcross m edian +75m V
Vcross m edian
Vcross m edian
Vcross m edian -75m V
CLK
CLK
Figure 19. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
...................... DOC #: SP-AP-0051 (Rev. AA) Page 25 of 27
SL28504-2
Ordering Information
Part Number
Lead-free
Package Type
Product Flow
SL28504BZC-2
SL28504BZC-2T
SL28504BZI-2
SL28504BZI-2T
56-pin TSSOP
Commercial, 0 to 85C
Commercial, 0 to 85C
Commercial, -40 to 85C
Commercial, -40 to 85C
56-pin TSSOP–Tape and Reel
56-pin TSSOP
56-pin TSSOP–Tape and Reel
2
SL
B
28 504 Z C
T
Packaging Designator for Tape and Reel
Derivatives of a Generic Part
Temperature Designator
C : Commercial spec; I: Industrial Spec
Package Designator
Z : TSSOP;
Revision Number
A = 1st revision; B = 2nd revision......
Generic Part Number
Designated Family Number
Company Initials
Package Diagrams
56-Lead Thin Shrunk Small Outline Package Type II (6 mm x 12 mm) Z56
...................... DOC #: SP-AP-0051 (Rev. AA) Page 26 of 27
SL28504-2
Document History Page
Document Title: SL28504-2 Clock Generator for Intel®Eaglelake Chipset
DOC #: SP-AP-0051 (Rev. AA)
Orig. of
REV.
1.0
ECR#
Issue Date Change
Description of Change
10/5/07
10/16/07
01/21/08
BSHEN Initial Release
1.1
BSHEN Add SRC1 to pin 17/18. and tri-level trigger at 24.576M
1.2
BSHEN 1. Change Revision ID Byte7[7:4] to be 0001
2. Updated block diagram
3. Change Byte10[6:2] and Byte11[4] to be reserved
1.3
AA
07/26/09
04/29/09
BSHEN 1. Updated Package Dimensions to compliant to SLI POD specification
2. Updated the CR# pin & register
3. Remove PCIE Gen II compliant on Feature
1575
BSHEN 1. Correct VDD_IO pin description
2. Updated Industrial ordering information
3. Change document format for ISO complaint
...................... DOC #: SP-AP-0051 (Rev. AA) Page 27 of 27
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using
or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and
"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the
included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses
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