SL28506BZCT_技术文档

SL28506

Clock Generator for Intel^®Eaglelake Chipset

• 25 MHz Video clocks

Features

• 1396 Firewire clock

• Intel^®CK505 Rev. 1.0 Compliant

• Buffered Reference Clock 14.318 MHz

• Low power push-pull type differential output buffers

• 14.318 MHz Crystal Input or Clock Input

• Low-voltage frequency select input

• I²C support with readback capabilities

• PCI-Express Gen 2 Compliant SRC clocks (exclude

SRC0 and SRC1)

• 8-step programmable drive strength for single-ended

clocks

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Differential CPU clocks with selectable frequency

• 100 MHz Differential SRC clocks

• 100 MHz Differential LCD clock

• 96 MHz Differential DOT clock

• 48 MHz USB clock

• Industrial Temperature -40°C to 85°C

• 3.3V Power supply

• 64-pinTSSOP packages

CPU SRC PCI REF DOT96 USB_48 LCD SE

• 33 MHz PCI clocks

x2 / x3 x7/12 x6

x 1

x1

x2

• 27MHz non-spread Video clock

Pin Configuration

Block Diagram

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PCI0/OE#_0/2_A

VDD_PCI

PCI1/OE#_0/2_A

PCI2/TME

PCI3/CFG0*

PCI4/ SRC5_EN

PCIF0/ITP_EN

VSS_PCI

SCLK

2

SDATA

3

REF0/FSC/TEST_SEL

VDD_REF

4

5

XIN/CLKIN

6

XOUT

7

VSS_REF

8

FSB/TEST_MODE

CKPWRGD/PD#

VDD_CPU

9

VDD_48

USB_48/ FSA

VSS_48

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

CPU0

VDD_IO

CPU#0

SRC0/DOT96

SRC0#/DOT96#

VSS_IO

VSS_CPU

CPU1

CPU1#

VDD_PLL3

VDD_CPU_IO

IO_VOUT

SRC1/LCD100/SE1

SRC1#/LCD100#/SE2

VSS_PLL3

SRC8/ CPU2_ITP

SRC8#/ CPU2_ITP#

VDD_SRC_IO

SRC7/OE#_8

SRC7#/OE#_6

VSS_SRC

VDD_PLL3_IO

SRC2/SATA

SRC2#/SATA#

VSS_SRC

SRC3/OE#_0/2_B

SRC3#/OE#_1/4_B

VDD_SRC_IO

SRC4

SRC4#

VSS_SRC

SRC9

SRC9#

SRC11#//OE#_9

SRC6

SRC#

VDD_SRC

SRC5/PCI_STP#

SRC5#/CPU_STP#

VDD_SRC_IO

SRC10#

SRC10

SRC11/OE#_10

* 100K-ohm Internal Pull Down

......................... DOC #: SP-AP-0021 (Rev AA) Page 1 of 28

400 West Cesar Chavez, Austin, TX 78701

1+(512) 416-8500 1+(512) 416-9669

www.silabs.com

SL28506

64 TSSOP Pin Definition

Pin No.

Name

Type

Description

1

PCI0/OE#_0/2_A

I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or

SRC2. (Default PCI0, 33MHz clock)

2

3

VDD_PCI

PWR 3.3V Power supply for PCI PLL.

PCI1/OE#_1/4_A

I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or

SRC4. (Default PCI1, 33MHz clock)

4

5

PCI2/TME

I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock.

(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)

PCI3/CFG0

I/O, SE, 3.3V tolerant input for CPU frequency selection/3.3V 33MHz clock.

PD

(Refer to DC Electrical Specifications table for Vil_PCI3/CFG0 and

Vih_PCI3/CFG0 specifications).

6

7

PCI4/SRC5_EN

PCIF/ITP_EN

I/O, SE 3.3V tolerant input to enable SRC5/3.3V, 33MHz clock.

(Sampled on the CKPWRGD assertion)

1 = SRC5, 0 = CPU_STP#

I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/3.3V, 33MHz clock.

(Sampled on the CKPWRGD assertion)

1 = CPU2_ITP, 0 = SRC8

8

VSS_PCI

GND Ground for outputs.

9

VDD_48

PWR 3.3V Power supply for outputs and PLL.

10

USB_48/FSA

I/O

3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output.

(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)

11

12

13

VSS_48

GND Ground for outputs.

VDD_IO

PWR 0.7V Power supply for outputs.

SRC0/DOT96

O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.

(Selected via I2C default is SRC0)

14

SRC0#/DOT96#

O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.

(Selected via I2C default is SRC0)

15

16

17

VSS_IO

GND Ground for PLL2.

VDD_PLL3

PWR 3.3V Power supply for PLL3

SRC1/LCD100/SE1

O, DIF, 100MHz Differential serial reference clocks/100MHz LCD video clock/SE1 clocks.

SE

O, DIF, 100MHz Differential serial reference clocks/100MHz LCD video clock/SE2 clocks.

SE (Default SRC1, 100MHz clock)

(Default SRC1, 100MHz clock)

18

SRC1#/LCD100#/SE2

19

20

21

22

23

24

VSS_PLL3

GND Ground for PLL3.

VDD_PLL3_IO

SRC2/SATA

PWR IO Power supply for PLL3 outputs.

O, DIF 100MHz Differential serial reference clocks.

GND Ground for outputs.

SRC2#/SATA#

VSS_SRC

SRC3/OE#_0/2_B

I/O, 100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable

Dif

I/O, 100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable

Dif via I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock)

via I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock)

25

SRC3#OE#_1/4_B

.........................DOC #: SP-AP-0021 (Rev AA) Page 2 of 28

SL28506

64 TSSOP Pin Definition (continued)

Pin No.

26

Name

VDD_SRC_IO

SRC4

Type

Description

PWR IO power supply for SRC outputs.

27

O, DIF 100MHz Differential serial reference clocks.

GND Ground for outputs.

28

SRC4#

29

VSS_SRC

SRC9

30

O, DIF 100MHz Differential serial reference clocks.

31

SRC9#

32

SRC11#/OE#_9

I/O, 100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9

Dif (Default SRC11, 100MHz clock)

33

SRC11/OE#_10

I/O, 100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.

Dif (Default SRC11, 100MHz clock)

34

35

36

37

SRC10

O, DIF 100MHz Differential serial reference clocks.

SRC10#

O, DIF 100MHz Differential serial reference clocks.

VDD_SRC_IO

SRC5#CPU_STP#

PWR IO Power supply for SRC outputs.

I/O, 3.3V tolerant input for stopping CPU outputs/100MHz Differential serial reference

Dif

I/O, 3.3V tolerant input for stopping PCI and SRC outputs/100MHz Differential serial

Dif reference clocks.

clocks.

38

SRC5/PCI_STP#

39

40

41

42

43

VDD_SRC

SRC6#

PWR 3.3V Power supply for SRC PLL.

O, DIF 100MHz Differential serial reference clocks.

GND Ground for outputs.

SRC6

VSS_SRC

SRC7#/OE#_6

I/O, 100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.

Dif

I/O, 100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.

Dif (Default SRC7, 100MHz clock).

(Default SRC7, 100MHz clock).

44

SRC7/OE#_8

45

46

VDD_SRC_IO

PWR 0.7V power supply for SRC outputs.

SRC8#/CPU2#_ITP#

O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD

assertion = SRC8

ITP_EN = 1 @ CKPWRGD assertion = CPU2

(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11

Bit3:2)

47

SRC8/CPU2_ITP

O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD

assertion = SRC8

ITP_EN = 1 @ CKPWRGD assertion = CPU2

(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11

Bit3:2)

48

49

50

IO_VOUT

VDD_CPU_IO

CPU1#

PWR Integrated Linear Regulator Control.

PWR IO Power supply for CPU outputs.

O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending

on the configuration set in Byte 11 Bit3:2)

51

CPU1

O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending

on the configuration set in Byte 11 Bit3:2)

52

53

54

55

56

VSS_CPU

CPU#0

GND Ground for outputs.

O, DIF Differential CPU clock outputs.

PWR 3.3V Power supply for CPU PLL.

CPU0

VDD_CPU

CKPWRGD/PD#

I

3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,

FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.

After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for

asserting power down (active LOW).

.........................DOC #: SP-AP-0021 (Rev AA) Page 3 of 28

SL28506

64 TSSOP Pin Definition (continued)

Pin No.

Name

Type

Description

57

FSB/TEST_MODE

I

3.3V tolerant input for CPU frequency selection.

Selects Ref/N or Tri-state when in test mode

0 = Tri-state, 1 = Ref/N.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

58

59

60

61

VSS_REF

XOUT

GND Ground for outputs.

O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)

XIN/CLKIN

VDD_REF

I

14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.

PWR 3.3V Power supply for outputs and also maintains SMBUS registers during

power-down.

62

REF0/FSC/TEST_SEL

I/O

3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.

Selects test mode if pulled to V_{IHFS_C}when CKPWRGD is asserted HIGH. Refer

to DC Electrical Specifications table for V_{ILFS_C}, V_{IMFS_C}, V_{IHFS_C}specifications.

63

64

SMB_DATA

SMB_CLK

I/O

I

SMBus compatible SDATA.

SMBus compatible SCLOCK.

Table 1. Frequency Select Pin (FSA, FSB and FSC)

FSC

0

FSB

0

FSA

0

CPU

SRC

PCIF/PCI

27MHz

REF

DOT96

USB

266MHz

133MHz

200MHz

166MHz

333MHz

100MHz

400MHz

200MHz

0

1

0

1

0

1

100MHz

33MHz

27MHz

14.318MHz

96MHz

48MHz

1

0

1

0

1

0

1

their default setting at power-up. The use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

Frequency Select Pin (FSA, FSB and FSC)

Apply the appropriate logic levels to FSA, FSB, and FSC

inputs before CKPWRGD assertion to achieve host clock

frequency selection. When the clock chip sampled HIGH on

CKPWRGD and indicates that VTT voltage is stable then FSA,

FSB, and FSC input values are sampled. This process

employs a one-shot functionality and once the CKPWRGD

sampled a valid HIGH, all other FSA, FSB, FSC, and

CKPWRGD transitions are ignored except in test mode.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 2.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

The block write and block read protocol is outlined in Table 3

while Table 4 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h).

.

Table 2. Command Code Definition

Bit

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation

7

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

.........................DOC #: SP-AP-0021 (Rev AA) Page 4 of 28

SL28506

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Byte Count–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Data byte 1–8 bits

27:21

28

Slave address–7 bits

Read = 1

36:29

37

Acknowledge from slave

Data byte 2–8 bits

29

Acknowledge from slave

Byte Count from slave–8 bits

Acknowledge

45:38

46

37:30

38

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N–8 bits

Acknowledge from slave

Stop

....

46:39

47

Data byte 1 from slave–8 bits

Acknowledge

....

55:48

56

Data byte 2 from slave–8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave–8 bits

NOT Acknowledge

....

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Stop

27:21

28

Slave address–7 bits

Read

29

Acknowledge from slave

Data from slave–8 bits

NOT Acknowledge

Stop

37:30

38

39

.........................DOC #: SP-AP-0021 (Rev AA) Page 5 of 28

SL28506

Control Registers

Byte 0: Control Register 0

Bit

7

@Pup

HW

0

Name

FS_C

Description

CPU Frequency Select Bit, set by HW

6

FS_B

CPU Frequency Select Bit, set by HW

5

FS_A

4

iAMT_EN

Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP

0 = Legacy Mode, 1 = iAMT Enabled, Sticky 1

3

2

0

RESERVED

SRC_MAIN_SEL

Select source for SRC clock,

0 = SRC_MAIN = PLL1, PLL3_CFB Table applies

1 = SRC_MAIN = PLL3, PLL3_CFB Table does not apply

1

0

1

SATA_SEL

Select source of SATA clock

0 = SATA SRC_MAIN, 1= SATA PLL2

PD_Restore

Save Config. In powerdown

0 = Config. Cleared, 1 = Config. Saved

Byte 1: Control Register 1

Bit

7

@Pup

Name

Description

0

SRC0_SEL

PLL1_SS_DC

Select for SRC0 or DOT96, 0 = SRC0, 1 = DOT96

6

Select for down or center SS,

0 = Down spread, 1 = Center spread

5

0

PLL3_SS_DC

Select for down or center SS,

0 = Down spread, 1 = Center spread

4

3

2

1

0

1

PLL3_CFB3

PLL3_CFB2

PLL3_CFB1

PLL3_CFB0

Bit 4:1 only apply when SRC_SEL=0

0000 = PLL3 Disable Default

PLL3 OFF, SRC1 = SRC_MAIN

0001 = 100 MHz 0.5% SSC Stby PLL3 ON, SRC1 = SRC_MAIN

0010 = 100 MHz 0.5% SSC

0011 = 100 MHz 1.0% SSC

0100 = 100 MHz 1.5% SSC

0101 = 100 MHz 2.0% SSC

0110 = RESERVED

Only SRC1 sourced from PLL3

Note: SE clocks required to be

enabled through Byte 8 Bit[1:0]

0111 = RESERVED

1000 = 1394A(24.576M) on SE1 and SE2

1001 = 1394A(24.576M) on SE1 and 1394B (98.304M) on SE2

1010 = 1394B on SE1 and SE2

1011 = 27MHz_NSS on SE1 and SE2

1100 = 25MHz on SE1 and SE2

1101 = 25MHz on SE1 and SE2 Disabled (set whenPCI3/CFB0 is set high to

config to HW mode 3)

1110 = RESERVED

1111 = RESERVED

0

1

PCI_SEL

Select PCI Clock source from PLL1 or SRC_MAIN

0 = PLL1, 1 = SRC_MAIN

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

REF_OE

Output enable for REF

0 = Output Disabled, 1 = Output Enabled

6

1

USB_OE

Output enable for USB

0 = Output Disabled, 1 = Output Enabled

.........................DOC #: SP-AP-0021 (Rev AA) Page 6 of 28

SL28506

Byte 2: Control Register 2 (continued)

Bit

@Pup

Name

Description

5

1

PCIF0_OE

Output enable for PCIF0

0 = Output Disabled, 1 = Output Enabled

4

3

2

1

0

1

PCI4_OE

PCI3_OE

PCI2_OE

PCI1_OE

PCI0_OE

Output enable for PCI4

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI3

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI2

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI1

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI0

0 = Output Disabled, 1 = Output Enabled

Byte 3: Control Register 3

Bit

@Pup

Name

Description

7

1

SRC11_OE

Output enable for SRC11

0 = Output Disabled, 1 = Output Enabled

6

5

1

SRC10_OE

SRC9_OE

Output enable for SRC10

0 = Output Disabled, 1 = Output Enabled

Output enable for SRC9

0 = Output Disabled, 1 = Output Enabled

4

3

1

SRC8/ITP_OE

SRC7_OE

Output enable for SRC8 or ITP, 0 = Output Disabled, 1 = Output Enabled

Output enable for SRC7

0 = Output Disabled, 1 = Output Enabled

2

1

0

1

SRC6_OE

SRC5_OE

SRC4_OE

Output enable for SRC6

0 = Output Disabled, 1 = Output Enabled

Output enable for SRC5

0 = Output Disabled, 1 = Output Enabled

Output enable for SRC4

0 = Output Disabled, 1 = Output Enabled

Byte 4: Control Register 4

Bit

@Pup

Name

Description

7

1

SRC3_OE

Output enable for SRC3

0 = Output Disabled, 1 = Output Enabled

6

5

4

3

2

1

0

1

SRC2/SATA_OE

SRC1_OE

Output enable for SATA/SRC2

0 = Output Disabled, 1 = Output Enabled

Output enable for SRC

0 = Output Disabled, 1 = Output Enabled

SRC0/DOT96_OE

CPU1_OE

Output enable for SRC0/DOT96

0 = Output Disabled, 1 = Output Enabled

Output enable for CPU1

0 = Output Disabled, 1 = Output Enabled

CPU0_OE

Output enable for CPU0

0 = Output Disabled, 1 = Output Enabled

PLL1_SS_EN

PLL3_SS_EN

Enable PLL1’s spread modulation,

0 = Spread Disabled 1 = Spread Enabled

Enable PLL3’s spread modulation

0 = Spread Disabled, 1 = Spread Enabled

.........................DOC #: SP-AP-0021 (Rev AA) Page 7 of 28

SL28506

Byte 5: Control Register 5

Bit

@Pup

Name

Description

7

0

OE#_0/2_EN_A

Enable OE#_0/2 (clk req)

0 = Disabled OE#_0/2, 1 = Enabled OE#_0/2,

6

5

4

3

2

1

0

OE#_0/2_SEL_A

OE#_1/4_EN_A

OE#_1/4_SEL_A

OE#_0/2_EN_B

OE#_0/2_SEL_B

OE#_1/4_EN_B

OE#_1/4_SEL_B

Set OE#_0/2  SRC0 or SRC2

0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2

Enable OE#_1/4 (clk req)

0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,

Set OE#_1/4  SRC1 or SRC4

0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4

Enable OE#_0/2 (clk req)

0 = Disabled OE#_0/2 1 = Enabled OE#_0/2

Set OE#_0/2  SRC0 or SRC2

0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2

Enable OE#_1/4 (clk req)

0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,

Set OE#_1/4 SRC1 or SRC4

0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4

Byte 6: Control Register 6

Bit

7

@Pup

Name

OE#_6_EN

Description

Enable OE#_6 (clk req)  SRC6

Enable OE#_8 (clk req)  SRC8

Enable OE#_9 (clk req) SRC9

Enable OE#_10 (clk req)  SRC10

RESERVED

0

6

OE#_8_EN

5

OE#_9_EN

4

OE#_10_EN

RESERVED

LCD_100_STP_CTRL

3

2

RESERVED

1

Allows control of LCD_100 with assertion of PCI_STP#

0 = Free runningLCD_100, 1 = Stopped with PCI_STP#

0

SRC_STP_CTRL

Allows control of SRC with assertion of PCI_STP#

0 = Free running SRC 1 = Stopped with PCI_STP#

Byte 7: Vendor ID

Bit

7

@Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

0

1

0

Rev Code Bit 3

Rev Code Bit 2

Rev Code Bit 1

Rev Code Bit 0

Vendor ID bit 3

Vendor ID bit 2

Vendor ID bit 1

Vendor ID bit 0

6

5

4

3

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

.........................DOC #: SP-AP-0021 (Rev AA) Page 8 of 28

SL28506

Byte 8: Control Register 8

Bit

7

@Pup

Name

Description

0

1

Device_ID3

Device_ID2

Device_ID1

Device_ID0

0000 = CK505 Yellow Cover Device, 56-pin TSSOP

0001 = CK505 Yellow Cover Device, 64-pin TSSOP

7

0010 = CK505 Yellow Cover Device, 48-pin QFN (reserved)

0011 = CK505 Yellow Cover Device, 56-pin QFN (reserved)

0100 = CK505 Yellow Cover Device, 64-pin QFN (reserved)

0101 = CK505 Yellow Cover Device, 72-pin QFN (reserved)

0110 = CK505 Yellow Cover Device, 48-pin SSOP (reserved)

0111 = CK505 Yellow Cover Device, 56-pin SSOP (reserved)

1000 = Reserved

5

4

1001 = Reserved

1010 = Reserved

1011 = Reserved

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

3

2

1

0

RESERVED

SE1_OE

RESERVED

SE1 Output enable 0 = Output Disabled, 1 = Output Enabled

SE2 Output enable 0 = Output Disabled, 1 = Output Enabled

SE2_OE

Byte 9: Control Register 9

Bit

@Pup

Name

Description

7

0

PCIF0_STP_CTRL

Allows control of PCIF0 with assertion of PCI_STP#

0 = Free running PCIF, 1 = Stopped with PCI_STP#

6

5

HW_Pin

1

TME_STRAP

REF_Bit1

Trusted mode enable strap status, 0 = normal, 1 = no overclocking

REF drive strength control, See Byte 18 for more setting

0 = Low, 1 = High

4

3

0

TEST_MODE_SEL

Mode select either REF/N or tri-state

0 = All output tri-state, 1 = All output REF/N

TEST_MODE_ENTRY

Allow entry into test mode

0=Normal operation, 1=Enter test mode

2

1

0

1

0

1

IO_VOUT2

IO_VOUT1

IO_VOUT0

IO_VOUT[2,1,0]

000 = 0.3V

001 = 0.4V

010 = 0.5V

011 = 0.6V

100 = 0.7V

101 = 0.8V, Default

110 = 0.9V

111 = 1.0V

Byte 10: Control Register 10

Bit

@Pup

Name

Description

7

HW

SRC5_EN_STRAP

Read only bit for SRC5_EN_STRAP

0 = CPU/PCI_STP enabled, 1 = SRC5 pair enabled

6

5

4

1

PLL3_EN

PLL2_EN

PLL3 Enabled

0 = PLL3 disabled, 1 = PLL3 enabled

PLL2 Enabled

0 = PLL2 disabled, 1 = PLL2 enabled

SRC_DIV_EN

SRC Divider Enabled

0 = SRC Divider disabled, 1 = SRC Divider enabled

.........................DOC #: SP-AP-0021 (Rev AA) Page 9 of 28

SL28506

Byte 10: Control Register 10 (continued)

Bit

@Pup

Name

Description

3

1

PCI_DIV_EN

PCI Divider Enabled

0 = PCI Divider disabled, 1 = PCI Divider enabled

2

1

0

1

CPU_DIV_EN

CPU1_STP_CRTL

CPU0_STP_CRTL

CPU Divider Enabled

0 = CPU Divider disabled, 1 = CPU Divider enabled

Allow control of CPU1 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Allow control of CPU0 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Byte 11: Control Register 11

Bit

7

@Pup

HW

Name

Description

PCI3_CFG1

PCI3_CFG0

6

HW

PLL1

Output

Low 0 -Def CPU / SRC / PCI33 Dow n

PLL2

CFG PCI2/T PCI3/

[1:0]

ME CGF0

Mode

SSC

Output

USB

SSC

NA

00

x

0

01

Mid

1

2

CPU

Dow n

Center

USB

NA

10

High

USB

NA

5

0

25MHz_EN_SE1

25MHz Output Enabled applies to Powerdown / M1

(Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3)

0 = 25MHz disabled in Powerdown / M1

1 = 25MHz enabled in Powerdown / M1; Sticky 1

4

3

2

1

0

1

RESERVED

CPU2_AMT_EN

CPU1_AMT_EN

RESERVED

PCIF0/ITP_EN AMT_EN

CPU2_AMT_EN CPU1_AMT_EN

Description

x

1

0

1

0

1

0

1

Reserved

CPU1 = M1 Clock

CPU2 - M1 Clock

CPU1 and CPU2 = M1 Clock

1

0

1

PCI-E_GEN2

PCI-E_Gen2 Compliant (Read Only)

0 = non Gen2, 1= Gen2 Compliant

CPU2_STP_CRTL

Allow control of CPU2 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Byte 12: Byte Count

Bit

7

@Pup

Name

RESERVED

BC5

Description

0

1

0

1

RESERVED

Byte count

6

5

4

BC4

3

BC3

2

BC2

1

BC1

0

BC0

.......................DOC #: SP-AP-0021 (Rev AA) Page 10 of 28

SL28506

Byte 13: Control Register 13

Bit

@Pup

Name

Description

7

1

USB_Bit1

USB drive strength control, See Byte 18 for more setting

0 = Low, 1= High

6

5

4

3

1

0

1

PCI/PCIF_Bit1

PLL1_Spread

SATA_SS_EN

EN_CFG0_SET

PCI drive strength control, See Byte 18 for more setting

0 = Low, 1 = High

Select percentage of spread for PLL1

0 = 0.5%, 1=0.45%

Enable SATA spread modulation,

0 = Spread Disabled 1 = Spread Enabled

By defalult CFG0 pin strap sets the SMBus initial values to select the HW

mode. When this bit is written0, subsequent SMBus accesses is the Lathes

Open state, can overwrite the CFG0 pin setting into the SMBus bits and set

the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5

2

1

SE1/SE2_Bit1

SE1 and SE2 drive strength control, See Byte 18 for more setting

0 = Low, 1 = High

1

0

1

RESERVED

SW_PCI

RESERVED

SW PCI_STP# Function

0 = SW PCI_STP assert, 1 = SW PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will

be stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will

resume in a synchronous manner with no short pulses.

Byte 14: Control Register 14

Bit

7

@Pup

Name

Description

0

CPU_DAF_N7

CPU_DAF_N6

CPU_DAF_N5

CPU_DAF_N4

CPU_DAF_N3

CPU_DAF_N2

CPU_DAF_N1

CPU_DAF_N0

If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and

CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The

setting of the FS_Override bit determines the frequency ratio for CPU and

other output clocks. When it is cleared, the same frequency ratio stated in

the Latched FS[C:A] register will be used. When it is set, the frequency ratio

stated in the FSEL[2:0] register will be used

6

5

4

3

2

1

0

Byte 15: Control Register 15

Bit

7

@Pup

Name

Description

0

CPU_DAF_N8

CPU_DAF_M6

CPU_DAF_M5

CPU_DAF_M4

CPU_DAF_M3

CPU_DAF_M2

CPU_DAF_M1

CPU_DAF_M0

See Byte 14 for description

6

If Prog_CPU_EN is set, the values programmed are in CPU_FSEL_N[8:0]

and CPU_FSEL_M[6:0] will be used to determine the CPU output

frequency. The setting of the FS_Override bit determines the frequency

ratio for CPU and other output clocks. When it is cleared, the same

frequency ratio stated in the Latched FS[C:A] register will be used. When it

is set, the frequency ratio stated in the FSEL[2:0] register will be used

5

4

3

2

1

0

Byte 16: Control Register 16

Bit @Pup

Name

Description

....................... DOC #: SP-AP-0021 (Rev AA) Page 11 of 28

SL28506

Byte 16: Control Register 16

7

6

5

4

3

2

1

0

PCI-E_N7

PCI-E_N6

PCI-E_N5

PCI-E_N4

PCI-E_N3

PCI-E_N2

PCI-E_N1

PCI-E_N0

If Prog_SRC_EN is set, the values programmed in SRC_DAF_N[7:0] will

be used to determine the SRC output frequency.

Byte 17: Control Register 17

Bit

7

@Pup

Name

Description

Enable Smooth Switching, 0 = Disabled, 1= Enabled

Smooth switch select, 0 = CPU_PLL, 1 = SRC_PLL

RESERVED

0

SMSW_EN

6

SMSW_SEL

RESERVED

Prog_PCI-E_EN

5

4

Programmable PCI-E frequency enable

0 = Disabled, 1= Enabled

3

0

Prog_CPU_EN

Programmable CPU frequency enable

0 = Disabled, 1= Enabled

2

1

0

RESERVED

Byte 18: Control Register 18

Bit

7

@Pup

Name

Description

0

1

0

PCIF/PCI_Bit2

PCIF/PCI_Bit0

USB_Bit2

Drive Strength Control - Bit[2:0]

6

Bit 2

(Byte18)

1

Bit 0

(Byte 18)

1

Buffer

Strength

Strongest

Bit 1

(Various Bytes)

5

1

0

1

0

4

USB_Bit0

1

0

1

0

1

0

1

0

3

SE1/SE2_Bit2

SE1/SE2_Bit0

REF_Bit2

2

1

Default PCI

0

REF_Bit0

Default REF/Usb

Weakest

Table 5. Output Driver Status during PCI-STP# and CPU-STP#

PCI_STP# Asserted

CPU_STP# Asserted

Running

SMBus OE Disabled

Single-ended Clocks Stoppable

Non stoppable

Stoppable

Driven low

Running

Differential Clocks

Clock driven high

Clock# driven low

Running

Clock driven high

Clock# driven low

Running

Clock driven Low or 20K

pulldown

Non stoppable

.......................DOC #: SP-AP-0021 (Rev AA) Page 12 of 28

SL28506

Table 6. Output Driver Status

All Differential Clocks except

CPU1

All Single-ended Clocks

w/o Strap w/ Strap

Low Hi-z

CPU1

Clock

Clock#

Clock

Clock#

Latches Open State

Powerdown

M1

Low or 20K pulldown Low

Low

Hi-z

Running

Smooth Switching

Dial-A-Frequency^®(CPU andSRC)

The device contains one smooth switch circuit that is shared

by the CPU PLL and SRC PLL. The smooth switch circuit

ensures that when the output frequency changes by

overclocking, the transition from the old frequency to the new

frequency is a slow, smooth transition containing no glitches.

The rate of change of output frequency when using the smooth

switch circuit is less than 1 MHz/0.667 s. The frequency

overshoot and undershoot is less than 2%.

This feature allows the user to over-clock their system by

slowly stepping up the CPU or SRC frequency. When the

programmable output frequency feature is enabled, the CPU

and SRC frequencies are determined by the following

equation:

Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.

The Smooth Switch circuit assigns auto or manual. In Auto

mode, clock generator assigns smooth switch automatically

when the PLL does overclocking. For manual mode, assign

the smooth switch circuit to PLL via Smbus. By default the

smooth switch circuit is set to auto mode. PLL can be

over-clocked when it does not have control of the smooth

switch circuit but it is not guaranteed to transition to the new

frequency without large frequency glitches.

• “N” and “M” are the values programmed in Programmable

Frequency Select N-Value Register and M-Value Register,

respectively.

• “G” stands for the PLL Gear Constant, which is determined

by the programmed value of FS[E:A]. See Table 1,

Frequency Select Table for the Gear Constant for each

Frequency selection. The PCI Express only allows user

control of the N register, the M value is fixed and

documented in Table 1, Frequency Select Table.

Do not enable over-clocking and change the N values of both

PLLs in the same SMBUS block write and use smooth switch

mechanism on spread spectrum on/off.

In this mode, the user writes the desired N and M values into

the DAF I2C registers. The user cannot change only the M

value and must change both the M and the N values at the

same time, if they require a change to the M value. The user

may change only the N value.

PD_RESTORE

If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PD# LOW,

the SL28506 initiates a full reset. The result of this is that the

clock chip emulates a cold power on start and goes to the

“Latches Open” state. If the PD_RESTORE bit is set to a ‘1’

then the configuration is stored upon PD# asserted LOW. Note

that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then the PD_RE-

STORE bit must be ignored. In other words, in Intel iAMT

mode, PD# reset is not allowed.

Associated Register Bits

• CPU_DAF Enable – This bit enables CPU DAF mode. By

default, it is not set. When set, the operating frequency is

determined by the values entered into the CPU_DAF_N

register. Note that the CPU_DAF_N and M register must

contain valid values before CPU_DAF is set. Default = 0,

(No DAF).

PD# (Power down) Clarification

• CPU_DAF_N – There are nine bits (for 512 values) to

linearly change the CPU frequency (limited by VCO range).

Default = 0, (0000). The allowable values for N are detailed

in Table 1, Frequency Select Table.

The CKPWRGD/PD# pin is a dual-function pin. During initial

power up, the pin functions as CKPWRGD. Once CKPWRGD

has been sampled HIGH by the clock chip, the pin assumes

PD# functionality. The PD# pin is an asynchronous active

LOW input used to shut off all clocks cleanly before shutting

off power to the device. This signal is synchronized internally

to the device before powering down the clock synthesizer. PD#

is also an asynchronous input for powering up the system.

When PD# is asserted LOW, clocks are driven to a LOW value

and held before turning off the VCOs and the crystal oscillator.

• CPU DAF M – There are 7 bits (for 128 values) to linearly

change the CPU frequency (limited by VCO range). Default

= 0, the allowable values for M are detailed in Table 1,

Frequency Select Table

• SRC_DAF Enable – This bit enables SRC DAF mode. By

default, it is not set. When set, the operating frequency is

determined by the values entered into the SRC_DAF_N

register. Note that the SRC_DAF_N register must contain

valid values before SRC_DAF is set. Default = 0, (No DAF).

PD# (Power down) Assertion

When PD is sampled HIGH by two consecutive rising edges

of CPUC, all single-ended outputs will be held LOW on their

next HIGH-to-LOW transition and differential clocks must held

LOW. When PD mode is desired as the initial power on state,

PD must be asserted HIGH in less than 10 s after asserting

CKPWRGD.

• SRC_DAF_N – There are nine bits (for 512 values) to

linearly change the CPU frequency (limited by VCO range).

Default = 0, (0000). The allowable values for N are detailed

in Table 1, Frequency Select Table.

.......................DOC #: SP-AP-0021 (Rev AA) Page 13 of 28

SL28506

PD# Deassertion

than 300 s of PD# deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs are enabled within a few clock cycles of

each clock. Figure 2 is an example showing the relationship of

clocks coming up.

The power up latency is less than 1.8 ms. This is the time from

the deassertion of the PD# pin or the ramping of the power

supply until the time that stable clocks are generated from the

clock chip. All differential outputs stopped in a three-state

condition, resulting from power down are driven high in less

PD#

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33 MHz

REF

Figure 1. Power down Assertion Timing Waveform

Ts table

<1.8 ms

PD#

CP UT , 133MHz

CP UC, 133MHz

S RCT 100MHz

S RCC 100MHz

US B , 48MHz

DOT 96T

DOT 96C

P CI, 33MHz

REF

Tdriv e_PW R D N #

<300 s , >200m V

Figure 2. Power down Deassertion Timing Waveform

.......................DOC #: SP-AP-0021 (Rev AA) Page 14 of 28

SL28506

FS_A, FS_B,FS_C,FS_D

CKPWRGD

PWRGD_VRM

0.2-0.3 ms

Delay

Wait for

VTT_PWRGD#

Device is not affected,

VTT_PWRGD# is ignored

Sample Sels

State 2

VDD Clock Gen

Clock State

State 0

Off

State 1

State 3

On

Clock Outputs

Clock VCO

On

Off

Figure 3. CKPWRGD Timing Diagram

.......................DOC #: SP-AP-0021 (Rev AA) Page 15 of 28

SL28506

CPU_STP# Assertion

CPU_STP# Deassertion

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configuration to be stoppable are stopped

within two to six CPU clock periods after sampled by two rising

edges of the internal CPUC clock. The final states of the

stopped CPU signals are CPUT = HIGH and CPUC = LOW.

The deassertion of the CPU_STP# signal causes all stopped

CPU outputs to resume normal operation in a synchronous

manner. No short or stretched clock pulses are produced when

the clock resumes. The maximum latency from the

deassertion to active outputs is no more than two CPU clock

cycles.

CPU_STP#

CPUT

CPUC

Figure 4. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

CPUC Internal

Tdrive_CPU_STP#,10 ns>200 mV

Figure 5. CPU_STP# Deassertion Waveform

.

PCI_STP# Assertion

The PCI_STP# signal is an active LOW input used for

synchronously stopping and starting the PCI outputs while the

rest of the clock generator continues to function. The set-up

time for capturing PCI_STP# going LOW is 10 ns (t_SU). (See

Figure 6.) The PCIF clocks are affected by this pin if their

corresponding control bit in the SMBus register is set to allow

them to be free running.

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 6. PCI_STP# Assertion Waveform

.......................DOC #: SP-AP-0021 (Rev AA) Page 16 of 28

SL28506

PCI_STP# Deassertion

.

The deassertion of the PCI_STP# signal causes all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods, after PCI_STP# transi-

tions to a HIGH level.

Tdrive_SRC

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 7. PCI_STP# Deassertion Waveform

.

Figure 8. Clock Generator Power up/Run State Diagram

.......................DOC #: SP-AP-0021 (Rev AA) Page 17 of 28

SL28506

C l o c k O f f t o M 1

3.3V

Vcc

2.0V

T_delay t

FSC

FSB

FSA

CPU_STP#

PCI_STP#

CKPWRGD/PD#

CK505 SMBUS

CK505 State

Off

Latches Open

M1

Off

BSEL[0..2]

Off

CK505 Core Logic

PLL1

Locked

CPU1

PLL2 & PLL3

All Other Clocks

REF Oscillator

T_delay2

T_delay3

Figure 9. BSEL Serial Latching

.......................DOC #: SP-AP-0021 (Rev AA) Page 18 of 28

SL28506

Absolute Maximum Conditions

Parameter

V_{DD_3.3V}

V_{DD_IO}

V_IN

Description

Supply Voltage

Condition

Min.

Max. Unit

Functional

–

4.6

1.5

4.6

150

85

V

IO Supply Voltage

Input Voltage

Functional

Relative to V_SS

Non-functional

Functional

–0.5

–65

0

V_DC

°C

T_S

Temperature, Storage

T_A

Commercial Temperature,

Operating Ambient

Industrial Temperature,

Operating Ambient

-40

+85

°C

T_J

Temperature, Junction

Functional

–

150

20

°C

°C/W

Ø_JC

Ø_JA

Dissipation, Junction to Case JEDEC (JESD 51)

Dissipation, Junction to Ambient JEDEC (JESD 51)

60

°C/

W

ESD_HBM

ESD Protection (Human Body JEDEC (JESD 22-A114)

Model)

2000

–

V

UL-94

MSL

Flammability Rating

UL (CLASS)

V–0

Moisture Sensitivity Level

1

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter

VDD core

Description

Condition

Min.

Max.

3.465

V_DD+ 0.3

0.8

Unit

3.3V Operating Voltage

3.3V Input High Voltage (SE)

3.3V Input Low Voltage (SE)

Input High Voltage

3.3 ± 5%

3.135

V

V_IH

2.0

V_IL

V_SS– 0.3

V

V_IHI2C

V_ILI2C

V_{IH_FS}

V_{IL_FS}

V_{IHFS_C_TEST}

SDATA, SCLK

2.2

–

V

Input Low Voltage

–

1.0

V

FS_[A,B] Input High Voltage

FS_[A,B] Input Low Voltage

FS_C Input High Voltage

0.7

1.5

V

V_SS– 0.3

0.35

V_DD+ 0.3

1.5

V

2

V

V_{IMFS_C_NORMAL}FS_C Input Middle Voltage

V_{ILFS_C_NORMAL}FS_C Input Low Voltage

0.7

V

V_SS– 0.3

0.35

VDD

2.00

0.900

5

V

PCI3/CFG0_{_}

PCI3/CFG0 Input High Voltage Typ. 2.75V

2.40

1.30

0

V

HIGH

PCI3/CFG0_{_MID}PCI3/CFG0 Input Mid Voltage Typ. 1.65V

PCI3/CFG0_{_LOW}PCI3/CFG0 Input Low Voltage Typ. 0.550V

V

I_IH

Input High Leakage Current

Input Low Leakage Current

Except internal pull-down resistors, 0 < V_IN< V_DD

Except internal pull-up resistors, 0 < V_IN< V_DD

–

A

V

I_IL

–5

2.4

–

V_OH

V_OL

V_{DD IO}

I_OZ

3.3V Output High Voltage (SE) I_OH= –1 mA

3.3V Output Low Voltage (SE) I_OL= 1 mA

Low Voltage IO Supply Voltage

–

0.4

V

1

3.465

10

V

High-impedance Output

Current

–10

A

C_IN

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

1.5

5

6

pF

nH

V

C_OUT

L_IN

–

0.7V_DD

0

7

V_XIH

V_XIL

Xin High Voltage

V_DD

0.3V_DD

Xin Low Voltage

V

.......................DOC #: SP-AP-0021 (Rev AA) Page 19 of 28

SL28506

DC Electrical Specifications

Parameter

IDD_PWRDWN

I_DD3.3V

Description

Condition

Min.

Max.

1

Unit

Power Down Current

mA

Dynamic Supply Current

–

250

.......................DOC #: SP-AP-0021 (Rev AA) Page 20 of 28

SL28506

AC Electrical Specifications

Parameter

Crystal

Description

Condition

Min.

Max.

Unit

L_ACC

Long-term Accuracy

–

300

ppm

Clock Input

T_DC

CLKIN Duty Cycle

Measured at VDD/2

47

0.5

–

53

4.0

%

V/ns

ps

T_R/T_F

CLKIN Rise and Fall Times

CLKIN Cycle to Cycle Jitter

CLKIN Long Term Jitter

Input Low Voltage

Measured between 0.2V_DDand 0.8V_DD

Measured at VDD/2

T_CCJ

250

T_LTJ

Measured at VDD/2

–

350

ps

V_IL

XIN / CLKIN pin

–

0.8

V

V_IH

Input High Voltage

XIN / CLKIN pin

2

VDD+0.3

20

V

I_IL

Input LowCurrent

XIN / CLKIN pin, 0 < VIN <0.8

XIN / CLKIN pin, VIN = VDD

–

uA

I_IH

Input HighCurrent

–

35

CPU at 0.7V

T_DC

45

55

CPU Clock Duty Cycle

Measured at 0V differential at 0.1s

Measured at 0V differential at 1 clock

%

ns

9.99900

7.49925

5.99940

4.99950

3.74963

2.99970

2.49975

10.00100

7.50075

6.00060

5.00050

3.75038

3.00030

2.50025

T_PERIOD

T_PERIODSS

T_PERIODAbs

100 MHz CPU Clock Period

133 MHz CPU Clock Period

166 MHz CPU Clock Period

200 MHz CPU Clock Period

266 MHz CPU Clock Period

333 MHz CPU Clock Period

400 MHz CPU Clock Period

10.02406 10.02607

100 MHz CPU Clock Period, SSC

133 MHz CPU Clock Period, SSC

166 MHz CPU Clock Period, SSC

200 MHz CPU Clock Period, SSC

266 MHz CPU Clock Period, SSC

333 MHz CPU Clock Period, SSC

400 MHz CPU Clock Period, SSC

100 MHz CPU Clock Absolute period

133 MHz CPU Clock Absolute period

166 MHz CPU Clock Absolute period

200 MHz CPU Clock Absolute period

266 MHz CPU Clock Absolute period

333 MHz CPU Clock Absolute period

400 MHz CPU Clock Absolute period

7.51804

6.01444

5.01203

3.75902

3.00722

2.50601

9.91400

7.41425

5.91440

4.91450

3.66463

2.91470

2.41475

9.91406

7.51955

6.01564

5.01303

3.75978

3.00782

2.50652

10.0860

7.58575

6.08560

5.08550

3.83538

3.08530

2.58525

10.1362

T_PERIODSSAbs100 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock

SSC

7.41430

5.91444

4.91453

3.66465

2.91472

7.62340

6.11572

5.11060

3.85420

3.10036

T_PERIODSSAbs133 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock

SSC

ns

T_PERIODSSAbs166 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock

SSC

T_PERIODSSAbs200 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock

SSC

T_PERIODSSAbs266 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock

SSC

T_PERIODSSAbs333 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock

SSC

.......................DOC #: SP-AP-0021 (Rev AA) Page 21 of 28

SL28506

AC Electrical Specifications (continued)

Parameter

Description

Condition

Min.

Max.

Unit

2.41477

2.59780

T_PERIODSSAbs400 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock

SSC

ns

T_CCJ

CPU Cycle to Cycle Jitter

CPU2_ITP Cycle to Cycle Jitter

Long-term Accuracy

Measured at 0V differential

–

85

125

100

150

8

ps

T_CCJ2

Measured at 0V differential

L_ACC

Measured at 0V differential

–

ppm

ps

T_SKEW

T_SKEW2

T_R/ T_F

T_RFM

CPU0 to CPU1 Clock Skew

CPU2_ITP to CPU0 Clock Skew

CPU Rising/Falling Slew rate

Rise/Fall Matching

Measured at 0V differential

–

Measured at 0V differential

–

ps

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

2.5

–

V/ns

%

20

V_HIGH

Voltage High

1.15

–

V

V_LOW

Voltage Low

–0.3

300

V

V_OX

Crossing Point Voltage at 0.7V Swing

550

mV

SRC at 0.7V

T_DC

SRC Duty Cycle

Measured at 0V differential

45

55

%

ns

9.99900

10.0010

T_PERIOD

T_PERIODSS

T_PERIODAbs

100 MHz SRC Period

Measured at 0V differential at 0.1s

Measured at 0V differential at 1 clock

10.02406 10.02607

100 MHz SRC Period, SSC

100 MHz SRC Absolute Period

9.87400

9.87406

–

10.1260

10.1762

3.0

T_PERIODSSAbs100 MHz SRC Absolute Period, SSC

T_SKEW(window)Any SRC Clock Skew from the earliest Measured at 0V differential

bank to the latest bank

T_CCJ

SRC Cycle to Cycle Jitter

SRC Long Term Accuracy

SRC Rising/Falling Slew Rate

Rise/Fall Matching

Measured at 0V differential

–

125

100

8

ps

ppm

V/ns

%

L_ACC

Measured at 0V differential

T_R/ T_F

T_RFM

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

2.5

–

20

V_HIGH

V_LOW

Voltage High

1.15

–

V

Voltage Low

–0.3

300

V

V_OX

Crossing Point Voltage at 0.7V Swing

550

mV

DOT96 at 0.7V

T_DC

DOT96 Duty Cycle

Measured at 0V differential

45

55

10.4177

10.6677

250

100

8

%

ns

10.4156

T_PERIOD

T_PERIODAbs

T_CCJ

DOT96 Period

Measured at 0V differential at 0.1s

Measured at 0V differential at 1 clock

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

10.1656

DOT96 Absolute Period

DOT96 Cycle to Cycle Jitter

DOT96 Long Term Accuracy

DOT96 Rising/Falling Slew Rate

Rise/Fall Matching

ns

–

ps

L_ACC

ppm

V/ns

%

T_R/ T_F

T_RFM

2.5

–

20

V_HIGH

V_LOW

Voltage High

1.15

–

V

Voltage Low

–0.3

300

V

V_OX

Crossing Point Voltage at 0.7V Swing

550

mV

LCD_100_SSC at 0.7V

T_DC

LCD_100 Duty Cycle

100 MHz LCD_100 Period

Measured at 0V differential

45

55

%

T_PERIOD

T_PERIODSS

T_PERIODAbs

Measured at 0V differential at 0.1s

9.99900

10.0010

ns

100 MHz LCD_100 Period, SSC -0.5% Measured at 0V differential at 0.1s

10.02406 10.02607 ns

9.74900 10.25100 ns

100 MHz LCD_100 Absolute Period

Measured at 0V differential at 1 clock

T_PERIODSSAbs100 MHz LCD_100 Absolute Period,

SSC

9.74906

10.3012

ns

.......................DOC #: SP-AP-0021 (Rev AA) Page 22 of 28

SL28506

AC Electrical Specifications (continued)

Parameter

T_CCJ

Description

LCD_100 Cycle to Cycle Jitter

LCD_100 Long Term Accuracy

LCD_100 Rising/Falling Slew Rate

Rise/Fall Matching

Condition

Min.

–

Max.

250

100

8

Unit

ps

Measured at 0V differential

L_ACC

T_R/ T_F

T_RFM

V_HIGH

V_LOW

V_OX

Measured at 0V differential

–

ppm

V/ns

%

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

2.5

–

20

Voltage High

1.15

–

V

Voltage Low

–0.3

300

V

Crossing Point Voltage at 0.7V Swing

550

mV

PCI/PCIF at 3.3V

T_DC

PCI Duty Cycle

Measurement at 1.5V

45

55

%

ns

29.99700 30.00300

30.08421 30.23459

29.49700 30.50300

29.56617 30.58421

T_PERIOD

T_PERIODSS

T_PERIODAbs

Spread Disabled PCIF/PCI Period

Spread Enabled PCIF/PCI Period

Spread Disabled PCIF/PCI Period

T_PERIODSSAbsSpread Enabled PCIF/PCI Period

T_HIGH

T_LOW

T_HIGH

Spread Enabled PCIF and PCI high time Measurement at 2V

Spread Enabled PCIF and PCI low time Measurement at 0.8V

12.27095 16.27995 ns

11.87095 16.07995 ns

12.27365 16.27665 ns

Spread Disabled PCIF and PCI high

time

Measurement at 2.V

T_LOW

Spread Disabled PCIF and PCI low time Measurement at 0.8V

11.87365 16.07665 ns

T_R/ T_F

T_SKEW

T_CCJ

PCIF/PCI Rising/Falling Slew Rate

Measured between 0.8V and 2.0V

1.0

–

4.0

1000

500

V/ns

ps

Any PCI clock to Any PCI clock Skew Measurement at 1.5V

PCIF and PCI Cycle to Cycle Jitter

PCIF/PCI Long Term Accuracy

Measurement at 1.5V

–

ps

L_ACC

–

100

ppm

48_M at 3.3V

T_DC

Duty Cycle

Measurement at 1.5V

Measurement at 2V

45

55

%

ns

20.83125 20.83542

20.48125 21.18542

8.216563 11.15198

7.816563 10.95198

T_PERIOD

T_PERIODAbs

T_HIGH

Period

Absolute Period

48_M High time

ns

T_LOW

48_M Low time

Measurement at 0.8V

Measured between 0.8V and 2.0V

Measurement at 1.5V

ns

T_R/ T_F

T_CCJ

Rising and Falling Edge Rate

Cycle to Cycle Jitter

48M Long Term Accuracy

1.0

–

2.0

350

100

V/ns

ps

L_ACC

–

ppm

27M_NSS/27M_SS at 3.3V

T_DC

Duty Cycle

Measurement at 1.5V

45

55

%

T_PERIOD

Spread Disabled 27M Period

Spread Enabled 27M Period

Rising and Falling Edge Rate

Cycle to Cycle Jitter

Measurement at 1.5V

37.03594 37.03813 ns

37.01299 37.13172 ns

Measurement at 1.5V

T_R/ T_F

T_CCJ

Measured between 0.8V and 2.0V

Measurement at 1.5V

1.0

–

4.0

250

50

V/ns

ps

L_ACC

27_M Long Term Accuracy

Measured at crossing point V_OX

–

ppm

REF

T_DC

REF Duty Cycle

REF Period

Measurement at 1.5V

Measurement at 2V

Measurement at 0.8V

45

55

%

ns

69.82033 69.86224

68.83429 70.84826

29.97543 38.46654

29.57543 38.26654

T_PERIOD

T_PERIODAbs

T_HIGH

T_LOW

REF Absolute Period

REF High time

REF Low time

.......................DOC #: SP-AP-0021 (Rev AA) Page 23 of 28

SL28506

AC Electrical Specifications (continued)

Parameter

T_R/ T_F

T_SKEW

T_CCJ

Description

REF Rising and Falling Edge Rate

REF Clock to REF Clock

REF Cycle to Cycle Jitter

Long Term Accuracy

Condition

Measured between 0.8V and 2.0V

Measurement at 1.5V

Min.

1.0

–

Max.

4.0

Unit

V/ns

ps

500

1000

100

Measurement at 1.5V

–

ps

L_ACC

Measurement at 1.5V

–

ppm

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SSStopclock Set-up Time

–

1.8

–

ms

ns

10.0

Test and Measurement Set-up

For PCI Single-ended Signals and Reference

The following diagram shows the test load configurations for

the single-ended PCI, USB, and REF output signals.

Measurement

Point

22

L1

L2

50

4 pF

L1 = 0.5", L2 = 8"

22

PCI/USB

Measurement

Point

50

L2

L1

Figure 10. Single-ended PCI and USB Double Load Configuration

Measurement

15

L2

L1

Point

50

4 pF

Measurement

Point

4 pF

15

L1

L2

REF

50

Measurement

Point

4 pF

L2

50

L1 = 0.5", L2 = 8"

Figure 11. Single-ended REF Triple Load Configuration

Figure 12. Single-ended Output Signals (for AC Parameters Measurement)

.......................DOC #: SP-AP-0021 (Rev AA) Page 24 of 28

SL28506

For CPU, SRC, and DOT96 Signals and Reference

This diagram shows the test load configuration for the differential CPU and SRC outputs

Measurement

33

L1

L2

Point

OUT+

OUT-

50

2 pF

L1 = 0.5", L2 = 7"

Measurement

Point

33

L2

50

Figure 13. 0.7V Differential Load Configuration

Clock Period (Differential)

Positive Duty Cycle (Differential)

Negative Duty Cycle (Differential)

0.0V

Clock-Clock#

Rise

Edge

Rate

Fall

Edge

Rate

VIH = +150mV

0.0V

VIL = -150mV

Clock-Clock#

Figure 14. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)

.......................DOC #: SP-AP-0021 (Rev AA) Page 25 of 28

SL28506

V_MAX= 1.15V

CLK#

Vcross_MAX= 550mV

Vcross_MIN= 300mV

Vcross_MAX= 550mV

Vcross_MIN= 300mV

CLK

V_MIN= 0.30V

CLK#

Vcross delta = 140mV

CLK

CLK#

Vcross median +75mV

Vcross median

Vcross median -75mV

CLK

Figure 15. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)

Ordering Information

Part Number

Package Type

Product Flow

Lead-free

SL28506BZC

SL28506BZCT

SL28506BZI

SL28506BZIT

64-pin TSSOP

Commercial, 0 to 85C

Industrial, -40 to 85C

64-pin TSSOP–Tape and Reel

64-pin TSSOP

64-pin TSSOP–Tape and Reel

This device is Pb-free, Halogen-free and RoHS compliant. Parts supporting extended temperature is available upon request

.......................DOC #: SP-AP-0021 (Rev AA) Page 26 of 28

SL28506

Package Diagrams

64-Lead Thin Shrunk Small Outline Package (6 mm x 17 mm)

.......................DOC #: SP-AP-0021 (Rev AA) Page 27 of 28

SL28506

Document History Page

Document Title: SL28506 Clock Generator for Intel^®Eaglelake Chipset

DOC #: SP-AP-0021 (Rev AA)

Orig. of

REV. ECR# Issue Date Change

Description of Change

1.0

1.1

7/12/07

JMA

New datasheet

10/30/07

1. Changed -1% spread to -0.45% spread in Byte 13 Bit 5

2. Added part number ordering information

3. Updated ordering number as general type

1.2

1.3

12/15/07

8/4/08

BSHEN 1. Changed Revision ID as 0001

2. Updated ordering number as SL28506BZC

JMA

1. Changed operating temperature range from 0C-85C to 0C-70C

2. Added note on RoHS and Pb-free

3. Removed Preliminary wording

1.4

AA

4/1/09

4/2/10

JMA

1 Update Package diagram

1460

1. Added new feature for XIN to support also CLKIN input

2. Updated revision and ordering information

3. Updated JEDEC information

4. Updated format to be ISO compliant

5. Updated commercial temperature grade back to 0C-85C

6. Merged commercial and industrial temperature

7. Added Bit 0 in Byte 3

8. Updated package ID in Byte 8 to reflect package

9. Updated Feature portion to include exclusion of SRC0 and SRC1 from PCIe Gen 2 require-

ments

10. Updated Byte 11 Bit 1 to be a read only bit

.......................DOC #: SP-AP-0021 (Rev AA) Page 28 of 28

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using

or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and

"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent

of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in

weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,

EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,

ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laborato-

ries Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand

names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

http://www.silabs.com


型号：	SL28506BZCT
厂家：	SILICON
描述：	Clock Generator for IntelÂ® Eaglelake Chipset 时钟光电二极管外围集成电路晶体
文件：	总29页 (文件大小：425K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SL28506BZCT [SILICON]

相关型号：

SL28506BZI

SL28506BZI-2

SL28506BZI-2T

SL28506BZIT

SL28540ALC

SL28540ALCT

SL28541

SL28541BQCR

SL28541BQCRT

SL28541BQIR

SL28541BQIRT

SL28541BZC