SL28504BZC_技术文档

SL28504

Clock Generator for Intel^Eaglelake Chipset

• 25MHz Free run for WOL

Features

• Selectable 25MHz/24.576MHz

• Buffered Reference Clock 14.318 MHz

• Compliant to Intel^®CK505

• Low power push-pull type differential output buffers

• Integrated voltage regulator

• Low-voltage frequency select input

• I²C support with readback capabilities

• Integrated resistors on differential clocks

• Scalable low voltage VDD_IO (3.3V to 1.05V)

• Differential CPU clocks with selectable frequency

• 100 MHz Differential SRC clocks

• 96 MHz Differential DOT clock

• Triangular Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V Power supply

• 64-pin TSSOP packages

CPU

SRC

PCI

x6

REF

x 2

DOT96 USB_48 24.576M 25M

x 1 x1 x1 x2

• 48 MHz USB clocks

x2 / x3

x8/x11

• 33 MHz PCI clock

Pin Configuration

PCI_0/ CR#_A

VDD_PCI

1

64

SCLK

2

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

SDATA

PCI_1 / CR#_B

PCI_2 / TME

PCI_3

3

REF0/FSC/TEST_SEL

VDD_REF

4

5

XTAL_IN

PCI_4 / GCLK_SEL

PCIF_0 / ITP_EN

VSS_PCI

6

XTAL_OUT

7

VSS_REF

8

FSB/ TEST_MODE

CK_PWRGD / PWRDWN#

VDD_CPU

VDD_48

9

USB_48 / FSA

VSS_48

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

CPU0

VDD_IO

CPU0#

SRC0 / DOT96

SRC0# / DOT96#

VSS_IO

VSS_CPU

CPU1

CPU1#

VDD_PLL3

VDD_CPU_IO

*SEL_24.576M

SRC8 / CPU2_ITP

SRC8# / CPU2_ITP#

VDD_SRC_IO

SRC7 / CR#_F

SRC7# / CR#_E

VSS_SRC

SRC1 / 25M0_F

SRC1#/ 25M1_24.576M

VSS_PLL3

SL28504

VDD_PLL3_IO

SRC2 / SATA

SRC2# / SATA#

VSS_SRC

SRC3 / CR#_C

SRC3# / CR#_D

VDD_SRC_IO

SRC4

SRC6

SRC6#

VDD_SRC

SRC5/ PCI_STOP#

SRC5#/ CPU_STOP#

VDD_SRC_IO

SRC10#

SRC4#

VSS_SRC

SRCT9

SRCC9

SRC10

SRC11# / CR#_G

SRC11 / CR#_H

* Internal Pull-Down

........................ DOC #: SP-AP-0052 (Rev. AA) Page 1 of 31

400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669

www.silabs.com

SL28504

Block Diagram

Xin

14.318MHz

Crystal

REF0

Xout

PLL Reference

Divider

CPU[1:0]

PLL1

SRC8/CPU2_ITP

PCI[4:0]; PCIF0

SRC

PLL3

Divider

SRC_SATA

25M0_F

Divider

PLL4

PLL2

25M1_24.576M

DOT96/SRC0

USB_48

Divider

PCI_STOP#

CPU_STOP#

FSC:A]

SATA_SEL

Control Logic

CK_PWRGD/PD#

SDATA

SEL_24.576M

SCLK

64-TSSOP Pin Definitions

Pin No.

Name

PCI0 / CR#_A

Type

Description

1

I/O, SE 33 MHz Clock/3.3V Clock Request # Input

Mappable via I2C to control either SRC 0 or SRC 2. Default PCI0.

To configure this pin to serve as a Clock Request pin for either SRC pair 2 or pair

0 using the CR#_A_EN bit located in byte 5 bit 7, first disable PCI output (Hi-z) in

byte 2, bit 1.

0 = PCI0 enabled (default)

1= CR#_A enabled.

Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair

Byte 5, bit 6:

0 = CR#_A controls SRC0 pair (default)

1= CR#_A controls SRC2 pair

2

3

VDD_PCI

PWR 3.3V Power supply for PCI PLL.

PCI1 / CR#_B

I/O, SE 33 MHz Clock/3.3V Clock Request # Input

Mappable via I2C to control either SRC 1 or SRC 4. Default PCI1.

To configure this pin to serve as a Clock Request pin for either SRC pair 1 or pair

4 using the CR#_B_EN bit located in byte 5, bit 5, first disable PCI output (Hi-z) in

byte 2, bit 1.

0 = PCI1 enabled (default)

1= CR#_B enabled.

Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair

Byte 5, bit 4:

0 = CR#_B controls SRC1 pair (default)

1= CR#_B controls SRC4 pair

4

PCI_2

O, SE 33 MHz clock.

........................ DOC #: SP-AP-0052 (Rev. AA) Page 2 of 31

SL28504

64-TSSOP Pin Definitions

Pin No.

Name

Type

Description

5

PCI_3

O, SE 33 MHz clock.

6

7

PCI4 /SRC5_EN

PCIF_0/ITP_EN

I/O, SE 33 MHz clock output/3.3V-tolerant input for SRC enable

(Sampled on CKPWRGD assertion)

1 = SRC5, 0 =CPU_STOP#/PCI_STOP#

I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled

on the CK_PWRGD assertion)

1 = CPU2_ITP, 0 = SRC8

8

VSS_PCI

GND Ground for outputs.

9

VDD_48

PWR 3.3V Power supply for outputs and PLL.

10

USB_48/FSA

I/O

3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output. Refer

to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

11

12

13

VSS_48

GND Ground for outputs.

VDD_IO

PWR 3.3V-1.05V Power supply for outputs.

SRC0/DOT96T

O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected

via I2C default is SRC0.

14

SRC0#/DOT96#

O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output. Selected

via I2C default is SRC0.

15

16

17

18

VSS_IO

GND Ground for PLL2.

VDD_PLL3

PWR 3.3V Power supply for PLL3

SRC1/25M0_F

SRC1#/25M1_24.576M

O, SE 100 MHz Differential serial reference clocks/ Free run 25MHz clock output

O, SE 100 MHz Differential serial reference clocks/ 25MHz clock output/24.576MHz clock

output

19

20

21

22

23

24

VSS_PLL3

GND Ground for PLL3.

VDD_PLL3_IO

SRC2_SATA

SRC2#_SATA#

VSS_SRC

PWR 3.3V-1.05V power supply for PLL3

O, DIF 100 MHz Differential serial reference clocks.

GND Ground for outputs.

SRC3 / CR#_C

I/O, 100 MHz differential serial reference clock output /3.3V Clock Request #_C/D

DIF input

Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.

The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC

to stop when asserted

25

SRC3# / CR#_D

I/O, 100 MHz differential serial reference clock output/3.3V Clock Request #_C/D

DIF input

Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.

The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC

to stop when asserted

26

27

28

29

30

31

32

VDD_SRC_IO

SRC4

PWR 3.3V-1.05V power supply for SRC outputs.

O, DIF 100 MHz Differential serial reference clocks.

GND Ground for outputs.

SRC4#

VSS_SRC

SRC9

O, DIF 100 MHz Differential serial reference clocks.

SRC9#

SRC11#/ CR#_G

I/O, 100 MHz differential serial reference clocks/3.3V CR#_G Input.

DIF Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.

When selected, CR#_G controls SRC9, CR#_H controls SRC10

33

SRC11/ CR#_H

I/O, 100 MHz Differential serial reference clocks/3.3V CR#_H Input.

DIF Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.

When selected, CR#_G controls SRC9, CR#_H controls SRC10

........................ DOC #: SP-AP-0052 (Rev. AA) Page 3 of 31

SL28504

64-TSSOP Pin Definitions

Pin No.

34

Name

Type

Description

SRC10

O, DIF 100 MHz Differential serial reference clocks.

PWR 3.3V-1.05V power supply for SRC outputs.

35

SRC#10

36

VDD_SRC_IO

37

CPU_STOP#/SRC5#

I/O, 3.3V tolerant input for stopping CPU outputs./100 MHz Differential serial reference

Dif clocks. The option is selected by SRC5_EN

38

PCI_STOP#/SRC5

I/O, 3.3V tolerant input for stopping PCI and SRC outputs./ 100 MHz Differential serial

Dif reference clocks.The option is selected by SRC5_EN

39

40

41

42

43

44

45

46

VDD_SRC

SRC6#

PWR 3.3V Power supply for SRC PLL.

O, DIF 100 MHz Differential serial reference clocks.

GND Ground for outputs.

SRC6

VSS_SRC

SRC7#

O, DIF 100 MHz Differential serial reference clocks

O, DIF 00 MHz Differential serial reference clocks

PWR 3.3V-1.05V power supply for SRC outputs.

SRC7

VDD_SRC_IO

SRC8#/CPUC2_ITP#

O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD

assertion = SRC8

ITP_EN = 1 @ CK_PWRGD assertion = CPU2

Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11

Bit3:2.

47

48

SRC8/CPUT2_ITP

SEL_24.576M

O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD

assertion = SRC8

ITP_EN = 1 @ CK_PWRGD assertion = CPU2

Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11

Bit3:2.

I, PD Select 25M1_24.576M output and SRC1

0 = 25M1, M= SRC1, 1 = 24.576M

49

50

VDD_CPU_IO

CPU1#

PWR 3.3V-1.05V power supply for CPU outputs.

O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending

on the configuration set in Byte 11 Bit3:2.

51

CPU1

O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending

on the configuration set in Byte 11 Bit3:2.

52

53

54

55

56

VSS_CPU

GND Ground for outputs.

CPU0#

O, DIF Differential CPU clock outputs.

PWR 3.3V Power supply for CPU PLL.

CPU0

VDD_CPU

CK_PWRGD/PWRDWN#

I

3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,

FS_C, and ITP_EN.

After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for

asserting power down (active LOW).

57

FSB/TEST_MODE

I

3.3V tolerant input for CPU frequency selection.

Selects Ref/N or Tri-state when in test mode

0 = Tri-state, 1 = Ref/N.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

58

59

60

61

VSS_REF

XTAL_OUT

XTAL_IN

GND Ground for outputs.

O, SE 14.318 MHz Crystal output.

I

14.318 MHz Crystal input.

VDD_REF

PWR 3.3V Power supply for outputs and also maintains SMBUS registers during

power-down.

62

REF0/FSC/TEST_SEL

I/O

3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects

test mode if pulled to V_{IHFS_C}when CK_PWRGD is asserted HIGH. Refer to DC

Electrical Specifications table for V_{ILFS_C}, V_{IMFS_C}, V_{IHFS_C}specifications.

........................ DOC #: SP-AP-0052 (Rev. AA) Page 4 of 31

SL28504

64-TSSOP Pin Definitions

Pin No.

63

Name

SMB_DATA

SMB_CLK

Type

I/O

I

Description

SMBus compatible SDATA.

SMBus compatible SCLOCK.

64

........................ DOC #: SP-AP-0052 (Rev. AA) Page 5 of 31

SL28504

Frequency Select Pin (FSA, FSB and FSC)

FSC

0

FSB

0

FSA

0

CPU

SRC

PCIF/PCI

REF

DOT96

USB

266 MHz

133 MHz

200 MHz

166 MHz

333 MHz

100 MHz

400 MHz

Reserved

0

1

0

1

0

1

100 MHz

33 MHz

14.318 MHz

Reserved

96 MHz

48 MHz

1

0

1

0

1

0

1

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

Frequency Select Pin (FSA, FSB and FSC)

Apply the appropriate logic levels to FSA, FSB, and FSC

inputs before CK-PWRGD assertion to achieve host clock

frequency selection. When the clock chip sampled HIGH on

CK-PWRGD and indicates that VTT voltage is stable then

FSA, FSB, and FSC input values are sampled. This process

employs a one-shot functionality and once the CK-PWRGD

sampled a valid HIGH, all other FSA, FSB, FSC, and

CK-PWRGD transitions are ignored except in test mode

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, Access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 1.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

The block write and block read protocol is outlined in Table 2

while Table 3 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h)

their default setting at power-up. The use of this interface is

.

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Description

Block Read Protocol

Description

Bit

1

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

Byte Count–8 bits

20

(Skip this step if I²C_EN bit set)

28

36:29

37

Acknowledge from slave

Data byte 1–8 bits

27:21

28

Slave address–7 bits

Read = 1

Acknowledge from slave

Data byte 2–8 bits

29

Acknowledge from slave

Byte Count from slave–8 bits

45:38

37:30

........................ DOC #: SP-AP-0052 (Rev. AA) Page 6 of 31

SL28504

Table 2. Block Read and Block Write Protocol (continued)

Block Write Protocol

Block Read Protocol

Description

Bit

46

....

Description

Acknowledge from slave

Bit

38

Acknowledge

Data Byte /Slave Acknowledges

Data Byte N–8 bits

Acknowledge from slave

Stop

46:39

47

Data byte 1 from slave–8 bits

Acknowledge

55:48

56

Data byte 2 from slave–8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave–8 bits

NOT Acknowledge

....

Stop

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Stop

27:21

28

Slave address–7 bits

Read

29

Acknowledge from slave

Data from slave–8 bits

NOT Acknowledge

Stop

37:30

38

39

........................ DOC #: SP-AP-0052 (Rev. AA) Page 7 of 31

SL28504

Control Registers

Byte 0: Control Register 0

Bit

7

@Pup

HW

0

Name

FS_C

Description

CPU Frequency Select Bit, set by HW

6

FS_B

CPU Frequency Select Bit, set by HW

5

FS_A

4

iAMT_EN

Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP

0 = Legacy Mode, 1 = iAMT Enabled

3

2

1

0

Reserved

SATA_SEL

Reserved

Select source of SATA clock

0 = PLL3, 1= PLL4

0

1

PD_Restore

Save Config. In powerdown

0 = Config. Cleared, 1 = Config. Saved

Byte 1: Control Register 1

Bit

@Pup

Name

Description

7

0

SRC0_SEL

Select for SRC0 or DOT96

0 = SRC0, 1 = DOT96

6

5

0

PLL1_SS_DC

PLL3_SS_DC

Select for down or center SS

0 = Down spread, 1 = Center spread

Select for down or center SS

0 = Down spread, 1 = Center spread

4

3

2

1

0

1

Reserved

PCI_SEL

Reserved

Select source of PCI clocks

0=PLL1, 1=PLL3

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

REF0_OE

Output enable for REF0

0 = Output Disabled, 1 = Output Enabled

6

5

4

3

2

1

0

1

USB48_OE

PCIF0_OE

PCI4_OE

PCI3_OE

PCI2_OE

PCI1_OE

PCI0_OE

Output enable for USB48

0 = Output Disabled, 1 = Output Enabled

Output enable for PCIF5

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI4

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI3

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI2

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI1

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI0

0 = Output Disabled, 1 = Output Enabled

........................ DOC #: SP-AP-0052 (Rev. AA) Page 8 of 31

SL28504

Byte 3: Control Register 3

Bit

@Pup

Name

Description

7

1

SRC11_OE

Output enable for SRC11

0 = Output Disabled, 1 = Output Enabled

6

5

4

3

2

1

SRC10_OE

SRC9_OE

Output enable for SRC10

0 = Output Disabled, 1 = Output Enabled

Output enable for SRC9

0 = Output Disabled, 1 = Output Enabled

SRC8/CPU2_ITP_OE

SRC7_OE

Output enable for SRC8 or CPU2_ITP

0 = Output Disabled, 1 = Output Enabled

Output enable for SRC7

0 = Output Disabled, 1 = Output Enabled

SRC6_OE

Output enable for SRC6

0 = Output Disabled, 1 = Output Enabled

1

0

1

RESERVED

SRC4_OE

RESERVED

Output enable for SRC4

0 = Output Disabled, 1 = Output Enabled

Byte 4: Control Register 4

Bit

@Pup

Name

Description

7

1

SRC3_OE

Output enable for SRC3

0 = Output Disabled, 1 = Output Enabled

6

5

4

3

2

1

0

1

SRC2/SATA_OE

SRC1_OE

Output enable for SRC2/SATA

0 = Output Disabled, 1 = Output Enabled

Output enable for SRC1

0 = Output Disabled, 1 = Output Enabled

SRC0/DOT96_OE

CPU1_OE

Output enable for SRC0/DOT96

0 = Output Disabled, 1 = Output Enabled

Output enable for CPU1

0 = Output Disabled, 1 = Output Enabled

CPU0_OE

Output enable for CPU0

0 = Output Disabled, 1 = Output Enabled

PLL1_SS_EN

PLL3_SS_EN

Enable PLL1s spread modulation,

0 = Spread Disabled, 1 = Spread Enabled

Enable PLL3s spread modulation

0 = Spread Disabled, 1 = Spread Enabled

Byte 5: Control Register 5

Bit

@Pup

Name

Description

7

0

CR#_A_EN

Enable CR#_A (clk req)

0 = Disabled, 1 = Enabled,

6

5

4

3

2

0

CR#_A_SEL

CR#_B_EN

CR#_B_SEL

CR#_C_EN

CR#_C_SEL

Set CR#_A  SRC0 or SRC2

0 = CR#_ASRC0, 1 = CR#_ASRC2

Enable CR#_B(clk req)

0 = Disabled, 1 = Enabled,

Set CR#_B  SRC1 or SRC4

0 = CR#_BSRC1, 1 = CR#_BSRC4

Enable CR#_C (clk req)

0 = Disabled, 1 = Enabled

Set CR#_C  SRC0 or SRC2

0 = CR#_CSRC0, 1 = CR#_CSRC2

........................ DOC #: SP-AP-0052 (Rev. AA) Page 9 of 31

SL28504

Byte 5: Control Register 5 (continued)

Bit

@Pup

Name

Description

1

0

CR#_D_EN

Enable CR#_D (clk req)

0 = Disabled, 1 = Enabled

0

CR#_D_SEL

Set CR#_D SRC1 or SRC4

0 = CR#_DSRC1, 1 = CR#_DSRC4

Byte 6: Control Register 6

Bit

@Pup

Name

Description

7

0

CR#_E_EN

Enable CR#_E (clk req)  SRC6

0 = Disabled, 1 = Enabled

6

5

4

0

CR#_F_EN

CR#_G_EN

CR#_H_EN

Enable CR#_F (clk req)  SRC8

0 = Disabled, 1 = Enabled

Enable CR#_G (clk req)  SRC9

0 = Disabled, 1 = Enabled

Enable CR#_H (clk req)  SRC10

0 = Disabled, 1 = Enabled

3

2

1

0

Reserved

SRC_STP_CTRL

Allows control of SRC with assertion of PCI_STOP#

0 = Free running SRC 1 = Stopped with PCI_STOP#

Byte 7: Vendor ID

Bit

7

@Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

0

1

0

Rev Code Bit 3

Rev Code Bit 2

Rev Code Bit 1

Rev Code Bit 0

Vendor ID bit 3

Vendor ID bit 2

Vendor ID bit 1

Vendor ID bit 0

6

5

4

3

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

Byte 8: Control Register 8

Bit

7

@Pup

Name

Description

0

1

Device_ID3

Device_ID2

Device_ID1

Device_ID0

0000 = 56-TSSOP

0001 = 64-TSSOP

0010 = Reserved

0011 = 56-QFN

6

5

0100 = 64-QFN

0101 = Reserved

0110 = Reserved

0111 = 56-SSOP

1000 = Reserved

1001 = Reserved

1010 = Reserved

1011 = Reserved

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

4

...................... DOC #: SP-AP-0052 (Rev. AA) Page 10 of 31

SL28504

Byte 8: Control Register 8 (continued)

Bit

3

@Pup

Name

Reserved

25M0_F_OE

Description

0

1

Reserved

2

Reserved

1

Output enable for 25M0_F

0 = Output Disabled, 1 = Output Enabled

0

1

25M1_24.576M_OE

Output enable for 25M1_24.576M

0 = Output Disabled, 1 = Output Enabled

Byte 9: Control Register 9

Bit

@Pup

Name

Description

7

0

PCIF5_STP_CTRL

Allows control of PCIF5 with assertion of PCI_STOP#

0 = Free running PCIF, 1 = Stopped with PCI_STOP#

6

5

0

1

Reserved

REF Bit1

Reserved

REF drive strength Setting 1 of 3 (see Byte 13 and 14 for more settings)

0 = Low, 1 = High

4

3

0

TEST _MODE_SEL

Test mode select either REF/N or tri-state

0 = All outputs tri-state, 1 = All output REF/N

TEST_MODE_ENTRY

Allows entry into test mode

0 = Normal Operation, 1 = Enter test mode(s)

2

1

0

1

0

1

12C_VOUT<2>

12C_VOUT<1>

12C_VOUT<0>

I2C_VOUT[2:0]

000 = 0.30V

001 = 0.40V

010 = 0.50V

011 = 060V

100 = 0.70V

101 = 0.80V (default)

110 = 0.90V

111 = 1.00V

Byte 10: Control Register 10

Bit

@Pup

Name

Description

7

HW

SRC5_EN

SRC5_EN latche status

0= CPU_STP#/PCI_STP#; 1= SRC5

6

5

4

3

2

1

0

1

Reserved

CPU1_STP_CTRL

Enable CPU_STOP# control of CPU1

0 = Free running, 1= Stoppable

0

1

CPU0_STP_CTRL

Enable CPU_STOP# control of CPU0

0 = Free running, 1= Stoppable

Byte 11: Control Register 11

Bit

7

@Pup

Name

Description

0

1

Reserved

25M0_F

Reserved

6

5

25M0_F Output Enabled applies to Powerdown / M1

0 = 25MHz disabled in Powerdown / M1

1 = 25MHz enabled in Powerdown / M1; Sticky 1

...................... DOC #: SP-AP-0052 (Rev. AA) Page 11 of 31

SL28504

Byte 11: Control Register 11 (continued)

4

3

2

0

1

Reserved

CPU2_iAMT_EN

CPU1_iAMT_EN

PCIF5/ITP_EN

AMT_EN

CPU2_AMT_EN CPU1_AMT_EN

Description

x

1

0

1

0

1

0

1

Reserved

CPU1 = M1 Clock

CPU2 - M1 Clock

CPU1 and CPU2 = M1 Clock

1

0

1

Reserved

CPU2_STP_CRTL

Allow control of CPU2 with assertion of CPU_STOP#

0 = Free running, 1 = Stopped with CPU_STOP#

Byte 12: Byte Count

Bit

7

@Pup

Name

Reserved

BC5

Description

0

1

0

1

Reserved

Byte count

6

5

4

BC4

3

BC3

2

BC2

1

BC1

0

BC0

Byte 13: Control Register 13

Bit

7

@Pup

Name

Description

0

1

0

1

0

PCIF/PCI Bit 2

PCIF/PCI Bit 1

PCIF/PCI Bit 0

USB Bit 2

Drive Strength Control - Bit[2:0]

Note: REF Bit 1 is located in Byte 9 Bit 5

6

5

Buffer

Strength

Bit 2

(Various Bytes)

Bit 1

Bit 0

(Various Bytes) (Various Bytes)

4

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Strongest

3

USB Bit 1

2

USB Bit 0

1

REF Bit 2

0

REF Bit 0

Default

Weakest

Byte 14: Control Register 14

Bit

@Pup

Name

Description

7

0

SE1/SE2 Bit 2

SE1/SE2 Bit 2 drive strength

0 = Low, 1 = High

6

5

1

0

SE1/SE2 Bit 1

SE1/SE2 Bit 0

SE1/SE2 Bit 1 drive strength

0 = Low, 1 = High

SE1/SE2 Bit 0 drive strength

0 = Low, 1 = High

4

3

0

RESERVED

...................... DOC #: SP-AP-0052 (Rev. AA) Page 12 of 31

SL28504

Bit

@Pup

Name

Description

Enable SATA spread modulation,

0 = Spread Disabled, 1 = Spread Enabled

2

1

SATA_SS_EN

1

0

1

EN_CFG0_SET

SW_PCI

By defalult CFG0 pin strap sets the SMBus initial values to select the HW

mode. When this bit is written0, subsequent SMBus accesses is the Lathes

Open state, can overwrite the CFG0 pin setting into the SMBus bits and set

the mode before the M0 state: specifically B0b2, B1b[6,4,3], B9b1, B11b5

SW PCI_STP# Function

0 = SW PCI_STP assert, 1 = SW PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are

stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are

resumed in a synchronous manner with no short pulses.

Byte 15: Control Register 15

Bit

7

@Pup

Name

Description

0

CPU_DAF_N7

CPU_DAF_N6

CPU_DAF_N5

CPU_DAF_N4

CPU_DAF_N3

CPU_DAF_N2

CPU_DAF_N1

CPU_DAF_N0

If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and

CPU_DAF_M[6:0] are used to determine the CPU output frequency.

6

5

4

3

2

1

0

Byte 16: Control Register 16

Bit

7

@Pup

Name

Description

0

CPU_DAF_N8

CPU_DAF_M6

CPU_DAF_M5

CPU_DAF_M4

CPU_DAF_M3

CPU_DAF_M2

CPU_DAF_M1

CPU_DAF_M0

See Byte 14 for description

6

If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and

CPU_DAF_M[6:0] are used to determine the CPU output frequency.

5

4

3

2

1

0

Byte 17: Control Register 17

Bit

7

@Pup

Name

Description

PCI-E Dial-A-Frequency^®Bit N7

PCI-E Dial-A-Frequency Bit N6

PCI-E Dial-A-Frequency Bit N5

PCI-E Dial-A-Frequency Bit N4

PCI-E Dial-A-Frequency Bit N3

PCI-E Dial-A-Frequency Bit N2

PCI-E Dial-A-Frequency Bit N1

PCI-E Dial-A-Frequency Bit N0

0

PCI-E_N7

PCI-E_N6

PCI-E_N5

PCI-E_N4

PCI-E_N3

PCI-E_N2

PCI-E_N1

PCI-E_N0

6

5

4

3

2

1

0

...................... DOC #: SP-AP-0052 (Rev. AA) Page 13 of 31

SL28504

Byte 18: Control Register 18

Bit

@Pup

Name

Description

7

0

SMSW_EN

Enable Smooth Switching

0 = Disabled, 1= Enabled

6

5

4

0

SMSW_SEL

Prog_PCI-E_EN

Prog_CPU_EN

Smooth switch select

0 = CPU_PLL, 1 = SRC_PLL

Programmable PCI-E frequency enable

0 = Disabled, 1= Enabled

Programmable CPU frequency enable

0 = Disabled, 1= Enabled

3

2

1

0

RESERVED

Table 4. Crystal Recommendations

Frequency

Drive

(max.)

Shunt Cap Motional

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

(Fund)

Cut

Loading Load Cap

(max.)

14.31818 MHz

AT

Parallel 20 pF

0.1 mW

5 pF

0.016 pF

35 ppm

30 ppm

5 ppm

The SL28504 requires a Parallel Resonance Crystal. Substi-

tuting a series resonance crystal causes the SL28504 to

operate at the wrong frequency and violates the ppm specifi-

cation. For most applications there is a 300-ppm frequency

shift between series and parallel crystals due to incorrect

loading

crystal loading correctly. Again, the capacitance on each side

is in series with the crystal. The total capacitance on both side

is twice the specified crystal load capacitance (CL). Trim

capacitors are calculated to provide equal capacitive loading

on both sides.

Crystal Loading

C lo ck C h ip

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, use the total capac-

itance the crystal sees to calculate the appropriate capacitive

loading (CL).

C i2

C i1

P in

3 to 6 p

Figure 1 shows a typical crystal configuration using the two

trim capacitors. It is important that the trim capacitors are in

series with the crystal. It is not true that load capacitors are in

parallel with the crystal and are approximately equal to the

load capacitance of the crystal.

X 2

X 1

C s2

C s1

T ra ce

2 .8 p F

X T A L

C e 1

C e 2

T rim

3 3 p F

Figure 2. Crystal Loading Example

,

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

Load Capacitance (each side)

Ce = 2 * CL – (Cs + Ci)

Figure 1. Crystal Capacitive Clarification

Total Capacitance (as seen by the crystal)

Calculating Load Capacitors

1

CLe

=

1

(

)

In addition to the standard external trim capacitors, consider

the trace capacitance and pin capacitance to calculate the

+

Ce2 + Cs2 + Ci2

Ce1 + Cs1 + Ci1

...................... DOC #: SP-AP-0052 (Rev. AA) Page 14 of 31

SL28504

CL ................................................... Crystal load capacitance

CLe .........................................Actual loading seen by crystal

using standard value trim capacitors

Smooth Switching

The device contains one smooth switch circuit that is shared

by the CPU PLL and SRC PLL. The smooth switch circuit

ensures that when the output frequency changes by

overclocking, the transition from the old frequency to the new

frequency is a slow, smooth transition containing no glitches.

The rate of change of output frequency when using the smooth

switch circuit is less than 1 MHz/0.667 s. The frequency

overshoot and undershoot is less than 2%.

Ce .....................................................External trim capacitors

Cs ............................................. Stray capacitance (terraced)

Ci .......................................................... Internal capacitance

(lead frame, bond wires, etc.)

Dial-A-Frequency^®(CPU and PCIEX)

The Smooth Switch circuit assigns auto or manual. In Auto

mode, clock generator assigns smooth switch automatically

when the PLL does overclocking. For manual mode, assign

the smooth switch circuit to PLL via Smbus. By default the

smooth switch circuit is set to auto mode. PLL can be

over-clocked when it does not have control of the smooth

switch circuit but it is not guaranteed to transition to the new

frequency without large frequency glitches.

This feature allows the user to over-clock their system by

slowly stepping up the CPU or SRC frequency. When the

programmable output frequency feature is enabled, the CPU

and SRC frequencies are determined by the following

equation:

Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.

Do not enable over-clocking and change the N values of both

PLLs in the same SMBUS block write and use smooth switch

mechanism on spread spectrum on/off.

• “N” and “M” are the values programmed in Programmable

Frequency Select N-Value Register and M-Value Register,

respectively.

• “G” stands for the PLL Gear Constant, which is determined

by the programmed value of FS[E:A]. See Table ,

Frequency Select Table for the Gear Constant for each

Frequency selection. The PCI Express only allows user

control of the N register, the M value is fixed and

documented in Table , Frequency Select Table.

PD_RESTORE

If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#

LOW, the SL28504 initiates a full reset. The result of this is that

the clock chip emulates a cold power on start and goes to the

“Latches Open” state. If the PD_RESTORE bit is set to a ‘1’

then the configuration is stored upon PWRDWN# asserted

LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then

the PD_RESTORE bit must be ignored. In other words, in Intel

iAMT mode, PWRDWN# reset is not allowed.

In this mode, the user writes the desired N and M values into

the DAF I2C registers. The user cannot change only the M

value and must change both the M and the N values at the

same time, if they require a change to the M value. The user

may change only the N value.

PWRDWN# (Power down) Clarification

The CKPWRGD/PWRDWN# pin is a dual-function pin. During

initial power up, the pin functions as CKPWRGD. Once

CKPWRGD has been sampled HIGH by the clock chip, the pin

assumes PD# functionality. The PD# pin is an asynchronous

active LOW input used to shut off all clocks cleanly before

shutting off power to the device. This signal is synchronized

internally to the device before powering down the clock

synthesizer. PD# is also an asynchronous input for powering

up the system. When PD# is asserted LOW, clocks are driven

to a LOW value and held before turning off the VCOs and the

crystal oscillator.

Associated Register Bits

• CPU_DAF Enable – This bit enables CPU DAF mode. By

default, it is not set. When set, the operating frequency is

determined by the values entered into the CPU_DAF_N

register. Note that the CPU_DAF_N and M register must

contain valid values before CPU_DAF is set. Default = 0,

(No DAF).

• CPU_DAF_N – There are nine bits (for 512 values) to

linearly change the CPU frequency (limited by VCO range).

Default = 0, (0000). The allowable values for N are detailed

in Table , Frequency Select Table.

PWRDWN# (Power down) Assertion

• CPU DAF M – There are 7 bits (for 128 values) to linearly

change the CPU frequency (limited by VCO range). Default

= 0, the allowable values for M are detailed in Table ,

Frequency Select Table

When PD is sampled HIGH by two consecutive rising edges

of CPUC, all single-ended outputs will be held LOW on their

next HIGH-to-LOW transition and differential clocks must held

LOW. When PD mode is desired as the initial power on state,

PD must be asserted HIGH in less than 10 s after asserting

CKPWRGD.

• SRC_DAF Enable – This bit enables SRC DAF mode. By

default, it is not set. When set, the operating frequency is

determined by the values entered into the SRC_DAF_N

register. Note that the SRC_DAF_N register must contain

valid values before SRC_DAF is set. Default = 0, (No DAF).

PWRDWN# Deassertion

The power up latency is less than 1.8 ms. This is the time from

the deassertion of the PD# pin or the ramping of the power

supply until the time that stable clocks are generated from the

clock chip. All differential outputs stopped in a three-state

condition, resulting from power down are driven high in less

than 300 s of PD# deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs are enabled within a few clock cycles of

• SRC_DAF_N – There are nine bits (for 512 values) to

linearly change the CPU frequency (limited by VCO range).

Default = 0, (0000). The allowable values for N are detailed

in Table , Frequency Select Table.

...................... DOC #: SP-AP-0052 (Rev. AA) Page 15 of 31

SL28504

each clock. Figure 4 is an example showing the relationship of

clocks coming up.

PD#

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33 MHz

REF

Figure 3. Power down Assertion Timing Waveform

Ts table

<1.8 ms

PD#

CP UT , 133MHz

CP UC, 133MHz

S RCT 100MHz

S RCC 100MHz

US B , 48MHz

DOT 96T

DOT 96C

P CI, 33MHz

REF

Tdriv e_PW R D N #

<300 s , >200m V

Figure 4. Power down Deassertion Timing Waveform

...................... DOC #: SP-AP-0052 (Rev. AA) Page 16 of 31

SL28504

Figure 5. CK_PWRGD Timing Diagram

...................... DOC #: SP-AP-0052 (Rev. AA) Page 17 of 31

SL28504

CPU_STP# Assertion

CPU_STP# Deassertion

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configuration to be stoppable are stopped

within two to six CPU clock periods after sampled by two rising

edges of the internal CPUC clock. The final states of the

stopped CPU signals are CPUT = HIGH and CPUC = LOW.

The deassertion of the CPU_STP# signal causes all stopped

CPU outputs to resume normal operation in a synchronous

manner. No short or stretched clock pulses are produced when

the clock resumes. The maximum latency from the

deassertion to active outputs is no more than two CPU clock

cycles.

CPU_STP#

CPUT

CPUC

Figure 6. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

CPUC Internal

Tdrive_CPU_STP#,10 ns>200 mV

Figure 7. CPU_STP# Deassertion Waveform

1.8 ms

CPU_STOP#

PD#

CPUT(Free Running

CPUC(Free Running

CPUT(Stoppable)

CPUC(Stoppable)

DOT96T

DOT96C

Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven

...................... DOC #: SP-AP-0052 (Rev. AA) Page 18 of 31

SL28504

1.8 ms

CPU_STOP#

PD#

CPUT(Free Running)

CPUC(Free Running)

CPUT(Stoppable)

CPUC(Stoppable)

DOT96T

DOT96C

Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state

.

PCI_STP# Assertion

The PCI_STP# signal is an active LOW input used for

synchronously stopping and starting the PCI outputs while the

rest of the clock generator continues to function. The set-up

time for capturing PCI_STP# going LOW is 10 ns (t_SU). (See

Figure 10.) The PCIF clocks are affected by this pin if their

corresponding control bit in the SMBus register is set to allow

them to be free running.

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 10. PCI_STP# Assertion Waveform

PCI_STP# Deassertion

.

The deassertion of the PCI_STP# signal causes all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods, after PCI_STP# transi-

tions to a HIGH level.

Tdrive_SRC

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 11. PCI_STP# Deassertion Waveform

...................... DOC #: SP-AP-0052 (Rev. AA) Page 19 of 31

SL28504

.

Table 5. Output Driver Status during PCI-STOP# and CPU-STOP#

PCI_STOP# Asserted

CPU_STOP# Asserted

Running

SMBus OE Disabled

Single-ended Clocks Stoppable

Non stoppable

Stoppable

Driven low

Running

Differential Clocks

Clock driven high

Clock# driven low

Running

Clock driven high

Clock# driven low

Running

Clock driven Low or 20K

pulldown

Non stoppable

Table 6. Output Driver Status

All Differential Clocks except

CPU1

All Single-ended Clocks

w/o Strap w/ Strap

Low Hi-z

CPU1

Clock

Clock#

Clock

Clock#

Latches Open State

Powerdown

M1

Low or 20K pulldown Low

Low

Hi-z

Running

.

Figure 12. Clock Generator Power up/Run State Diagram

...................... DOC #: SP-AP-0052 (Rev. AA) Page 20 of 31

SL28504

C l o c k O f f t o M1

3.3V

Vcc

2.0V

T_delay t

FSC

FSB

FSA

CPU_STOP#

PCI_STOP#

CKPWRGD/PWRDWN

CK505 SMBUS

CK505 State

Off

Latches Open

Off

M1

BSEL[0..2]

Off

CK505 Core Logic

PLL1

Locked

CPU1

PLL2 & PLL3

All Other Clocks

REF Oscillator

T_delay2

T_delay3

Figure 13. BSEL Serial Latching

...................... DOC #: SP-AP-0052 (Rev. AA) Page 21 of 31

SL28504

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Analog Supply Voltage

IO Supply Voltage

Input Voltage

Condition

Min.

Max.

4.6

1.5

4.6

150

85

Unit

V

–

V_{DD_A}

V_{DD_IO}

V_IN

V

Relative to V_SS

Non-functional

Functional

–0.5

–65

-40

V_DC

°C

T_S

Temperature, Storage

T_A

Temperature, Operating

Ambient

T_J

Temperature, Junction

Functional

–

150

20

°C

Ø_JC

Dissipation, Junction to Case Mil-STD-883E Method 1012.1

°C/

W

Ø_JA

Dissipation, Junction to Ambient JEDEC (JESD 51)

–

60

–

°C/

W

ESD_HBM

ESD Protection (Human Body MIL-STD-883, Method 3015

Model)

2000

V

UL-94

MSL

Flammability Rating

At 1/8 in.

V–0

1

Moisture Sensitivity Level

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter

VDD core

Description

Condition

Min.

3.135

2.0

Max.

3.465

V_DD+ 0.3

0.8

Unit

3.3V Operating Voltage

3.3V Input High Voltage (SE)

3.3V Input Low Voltage (SE)

Input High Voltage

3.3 ± 5%

V

V_IH

V_IL

V_SS– 0.3

2.2

V

V_IHI2C

V_ILI2C

V_{IH_FS}

V_{IL_FS}

V_{IHFS_C_TEST}

SDATA, SCLK

–

V

Input Low Voltage

–

1.0

V

FS_[A,B] Input High Voltage

FS_[A,B] Input Low Voltage

FS_C, Input High Voltage

0.7

1.5

V

V_SS– 0.3

2

0.35

V_DD+ 0.3

1.5

V

V_{IMFS_C_NORMAL}FS_C, Input Middle Voltage

V_{ILFS_C_NORMAL}FS_C, Input Low Voltage

0.7

V

V_SS– 0.3

–

0.35

5

V

I_IH

SEL_24.576M_{_HI}SEL_24.576M Input High

Voltage

SEL_24.576M_{_MI}SEL_24.576M Input Mid

Voltage

SEL_24.576M_{_LO}SEL_24.576M Input Low

Input High Leakage Current

Except internal pull-down resistors, 0 < V_IN< V_DD

Typ. 2.75V

A

V

2.40

VDD

GH

Typ. 1.65V

1.30

0

2.00

V

D

Typ. 0.550V

0.900

Voltage

W

I_IL

Input Low Leakage Current

Except internal pull-up resistors, 0 < V_IN< V_DD

–5

2.4

–

A

V

V_OH

V_OL

3.3V Output High Voltage (SE) I_OH= –1 mA

3.3V Output Low Voltage (SE) I_OL= 1 mA

Low Voltage IO Supply Voltage

0.4

V

V_{DD IO}

V_OH

V_OL

1

3.465

0.90

0.40

10

3.3V Input High Voltage (DIFF)

0.70

V

3.3V Input Low Voltage (DIFF)

I_OZ

High-impedance Output

Current

–10

1.5

A

C_IN

Input Pin Capacitance

Output Pin Capacitance

5

6

pF

C_OUT

...................... DOC #: SP-AP-0052 (Rev. AA) Page 22 of 31

SL28504

DC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

7

Unit

L_IN

Pin Inductance

–

nH

V

V_XIH

Xin High Voltage

Xin Low Voltage

0.7V_DD

V_DD

0.3V_DD

250

V_XIL

0

–

V

I_DD3.3V

Dynamic Supply Current

mA

...................... DOC #: SP-AP-0052 (Rev. AA) Page 23 of 31

SL28504

AC Electrical Specifications

Parameter

Crystal

T_DC

Description

Condition

Min.

Max.

Unit

XIN Duty Cycle

XIN Period

The device operates reliably with input

dutycyclesupto30/70buttheREFclock

duty cycle will not be within specification

47.5

52.5

%

T_PERIOD

When XIN is driven from an external

clock source

69.841

71.0

ns

T_R/T_F

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Measured between 0.3V_DDand 0.7V_DD

–

10.0

500

ns

ps

T_CCJ

As an average over 1-s duration

CPU at 0.7V

T_DC

45

55

CPUT and CPUC Duty Cycle

Measured at 0V differential at 0.1s

%

ns

9.99900

7.49925

5.99940

4.99950

3.74963

2.99970

2.49975

10.0100

7.50075

6.00060

5.00050

3.75038

3.00030

2.50025

T_PERIOD

T_PERIODSS

T_PERIODAbs

100 MHz CPUT and CPUC Period

133 MHz CPUT and CPUC Period

166 MHz CPUT and CPUC Period

200 MHz CPUT and CPUC Period

266 MHz CPUT and CPUC Period

333 MHz CPUT and CPUC Period

400 MHz CPUT and CPUC Period

10.02406 10.02607

100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

166 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

200 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

266 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

333 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

400 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

7.51804

6.01444

5.01203

3.75902

3.00722

2.50601

9.91400

7.51955

6.01564

5.01303

3.75978

3.00782

2.50652

10.0860

100 MHz CPUT and CPUC Absolute

period

Measured at 0V differential at 1 clock

Measured at 0V differential @ 1 clock

7.41425

5.91440

4.91450

3.66463

2.91470

2.41475

9.91406

7.41430

5.91444

4.91453

3.66465

7.58575

6.08560

5.08550

3.83538

3.08530

2.58525

10.1362

7.62340

6.11572

5.11060

3.85420

T_PERIODAbs

133 MHz CPUT and CPUC Absolute

period

ns

166 MHz CPUT and CPUC Absolute

period

200 MHz CPUT and CPUC Absolute

period

266 MHz CPUT and CPUC Absolute

period

333 MHz CPUT and CPUC Absolute

period

400 MHz CPUT and CPUC Absolute

period

T_PERIODSSAbs100 MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs133 MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs166 MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs200 MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs266 MHz CPUT and CPUC Absolute

period, SSC

...................... DOC #: SP-AP-0052 (Rev. AA) Page 24 of 31

SL28504

AC Electrical Specifications (continued)

Parameter

Description

Condition

Min.

Max.

Unit

2.91472

3.10036

T_PERIODSSAbs333 MHz CPUT and CPUC Absolute

period, SSC

Measured at 0V differential @ 1 clock

ns

2.41477

2.59780

T_PERIODSSAbs400 MHz CPUT and CPUC Absolute

period, SSC

Measured at 0V differential @ 1 clock

ns

T_CCJ

CPU Cycle to Cycle Jitter

CPU2_ITP Cycle to Cycle Jitter

Long-term Accuracy

Measured at 0V differential

–

85

125

100

150

8

ps

T_CCJ2

Measured at 0V differential

L_ACC

Measured at 0V differential

–

ppm

ps

T_SKEW

T_SKEW2

T_R/ T_F

T_RFM

CPU0 to CPU1 Clock Skew

CPU2_ITP to CPU0 Clock Skew

CPU Rising/Falling Slew rate

Rise/Fall Matching

Measured at 0V differential

–

Measured at 0V differential

–

ps

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

2.5

–

V/ns

%

20

V_HIGH

Voltage High

1.15

–

V

V_LOW

Voltage Low

–0.3

300

V

V_OX

Crossing Point Voltage at 0.7V Swing

550

mV

SRC at 0.7V

T_DC

SRC Duty Cycle

Measured at 0V differential

45

55

%

ns

9.99900

10.0010

T_PERIOD

T_PERIODSS

T_PERIODAbs

100 MHz SRC Period

Measured at 0V differential @ 0.1s

Measured at 0V differential @ 1 clock

10.02406 10.02607

100 MHz SRC Period, SSC

100 MHz SRC Absolute Period

9.87400

9.87406

–

10.1260

10.1762

3.0

T_PERIODSSAbs100 MHz SRC Absolute Period, SSC

T_SKEW(window)Any SRC Clock Skew from the earliest Measured at 0V differential

bank to the latest bank

T_CCJ

SRC Cycle to Cycle Jitter

SRC Long Term Accuracy

SRC Rising/Falling Slew Rate

Rise/Fall Matching

Measured at 0V differential

–

125

100

8

ps

ppm

V/ns

%

L_ACC

Measured at 0V differential

T_R/ T_F

T_RFM

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

2.5

–

20

V_HIGH

V_LOW

V_OX

Voltage High

1.15

–

V

Voltage Low

–0.3

300

V

Crossing Point Voltage at 0.7V Swing

550

mV

DOT96 at 0.7V

T_DC

DOT96 Duty Cycle

Measured at 0V differential

45

55

10.4177

10.6677

250

100

8

%

ns

ps

ppm

V/ns

%

10.4156

T_PERIOD

T_PERIODAbs

T_CCJ

DOT96 Period

Measured at 0V differential at 0.1s

Measured at 0V differential at 1 clock

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

10.1656

DOT96 Absolute Period

DOT96 Cycle to Cycle Jitter

DOT96 Long Term Accuracy

DOT96 Rising/Falling Slew Rate

Rise/Fall Matching

–

L_ACC

T_R/ T_F

T_RFM

2.5

–

20

V_HIGH

V_LOW

V_OX

Voltage High

1.15

–

V

Voltage Low

–0.3

300

–

V

Crossing Point Voltage at 0.7V Swing

Rise/Fall Matching

550

20

mV

%

T_RFM

Measured single-endedly from ±75 mV

V_HIGH

V_LOW

V_OX

Voltage High

1.15

–

V

Voltage Low

–0.3

300

V

Crossing Point Voltage at 0.7V Swing

550

mV

PCI/PCIF at 3.3V

...................... DOC #: SP-AP-0052 (Rev. AA) Page 25 of 31

SL28504

AC Electrical Specifications (continued)

Parameter

T_DC

Description

PCI Duty Cycle

Condition

Measurement at 1.5V

Min.

Max.

Unit

%

45

55

29.99700 30.00300

30.08421 30.23459

29.49700 30.50300

29.56617 30.58421

T_PERIOD

Spread Disabled PCIF/PCI Period

Spread Enabled PCIF/PCI Period

Spread Disabled PCIF/PCI Period

Measurement at 1.5V

ns

T_PERIODSS

T_PERIODAbs

ns

T_PERIODSSAbsSpread Enabled PCIF/PCI Period

ns

T_HIGH

T_LOW

T_HIGH

Spread Enabled PCIF and PCI high time Measurement at 2V

Spread Enabled PCIF and PCI low time Measurement at 0.8V

12.27095 16.27995 ns

11.87095 16.07995 ns

12.27365 16.27665 ns

Spread Disabled PCIF and PCI high

time

Measurement at 2.V

T_LOW

Spread Disabled PCIF and PCI low time Measurement at 0.8V

11.87365 16.07665 ns

T_R/ T_F

T_SKEW

T_CCJ

PCIF/PCI Rising/Falling Slew Rate

Measured between 0.8V and 2.0V

1.0

–

4.0

1000

500

100

V/ns

ps

Any PCI clock to Any PCI clock Skew Measurement at 1.5V

PCIF and PCI Cycle to Cycle Jitter

PCIF/PCI Long Term Accuracy

Measurement at 1.5V

–

ps

L_ACC

–

ppm

48_M at 3.3V

T_DC

Duty Cycle

Measurement at 1.5V

Measurement at 2V

45

55

%

ns

20.83125 20.83542

20.48125 21.18542

8.216563 11.15198

7.816563 10.95198

T_PERIOD

T_PERIODAbs

T_HIGH

T_LOW

Period

Absolute Period

48_M High time

ns

48_M Low time

Measurement at 0.8V

Measured between 0.8V and 2.0V

Measurement at 1.5V

ns

T_R/ T_F

T_CCJ

Rising and Falling Edge Rate

Cycle to Cycle Jitter

48M Long Term Accuracy

1.0

–

2.0

350

100

V/ns

ps

L_ACC

–

ppm

25_M

Measurement at 1.5V

45

39.996

1.0

55

40.004

4.0

%

ns

T_DC

Duty Cycle

Measurement at 1.5V

T_PERIOD

T_R/T_F

Period

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

Rising and Falling Edge Rate

Cycle to Cycle Jitter

25M Long Term Accuracy

–

500

T_CCJ

Measurement at 1.5V

–

50

ppm

L_ACC

1394A - 24.576M

Measurement at 1.5V

45

40.686

1.0

55

40.694

4.0

%

ns

T_DC

Duty Cycle

Measurement at 1.5V

T_PERIOD

T_R/T_F

T_CCJ

Period

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

Rising and Falling Edge Rate

Cycle to Cycle Jitter

24M Long Term Accuracy

–

200

Measurement at 1.5V

–30

30

ppm

L_ACC

REF

T_DC

REF Duty Cycle

Measurement at 1.5V

Measurement at 2V

45

55

%

ns

69.82033 69.86224

68.83429 70.84826

29.97543 38.46654

29.57543 38.26654

T_PERIOD

T_PERIODAbs

T_HIGH

T_LOW

REF Period

ns

REF Absolute Period

REF High time

ns

Measurement at 0.8V

Measured between 0.8V and 2.0V

Measurement at 1.5V

ns

REF Low time

T_R/ T_F

T_SKEW

T_CCJ

REF Rising and Falling Edge Rate

REF Clock to REF Clock

REF Cycle to Cycle Jitter

1.0

–

4.0

500

V/ns

ps

–

1000

ps

...................... DOC #: SP-AP-0052 (Rev. AA) Page 26 of 31

SL28504

AC Electrical Specifications (continued)

Parameter

L_ACC

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SSStopclock Set-up Time

Description

Condition

Measurement at 1.5V

Min.

Max.

Unit

Long Term Accuracy

–

100

ppm

–

1.8

–

ms

ns

10.0

Test and Measurement Set-up

For PCI Single-ended Signals and Reference

The following diagram shows the test load configurations for

the single-ended PCI, USB, and REF output signals.

Measurement

Point

22

L1

L2

50

4 pF

L1 = 0.5", L2 = 8"

22

PCI/USB

Measurement

Point

50

L2

L1

Figure 14. Single-ended PCI and USB Double Load Configuration

Measurement

15

L2

L1

Point

50

4 pF

Measurement

Point

4 pF

15

L1

L2

REF

50

Measurement

Point

4 pF

L2

50

Figure 15. Single-ended REF Triple Load Configuration

Figure 16. Single-ended Output Signals (for AC Parameters Measurement)

For CPU, SRC, and DOT96 Signals and Reference

This diagram shows the test load configuration for the differential CPU and SRC outputs

...................... DOC #: SP-AP-0052 (Rev. AA) Page 27 of 31

SL28504

Figure 17. 0.7V Differential Load Configuration

Clock Period (Differential)

Positive Duty Cycle (Differential)

Negative Duty Cycle (Differential)

0.0V

Clck-Clck#

Rise

Edge

Rate

Fall

Edge

Rate

VIH = +150V

0.0V

VIH = +150V

0.0V

VIL = -150V

Clock-Clock#

Figure 18. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)

V _M

=

1 .1 5 V

V _M

=

A X

1 .1 5 V

A X

C L K #

V c ro s s _M

V c r o s s _M

=

5 5 0 m V

3 0 0 m V

V c r o s s _M

=

5 5 0 m V

3 0 0 m V

A X

IN

=

IN

C L K

V _M

=

0 .3 0 V

V _M

=

IN

0 .3 0 V

IN

C L K #

V c r o s s d e lta

= 1 4 0 m V

V c r o s s d e lta

=

1 4 0 m V

C L K #

V c r o s s m e d ia n + 7 5 m V

V c r o s s m e d ia n

V c r o s s m e d ia n - 7 5 m V

C L K

Figure 19. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)

...................... DOC #: SP-AP-0052 (Rev. AA) Page 28 of 31

SL28504

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

SL28504BZC

SL28504BZCT

SL28504BZI

64-pin TSSOP

Commercial, 0 to 85C

Industrial, -40 to 85C

64-pin TSSOP–Tape and Reel

64-pin TSSOP

SL28504BZIT

64-pin TSSOP–Tape and Reel

Packaging Designator for Tape and Reel

SL

B

28 504 Z C T

Temperature Designator

C : Commercial spec; I: Industrial spec

Package Designator

Z: TSSOP; L: QFN

Revision Number

A = 1^strevision; B = 2^ndrevision......

Generic Part Number

Designated Family Number

Company Initials

Package Diagrams

64-Lead Thin Shrunk Small Outline Package (6 mm x 17 mm) Z64

...................... DOC #: SP-AP-0052 (Rev. AA) Page 29 of 31

SL28504

Package Diagrams

...................... DOC #: SP-AP-0052 (Rev. AA) Page 30 of 31

SL28504

Document History Page

Document Title: SL28504 Clock Generator for Intel^Eaglelake Chipset

Orig. of

REV.

1.0

ECR#

Issue Date Change

Description of Change

10/5/07

10/19/07

01/21/08

BSHEN Initial Release

1.1

BSHEN Add SRC1 to pin 17/18. and tri-level trigger at 24.576M

1.2

BSHEN 1. Change Revision ID Byte7[7:4] to be 0001

2. Updated block diagram

3. Change Byte10[6:2] and Byte11[4] to be reserved

1.3

1.4

05/26/09

06/24/09

BSHEN 1. Update TSSOP64 package dimension to compliant to SLI-POD spec

BSHEN 1. Correct the pin out with CLK request pin

2. Correct the CLK request register

3. Remove QFN package,

AA

1576

04/28/10

BSHEN 1. Updated Industrial ordering information

2. Correct VDD_IO pin description

3. Updated document format for ISO compliance.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-

icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the

use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or

parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-

sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-

cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

...................... DOC #: SP-AP-0052 (Rev. AA) Page 31 of 31


型号：	SL28504BZC
厂家：	SILICON
描述：	Clock Generator for Intelï Eaglelake Chipset
文件：	总31页 (文件大小：246K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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