SL28610 [SILICON]
Low Power Clock Generator for Intel® Ultra Mobile Platform;型号: | SL28610 |
厂家: | SILICON |
描述: | Low Power Clock Generator for Intel® Ultra Mobile Platform |
文件: | 总23页 (文件大小:277K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SL28610
Low Power Clock Generator for Intel® Ultra Mobile Platform
Features
• Supports intel's Moorestown and Menlow clocking
requirements
• Compliant to Intel® CK610
• Buffered Reference Clock 14.318MHz
• 14.318 MHz Crystal Input or Clock Input
• Low-voltage frequency select input
• I2C support with readback capabilities
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Integrated resistors on differential clocks
• Differential CPU clocks with selectable frequency
• 100MHz Differential PCIe clocks
• Industrial Temperature -40°C to 85°C
• 48-pin QFN package
• 100MHz LCD Video Clock
• 96MHz Differential DOT clock
CPU
x3
PCIe DOT96 LCD
x3 x 1 x1
REF
x 1
Block Diagram
Pin Configuration
* 100K-ohm Internal pull down
** 10K-ohm Internal pull-up
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 1 of 23
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500 1+(512) 416-9669
www.silabs.com
SL28610
Pin Definitions
Pin No.
Name
CPU_STP#
Type
Description
1
2
3
4
5
6
I, SE 3.3V input for CPU_STP# (active low) functionality
I, SE 3.3V LVTTL input (active low)
CKPWRGD#/PD
XOUT
O, SE 3.3V, 14.31818MHz crystal output (When used a clock input, float XOUT)
I, SE 3.3V, 14.31818MHz crystal input, 3.3V Clock Input.
XIN/CLKIN
VDD3.3V
PWR 3.3V power supply for single-ended clock
REF / PCIe_SEL
IO, PD, 3.3V, 14.31818MHz output / 1.5V input active high signal latched on CKPWRGD#
SE
signal to select PCIe from PLL3 (share with LCD PLL; 100K-ohm internal pull-down)
7
VSS
GND Ground
8
VDD1.5_CORE
FSC
PWR 1.5V power supply for core
I, SE 1.05V Frequency Select C
9
10
TEST_MODE
I, SE 3.3V-tolerant input to selects Ref/N or Tri-state when in test mode.
0 = Tri-state, 1 = Ref/N
11
TEST_SEL
I, SE 3.3V-tolerant input to selects TEST_SEL
0 = Normal, 1 = Test Entry
12
13
14
15
16
17
18
19
20
21
22
23
24
SCLK
I, SE 3.3V SMBus Clock Line
SDATA
I/O, SE 3.3V SMBus Data Line
VDD1.5_CORE
VDD1.5_IO
DOT96#
DOT96
PWR 1.5V power supply for core
PWR 1.5V power supply for differential outputs
O, DIFF Fixed complimentary 96MHz clock output
O, DIFF Fixed true 96MHz clock output
GND Ground
VSS
VSS
GND Ground
LCD_SSC#
LCD_SSC
VDD1.5_IO
VDD1.5_CORE
OE_0#
O, DIF Complementary 100MHz Differential clock
O, DIF True 100MHz Differential clock
PWR 1.5V power supply for differential outputs
PWR 1.5V power supply for core
I, SE Output enable for PCIe0, (10K-ohm internal pull-up)
0 =enable, 1=disable
25
26
27
28
VSS
GND Ground
PCIe0#
PCIe0
OE_1#
O, DIF Complementary 100MHz Differential clock
O, DIF True 100MHz Differential clock
I, SE Output enable for PCIe1, (10K-ohm internal pull-up)
0 =enable, 1=disable
29
30
31
32
33
34
35
36
VDD1.5_CORE
VDD1.5_IO
PCIe1#
PWR 1.5V Power Supply for core
PWR 1.5V Power Supply for differential output
O, DIF Complementary 100MHz Differential clock
O, DIF True 100MHz Differential clock
GND Ground
PCIe1
VSS
PCIe2#
O, DIF Complementary 100MHz Differential clock
O, DIF True 100MHz Differential clock
PCIe2
OE_2#
I, SE Output enable for PCIe2, (10K-ohm internal pull-up)
0 =enable, 1=disable
37
38
39
FSB
I, SE 1.05V Frequency Select B
CPU0#
CPU0
O, DIF Complementary Host Differential clock
O, DIF True Host Differential clock
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 2 of 23
SL28610
Pin Definitions (continued)
Pin No.
40
Name
Type
Description
VSS
GND Ground
41
VDD1.5_IO
VDD1.5_CORE
CPU1#
PWR 1.5V Power Supply for differential output
PWR 1.5V Power Supply for core
42
43
O, DIF Complementary Host Differential clock
O, DIF True Host Differential clock
44
CPU1
45
VSS_CPU
VDD1.5_IO
CPU2#
GND Ground
46
PWR 1.5V Power Supply for differential output
O, DIF Complementary Host Differential clock
O, DIF True Host Differential clock
47
48
CPU2
Table 1. Frequency Select Pin (FSB and FSC)
FSC
FSB
CPU
PCIe
LCD
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
REF
1
0
0
1
0
0
1
1
100 MHz
133 MHz
166 MHz
200 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Frequency Select Pin (FSB and FSC)
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Apply the appropriate logic levels to FSB and FSC inputs
before CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled LOW on CKPWRGD
and indicates that VTT voltage is stable then FSB and FSC
input values are sampled. This process employs a one-shot
functionality and once the CKPWRGD sampled a valid LOW,
all other FSB, FSC, and CKPWRGD transitions are ignored
except in test mode.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
their default setting at power-up. The use of this interface is
.
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
18:11
19
18:11
19
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 3 of 23
SL28610
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Description
Bit
Description
Bit
27:20
Byte Count–8 bits
20
Repeat start
(Skip this step if I2C_EN bit set)
Acknowledge from slave
Data byte 1–8 bits
28
36:29
37
27:21
28
Slave address–7 bits
Read = 1
Acknowledge from slave
Data byte 2–8 bits
29
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
45:38
46
37:30
38
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
....
46:39
47
Data byte 1 from slave–8 bits
Acknowledge
....
....
Acknowledge from slave
Stop
55:48
56
Data byte 2 from slave–8 bits
Acknowledge
....
....
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
....
....
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 4 of 23
SL28610
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
PLL1_EN
PLL1 Enable
0 = Disabled, 1 = Enabled
6
5
1
1
PLL2_EN
PLL3_EN
PLL2 Enable
0 = Disabled, 1 = Enabled
PLL3 Enable
0 = Disabled, 1 = Enabled
4
3
0
1
RESERVED
CPU_DIV
RESERVED
CPU Output Divider Enable
0 = Disabled, 1 = Enabled
2
1
0
1
1
1
PCIe_DIV
LCD_DIV
PCIe Output Divider Enable
0 = Disabled, 1 = Enabled
LCD Output Divider Enable
0 = Disabled, 1 = Enabled
DOT96_DIV
DOT96 Output Divider Enable
0 = Disabled, 1 = Enabled
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PLL1_Spread _EN
PLL1 Spread Enable
0 = Disabled, 1 = Enabled
6
1
PLL3_Spread _EN
PLL3 Spread Enable
0 = Disabled, 1 = Enabled
5
4
3
0
0
0
PLL3_CFB2
PLL3_CFB1
PLL3_CFB0
PLL3 Spread Spectrum Select
PLL3_CFB[2:0]
000 = -%0.5 (Down Spread) - Default
001 = -%1.0, DS
010 = -%1.5, DS
011 = -% 2.0, DS
100 = %+0.30 (Center Spread)
101 = %+0.50, CS
110 = %+1.00, CS
111 = %+1.25, CS
2
1
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
CPU0_OE
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
6
5
4
3
1
1
1
1
CPU1_OE
CPU2_OE
PCIe0_OE
PCIe1_OE
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
Output enable for CPU2
0 = Output Disabled, 1 = Output Enabled
Output enable for PCIe0
0 = Output Disabled, 1 = Output Enabled
Output enable for PCIe1
0 = Output Disabled, 1 = Output Enabled
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 5 of 23
SL28610
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
2
1
PCIe2_OE
Output enable for SCR2
0 = Output Disabled, 1 = Output Enabled
1
0
1
1
DOT96_OE
LCD_OE
Output enable for DOT96
0 = Output Disabled, 1 = Output Enabled
Output enable for LCD
0 = Output Disabled, 1 = Output Enabled
Byte 3: Control Register 3
Bit
7
@Pup
Name
Description
RESERVED
1
1
1
RESERVED
RESERVED
REF_OE
6
RESERVED
5
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
4
1
REF_Bit1
REF Slew Rate Control Bit2(see Byte 16 Bit [7:6] for Slew Rate REF_Bit0 & REF_Bit2)
0 = 1 load, 1 = 2 loads
3
2
0
0
RESERVED
CPU0_STP#
RESERVED
CPU0 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
1
0
0
0
CPU1_STP#
CPU2_STP#
CPU1 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
CPU2 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
Byte 4: Control Register 4
Bit
7
@Pup
HW
HW
HW
HW
HW
HW
HW
HW
Name
Description
PLL1 M DIV 7
PLL1 M DIV 6
PLL1 M DIV 5
PLL1 M DIV 4
PLL1 M DIV 3
PLL1 M DIV 2
PLL1 M DIV 1
PLL1 M DIV 0
This is a read only register of the multiplier used for PLL1 M Divider
HW= Read Only
6
5
4
3
2
1
0
Byte 5: Control Register 5
Bit
7
@Pup
HW
HW
HW
HW
HW
HW
HW
HW
Name
Description
PLL1 N DIV 7
PLL1 N DIV 6
PLL1 N DIV 5
PLL1 N DIV 4
PLL1 N DIV 3
PLL1 N DIV 2
PLL1 N DIV 1
PLL1 N DIV 0
This is a read only register of the multiplier used for PLL1 N Divider
HW= Read Only
6
5
4
3
2
1
0
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 6 of 23
SL28610
Byte 6: Control Register 6
Bit
7
@Pup
HW
HW
HW
HW
HW
HW
HW
HW
Name
Description
PLL2 N DIV 8
PLL2 N DIV 9
PLL2 M DIV 5
PLL2 M DIV 4
PLL2 M DIV 3
PLL2 M DIV 2
PLL2 M DIV 1
PLL2 M DIV 0
This is a read only register of the multiplier used for PLL2 M and N Dividers
HW= Read Only
6
5
4
3
2
1
0
Byte 7: Control Register 7
Bit
7
@Pup
HW
HW
HW
HW
HW
HW
HW
HW
Name
Description
PLL2 N DIV 7
PLL2 N DIV 6
PLL2 N DIV 5
PLL2 N DIV 4
PLL2 N DIV 3
PLL2 N DIV 2
PLL2 N DIV 1
PLL2 N DIV 0
This is a read only register of the multiplier used for PLL2 N Divider
HW= Read Only
6
5
4
3
2
1
0
Byte 8: Control Register 8
Bit
7
@Pup
HW
HW
HW
HW
HW
HW
HW
HW
Name
Description
PLL3 M DIV 7
PLL3 M DIV 6
PLL3 M DIV 5
PLL3 M DIV 4
PLL3 M DIV 3
PLL3 M DIV 2
PLL3 M DIV 1
PLL3 M DIV 0
This is a read only register of the multiplier used for PLL3 M Divider
HW= Read Only
6
5
4
3
2
1
0
Byte 9: Control Register 9
Bit
7
@Pup
HW
HW
HW
HW
HW
HW
HW
HW
Name
Description
PLL3 N DIV 7
PLL3 N DIV 6
PLL3 N DIV 5
PLL3 N DIV 4
PLL3 N DIV 3
PLL3 N DIV 2
PLL3 N DIV 1
PLL3 N DIV 0
This is a read only register of the multiplier used for PLL3 N Divider
HW= Read Only
6
5
4
3
2
1
0
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 7 of 23
SL28610
Byte 10: Control Register 10
Bit
7
@Pup
HW
Name
FSB
Description
FSB status bit, CPU Frequency Select Bit, read only
FSC status bit, CPU Frequency Select Bit, read only
6
HW
FSC
5
HW
OE#_0
OE#_0 status bit, PCIe0 enable status, read only
0 = PCIe0 disabled, 1 = PCIe0 enabled
4
3
HW
HW
OE#_1
OE#_2
OE#_0 status bit, PCIe1 enable status, read only
0 = PCIe1 disabled, 1 = PCIe1 enabled
OE#_0 status bit, PCIe2 enable status, read only
0 = PCIe2 disabled, 1 = PCIe2 enabled
2
1
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Byte 11: Control Register 11
Bit
7
@Pup
Name
Description
Vendor ID Bit 3
1
0
0
0
0
0
0
1
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
6
Vendor ID Bit 2
5
Vendor ID Bit 1
4
Vendor ID Bit 0
3
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
2
1
0
Byte 12: Byte Count 12
Bit
7
@Pup
Name
Description
1
0
1
0
Device_ID3
Device_ID2
Device_ID1
Device_ID0
0000 = Reserved
0001 = Reserved
0010 = Reserved
0011 = Reserved
0100 = Reserved
0101 = Reserved
6
5
4
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = Reserved
1010 = CK610 Yellow Cover Device, 48-pin QFN
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
7
2
1
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 8 of 23
SL28610
Byte 13: Control Register 13
Bit
7
@Pup
Name
Description
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
5
4
3
2
1
0
Byte 14: Control Register 14
Bit
7
@Pup
Name
Description
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
5
4
7
2
1
0
Byte 15: Control Register 15
Bit
7
@Pup
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Description
0
0
0
1
0
1
1
0
Byte count 7
Byte count 6
Byte count 5
Byte count 4
Byte count 3
Byte count 2
Byte count 1
Byte count 0
6
5
4
3
2
1
0
Byte 16: Control Register 16
Bit
7
@Pup
Name
Description
0
1
REF_Bit2
REF_Bit0
REF Slew Rate Control Bit2 & Bit0 (see Byte 3 Bit 4 for Slew Rate REF_Bit1)
6
5:0
0
RESERVED
RESERVED
........................DOC #: SP-AP-0078 (Rev. 1.0) Page 9 of 23
SL28610
Byte 17: Control Register 17
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
PLL1_DAF_N7
PLL1_DAF_N6
PLL1_DAF_N5
PLL1_DAF_N4
PLL1_DAF_N3
PLL1_DAF_N2
PLL1_DAF_N1
PLL1_DAF_N0
If Prog_PLL1_EN is set, the values programmed in PLL1_DAF_N[7:0] and
PLL1_DAF_M[7:0] are used to determine the PLL1 output frequency.
6
5
4
7
2
1
0
Byte 18: Control Register 18
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
PLL1_DAF_M7
PLL1_DAF_M6
PLL1_DAF_M5
PLL1_DAF_M4
PLL1_DAF_M3
PLL1_DAF_M2
PLL1_DAF_M1
PLL1_DAF_M0
If Prog_PLL1_EN is set, the values programmed in PLL1_DAF_N[7:0] and
PLL1_DAF_M[7:0] are used to determine the PLL1 output frequency.
6
5
4
7
2
1
0
Byte 19: Control Register 19
Bit
7
@Pup
Name
Description
RESERVED
RESERVED
0
0
0
RESERVED
RESERVED
Prog_PLL1_EN
6
5
Programmable PLL1 frequency enable
0 = Disabled, 1= Enabled
4
3
0
0
Prog_PLL3_EN
Programmable PLL3 frequency enable
0 = Disabled, 1= Enabled
CPU_OEB_DRIVE _Mode Controls CPU Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
2
1
0
0
0
0
PCIe_OEB_DRIVE _Mode Controls PCIe Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
LVDS_OEB_DRIVE _Mode Controls LVDS Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
DOT_OEB_DRIVE _Mode Controls DOT Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 10 of 23
SL28610
Byte 20: Control Register 20
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
PLL3_DAF_N7
PLL3_DAF_N6
PLL3_DAF_N5
PLL3_DAF_N4
PLL3_DAF_N3
PLL3_DAF_N2
PLL3_DAF_N1
PLL3_DAF_N0
If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and
PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.
6
5
4
7
2
1
0
Byte 21: Control Register 21
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
PLL3_DAF_M7
PLL3_DAF_M6
PLL3_DAF_M5
PLL3_DAF_M4
PLL3_DAF_M3
PLL3_DAF_M2
PLL3_DAF_M1
PLL3_DAF_M0
If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and
PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.
6
5
4
7
2
1
0
next HIGH-to-LOW transition and differential clocks must held
CKPWRGD#/PD (Power down) Clarification
HIGH. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
The CKPWRGD#/PD pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD#. Once
CKPWRGD# has been sampled HIGH by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD is also an asynchronous input for powering up
the system. When PD is asserted HIGH, clocks are driven to
a LOW value and held before turning off the VCOs and the
crystal oscillator.
CKPWRGD#/PD (Power Down) Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
CKPWRGD#/PD (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held HIGH on their
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 11 of 23
SL28610
Figure 1. Power down Assertion Timing Waveform
Figure 2. Power down Deassertion Timing Waveform
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 12 of 23
SL28610
Figure 3. CKPWRGD# Timing Diagram
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 13 of 23
SL28610
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 5. CPU_STP# Deassertion Waveform
.
.
Table 1. Output Driver Status during PCI_STPPCI_STP# and CPU_STP#
CPU_STP# Asserted SMBus Disabled OE# Pins Disabled
Running
Single-ended Clocks Stoppable
Non stoppable
Stoppable
Driven low
Driven low
Running
Differential Clocks
Clock driven high
Clock# driven low
Running
Clock driven high*
Clock# driven low*
Driven Low
Non stoppable
Note: *Differential clocks output state can be configured through Byte 19 bits 3:.0
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 14 of 23
SL28610
Absolute Maximum Conditions
Parameter
3.3V_VDD
1.5V_VDD_CORE 1.5V Supply Voltage
Description
Condition
Min.
–0.5
–0.5
–0.5
–0.5
–65
0
Max.
4.6
2.1
2.1
4.6
150
85
Unit
V
3.3V Supply Voltage
Functional
Functional
V
1.5V_VDD_IO
DIFF I/O Supply Voltage
Input Voltage
Functional
V
VIN
TS
TA
Relative to VSS
Non-functional
Functional
VDC
°C
°C
Temperature, Storage
Commercial Temperature,
Operating Ambient
Industrial Temperature, Operating
Ambient
-40
+85
°C
TJ
Temperature, Junction
Functional
–
–
150
20
60
–
°C
°C/W
°C/W
V
ØJC
Dissipation, Junction to Case
Dissipation, Junction to Ambient
JEDEC (JESD 51)
ØJA
JEDEC (JESD 51)
–
ESDHBM
ESD Protection (Human Body
Model)
JEDEC (JESD 22-A114)
2000
UL-94
Flammability Rating
UL (CLASS)
V–0
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
Min.
1.425
1.425
Max.
1.575
1.575
Unit
V
1.5V_VDD_CORE 1.5V Operating Voltage
1.5V ± 5%
1.5V ± 5%
1.5V_VDD_IO
1.5V Differential I/O Supply
Voltage
V
3.3V_VDD
3.3V_VIH
3.3V_VIL
VIHI2C
VILI2C
VIH_FS
VIL_FS
VIH
3.3V Operating Voltage
3.3V Input High Voltage (SE)
3.3V Input Low Voltage (SE)
Input High Voltage
3.3 ± 5%
3.135
3.465
V
V
3.3V_VDD
2
VSS – 0.3
2.2
3.3V_CORE+ 0.3
0.8
V
SDATA, SCLK
SDATA, SCLK
1.05V_CORE
–
V
Input Low Voltage
–
1.0
V
FS_[C,B] Input High Voltage
FS_[C,B] Input Low Voltage
OE# Input High Voltage
OE# Input Low Voltage
0.9
1.5V_CORE + 0.3
V
GND-0.3
1.2
0.25
V
1.5V_CORE
1.5V_CORE + 0.3
V
VIL
GND-0.3
2.0
0.3
VDD+0.3
0.8
V
VIH
PCIe_SEL Input High Voltage 3.3V_CORE
PCIe_SEL Input Low Voltage
V
VIL
GND-0.3
–
V
IIH
Input High Leakage Current
Except internal pull-down resistors,
0 < VIN < VDD
5
A
IIL
Input Low Leakage Current
Except internal pull-up resistors, 0
< VIN < VDD
–5
–
A
VOH
VOL
3.3V Output High Voltage (SE) IOH = –1 mA
3.3V Output Low Voltage (SE) IOL = 1 mA
Low Voltage IO Supply Voltage
2.4
–
–
V
V
0.4
0.88
10
VDD IO
IOZ
0.72
–10
High-impedance Output
Current
A
CIN
Input Pin Capacitance
1.5
5
pF
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 15 of 23
SL28610
DC Electrical Specifications (continued)
Parameter
COUT
Description
Output Pin Capacitance
Pin Inductance
Condition
Min.
Max.
Unit
pF
6
LIN
–
7
nH
V
VXIH
VXIL
Power
Xin High Voltage
0.7VDD
VDD
Xin Low Voltage
0
–
0.3VDD
100
V
Power Consumption
mW
AC Electrical Specifications
Parameter
Crystal
TDC
Description
Condition
Min.
Max.
Unit
XIN Duty Cycle
XIN Period
The device operates reliably with input
dutycyclesupto30/70buttheREFclock
duty cycle will not be within specification
47.5
52.5
71.0
%
TPERIOD
When XIN is driven from an external
clock source
69.841
ns
TR/TF
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Long-term Accuracy
Measured between 0.3VDD and 0.7VDD
As an average over 1-s duration
Measured at VDD/2 differential
–
–
–
10.0
500
250
ns
ps
TCCJ
LACC
ppm
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
0.5
–
53
4.0
%
V/ns
ps
TR/TF
CLKIN Rise and Fall Times
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input Low Voltage
Measured between 0.2VDD and 0.8VDD
Measured at VDD/2
TCCJ
250
TLTJ
Measured at VDD/2
–
350
ps
VIL
XIN / CLKIN pin
–
0.8
V
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
20
V
IIL
Input LowCurrent
XIN / CLKIN pin, 0 < VIN <0.8
XIN / CLKIN pin, VIN = VDD
–
uA
uA
IIH
Input HighCurrent
–
35
CPU at 0.7V
TDC
CPU Clock Duty Cycle
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured at 0V differential at1 clock
Measured at 0V differential at 1 clock
45
55
%
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
100 MHz CPU Clock Period
9.997001 10.00300 ns
7.497751 7.587251 ns
5.998201 6.001801 ns
133 MHz CPU Clock Period
166 MHz CPU Clock Period
200 MHz CPU Clock Period
4.99950
5.00050
ns
100 MHz CPU Clock Period, SSC
133 MHz CPU Clock Period, SSC
166 MHz CPU Clock Period, SSC
200 MHz CPU Clock Period, SSC
100 MHz CPU Clock Absolute period
133 MHz CPU Clock Absolute period
166 MHz CPU Clock Absolute period
200 MHz CPU Clock Absolute period
9.997001 10.05327 ns
7.412751 7.624950 ns
5.998201 6.031960 ns
5.01203
5.01303
ns
9.912001 10.08800 ns
7.412751 7.587251 ns
5.913201 6.086801 ns
4.91450
5.08550
ns
TPERIODSSAbs 100 MHz CPU Clock Absolute period, Measured at 0V differential at1 clock
SSC
9.912001 10.13827 ns
TPERIODSSAbs 133 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
7.412751 7.624950 ns
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 16 of 23
SL28610
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
TPERIODSSAbs 166 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
5.913201 6.116960 ns
200 MHz CPU Clock Absolute period,
SSC
Measured at 0V differential at 1 clock
4.91453
5.11060
ns
TPERIODSSAbs
TCCJ
CPUT/C Cycle to Cycle Jitter
Measured at 0V differential
–
–
85
300
2800
100
4
ps
ppm
ppm
ps
LACC_non-SSC Long-term Accuracy
Measured at 0V differential
LACC_SSC
TSKEW
TR / TF
TRFM
Long-term Accuracy
Measured at 0V differential
–
Pin-to-pin Skew
Measured at 0V differential
–
CPU Clock Rise and Fall Time
Rise/Fall Matching
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
Measured single-endedly
0.6
–
V/ns
%
20
Vabs
Absolute Min and Max VSWING
–0.3
300
1.15V
550
140
V
VOX
Crossing Point Voltage at 0.7V Swing Measured single-endedly
mV
mV
V
Vox_variation Crossing Point Variation
Measured single-endedly
Measured single-endedly
VOVS
Maximum Voltage (Overshoot)
VHIGH+
0.3V
VUDS
Maximum Voltage (Undershoot)
Ring back voltage
Measured single-endedly
Measured single-endedly
Measured single-endedly
0.3
-100
500
V
VRB
100
mV
ps
TSTABLE
PCIe at 0.7V
TDC
Time before VRB
PCIe Clock Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
TPERIODSS
TPERIODAbs
100 MHz PCIe Clock Period
100 MHz PCIe Clock Period, SSC
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
9.997001 10.0030
ns
9.997001 10.05327 ns
9.912001 10.08800 ns
9.912001 10.13827 ns
100 MHz PCIe Clock Absolute Period Measured at 0V differential at 1 clock
TPERIODSSAbs 100 MHz PCIePCIe Clock Absolute
Period, SSC
Measured at 0V differential at 1 clock
TCCJ
PCIe Clock Cycle to Cycle Jitter
Measured at 0V differential
–
–
125
300
2800
100
4
ps
ppm
ppm
ps
LACC_non-SSC Long-term Accuracy
Measured at 0V differential
LACC_SSC
TSKEW
TR / TF
TRFM
Long-term Accuracy
Measured at 0V differential
–
Pin-to-pin Skew
Measured at 0V differential
–
PCIe Clock Rise and Fall Time
Rise/Fall Matching
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
Measured single-endedly
0.6
–
V/ns
%
20
Vabs
Absolute Min and Max VSWING
–0.3
300
1.15V
550
140
V
VOX
Crossing Point Voltage at 0.7V Swing Measured single-endedly
mV
mV
V
Vox_variation Crossing Point Variation
Measured single-endedly
Measured single-endedly
VOVS
Maximum Voltage (Overshoot)
VHIGH+
0.3V
VUDS
Maximum Voltage (Undershoot)
Ring back voltage
Measured single-endedly
Measured single-endedly
Measured single-endedly
0.3
-100
500
V
VRB
100
55
mV
ps
TSTABLE
DOT96 at 0.7V
TDC
Time before VRB
DOT96 Clock Duty Cycle
Measured at 0V differential
45
%
TPERIOD
TPERIODAbs
TCCJ
DOT96 Clock Period
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
10.41354 10.41979 ns
10.16354 10.66979 ns
DOT96 Clock Absolute Period
DOT96 Clock Cycle to Cycle Jitter
DOT96 Clock Long Term Accuracy
–
–
250
300
ps
LACC
ppm
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 17 of 23
SL28610
AC Electrical Specifications (continued)
Parameter
TSKEW
Description
Pin-to-pin Skew
Condition
Min.
–
Max.
100
4
Unit
ps
Measured at 0V differential
TR / TF
TRFM
Vabs
DOT96 Clock Rise and Fall Time
Rise/Fall Matching
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
Measured single-endedly
0.6
–
V/ns
%
20
Absolute Min and Max VSWING
–0.3
300
1.15V
550
140
V
VOX
Crossing Point Voltage at 0.7V Swing Measured single-endedly
mV
mV
V
Vox_variation Crossing Point Variation
Measured single-endedly
Measured single-endedly
VOVS
Maximum Voltage (Overshoot)
VHIGH+
0.3V
VUDS
Maximum Voltage (Undershoot)
Ring back voltage
Measured single-endedly
Measured single-endedly
Measured single-endedly
0.3
-100
500
V
VRB
100
mV
ps
TSTABLE
Time before VRB
LCD_100_SSC at 0.7V
TDC
SSC Clock Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
TPERIODSS
TPERIODAbs
100 MHz SSC Clock Period
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
9.997001 10.0030
ns
100 MHz SSC Clock Period, SSC
100 MHz SSC Clock Absolute Period
9.997001 10.05327 ns
9.912001 10.08800 ns
9.912001 10.13827 ns
TPERIODSSAbs 100 MHz SSC Clock Absolute Period, Measured at 0V differential at 1 clock
SSC
TCCJ
LACC
TSKEW
TR / TF
TRFM
Vabs
SSC Clock Cycle to Cycle Jitter
SSC Clock Long Term Accuracy
Pin-to-pin Skew
Measured at 0V differential
–
–
250
300
100
4
ps
ppm
ps
Measured at 0V differential
Measured at 0V differential
–
SSC Clock Rise and Fall Time
Rise/Fall Matching
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
Measured single-endedly
0.6
–
V/ns
%
20
Absolute Min and Max VSWING
–0.3
300
1.15V
550
140
V
VOX
Crossing Point Voltage at 0.7V Swing Measured single-endedly
mV
mV
V
Vox_variation Crossing Point Variation
Measured single-endedly
Measured single-endedly
VOVS
Maximum Voltage (Overshoot)
VHIGH+
0.3V
VUDS
Maximum Voltage (Undershoot)
Ring back voltage
Measured single-endedly
Measured single-endedly
Measured single-endedly
0.3
-100
500
V
VRB
100
55
mV
ps
TSTABLE
REF
Time before VRB
TDC
REF Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
Measured single-endedly
Measurement at 1.5V
45
%
TPERIOD
TPERIODAbs
TR / TF
TSKEW
TCCJ
REF Period
69.82033 69.86224 ns
68.82033 70.86224 ns
REF Absolute Period
REF Rising and Falling Edge Rate
REF Clock to REF Clock
REF Cycle to Cycle Jitter
Clock High /Low Time
Long Term Accuracy
1.0
–
4.0
500
1000
39
V/ns
ps
–
ps
THIGH/LOSW
LACC
32
–
95
ppm
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS Stopclock Set-up Time
–
1.8
–
ms
ns
10.0
1
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 18 of 23
SL28610
Test and Measurement Set-up
For Single-ended Reference Clock
The following diagram shows the load configurations for the single-ended REF output signals.
Figure 6. Single-ended REF Load Configuration
Figure 7. Single-ended Output Signals (for AC Parameters Measurement)
For CPU, PCIe, and DOT96 Signals and Reference
This diagram shows the test load configuration for the differential CPU and PCIe outputs
Figure 8. 0.7V Differential Load Configuration
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 19 of 23
SL28610
Clock Period (Differential)
Positive Duty Cycle (Differential)
Negative Duty Cycle (Differential)
0.0V
0.0V
Clock-Clock#
Rise
Edge
Rate
Fall
Edge
Rate
VIH = +150mV
0.0V
VIH = +150mV
0.0V
VIL = -150mV
VIL = -150mV
Clock-Clock#
Figure 9. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
VMAX = 1.15V
VMAX = 1.15V
CLK#
VcrossMAX = 550mV
VcrossMIN = 300mV
VcrossMAX = 550mV
VcrossMIN = 300mV
CLK
VMIN = 0.30V
VMIN = 0.30V
CLK#
Vcross delta = 140mV
Vcross delta = 140mV
CLK
CLK#
CLK#
Vcross median +75mV
Vcross median
Vcross median
Vcross median -75mV
CLK
CLK
Figure 10. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 20 of 23
SL28610
Ordering Information
Part Number
Lead-free
Package Type
Product Flow
SL28610BLC
SL28610BLI
48-pin QFN
48-pin QFN
Commerial, 0 to 85C
Industrial, -40 to 85C
This device is Pb free and RoHS compliant.
SL 28 610 B L C -T
Packaging Designator for Tape and Reel
Temperature Designator
Package Designator
L : QFN
Revision Number
A = 1st Silicon
Generic Part Number
Designated Family Number
Company Initials
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 21 of 23
SL28610
Package Diagrams
48-Lead QFN 6 x 6mm LF48A
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 22 of 23
SL28610
Document History Page
Document Title: SL28610 PC Low Power Clock Generator for Intel® Ultra Mobile Platform
DOC #: SP-AP-0078 (Rev. 1.0)
Orig. of
REV.
1.0
ECR#
Issue Date Change
Description of Change
09/15/08
10/12/09
JMA
JMA
New Datasheet
1.1
1. Renamed PWRGD# to CKPWRGD#
2. Updated block diagram to show differential outputs
3. Updated miscellaneous text contents
AA
AA
AA
1633
1801
1801
05/27/10
09/23/10
10/1/10
JMA
TRP
TRP
1. Updated to be ISO compliant
2. Added Clock input feature
3. Updated MIL-STD to JEDEC
1. Updates VIL_FS
2. Updated miscellaneous text and format contents
3. Removed crystal recommendations
1. Added clock feature
2. Updated block diagram
3. Updated SRC clock as PCIe
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
......................DOC #: SP-AP-0078 (Rev. 1.0) Page 23 of 23
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