SL28PCIE26ALIT_技术文档

SL28PCIe26

EProClock^®PCI Express Gen 2 & Gen 3 Generator

• EProClock^®Programmable Technology

• I²C support with readback capabilities

Features

• Optimized 100 MHz Operating Frequencies to Meet the

Next Generation PCI-Express Gen 2 & Gen 3

• Triangular Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Low power push-pull type differential output buffers

• Integrated voltage regulator

• 25MHz Crystal Input or Clock input

• Industrial Temperature -40^oC to 85^oC

• 3.3V Power supply

• Integrated resistors on differential clocks

• Four 100-MHz differential PCI-Express clocks

• Low jitter (<50pS)

• 32-pin QFN package

Block Diagram

Pin Configuration

DOC#: SP-AP-0774 (Rev. 0.2)

Page 1 of 14

400 West Cesar Chavez, Austin, TX 78701

1+(512) 416-8500 1+(512) 416-9669

www.silabs.com

SL28PCIe26

32-QFN Pin Definitions

PinNo.

1

Name

Type

Description

VDD

VSS

PWR 3.3V Power Supply

GND Ground

2

3

NC

No Connect.

4

NC

5

VDD

NC

PWR 3.3V Power Supply

6

NC

No Connect.

7

NC

8

VSS

GND Ground

9

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SRC0

SRC0#

VSS

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complement differential serial reference clock

GND Ground

SRC1

SRC1#

VDD

NC

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complement differential serial reference clock

PWR 3.3V Power Supply

NC

No Connect.

VDD

SRC2#

SRC2

VSS

PWR 3.3V Power Supply

O, DIF 100MHz Complement differential serial reference clock

O, DIF 100MHz True differential serial reference clock

GND Ground

SRC3#

SRC3

VDD

O, DIF 100MHz Complement differential serial reference clock

O, DIF 100MHz True differential serial reference clock

PWR 3.3V Power Supply

CKPWRGD/PD#

VSS

I

3.3V LVTTT input pin. When PD# is asserted low, the device will power down.

GND Ground

XOUT

O, SE 25MHz Crystal output, Float XOUT if using CLKIN (Clock Input)

XIN/CLKIN

VDD

I

25MHz Crystal input or 3.3V, 25MHz Clock Input

PWR 3.3V Power Supply

NC

I/O

I

No Connect.

SDATA

SCLK

SMBus compatible SDATA

SMBus compatible SCLOCK

EProClock^®Programmable Technology

EProClock^®is the world’s first non-volatile programmable

clock. The EProClock^®technology allows board designer to

promptly achieve optimum compliance and clock signal

integrity; historically, attainable typically through device and/or

board redesigns.

EProClock^®technology can be configured through SMBus or

hard coded.

- Differential duty cycle control on true or compliment or both

- Differential amplitude control

- Differential slew rate control

- Program different spread profiles and modulation rates

Serial Data Interface

Features:

- > 4000 bits of configurations

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

- Can be configured through SMBus or hard coded

- Custom frequency sets

- Differential skew control on true or compliment or both

DOC#: SP-AP-0774 (Rev. 0.2)

Page 2 of 14

SL28PCIe26

their default setting at power-up. The use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

block write/read operation, access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 1.

Data Protocol

The block write and block read protocol is outlined in Table 2

while Table 3 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h).

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Description

Block Read Protocol

Description

Bit

1

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Byte Count–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Data byte 1–8 bits

27:21

28

Slave address–7 bits

Read = 1

36:29

37

Acknowledge from slave

Data byte 2–8 bits

29

Acknowledge from slave

Byte Count from slave–8 bits

Acknowledge

45:38

46

37:30

38

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N–8 bits

Acknowledge from slave

Stop

....

46:39

47

Data byte 1 from slave–8 bits

Acknowledge

....

55:48

56

Data byte 2 from slave–8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave–8 bits

NOT Acknowledge

Stop

....

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

20

DOC#: SP-AP-0774 (Rev. 0.2)

Page 3 of 14

SL28PCIe26

Table 3. Byte Read and Byte Write Protocol

28

29

Acknowledge from slave

Stop

27:21

28

Slave address–7 bits

Read

29

Acknowledge from slave

Data from slave–8 bits

NOT Acknowledge

Stop

37:30

38

39

Control Registers

Byte 0: Control Register 0

Bit

7

@Pup

Name

Description

1

0

1

0

1

RESERVED

PD_Restore

RESERVED

6

5

4

3

2

1

0

Save configuration when PD# is asserted

0 = Config. cleared, 1 = Config. saved

Byte 1: Control Register 1

Bit

7

@Pup

Name

Description

RESERVED

1

0

RESERVED

PLL1_SS_DC

6

Select for down or center SS

0 = -0.5% Down spread, 1 = +/-0.5% Center spread

5

4

3

2

1

0

1

0

1

RESERVED

Byte 2: Control Register 2

Bit

7

@Pup

Name

Description

RESERVED

1

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

Byte 3: Control Register 3

Bit @Pup

Name

Description

DOC#: SP-AP-0774 (Rev. 0.2)

Page 4 of 14

SL28PCIe26

Byte 3: Control Register 3

7

6

5

4

3

2

1

0

1

RESERVED

Byte 4: Control Register 4

Bit

7

@Pup

Name

Description

1

RESERVED

SRC0_OE

RESERVED

6

Output enable for SRC0

0 = Output Disabled, 1 = Output Enabled

5

1

SRC1_OE

Output enable for SRC1

0 = Output Disabled, 1 = Output Enabled

4

3

0

1

RESERVED

SRC3_OE

RESERVED

Output enable for SRC3

0 = Output Disabled, 1 = Output Enabled

2

1

0

1

0

1

SRC2_OE

PLL1_SS_EN

RESERVED

Output enable for SRC2

0 = Output Disabled, 1 = Output Enabled

Enable PLL1s spread modulation,

0 = Spread Disabled, 1 = Spread Enabled

RESERVED

Byte 5: Control Register 5

Bit

7

@Pup

Name

Description

RESERVED

0

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

Byte 6: Control Register 6

Bit

7

@Pup

Name

Description

RESERVED

0

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

DOC#: SP-AP-0774 (Rev. 0.2)

Page 5 of 14

SL28PCIe26

Byte 7: Vendor ID

Bit

7

@Pup

Name

Description

0

1

0

1

0

Rev Code Bit 3

Rev Code Bit 2

Rev Code Bit 1

Rev Code Bit 0

Vendor ID bit 3

Vendor ID bit 2

Vendor ID bit 1

Vendor ID bit 0

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

6

5

4

3

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

Byte 8: Control Register 8

Bit

7

@Pup

Name

Description

1

0

Device_ID3

Device_ID2

Device_ID1

Device_ID0

RESERVED

6

5

4

3

2

1

0

Byte 9: Control Register 9

Bit

7

@Pup

Name

RESERVED

Description

0

1

0

RESERVED

6

RESERVED

5

RESERVED

4

TEST _MODE_SEL

Test mode select either REF/N or tri-state

0 = All outputs tri-state, 1 = All output REF/N

3

0

TEST_MODE_ENTRY

Allows entry into test mode

0 = Normal Operation, 1 = Enter test mode(s)

2

1

0

1

0

1

I2C_VOUT<2>

I2C_VOUT<1>

I2C_VOUT<0>

Amplitude configurations differential clocks

I2C_VOUT[2:0]

000 = 0.30V

001 = 0.40V

010 = 0.50V

011 = 0.60V

100 = 0.70V

101 = 0.80V (default)

110 = 0.90V

111 = 1.00V

Byte 10: Control Register 10

Bit

7

@Pup

Name

Description

0

RESERVED

6

5

4

3

DOC#: SP-AP-0774 (Rev. 0.2)

Page 6 of 14

SL28PCIe26

Byte 10: Control Register 10

Bit

2

@Pup

Name

Description

0

1

RESERVED

1

0

Byte 11: Control Register 11

Bit

7

@Pup

Name

0

1

RESERVED

6

5

4

3

2

1

0

Byte 12: Byte Count

Bit

7

@Pup

Name

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

Description

0

1

Byte count register for block read operation.

The default value for Byte count is 15.

In order to read beyond Byte 15, the user should change the byte count

limit.to or beyond the byte that is desired to be read.

6

5

4

3

2

1

0

Byte 13: Control Register 13

Bit

7

@Pup

Name

Description

RESERVED

1

0

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

Byte 14: Control Register 14

Bit

7

@Pup

Name

Description

1

0

1

RESERVED

6

5

DOC#: SP-AP-0774 (Rev. 0.2)

Page 7 of 14

SL28PCIe26

Bit

4

@Pup

Name

OTP_4

OTP_3

OTP_2

OTP_1

OTP_0

Description

0

1

0

1

OTP_ID

Idenification for programmed device

3

2

1

0

.

PD# (Power down) Assertion

Table 4. Output Driver Status

All Differential Clocks

When PD is sampled HIGH by two consecutive rising edges

of SRCC, differential clocks must held LOW. When PD mode

is desired as the initial power on state, PD must be asserted

HIGH in less than 10 s after asserting CKPWRGD.

Clock

Clock#

PD# = 0 (Power down)

Low

PD# Deassertion

PD# (Power down) Clarification

The power up latency is less than 1.8 ms. This is the time from

the deassertion of the PD# pin or the ramping of the power

supply until the time that stable clocks are generated from the

clock chip. All differential outputs stopped in a three-state

condition, resulting from power down are driven high in less

than 300 s of PD# deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs are enabled within a few clock cycles of

each clock. Figure 2 is an example showing the relationship of

clocks coming up.

The CKPWRGD/PD# pin is a dual-function pin. During initial

power up, the pin functions as CKPWRGD. Once CKPWRGD

has been sampled HIGH by the clock chip, the pin assumes

PD# functionality. The PD# pin is an asynchronous active

LOW input used to shut off all clocks cleanly before shutting

off power to the device. This signal is synchronized internally

to the device before powering down the clock synthesizer. PD#

is also an asynchronous input for powering up the system.

When PD# is asserted LOW, clocks are driven to a LOW value

and held before turning off the VCOs and the crystal oscillator.

Figure 1. Power down Assertion Timing Waveform

Figure 2. Power down Deassertion Timing Waveform

.

DOC#: SP-AP-0774 (Rev. 0.2)

Page 8 of 14

SL28PCIe26

Absolute Maximum Conditions

Parameter

V_{DD_3.3V}

Description

Main Supply Voltage

Input Voltage

Condition

Min.

–

Max.

4.6

Unit

V

Functional

V_IN

T_S

T_A

Relative to V_SS

Non-functional

Functional

–0.5

–65

0

4.6

V_DC

°C

Temperature, Storage

150

85

Temperature, Operating

Ambient, Commercial

°C

T_A

Temperature, Operating

Ambient, Industrial

Functional

–40

85

°C

T_J

Temperature, Junction

–

150

20

Ø_JC

Dissipation, Junction to Case JEDEC (JESD 51)

°C/

W

Ø_JA

Dissipation, Junction to Ambient JEDEC (JESD 51)

–

60

–

°C/

W

ESD_HBM

UL-94

ESD Protection (Human Body JEDEC (JESD 22 - A114)

Model)

2000

V

Flammability Rating

UL (Class)

V–0

DC Electrical Specifications

Parameter

VDD core

Description

Condition

Min.

3.135

2.0

Max.

Unit

V

3.3V Operating Voltage

3.3V Input High Voltage (SE)

3.3V Input Low Voltage (SE)

Input High Voltage

3.3 ± 5%

3.465

V_IH

V_DD+ 0.3

V

V_IL

V_SS– 0.3

2.2

0.8

–

V

V_IHI2C

V_ILI2C

I_IH

SDATA, SCLK

V

Input Low Voltage

–

1.0

5

V

Input High Leakage Current

Except internal pull-down resistors, 0 < V_IN

V_DD

<

–

A

I_IL

Input Low Leakage Current

Except internal pull-up resistors, 0 < V_IN< V_DD

–5

–

A

I_OZ

High-impedance Output

Current

–10

10

C_IN

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

1.5

5

6

pF

C_OUT

L_IN

–

7

nH

mA

IDD__PD

I_{DD_3.3V}

Power Down Current

Dynamic Supply Current

1

All outputs enabled. Differential clocks with 7”

traces 2pF load.

50

DOC#: SP-AP-0774 (Rev. 0.2)

Page 9 of 14

SL28PCIe26

AC Electrical Specifications

Parameter

Crystal

L_ACC

Description

Condition

Min.

Max.

Unit

Long-term Accuracy

Measured at VDD/2 differential

–

250

ppm

Clock Input

T_DC

CLKIN Duty Cycle

Measured at VDD/2

47

0.5

–

53

4.0

%

V/ns

ps

T_R/T_F

CLKIN Rise and Fall Times

CLKIN Cycle to Cycle Jitter

CLKIN Long Term Jitter

Input High Voltage

Measured between 0.2V_DDand 0.8V_DD

Measured at VDD/2

T_CCJ

250

350

VDD+0.3

0.8

T_LTJ

Measured at VDD/2

–

ps

V_IH

XIN / CLKIN pin

2

V

V_IL

Input Low Voltage

XIN / CLKIN pin

–

V

I_IH

Input HighCurrent

XIN / CLKIN pin, VIN = VDD

XIN / CLKIN pin, 0 < VIN <0.8

–

35

uA

I_IL

Input LowCurrent

-35

–

SRC at 0.7V

T_DC

Duty Cycle

Period

Measured at 0V differential

45

55

%

ns

ps

9.99900

10.0010

T_PERIOD

T_PERIODSS

T_PERIODAbs

Measured at 0V differential at 0.1s

Measured at 0V differential at 1 clock

Measured at 0V differential

10.02406 10.02607

Period, SSC

Absolute Period

9.87400

9.87406

–

10.1260

10.1762

125

T_PERIODSSAbsAbsolute Period, SSC

T_CCJ

Cycle to Cycle Jitter

RMS_GEN1

Output PCIe* Gen1 REFCLK phase

jitter

BER = 1E-12 (including PLL BW 8 - 16

MHz, ζ = 0.54, Td=10 ns,

0

108

3.0

ps

Ftrk=1.5 MHz)

RMS_GEN2

RMS_GEN3

Output PCIe* Gen2 REFCLK phase

jitter

Includes PLL BW 8 - 16 MHz, Jitter

Peaking = 3dB, ζ = 0.54, Td=10 ns),

Low Band, F < 1.5MHz

Output PCIe* Gen2 REFCLK phase

jitter

Includes PLL BW 8 - 16 MHz, Jitter

Peaking = 3dB, ζ = 0.54, Td=10 ns),

Low Band, F < 1.5MHz

0

3.1

1.0

ps

Output phase jitter impact – PCIe*

Gen3

Includes PLL BW 2 - 4 MHz,

CDR = 10MHz)

L_ACC

T_R/ T_F

V_HIGH

V_LOW

V_OX

Long Term Accuracy

Rising/Falling Slew Rate

Voltage High

Measured at 0V differential

–

100

8

ppm

V/ns

V

Measured differentially from ±150 mV

2.5

1.15

–

Voltage Low

–0.3

300

V

Crossing Point Voltage at 0.7V Swing

550

mV

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SSStopclock Set-up Time

–

1.8

–

ms

ns

10.0

DOC#: SP-AP-0774 (Rev. 0.2)

Page 10 of 14

SL28PCIe26

Test and Measurement Set-up

For Differential Clock Signals

This diagram shows the test load configuration for the differential clock signals

Figure 3. 0.7V Differential Load Configuration

Figure 4. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)

DOC#: SP-AP-0774 (Rev. 0.2)

Page 11 of 14

SL28PCIe26

Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)

DOC#: SP-AP-0774 (Rev. 0.2)

Page 12 of 14

SL28PCIe26

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

SL28PCIe26ALC

SL28PCIe26ALCT

SL28PCIe26ALI

SL28PCIe26ALIT

32-pin QFN

Industrial, 0 to 85C

Industrial, -40 to 85C

32-pin QFN–Tape and Reel

32-pin QFN

32-pin QFN–Tape and Reel

Package Diagrams

32-Lead QFN 5x 5mm

DOC#: SP-AP-0774 (Rev. 0.2)

Page 13 of 14

SL28PCIe26

Document History Page

Document Title: SL28PCIe26 PC EProClock^®PCI Express Gen 2 & Gen 3 Generator

DOC#: SP-AP-0774 (Rev. 0.2)

Orig. of

Change

JMA

REV.

1.0

Issue Date

9/17/09

Description of Change

Initial Release

1.1

10/13/09

05/17/10

JMA

Updated miscellanous text content

AA

JMA

1. Added CLKINFeatures.

2. Updated default spread to be non-spread PCI-Express

3. Updated I2C registers

4. Updated IDD Spec

AA

10/21/10

11/17/10

TRP

Updated miscellanous text content

1. Updated IDD condition on trace lenght to 7”

2. Added spread percentage on Byte1 bit6

DOC#: SP-AP-0774 (Rev. 0.2)

Page 14 of 14

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using

or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and

"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent

of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in

weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

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Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,

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Silicon Laboratories Inc.

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Austin, TX 78701

USA

http://www.silabs.com


型号：	SL28PCIE26ALIT
厂家：	SILICON
描述：	Clock Generator, CMOS, QFN-32 时钟外围集成电路晶体
文件：	总15页 (文件大小：390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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