SL28PCIe30ALIT_技术文档

SL28PCIe30

EProClock^®Programmable PCIe Gen 2 Clock Generator

• 25MHz Crystal Input or Clock input

• EProClock^®Programmable Technology

• I²C support with readback capabilities

Features

• Compliant to PCI-Express Gen 1 and Gen 2

• Low power push-pull type differential output buffers

• Integrated resistors on differential clocks

• Triangular Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Wireless friendly 3-bits slew rate control on

single-ended clocks.

• Industrial Temperature -40^oC to 85^oC

• 3.3V Power supply

• 100MHz Differential SRC clocks

• 32-pin QFN package

• Two Programmable Single Ended clocks

• Buffered Reference Clock 25MHz

SRC

x6

25M

x1

Prog_SE

x2

Block Diagram

Pin Configuration

XIN / CLKIN

XOUT

Crystal/

CLKIN

25M

PLL 1

(SSC)

Divider

SRC [5:0]

PLL 2

(SSC)

Prog_SE1

Prog_SE2

PLL 3

(non-SSC)

Divider

EProClock^TM

Technology

SCLK

SDATA

VR

Logic Core

DOC#: SP-AP-0775 (Rev. 0.2)

400 West Cesar Chavez, Austin, TX 78701

Page 1 of 16

1+(512) 416-8500 1+(512) 416-9669

www.silabs.com

SL28PCIe30

32-QFN Pin Definitions

PinNo.

Name

Type

Description

1

2

3

VDD

PWR 3.3V Power Supply

VDD_Prog_SE2

Prog_SE2

PWR 3.3V Power Supply for Prog_SE2 clock

O, SE Programmable Single ended output with OTP programmable (EProClock^TM

)

custom frequency

4

VSS_Prog_SE2

VSS_SRC

SRC0

GND

Ground for Prog_SE2 clock

Ground for SRC clocks

5

6

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complementary differential serial reference clock

PWR 3.3V Power Supply for SRC clocks

7

SRC0#

8

VDD_SRC

SRC1

9

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complementary differential serial reference clock

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complementary differential serial reference clock

GND Ground for SRC clocks

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

SRC1#

SRC2

SRC2#

VSS_SRC

VDD_SRC

SRC3#

PWR 3.3V Power Supply for SRC clocks

O, DIF 100MHz Complementary differential serial reference clock

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complementary differential serial reference clock

O, DIF 100MHz True differential serial reference clock

PWR 3.3V Power Supply for SRC clocks

SRC3

SRC4#

SRC4

VDD_SRC

SRC5#

O, DIF 100MHz Complementary differential serial reference clock

O, DIF 100MHz True differential serial reference clock

GND Ground for SRC clocks

SRC5

VSS_SRC

SCLK

I

I/O

O

I

SMBus compatible SCLOCK

SDATA

SMBus compatible SDATA

XOUT

25.00MHz clock output. Float XOUT if using only CLKIN (Clock input)

25.00MHz Crystal input or 3.3V, 25MHz Clock input

XIN/ CLKIN

VSS_REF

25M

GND Ground for 25M clock

O

25MHz reference output clock

VDD_REF

VDD_Prog_SE1

Prog_SE1

PWR 3.3V Power Supply for 25M clock

PWR 3.3V Power Supply for Prog_SE1 clock

O, SE Programmable Single ended output with OTP programmable (EProClock^TM

custom frequency

)

32

VSS_Prog_SE1

GND Ground for Prog_SE1 clock

EProClock^®Programmable Technology

EProClock^®is the world’s first non-volatile programmable

clock. The EProClock^®technology allows board designer to

promptly achieve optimum compliance and clock signal

integrity; historically, attainable typically through device and/or

board redesigns.

EProClock^®technology can be configured through SMBus or

hard coded.

- Can be configured through SMBus or hard coded

- Custom frequency sets

- Differential skew control on true or compliment or both

- Differential duty cycle control on true or compliment or both

- Differential amplitude control

- Differential and single-ended slew rate control

Features:

- Program Internal or External series resistor on single-ended

clocks

- > 4000 bits of configurations

DOC#: SP-AP-0775 (Rev. 0.2)

Page 2 of 16

SL28PCIe30

- Program different spread profiles

Data Protocol

- Program different spread modulation rate

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 1.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

their default setting at power-up. The use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

The block write and block read protocol is outlined in Table 2

while Table 3 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h).

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Description

Block Read Protocol

Description

Bit

1

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Byte Count–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Data byte 1–8 bits

27:21

28

Slave address–7 bits

Read = 1

36:29

37

Acknowledge from slave

Data byte 2–8 bits

29

Acknowledge from slave

Byte Count from slave–8 bits

Acknowledge

45:38

46

37:30

38

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N–8 bits

Acknowledge from slave

Stop

....

46:39

47

Data byte 1 from slave–8 bits

Acknowledge

....

55:48

56

Data byte 2 from slave–8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave–8 bits

NOT Acknowledge

Stop

....

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

1

Start

1

Start

DOC#: SP-AP-0775 (Rev. 0.2)

Page 3 of 16

SL28PCIe30

Table 3. Byte Read and Byte Write Protocol

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Stop

27:21

28

Slave address–7 bits

Read

29

Acknowledge from slave

Data from slave–8 bits

NOT Acknowledge

Stop

37:30

38

39

Control Registers

Byte 0: Control Register 0

Bit

7

@Pup

Name

Description

0

RESERVED

Spread Enable

RESERVED

6

5

Enable spread for SRC[1:5] outputs

0=Disable, 1= -0.5%

4

3

2

1

0

RESERVED

Byte 1: Control Register 1

Bit

7

@Pup

Name

Description

0

1

RESERVED

SRC0_OE

RESERVED

6

Output enable for SRC0

0 = Output Disabled, 1 = Output Enabled

5

4

3

0

1

RESERVED

SRC1_OE

RESERVED

Output enable for SRC1

0 = Output Disabled, 1 = Output Enabled

2

1

0

1

0

RESERVED

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

Prog_SE2_OE

Output enable for Prog_SE2

0 = Output Disabled, 1 = Output Enabled

6

0

RESERVED

DOC#: SP-AP-0775 (Rev. 0.2)

Page 4 of 16

SL28PCIe30

Byte 2: Control Register 2 (continued)

Bit

@Pup

Name

Description

5

1

Prog_SE1_OE

Output enable for Prog_SE1

0 = Output Disabled, 1 = Output Enabled

4

1

25M_OE

Output enable for 25M

0 = Output Disabled, 1 = Output Enabled

3

2

1

0

RESERVED

Byte 3: Control Register 3

Bit

@Pup

Name

Description

7

1

SRC4_OE

Output enable for SRC4

0 = Output Disabled, 1 = Output Enabled

6

1

SRC5_OE

Output enable for SRC5

0 = Output Disabled, 1 = Output Enabled

5

4

3

2

1

0

RESERVED

Byte 4: Control Register 4

Bit

7

@Pup

Name

Description

RESERVED

0

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

Byte 5: Control Register 5

Bit

7

@Pup

Name

Description

RESERVED

0

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

0

RESERVED

DOC#: SP-AP-0775 (Rev. 0.2)

Page 5 of 16

SL28PCIe30

Byte 6: Control Register 6

Bit

7

@Pup

Name

Description

SRC[4:5] amplitude adjustment

00= 700mV, 01=800mV, 10=900mV, 11= 1000mV

0

1

0

1

SRC[4:5]_AMP

SRC[1:3]_AMP

6

5

SRC[1:3] amplitude adjustment

00= 700mV, 01=800mV, 10=900mV, 11= 1000mV

4

3

2

1

0

1

0

1

RESERVED

SRC0_AMP

RESERVED

SRC0 amplitude adjustment

00= 700mV, 01=800mV, 10=900mV, 11= 1000mV

Byte 7: Vendor ID

Bit

7

@Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

0

1

0

Rev Code Bit 3

Rev Code Bit 2

Rev Code Bit 1

Rev Code Bit 0

Vendor ID bit 3

Vendor ID bit 2

Vendor ID bit 1

Vendor ID bit 0

6

5

4

3

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

Byte 8: Control Register 8

Bit

7

@Pup

Name

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

Description

0

1

Byte count register for block read operation.

The default value for Byte count is 15

In order to read beyond Byte 15, the user should change the byte count

limit.to or beyond the byte that is desired to be read.

6

5

4

3

2

1

0

Byte 9: Control Register 9

Bit

7

@Pup

Name

Description

0

1

RESERVED

SRC3_OE

RESERVED

6

Output enable for SRC3

0 = Output Disabled, 1 = Output Enabled

5

1

SRC2_OE

Output enable for SRC2

0 = Output Disabled, 1 = Output Enabled

4

3

2

1

0

1

RESERVED

DOC#: SP-AP-0775 (Rev. 0.2)

Page 6 of 16

SL28PCIe30

Byte 10: Control Register 10

Bit

7

@Pup

Name

Description

0

RESERVED

6

5

4

3

2

1

0

Byte 11: Control Register 11

Bit

7

@Pup

Name

Description

1

0

1

0

1

Prog_SE2_Bit2

Prog_SE2_Bit1

Prog_SE2_Bit0

25M_Bit2

Drive Strength Control - Bit[2:0] Normal mode default ‘101’

Wireless Friendly Mode default to ‘111’

6

5

4

3

25M_Bit1

2

25M_Bit0

1

RESERVED

0

Byte 12: Byte Count

Bit

7

@Pup

Name

Description

1

0

1

0

1

0

Prog_SE1_Bit2

Prog_SE1_Bit1

Prog_SE1_Bit0

RESERVED

Drive Strength Control - Bit[2:0] Normal mode default ‘101’

Wireless Friendly Mode default to ‘111’

6

5

4

3

2

1

0

Byte 13: Control Register 13

Bit

7

@Pup

Name

Description

RESERVED

1

0

1

0

RESERVED

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

RESERVED

1

RESERVED

DOC#: SP-AP-0775 (Rev. 0.2)

Page 7 of 16

SL28PCIe30

0

Wireless Friendly mode Wireless Friendly Mode

0 = Disabled, Default all single-ended clocks slew rate config bits to ‘101’

1 = Enabled, Default all single-ended clocks slew rate config bits to ‘111’

Byte 14: Control Register 14

Bit

7

@Pup

Name

RESERVED

OTP_4

Description

1

0

1

0

RESERVED

6

5

4

OTP_ID

Idenification for programmed device

3

OTP_3

2

OTP_2

1

OTP_1

0

OTP_0

.

Programmable frequency clarification

Both Prog_SE1 and Prog_SE2 can be factory programmed to

any frequency as required by the end user with a 3.3V swing

single ended output. Prog_SE1 clock can have a feature of

Spread Spectrum to reduce EMI where as Prog_SE2 is an

non-spread option.

SL28PCIe30 allows flexibility of programming a frequency to

two single ended outputs - Prog_SE1 and Prog_SE2 respec-

tively.

DOC#: SP-AP-0775 (Rev. 0.2)

Page 8 of 16

SL28PCIe30

Absolute Maximum Conditions

Parameter

V_{DD_3.3V}

Description

Main Supply Voltage

Input Voltage

Condition

Min.

–

Max.

4.6

Unit

V

Functional

V_IN

T_S

T_A

Relative to V_SS

Non-functional

Functional

–0.5

–65

0

4.6

V_DC

°C

Temperature, Storage

150

85

Temperature, Operating

Ambient, Commercial

°C

T_A

Temperature, Operating

Ambient, Industrial

Functional

–40

85

°C

T_J

Temperature, Junction

–

150

20

Ø_JC

Dissipation, Junction to Case JEDEC (JESD 51)

°C/

W

Ø_JA

Dissipation, Junction to Ambient JEDEC (JESD 51)

–

60

–

°C/

W

ESD_HBM

ESD Protection (Human Body JEDEC (JESD 22 - A114)

Model)

2000

V

UL-94

Flammability Rating

UL (Class)

V–0

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter

VDD core

Description

3.3V Operating Voltage

3.3V Input High Voltage (SE)

3.3V Input Low Voltage (SE)

Input High Voltage

Condition

Min.

3.135

2.0

Max.

3.465

V_DD+ 0.3

0.8

Unit

V

3.3 ± 5%

V_IH

V

V_IL

V_SS– 0.3

2.2

V

V_IHI2C

V_ILI2C

V_{IH_FS}

V_{IL_FS}

I_IH

SDATA, SCLK

–

V

Input Low Voltage

–

1.0

V

FS Input High Voltage

FS Input Low Voltage

Input High Leakage Current

0.7

VDD+0.3

0.35

V

V_SS– 0.3

–

V

Except internal pull-down resistors, 0 < V_IN

V_DD

<

5

A

I_IL

Input Low Leakage Current

Except internal pull-up resistors, 0 < V_IN< V_DD

–5

2.4

–

A

V

V_OH

V_OL

I_OZ

3.3V Output High Voltage (SE) I_OH= –1 mA

3.3V Output Low Voltage (SE) I_OL= 1 mA

0.4

10

V

High-impedance Output

Current

–10

A

C_IN

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

1.5

5

6

pF

C_OUT

L_IN

–

7

nH

mA

I_{DD_3.3V}

Dynamic Supply Current

All outputs enabled. SE clocks with 8” traces.

Differential clocks with 7” traces.

100

DOC#: SP-AP-0775 (Rev. 0.2)

Page 9 of 16

SL28PCIe30

AC Electrical Specifications

Parameter

Crystal

L_ACC

Description

Condition

Min.

Max.

Unit

Long-term Accuracy

Measured at VDD/2 differential

–

250

ppm

Clock Input

T_DC

CLKIN Duty Cycle

Measured at VDD/2

47

0.5

–

53

4.0

%

V/ns

ps

T_R/T_F

T_CCJ

CLKIN Rise and Fall Times

CLKIN Cycle to Cycle Jitter

CLKIN Long Term Jitter

Input High Voltage

Measured between 0.2V_DDand 0.8V_DD

Measured at VDD/2

250

350

VDD+0.3

0.8

T_LTJ

Measured at VDD/2

–

ps

V_IH

XIN / CLKIN pin

2

V

V_IL

Input Low Voltage

XIN / CLKIN pin

–

V

I_IH

Input High Current

XIN / CLKIN pin, VIN = VDD

XIN / CLKIN pin, 0 < VIN <0.8

–

35

uA

I_IL

Input Low Current

-35

–

SRC at 0.7V

T_DC

SRC Duty Cycle

Measured at 0V differential

45

–

55

%

T_SKEW(window)Any SRC Clock Skew from the earliest Measured at 0V differential

bank to the latest bank

3.0

ns

T_CCJ

SRC Cycle to Cycle Jitter

Measured at 0V differential

–

0

125

108

ps

RMS_GEN1

Output PCIe* Gen1 REFCLK phase

jitter

BER = 1E-12 (including PLL BW 8 - 16

MHz, ζ = 0.54, Td=10 ns,

Ftrk=1.5 MHz)

RMS_GEN2

Output PCIe* Gen2 REFCLK phase

jitter

Includes PLL BW 8 - 16 MHz, Jitter

Peaking = 3dB, ζ = 0.54, Td=10 ns),

Low Band, F < 1.5MHz

0

3.0

ps

RMS_GEN2

Output PCIe* Gen2 REFCLK phase

jitter

Includes PLL BW 8 - 16 MHz, Jitter

Peaking = 3dB, ζ = 0.54, Td=10 ns),

Low Band, F < 1.5MHz

3.1

ps

L_ACC

T_R/ T_F

V_HIGH

V_LOW

V_OX

SRC Long Term Accuracy

SRC Rising/Falling Slew Rate

Voltage High

Measured at 0V differential

–

100

8

ppm

V/ns

V

Measured differentially from ±150 mV

2.5

1.15

–

Voltage Low

–0.3

300

–0.3

300

V

Crossing Point Voltage at 0.7V Swing

Voltage Low

550

–

mV

V

V_LOW

V_OX

Crossing Point Voltage at 0.7V Swing

550

mV

Prog_SE1 at 3.3V

T_DC

Duty Cycle

Measurement at 1.5V

45

1.0

–

55

4.0

%

T_R/ T_F

T_CCJ

L_ACC

Rising/Falling Slew Rate

Cycle to Cycle Jitter

Long Term Accuracy

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

300

100

Measurement at 1.5V

–

ppm

Prog_SE2 at 3.3V

T_DC

Duty Cycle

Measurement at 1.5V

45

1.0

–

55

4.0

%

T_R/ T_F

T_CCJ

L_ACC

Rising/Falling Slew Rate

Cycle to Cycle Jitter

Long Term Accuracy

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

300

100

Measurement at 1.5V

–

ppm

DOC#: SP-AP-0775 (Rev. 0.2)

Page 10 of 16

SL28PCIe30

AC Electrical Specifications (continued)

Parameter

25M at 3.3V

T_DC

Description

Condition

Measurement at 1.5V

Min.

Max.

Unit

Duty Cycle

45

1.0

–

55

4.0

%

T_R/ T_F

T_CCJ

Rising and Falling Edge Rate

Cycle to Cycle Jitter

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

350

100

L_ACC

Long Term Accuracy

Measured at 1.5V

–

ppm

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SSStopclock Set-up Time

–

1.8

–

ms

ns

10.0

DOC#: SP-AP-0775 (Rev. 0.2)

Page 11 of 16

SL28PCIe30

Test and Measurement Set-up

For Single Ended Clocks

The following diagram shows the test load configurations for the single-ended output signals.

Figure 1. Single-ended clocks Single Load Configuration

Figure 2. Single-ended clocks Double Load Configuration

Figure 3. Single-ended Output Signals (for AC Parameters Measurement)

DOC#: SP-AP-0775 (Rev. 0.2)

Page 12 of 16

SL28PCIe30

For Differential Clock Signals

This diagram shows the test load configuration for the differential clock signals

Figure 4. 0.7V Differential Load Configuration

Figure 5. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)

DOC#: SP-AP-0775 (Rev. 0.2)

Page 13 of 16

SL28PCIe30

Figure 6. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)

DOC#: SP-AP-0775 (Rev. 0.2)

Page 14 of 16

SL28PCIe30

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

SL28PCIe30ALC

SL28PCIe30ALCT

SL28PCIe30ALI

SL28PCIe30ALIT

32-pin QFN

Commercial, 0 to 85C

Industrial, -40 to 85C

32-pin QFN – Tape and Reel

32-pin QFN

32-pin QFN – Tape and Reel

Package Diagrams

32-Lead QFN 5x 5mm

DOC#: SP-AP-0775 (Rev. 0.2)

Page 15 of 16

SL28PCIe30

Document History Page

Document Title: SL28PCIe30 PC EProClock^®Programmable PCIe Gen 2 Clock Generator

DOC#: SP-AP-0775 (Rev. 0.2)

Orig. of

Change

TRP

REV.

AA

Issue Date

11/7/10

Description of Change

Initial Release

AA

12/7/10

TRP

1. Updated datasheet title

2. Added feature of PCIe Gen1 and Gen2 compliance

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-

icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the

use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or

parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-

sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-

cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

DOC#: SP-AP-0775 (Rev. 0.2)

Page 16 of 16


型号：	SL28PCIe30ALIT
厂家：	SILICON
描述：	EProClockÂ® Programmable PCIe Gen 2 Clock Generator PC
文件：	总16页 (文件大小：338K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SL28PCIe30ALIT [SILICON]

相关型号：

SL28S0

SL28S1

SL28S2

SL28S3

SL28S4

SL28S5

SL28SRC01BZC

SL28SRC01BZI

SL28SRC01BZIT

SL28SRC02

SL28SRC02BZCT

SL28SRC02BZI