SST32HF1641-70-4C-LFS

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

SST32HF324 / 32832Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM

Preliminary Specifications

(x16) MCP ComboMemories

FEATURES:

•

ComboMemories organized as:

•

Security-ID Feature

– SST32HF1621C: 1M x16 Flash + 128K x16 SRAM

– SST32HF1641x: 1M x16 Flash + 256K x16 SRAM

– SST32HF1681: 1M x16 Flash + 256K x16 SRAM

– SST32HF3241x: 2M x16 Flash + 256K x16 SRAM

– SST32HF3281: 2M x16 Flash + 512K x16 SRAM

– SST32HF6481: 4M x16 Flash + 512K x16 SRAM

Single 2.7-3.3V Read and Write Operations

Concurrent Operation

– Read from or Write to SRAM while

Erase/Program Flash

Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

Low Power Consumption:

– Active Current: 15 mA (typical) for

Flash or SRAM Read

– SST: 128 bits; User: 128 bits

Hardware Block-Protection/WP# Input Pin

– Bottom Block-Protection (bottom 32 KWord)

Fast Read Access Times:

– Flash: 70 ns and 90 ns

– SRAM: 70 ns and 90 ns

Latched Address and Data for Flash

Flash Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Word-Program Time: 7 µs (typical)

•

Flash Automatic Erase and Program Timing

– Internal V_PPGeneration

Flash End-of-Write Detection

– Standby Current:

– Toggle Bit

– Data# Polling

- SST32HFx1: 60 µA (typical)

- SST32HFx1C: 12 µA (typical)

Flexible Erase Capability

– Uniform 2 KWord sectors

– Uniform 32 KWord size blocks

•

CMOS I/O Compatibility

JEDEC Standard Command Set

Package Available

– 63-ball LFBGA (8mm x 10mm x 1.4mm)

– 62-ball LFBGA (8mm x 10mm x 1.4mm)

– 64-ball LFBGA (8mm x 10mm x 1.4mm)

•

Erase-Suspend/Erase-Resume Capabilities

PRODUCT DESCRIPTION

The SST32HFx1/x1C ComboMemory devices integrate

a CMOS flash memory bank with a CMOS SRAM mem-

ory bank in a Multi-Chip Package (MCP), manufactured

with SST’s proprietary, high performance SuperFlash

technology. The SST32HF16x1/32x1/6481 devices use a

PseudoSRAM. The SST32HF16x1C/32x1C devices use

standard SRAM.

signals. The SRAM bank enable signal, BES# selects the

SRAM bank. The flash memory bank enable signal, BEF#

selects the flash memory bank. The WE# signal has to be

used with Software Data Protection (SDP) command

sequence when controlling the Erase and Program opera-

tions in the flash memory bank. The SDP command

sequence protects the data stored in the flash memory

bank from accidental alteration.

Featuring high performance Word-Program, the flash

memory bank provides a maximum Word-Program time of

7 µsec. To protect against inadvertent flash write, the

SST32HFx1/x1C devices contain on-chip hardware and

software data protection schemes. The SST32HFx1/x1C

devices offer a guaranteed endurance of 10,000 cycles.

Data retention is rated at greater than 100 years.

The SST32HFx1/x1C provide the added functionality of

being able to simultaneously read from or write to the

SRAM bank while erasing or programming in the flash

memory bank. The SRAM memory bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Word-Program concurrently. All

flash memory Erase and Program operations will automati-

cally latch the input address and data signals and complete

the operation in background without further input stimulus

requirement. Once the internally controlled Erase or Pro-

gram cycle in the flash bank has commenced, the SRAM

bank can be accessed for Read or Write.

The SST32HFx1/x1C devices consist of two independent

memory banks with respective bank enable signals. The

Flash and SRAM memory banks are superimposed in the

same memory address space. Both memory banks share

common address lines, data lines, WE# and OE#. The

memory bank selection is done by memory bank enable

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

S71236-02-000

1

6/04

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

The SST32HFx1/x1C devices are suited for applications

that use both flash memory and (P)SRAM memory to store

code or data. For systems requiring low power and small

form factor, the SST32HFx1/x1C devices significantly

improve performance and reliability while lowering power

consumption when compared with multiple chip solutions.

The SST32HFx1/x1C inherently use less energy during

Erase and Program operations than alternative flash tech-

nologies. The total energy consumed is a function of the

applied voltage, current, and time of application. Since, for

any given voltage range, SuperFlash technology uses less

current to program and has a shorter erase time, the total

energy consumed during any Erase or Program operation

is less than alternative flash technologies.

Concurrent Read/Write Operation

The SST32HFx1/x1C provide the unique benefit of being

able to read from or write to SRAM, while simultaneously

erasing or programming the flash. This allows data alter-

ation code to be executed from SRAM, while altering the

data in flash. See Figure 27 for a flowchart. The following

table lists all valid states.

CONCURRENT READ/WRITE STATE TABLE

Flash

Program/Erase

SRAM

Read

Write

The device will ignore all SDP commands when an Erase

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operation is in progress.

SuperFlash technology provides fixed Erase and Program

times independent of the number of Erase/Program cycles

that have occurred. Therefore the system software or hard-

ware does not have to be modified or de-rated as is neces-

sary with alternative flash technologies, whose Erase and

Program times increase with accumulated Erase/Program

cycles.

Flash Read Operation

The Read operation of the SST32HFx1/x1C devices is

controlled by BEF# and OE#. Both have to be low, with

WE# high, for the system to obtain data from the outputs.

BEF# is used for flash memory bank selection. When

BEF# is high, the chip is deselected and only standby

power is consumed. OE# is the output control and is used

to gate data from the output pins. The data bus is in high

impedance state when OE# is high. Refer to Figure 7 for

further details.

Device Operation

The SST32HFx1/x1C use BES1#, BES2 and BEF# to con-

trol operation of either the flash or the SRAM memory

bank. When BEF# is low, the flash bank is activated for

Read, Program or Erase operation. When BES1# is low,

and BES2 is high the SRAM is activated for Read and

Write operation. BEF# and BES1# cannot be at low level,

and BES2 cannot be at high level at the same time. If all

bank enable signals are asserted, bus contention will

result and the device may suffer permanent damage.

All address, data, and control lines are shared by flash and

SRAM memory banks which minimizes power consump-

tion and loading. The device goes into standby when BEF#

and BES1# bank enables are raised to V_IHC(Logic High) or

when BEF# is high and BES2 is low.

S71236-02-000

6/04

2

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Flash Word-Program Operation

Erase-Suspend/Erase-Resume Commands

The flash memory bank of the SST32HFx1/x1C devices is

programmed on a word-by-word basis. Before Program

operations, the memory must be erased first. The Program

operation consists of three steps. The first step is the three-

byte load sequence for Software Data Protection. The sec-

ond step is to load word address and word data. During the

Word-Program operation, the addresses are latched on the

falling edge of either BEF# or WE#, whichever occurs last.

The data is latched on the rising edge of either BEF# or

WE#, whichever occurs last. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or BEF#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed, within 10

µs. See Figures 8 and 9 for WE# and BEF# controlled Pro-

gram operation timing diagrams and Figure 22 for flow-

charts. During the Program operation, the only valid flash

Read operations are Data# Polling and Toggle Bit. During

the internal Program operation, the host is free to perform

additional tasks. During the command sequence, WP#

should be statically held high or low. Any SDP commands

loaded during the internal Program operation will be

ignored.

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memory location, or program data into any

sector/block that is not suspended for an Erase operation.

The operation is executed by issuing one byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode typically within 20

µs after the Erase-Suspend command had been issued.

Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address

location within erase-suspended sectors/blocks will output

DQ₂toggling and DQ₆at “1”. While in Erase-Suspend

mode, a Word-Program operation is allowed except for the

sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has

been suspended the system must issue Erase Resume

command. The operation is executed by issuing one byte

command sequence with Erase Resume command (30H)

at any address in the last Byte sequence.

Flash Chip-Erase Operation

The SST32HFx1/x1C provide a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1” state. This is useful when the entire device must be

quickly erased.

Flash Sector/Block-Erase Operation

The Flash Sector/Block-Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST32HFx1/x1C offer both Sector-Erase

and Block-Erase mode. The sector architecture is based

on uniform sector size of 2 KWord. The Block-Erase mode

is based on uniform block size of 32 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The address lines

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address 5555H in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or BEF#, whichever occurs first. During the Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 5 for the command sequence, Figure 11 for tim-

ing diagram, and Figure 26 for the flowchart. Any com-

mands issued during the Chip-Erase operation are

ignored.

A_MS-A₁₁are used to determine the sector address. The

Block-Erase operation is initiated by executing a six-byte

command sequence with Block-Erase command (50H)

and block address (BA) in the last bus cycle. The address

lines A_MS-A₁₅are used to determine the block address.

The sector or block address is latched on the falling edge of

the sixth WE# pulse, while the command (30H or 50H) is

latched on the rising edge of the sixth WE# pulse. The

internal Erase operation begins after the sixth WE# pulse.

The End-of-Erase operation can be determined using

either Data# Polling or Toggle Bit methods. See Figures 13

and 14 for timing waveforms. Any commands issued during

the Sector- or Block-Erase operation are ignored, WP#

should be statically held high or low.

Write Operation Status Detection

The SST32HFx1/x1C provide two software means to

detect the completion of a write (Program or Erase) cycle,

in order to optimize the system Write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ₇) and Toggle Bit (DQ₆). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

S71236-02-000

6/04

3

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ₇or DQ_6.In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

TABLE 1: WRITE OPERATION STATUS

Status

DQ₇DQ₆

DQ₂

Normal

Standard

DQ₇# Toggle No Toggle

Operation Program

Standard

Erase

0

1

Toggle

1

Toggle

Erase-

Read from

Suspend Erase-Suspended

Mode

Sector/Block

Read from

Data

Non- Erase-Suspended

Sector/Block

Program

DQ₇# Toggle

N/A

Flash Data# Polling (DQ₇)

T1.0 1236

Note: DQ₇and DQ₂require a valid address when reading

When the SST32HFx1/x1C flash memory banks are in the

internal Program operation, any attempt to read DQ₇will

produce the complement of the true data. Once the Pro-

gram operation is completed, DQ₇will produce true data.

Note that even though DQ₇may have valid data immedi-

ately following the completion of an internal Write opera-

tion, the remaining data outputs may still be invalid: valid

data on the entire data bus will appear in subsequent suc-

cessive Read cycles after an interval of 1 µs. During inter-

nal Erase operation, any attempt to read DQ₇will produce

a ‘0’. Once the internal Erase operation is completed, DQ₇

will produce a ‘1’. The Data# Polling is valid after the rising

edge of the fourth WE# (or BEF#) pulse for Program opera-

tion. For Sector- or Block-Erase, the Data# Polling is valid

after the rising edge of the sixth WE# (or BEF#) pulse. See

Figure 10 for Data# Polling timing diagram and Figure 23

for a flowchart.

status information.

Flash Memory Data Protection

The SST32HFx1/x1C flash memory bank provides both

hardware and software features to protect nonvolatile data

from inadvertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

V_DDPower Up/Down Detection: The Write operation is

inhibited when V_DDis less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the flash Write operation. This prevents

inadvertent writes during power-up or power-down.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ₆will produce alternating “1”s

and “0”s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ₆bit will

stop toggling. The device is then ready for the next opera-

tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ₆)

is valid after the rising edge of sixth WE# (or BEF#) pulse.

DQ₆will be set to “1” if a Read operation is attempted on an

Erase-Suspended Sector/Block. If Program operation is ini-

tiated in a sector/block not selected in Erase-Suspend

mode, DQ₆will toggle.

An additional Toggle Bit is available on DQ₂, which can be

used in conjunction with DQ₆to check whether a particular

sector is being actively erased or erase-suspended. Table 1

shows detailed status bits information. The Toggle Bit

(DQ₂) is valid after the rising edge of the last WE# (or

BEF#) pulse of Write operation. See Figure 11 for Toggle

Bit timing diagram and Figure 23 for a flowchart.

S71236-02-000

6/04

4

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Hardware Block Protection

SRAM Read

The SST32HFx1/x1C support bottom hardware block

protection, which protects the bottom 32 KWord block of

the device. The Boot Block address is 000000H-007FFFH.

Program and Erase operations are prevented on the 32

KWord when WP# is low. If WP# is left floating, it is inter-

nally held high via a pull-up resistor, and the Boot Block is

unprotected, enabling Program and Erase operations on

that block.

The SRAM Read operation of the SST32HFx1/x1C is con-

trolled by OE# and BES1#, both have to be low with WE#

and BES2 high for the system to obtain data from the out-

puts. BES1# and BES2 are used for SRAM bank selection.

OE# is the output control and is used to gate data from the

output pins. The data bus is in high impedance state when

OE# is high. Refer to the Read cycle timing diagram, Fig-

ure 4, for further details.

Hardware Reset (RST#)

SRAM Write

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least T_RP,any in-progress operation will terminate and

return to Read mode. When no internal Program/Erase

operation is in progress, a minimum period of T_RHRis

required after RST# is driven high before a valid Read can

take place (see Figure 18).

The SRAM Write operation of the SST32HFx1/x1C is con-

trolled by WE# and BES1#, both have to be low, BES2

must be high for the system to write to the SRAM. During

the Word-Write operation, the addresses and data are ref-

erenced to the rising edge of either BES1#, WE#, or the

falling edge of BES2 whichever occurs first. The write time

is measured from the last falling edge of BES#1 or WE# or

the rising edge of BES2 to the first rising edge of BES1#, or

WE# or the falling edge of BES2. Refer to the Write cycle

timing diagrams, Figures 5 and 6, for further details.

The Erase or Program operation that has been interrupted

needs to be reinitiated after the device resumes normal

operation mode to ensure data integrity.

Product Identification

Flash Software Data Protection (SDP)

The Product Identification mode identifies the devices as

the SST32HFx1/x1C and manufacturer as SST. This

mode may be accessed by software operations only.

The hardware device ID Read operation, which is typi-

cally used by programmers, cannot be used on this

device because of the shared lines between flash and

SRAM in the multi-chip package. Therefore, applica-

tion of high voltage to pin A₉may damage this device.

Users may use the software Product Identification opera-

tion to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same socket. For details, see

Tables 4 and 5 for software operation, Figure 15 for the

software ID entry and read timing diagram and Figure 24

for the ID entry command sequence flowchart.

The SST32HFx1/x1C provide the JEDEC approved soft-

ware data protection scheme for all flash memory bank

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three-byte sequence. The three byte-load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST32HFx1/x1C devices are shipped with the software

data protection permanently enabled. See Table 5 for the

specific software command codes. During SDP command

sequence, invalid commands will abort the device to Read

mode, within T_RC.The contents of DQ₁₅-DQ₈can be V_ILor

V_IH,but no other value, during any SDP command

sequence.

TABLE 2: PRODUCT IDENTIFICATION

Address

Data

Manufacturer’s ID

Device ID

0000H

BFH

SST32HF16x1x

SST32HF32x1x

SST32HF6481

0001H

234BH

235BH

236BH

T2.1 1236

S71236-02-000

6/04

5

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

To program the user segment of the Security ID, the user

must use the Security ID Word-Program command. To

detect end-of-write for the SEC ID, read the toggle bits. Do

not use Data# Polling. Once this is complete, the Sec ID

should be locked using the User Sec ID Program Lock-Out.

This disables any future corruption of this space. Note that

regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

Product Identification Mode Exit/Reset

In order to return to the standard read mode, the Software

Product Identification mode must be exited. Exiting is

accomplished by issuing the Exit ID command sequence,

which returns the device to the Read operation. Please

note that the software reset command is ignored during an

internal Program or Erase operation. This command may

also be used to reset the device to Read mode after any

inadvertent transient condition that apparently causes the

device to behave abnormally, e.g. not read correctly. See

Table 5 for software command codes, Figure 16 for timing

waveform and Figure 24 for a flowchart.

The Secure ID space can be queried by executing a three-

byte command sequence with Enter Sec ID command

(88H) at address 5555H in the last byte sequence. To exit

this mode, the Exit Sec ID command should be executed.

Refer to Table 5 for more details.

Security ID

Design Considerations

The SST32HFx1/x1C devices offer a 256-bit Security ID

space. The Secure ID space is divided into two 128-bit seg-

ments - one factory programmed segment and one user

programmed segment. The first segment is programmed

and locked at SST with a random 128-bit number. The user

segment is left un-programmed for the customer to pro-

gram as desired.

SST recommends a high frequency 0.1 µF ceramic capac-

itor to be placed as close as possible between V_DDand

V_SS, e.g., less than 1 cm away from the V_DDpin of the

device. Additionally, a low frequency 4.7 µF electrolytic

capacitor from V_DDto V_SSshould be placed within 1 cm of

the V_DDpin.

FUNCTIONAL BLOCK DIAGRAM

SRAM/

PSRAM

Address Buffers

UBS#

LBS#

BES1#

BES2

Control Logic

BEF#

OE¹#

WE¹#

DQ - DQ

15

A

-A

0

8

MS

I/O Buffers

DQ - DQ

7

0

WP#

RESET#

Address Buffers

& Latches

SuperFlash

Memory

1236 B1.4

Notes: 1. For LS and L2S packages only:

WE# = WEF# and/or WES#

OE# = OEF# and/or OES#

S71236-02-000

6/04

6

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

TOP VIEW (balls facing down)

SST32HF16x1x/32x1x

8

7

6

5

4

3

2

1

NC

A20 A11 A15 A14 A13 A12

V

NC

SSF

A16

WEF# NC

RST#

A8

A10

A9 DQ15 WES# DQ14 DQ7

DQ13 DQ6 DQ4 DQ5

V

DQ12 BES2 V

V

DDS DDF

SSS

WP# NC

A19 DQ11

DQ10 DQ2 DQ3

LBS# UBS# OES#

DQ9 DQ8 DQ0 DQ1

A18 A17

NC A5

A7

A4

A6

A3

A2

A1 BES1#

OEF# NC NC

NC

A0 BEF#

V

SSF

A B C D E F G H J K

FIGURE 1: PIN ASSIGNMENTS FOR 62-BALL LFBGA (8MM X 10MM)

TOP VIEW (balls facing down)

8

NC

A15 A21

A11 A12 A13 A14

A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5

NC

A16

NC

V

NC

SS

7

6

5

4

3

2

1

NC DQ15 DQ7 DQ14 NC

WE# BES2 A20

WP# RST# NC

DQ4

DQ3

V

NC

DDS

DQ11

DDF

LBS# UBS# A18 A17 DQ1 DQ9 DQ10 DQ2

A7

A6

A3

A5

A2

A4

A1

V

OE# DQ0 DQ8 NC

SS

NC

A0 BEF# BES1# NC

A B C D E F G H J K

FIGURE 2: PIN ASSIGNMENTS FOR 63-BALL LFBGA (8MM X 10MM)

S71236-02-000

6/04

7

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

TOP VIEW (balls facing down)

SST32HF6481

8

7

6

5

4

3

2

1

NC

A20 A11 A15 A14 A13 A12

V

NC

SSF

A16

WEF# NC

RST#

A8

A10

A9 DQ15 WES# DQ14 DQ7

A21 DQ13 DQ6 DQ4 DQ5

V

NC DQ12 BES2 V

V

SSS

WP# NC

LBS# UBS# OES#

DDS DDF

A19 DQ11

DQ10 DQ2 DQ3

DQ9 DQ8 DQ0 DQ1

A18 A17

NC A5

A7

A4

A6

A3

A2

A1 BES1#

OEF# NC NC

NC

A0 BEF#

V

SSF

A B C D E F G H J K

FIGURE 3: PIN ASSIGNMENTS FOR 64-BALL LFBGA (8MM X 10MM)

TABLE 3: PIN DESCRIPTION

Symbol

Pin Name

Functions

A_MS¹to A₀Address Inputs

To provide flash address, A_MS-A₀.

To provide SRAM address, A_MS-A₀

DQ₁₅-DQ₀Data Inputs/Outputs

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle. The outputs are in

tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

BEF#

BES1#

BES2

OEF#²

OES#²

WEF#²

WES#²

OE#

Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low

SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low

SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high

Output Enable

Write Enable

Output Enable

Write Enable

To gate the data output buffers for Flash²only

To gate the data output buffers for SRAM²only

To control the Write operations for Flash²only

To control the Write operations for SRAM²only

To gate the data output buffers

WE#

To control the Write operations

UBS#

LBS#

WP#

Upper Byte Control (SRAM) To enable DQ₁₅-DQ₈

Lower Byte Control (SRAM) To enable DQ₇-DQ₀

Write Protect

Reset

To protect and unprotect sectors from Erase or Program operation

RST#

To Reset and return the device to Read mode

2

V_SSF

Ground

Flash²only

SRAM²only

2

V_SSS

Ground

V_SS

Ground

V_DD

Power Supply (Flash)

Power Supply (SRAM)

No Connection

2.7-3.3V Power Supply to Flash only

2.7-3.3V Power Supply to SRAM only

Unconnected pins

F

V_DD

S

NC

T3.2 1236

1. A_MS= Most Significant Address

A_MS= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

2. LS and L2S packages only

S71236-02-000

6/04

8

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

1

TABLE 4: OPERATIONAL MODES SELECTION

Mode

BEF#

BES1#

V_IH

X

BES2²

OE#³

X

WE#³

X

LBS#

X

UBS#

DQ_0-7

DQ_8-15

Full Standby

V_IH

X

HIGH-Z

V_IL

V_IH

X

Output Disable

V_IH

V_IL

V_IH

V_IL

V_IH

X

V_IH

X

V_IH

X

HIGH-Z

D_OUT

D_IN

HIGH-Z

D_OUT

D_IN

V_IH

X

V_IH

X

V_IH

V_IL

X

Flash Read

Flash Write

Flash Erase

SRAM Read

V_IH

X

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

X

V_IL

X

V_IH

X

V_IL

X

V_IH

X

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

X

V_IL

V_IH

V_IL

V_IH

X

D_OUT

HIGH-Z

D_OUT

D_IN

D_OUT

HIGH-Z

D_IN

SRAM Write

V_IH

V_IL

V_IH

X

V_IL

HIGH-Z

D_IN

HIGH-Z

Product

V_IL

V_IH

X

V_IL

V_IH

Manufacturer’s ID⁵

Identification⁴

Device ID⁵

V_IL

T4.1 1236

1. X can be V_ILor V_IH, but no other value.

2. Do not apply BEF# = V_IL, BES1# = V_ILand BES2 = V_IHat the same time

3. OE# = OEF# and OES#

WE# = WEF# and WES# for LS and L2S packages only

4. Software mode only

5. With A_MS-A₁= 0;SST Manufacturer’s ID = 00BFH, is read with A₀=0,

SST32HF16x1x Device ID = 234BH, is read with A₀=1,

SST32HF32x1x Device ID = 235BH, is read with A₀=1,

SST32HF6481 Device ID = 236BH, is read with A₀=1.

S71236-02-000

6/04

9

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

TABLE 5: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²

WA³

Data

Word-Program

Sector-Erase

Block-Erase

5555H

AAH 2AAAH 55H 5555H A0H

4

AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H

SA_X

BA_X

30H

50H

Chip-Erase

AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Erase-Suspend

Erase-Resume

Query Sec ID⁵

XXXXH B0H

XXXXH 30H

5555H

AAH 2AAAH 55H 5555H 88H

AAH 2AAAH 55H 5555H A5H

WA⁶

Data

User Security ID

Word-Program

XXH⁶0000H

User Security ID

Program Lock-Out

5555H

AAH 2AAAH 55H 5555H 85H

Software ID Entry^7,8

5555H

AAH 2AAAH 55H 5555H 90H

AAH 2AAAH 55H 5555H F0H

Software ID Exit^9,10

/Sec ID Exit

Software ID Exit^9,10

/Sec ID Exit

XXH

F0H

T5.1 1236

1. Address format A₁₄-A₀(Hex).

Addresses A₁₅-A₁₉can be V_ILor V_IH, but no other value, for Command sequence for SST32HF16x1x,

Addresses A₁₅-A₂₀can be V_ILor V_IH, but no other value, for Command sequence for SST32HF32x1x,

Addresses A₁₅- A₂₁can be V_ILor V_IH, but no other value, for Command sequence for SST32HF6481.

2. DQ₁₅-DQ₈can be V_ILor V_IH, but no other value, for Command sequence

3. WA = Program Word address

4. SA_Xfor Sector-Erase; uses A_MS-A₁₁address lines

BA_X, for Block-Erase; uses A_MS-A₁₅address lines

A

_MS= Most significant address

_MS= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481.

5. With A_MS-A₄= 0; Sec ID is read with A₃-A₀,

SST ID is read with A₃= 0 (Address range = 000000H to 000007H),

User ID is read with A₃= 1 (Address range = 000010H to 000017H).

Lock Status is read with A₇-A₀= 0000FFH. Unlocked: DQ₃= 1 / Locked: DQ₃= 0.

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.

7. The device does not remain in Software Product ID Mode if powered down.

8. With A_MS-A₁=0; SST Manufacturer ID = 00BFH, is read with A₀= 0,

SST32HF16x1x Device ID = 234BH, is read with A₀= 1,

SST32HF32x1x Device ID = 235BH, is read with A₀= 1,

SST32HF6481 Device ID = 236BH, is read with A₀= 1,

A

_MS= Most significant address

A_MS= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481.

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID

mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and

000010H-000017H.

S71236-02-000

6/04

10

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V_DD¹+0.3V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to V_DD¹+1.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Output Short Circuit Current². . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. V_DD= V_DDFand V_DDS

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range

Ambient Temp

0°C to +70°C

V_DD

Commercial

Extended

2.7-3.3V

-20°C to +85°C

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C_L= 30 pF

See Figures 20 and 21

S71236-02-000

6/04

11

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

TABLE 6: DC OPERATING CHARACTERISTICS (V_DD= V_DDFAND V_DDS= 2.7-3.3V)

Limits

Symbol Parameter

I_DDActive V_DDCurrent

Min

Max Units Test Conditions

Address input = V_ILT/V_IHT,at f=1/T_RCMin,

V_DD=V_DDMax, all DQs open

Read

Flash

OE#=V_IL, WE#=V_IH

18

30

40

mA

BEF#=V_IL, BES1#=V_IH, or BES2=V_IL

BEF#=V_IH, BES1#=V_{IL ,}BES2=V_IH

WE#=V_IL

SRAM

Concurrent Operation

Write¹

Flash

35

30

mA

BEF#=V_IL, BES1#=V_IH, or BES2=V_IL, OE#=V_IH

BEF#=V_IH, BES1#=V_{IL ,}BES2=V_IH

V_DD= V_DDMax, BEF#=BES1#=V_IHC, BES2=V_ILC

SRAM

I_SB

Standby V_DDCurrent SST32HFx1

SST32HFx1C

110

30

µA

I_RT

Reset V_DDCurrent

30

1

µA

V

Reset=V_SS0.3V

I_LI

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_IN=GND to V_DD, V_DD=V_DDMax

V_OUT=GND to V_DD, V_DD=V_DDMax

V_DD=V_DDMin

I_LO

10

0.8

0.3

V_IL

V_ILC

V_IH

Input Low Voltage (CMOS)

Input High Voltage

V

V_DD=V_DDMax

0.7 V_DD

V_DD-0.3

V

V_DD=V_DDMax

V_IHC

V_OLF

V_OHF

V_OLS

V_OHS

Input High Voltage (CMOS)

Flash Output Low Voltage

Flash Output High Voltage

SRAM Output Low Voltage

SRAM Output High Voltage

V

V_DD=V_DDMax

0.2

0.4

V

I_OL=100 µA, V_DD=V_DDMin

I_OH=-100 µA, V_DD=V_DDMin

IOL =1 mA, V_DD=V_DDMin

V_DD-0.2

2.2

V

IOH =-500 µA, V_DD=V_DDMin

T6.0 1236

1. I_DDactive while Erase or Program is in progress.

TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol

Parameter

Minimum

100

Units

µs

1

T_PU-READ

Power-up to Read Operation

Power-up to Program/Erase Operation

1

T_PU-WRITE

100

µs

T7.0 1236

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

V_I/O= 0V

Maximum

1

C_I/O

I/O Pin Capacitance

Input Capacitance

12 pF

1

C_IN

V_IN= 0V

T8.0 1236

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 9: FLASH RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Data Retention

Latch Up

Minimum Specification

Units

Test Method

1

N_END

10,000

100

Cycles JEDEC Standard A117

1

T_DR

Years

mA

JEDEC Standard A103

JEDEC Standard 78

1

I_LTH

100 + I_DD

T9.0 1236

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

S71236-02-000

6/04

12

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

AC CHARACTERISTICS

TABLE 10: SRAM READ CYCLE TIMING PARAMETERS

SST32HFx1/x1C-70

SST32HFx1/x1C-90

Symbol Parameter

Min

Max

Min

Max

Units

ns

T_RCS

T_AAS

T_BES

T_OES

T_BYES

Read Cycle Time

70

90

Address Access Time

70

35

70

90

45

90

ns

Bank Enable Access Time

Output Enable Access Time

UBS#, LBS# Access Time

BES# to Active Output

ns

1

T_BLZS

T_OLZS

0

ns

1

Output Enable to Active Output

UBS#, LBS# to Active Output

BES# to High-Z Output

ns

1

T_BYLZS

ns

1

T_BHZS

25

35

45

ns

1

T_OHZS

T_BYHZS

T_OHS

Output Disable to High-Z Output

UBS#, LBS# to High-Z Output

Output Hold from Address Change

0

ns

1

ns

10

ns

T10.0 1236

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 11: SRAM WRITE CYCLE TIMING PARAMETERS

SST32HFx1/x1C-70

SST32HFx1/x1C-90

Symbol Parameter

Min

70

60

0

Max

Min

90

80

0

Max

Units

ns

T_WCS

T_BWS

T_AWS

Write Cycle Time

Bank Enable to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

ns

T_ASTS

T_WPS

T_WRS

T_BYWS

T_ODWS

T_OEWS

T_DSS

ns

Write Pulse Width

60

0

80

0

ns

Write Recovery Time

ns

UBS#, LBS# to End-of-Write

Output Disable from WE# Low

Output Enable from WE# High

Data Set-up Time

60

80

ns

30

40

ns

0

30

0

40

0

ns

T_DHS

Data Hold from Write Time

ns

T11.0 1236

S71236-02-000

6/04

13

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

TABLE 12: FLASH READ CYCLE TIMING PARAMETERS V_DD= 2.7-3.6V

SST32HFx1/x1C-70

SST32HFx1/x1C-90

Symbol

T_RC

Parameter

Min

Max

Min

Max

Units

ns

Read Cycle Time

70

90

T_CE

Chip Enable Access Time

Address Access Time

70

35

90

45

ns

T_AA

ns

T_OE

Output Enable Access Time

BEF# Low to Active Output

OE# Low to Active Output

BEF# High to High-Z Output

OE# High to High-Z Output

Output Hold from Address Change

RST# Pulse Width

ns

1

T_CLZ

0

ns

1

T_OLZ

ns

1

T_CHZ

20

30

ns

1

T_OHZ

ns

1

T_OH

0

ns

1

T_RP

500

50

500

50

ns

1

T_RHR

RST# High before Read

RST# Pin Low to Read Mode

ns

1,2

T_RY

20

µs

T12.0 1236

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations.

This parameter does not apply to Chip-Erase operations.

TABLE 13: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter

Min

Max

Units

µs

T_BP

Word-Program Time

10

T_AS

Address Setup Time

Address Hold Time

WE# and BEF# Setup Time

WE# and BEF# Hold Time

OE# High Setup Time

OE# High Hold Time

BEF# Pulse Width

WE# Pulse Width

0

30

0

ns

T_AH

ns

T_CS

ns

T_CH

T_OES

T_OEH

T_CP

0

ns

0

ns

10

40

30

0

ns

T_WP

T_WPH

ns

1

WE# Pulse Width High

BEF# Pulse Width High

Data Setup Time

ns

1

T_CPH

T_DS

ns

1

T_DH

Data Hold Time

ns

1

T_IDA

Software ID Access and Exit Time

Sector-Erase

150

25

ns

T_SE

ms

T_BE

Block-Erase

25

T_SCE

Chip-Erase

50

ms

T13.2 1236

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

S71236-02-000

6/04

14

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

T

RCS

ADDRESSES A

MSS-0

T

OHS

T

AAS

T

BES1#

BES2

BES

T

BES

T

BHZS

BLZS

T

OES

OE#

T

OLZS

T

OHZS

T

BYES

UBS#, LBS#

T

BYLZS

T

BYHZS

DQ

15-0

DATA VALID

1236 F03.1

Note: A_MSS= Most Significant SRAM Address

_MSS= A₁₆for SST32HF1621C, A₁₇for SST32HFxx41x and A₁₈for SST32HFxx81

A

FIGURE 4: SRAM READ CYCLE TIMING DIAGRAM

S71236-02-000

6/04

15

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

T

WCS

3

ADDRESSES A

MSS -0

T

ASTS

T

WPS

WRS

WE#

T

AWS

T

BWS

BES1#

BES2

T

BWS

T

BYWS

UBS#, LBS#

T

OEWS

T

ODWS

T

DHS

T

DSS

NOTE 2

VALID DATA IN

NOTE 2

DQ

7-0

15-8,

1236 F04.1

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.

Because D_INsignals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. A_MSS= Most Significant SRAM Address

A_MSS= A₁₆for SST32HF1621C, A₁₇for SST32HFxx41x and A₁₈for SST32HFxx81

FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)¹

S71236-02-000

6/04

16

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

T

WCS

3

ADDRESSES A

MSS -0

T

WRS

WPS

WE#

T

BWS

BES1#

BES2

T

BWS

T

AWS

T

BYWS

ASTS

UBS#, LBS#

T

DHS

DSS

DQ

7-0

15-8,

NOTE 2

VALID DATA IN

1236 F05.1

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because D_INsignals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. A_MSS= Most Significant SRAM Address

A

_MSS= A₁₆for SST32HF1621C, A₁₇for SST32HFxx41x and A₁₈for SST32HFxx81

FIGURE 6: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)¹

S71236-02-000

6/04

17

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

T

AA

RC

ADDRESS A

MS-0

BEF#

OE#

T

CE

T

OE

T

OHZ

V

IH

OLZ

WE#

T

CHZ

T

OH

T

HIGH-Z

CLZ

HIGH-Z

DQ

15-0

DATA VALID

1236 F06.2

Note: A_MSF= Most Significant Flash Address

_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

A

FIGURE 7: FLASH READ CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

MS-0

T

AH

T

DH

T

WP

WE#

T

AS

DS

T

WPH

OE#

T

CH

BEF#

T

CS

DQ

15-0

XXAA

SW0

XX55

SW1

XXA0

SW2

DATA

WORD

(ADDR/DATA)

1236 F07.2

Note: A_MSF= Most Significant Flash Address

A_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

WP# must be held in proper logic state (V_ILor V_IH) 1 µs prior to and 1 µs after the command sequence

X can be V_ILor V_IH,but no other value

FIGURE 8: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

S71236-02-000

6/04

18

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

INTERNAL PROGRAM OPERATION STARTS

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

MS-0

T

AH

T

DH

T

CP

BEF#

T

AS

DS

T

CPH

OE#

WE#

T

CH

T

CS

DQ

15-0

XXAA

SW0

XX55

SW1

XXA0

SW2

DATA

WORD

(ADDR/DATA)

1236 F08.2

Note: A_MSF= Most Significant Flash Address

_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

A

WP# must be held in proper logic state (V_ILor V_IH) 1 µs prior to and 1 µs after the command sequence

X can be V_ILor V_IH,but no other value

FIGURE 9: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM

ADDRESSES A

MSF-0

BEF#

OE#

T

CE

T

OES

T

OEH

T

OE

WE#

Data

Data#

Data

DQ

7

1236 F09.1

Note: A_MSF= Most Significant Flash Address

A_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

FIGURE 10: FLASH DATA# POLLING TIMING DIAGRAM

S71236-02-000

6/04

19

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

ADDRESSES A

MSF-0

T

CE

BEF#

T

OES

T

OE

OEH

OE#

WE#

DQ and DQ

6

2

TWO READ CYCLES

WITH SAME OUTPUTS

1236 F10.1

Note: A_MSF= Most Significant Flash Address

_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

A

FIGURE 11: FLASH TOGGLE BIT TIMING DIAGRAM

T

SCE

SIX-BYTE CODE FOR CHIP-ERASE

5555 5555 2AAA

5555

2AAA

5555

ADDRESS A

MS-0

BEF#

OE#

T

WP

WE#

DQ

15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX10

SW5

1236 F11.2

Note: A_MSF= Most Significant Flash Address

_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

A

WP# must be held in proper logic state (V_ILor V_IH) 1 µs prior to and 1 µs after the command sequence

This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13)

X can be V_ILor V_IH,but no other value.

FIGURE 12: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM

S71236-02-000

6/04

20

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

T

BE

SIX-BYTE CODE FOR BLOCK-ERASE

5555 5555 2AAA

5555

2AAA

BA

ADDRESS A

X

MS-0

BEF#

OE#

T

WP

WE#

DQ

15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX50

SW5

1236 F13.2

Note: A_MSF= Most Significant Flash Address

_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

This device also supports BEF# controlled Block-Erase operation.

A

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13.)

BA_X= Block Address

WP# must be held in proper logic state (V_ILor V_IH) 1 µs prior to and 1 µs after the command sequence

X can be V_ILor V_IH,but no other value.

FIGURE 13: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM

S71236-02-000

6/04

21

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

T

SE

SIX-BYTE CODE FOR SECTOR-ERASE

2AAA 5555 5555 2AAA

5555

SA

ADDRESS A

X

MS-0

BEF#

OE#

T

WP

WE#

DQ

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX30

SW5

15-0

1236 F12.2

Note: A_MSF= Most Significant Flash Address

_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

This device also supports BEF# controlled Sector-Erase operation.

A

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13.)

SA_X= Sector Address

WP# must be held in proper logic state (V_ILor V_IH) 1 µs prior to and 1 µs after the command sequence

X can be V_ILor V_IH,but no other value.

FIGURE 14: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM

S71236-02-000

6/04

22

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

THREE-WORD SEQUENCE FOR

SOFTWARE ID ENTRY

ADDRESS A

14-0

5555

2AAA

5555

0000

0001

BEF#

OE#

T

IDA

T

WP

WE#

T

WPH

T

AA

DQ

15-0

XXAA

SW0

XX55

SW1

XX90

SW2

00BF

DEVICE ID

1236 F14.0

MFG ID

Note: X can be V_ILor V_IH,but no other value.

Device ID - See Table 2 on page 5

FIGURE 15: SOFTWARE ID ENTRY AND READ

THREE-WORD SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

5555

2AAA

5555

ADDRESS A

DQ

14-0

XXAA

XX55

XXF0

15-0

T

IDA

BEF#

OE#

T

WP

WE#

T

WHP

1236 F15.0

SW0

SW1

SW2

Note: X can be V_ILor V_IH,but no other value.

FIGURE 16: SOFTWARE ID EXIT AND RESET

S71236-02-000

6/04

23

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

THREE-BYTE SEQUENCE FOR

SEC ID ENTRY

ADDRESS A

5555

2AAA

5555

MSF-0

BEF#

OE#

T

IDA

T

WP

WE#

T

WPH

T

AA

DQ

15-0

XXAA

SW0

XX55

SW1

XX88

SW2

1236 F27.1

Note: A_MSF= Most Significant Flash Address

_MSF= A₁₉for SST32HF16x1x, A₂₀for SST32HF32x1x, and A₂₁for SST32HF6481

A

WP# must be held in proper logic state (V_ILor V_IH) 1 µs prior to and 1 µs after the command sequence.

X can be V_ILor V_IH,but no other value.

FIGURE 17: FLASH SEC ID ENTRY

S71236-02-000

6/04

24

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

T

RP

RST#

BEF#/OE#

T

RHR

1236 F23.2

FIGURE 18: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

T

RP

RST#

T

RY

BEF#/OE#

End-of-Write Detection

(Toggle-Bit)

1236 F24.2

FIGURE 19: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)

S71236-02-000

6/04

25

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

V

IHT

V

IT

INPUT

REFERENCE POINTS

OUTPUT

OT

V

ILT

1236 F16.0

AC test inputs are driven at V_IHT(0.9 V_DD) for a logic “1” and V_ILT(0.1 V_DD) for a logic “0”. Measurement reference points

for inputs and outputs are V_IT(0.5 V_DD) and V_OT(0.5 V_DD). Input rise and fall times (10% ↔90%) are <5 ns.

Note: V_IT- V_INPUTTest

V

_OT- V_OUTPUTTest

_IHT- V_INPUTHIGH Test

_ILT- V_INPUTLOW Test

FIGURE 20: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO TESTER

TO DUT

C

L

1236 F17.0

FIGURE 21: A TEST LOAD EXAMPLE

S71236-02-000

6/04

26

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Start

Write data: XXAAH

Address: 5555H

Write data: XX55H

Address: 2AAAH

Write data: XXA0H

Address: 5555H

Write Word

Address/Word

Data

Wait for end of

Program (T

Data# Polling

,

BP

bit, or Toggle bit

operation)

Program

Completed

1236 F18.0

Note: X can be V or V , but no other value

IL

IH

FIGURE 22: WORD-PROGRAM ALGORITHM

S71236-02-000

6/04

27

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Toggle Bit

Data# Polling

Internal Timer

Program/Erase

Initiated

Program/Erase

Initiated

Program/Erase

Initiated

Read DQ

7

Read word

Wait T

SCE, or BE

,

BP

T

No

Read same

word

Is DQ =

7

true data?

Program/Erase

Completed

Yes

No

Does DQ

match?

6

Program/Erase

Completed

Yes

Program/Erase

Completed

1236 F19.0

FIGURE 23: WAIT OPTIONS

S71236-02-000

6/04

28

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Sec ID Query Entry

Command Sequence

Software Product ID Entry

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX88H

Address: 5555H

Load data: XX90H

Address: 5555H

Wait T

IDA

Read Sec ID

Read Software ID

1236 F20.1

X can be V or V , but no other value

IL IH

FIGURE 24: SEC ID/SOFTWARE ID COMMAND FLOWCHARTS

S71236-02-000

6/04

29

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Software ID Exit/Sec ID Exit

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXF0H

Address: XXH

Load data: XX55H

Address: 2AAAH

Wait T

IDA

Load data: XXF0H

Address: 5555H

Return to normal

operation

Wait T

IDA

Return to normal

operation

X can be V or V , but no other value

IL IH

1236 F25.0

FIGURE 25: SOFTWARE ID/SEC ID COMMAND FLOWCHARTS

S71236-02-000

6/04

30

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Chip-Erase

Sector-Erase

Block-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX80H

Address: 5555H

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XX30H

Load data: XX50H

Address: SA

Address: BA

X

Wait T

BE

SCE

SE

Chip erased

to FFFFH

Sector erased

to FFFFH

Block erased

to FFFFH

1236 F21.0

Note: X can be V or V , but no other value.

IL

IH

FIGURE 26: ERASE COMMAND SEQUENCE

S71236-02-000

6/04

31

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Concurrent

Operation

Load SDP

Command

Sequence

Flash

Program/Erase

Initiated

Wait for End of

Write Indication

Read or Write

SRAM

End

Wait

Flash Operation

Completed

End Concurrent

Operation

1236 F22.0

FIGURE 27: CONCURRENT OPERATION FLOWCHART

S71236-02-000

6/04

32

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

PRODUCT ORDERING INFORMATION

Device

Speed

Suffix1

Suffix2

SST32HFxxxxC - XXX

-

XX

-

XX

Package Modifier

FS = 63 ball positions

S = 62 ball positions

2S = 64 ball positions

Package Type

L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)

Temperature Range

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

90 = 90 ns

Device

Blank = PseudoSRAM

C = Standard SRAM

Hardware Block Protection

1 = Bottom Boot Block

SRAM Density

2 = 2 Mbit

4 = 4 Mbit

8 = 8 Mbit

Flash Density

16 = 16 Mbit

32 = 32 Mbit

64 = 64 Mbit

Voltage

H = 2.7-3.3V

Product Series

32 = MPF+ + SRAM ComboMemory

Valid combinations for SST32HF1621C

SST32HF1621C-70-4C-LS

SST32HF1621C-90-4C-LS

SST32HF1621C-70-4C-LFS

SST32HF1621C-90-4C-LFS

SST32HF1621C-70-4E-LS

SST32HF1621C-90-4E-LS

SST32HF1621C-70-4E-LFS

SST32HF1621C-90-4E-LFS

S71236-02-000

6/04

33

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

Valid combinations for SST32HF1641

SST32HF1641-70-4C-LS

SST32HF1641-90-4C-LS

SST32HF1641-70-4C-LFS

SST32HF1641-90-4C-LFS

SST32HF1641-70-4E-LS

SST32HF1641-90-4E-LS

SST32HF1641-70-4E-LFS

SST32HF1641-90-4E-LFS

Valid combinations for SST32HF1641C

SST32HF1641C-70-4C-LS

SST32HF1641C-90-4C-LS

SST32HF1641C-70-4C-LFS

SST32HF1641C-90-4C-LFS

SST32HF1641C-70-4E-LS

SST32HF1641C-90-4E-LS

SST32HF1641C-70-4E-LFS

SST32HF1641C-90-4E-LFS

Valid combinations for SST32HF1681

SST32HF1681-70-4C-LS

SST32HF1681-90-4C-LS

SST32HF1681-70-4C-LFS

SST32HF1681-90-4C-LFS

SST32HF1681-70-4E-LS

SST32HF1681-90-4E-LS

SST32HF1681-70-4E-LFS

SST32HF1681-90-4E-LFS

Valid combinations for SST32HF3241

SST32HF3241-70-4C-LS

SST32HF3241-90-4C-LS

SST32HF3241-70-4C-LFS

SST32HF3241-90-4C-LFS

SST32HF3241-70-4E-LS

SST32HF3241-90-4E-LS

SST32HF3241-70-4E-LFS

SST32HF3241-90-4E-LFS

Valid combinations for SST32HF3241C

SST32HF3241C-70-4C-LS

SST32HF3241C-90-4C-LS

SST32HF3241C-70-4C-LFS

SST32HF3241C-90-4C-LFS

SST32HF3241C-70-4E-LS

SST32HF3241C-90-4E-LS

SST32HF3241C-70-4E-LFS

SST32HF3241C-90-4E-LFS

Valid combinations for SST32HF3281

SST32HF3281-70-4C-LS

SST32HF3281-90-4C-LS

SST32HF3281-70-4C-LFS

SST32HF3281-90-4C-LFS

SST32HF3281-70-4E-LS

SST32HF3281-90-4E-LS

SST32HF3281-70-4E-LFS

SST32HF3281-90-4E-LFS

Valid combinations for SST32HF6481

SST32HF6481-70-4C-L2S

SST32HF6481-90-4C-L2S

SST32HF6481-70-4C-LFS

SST32HF6481-90-4C-LFS

SST32HF6481-70-4E-L2S

SST32HF6481-90-4E-L2S

SST32HF6481-70-4E-LFS

SST32HF6481-90-4E-LFS

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

S71236-02-000

6/04

34

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

PACKAGING DIAGRAMS

TOP VIEW

10.00 0.20

BOTTOM VIEW

7.20

0.80

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

8.00 0.20

5.60

0.40 0.05

(62X)

0.80

A

B

C

D

E

F

G

H

J

K

J

H

G

F

E

D

C

B

A

A1 CORNER

1.30 0.10

SIDE VIEW

1mm

0.12

SEATING PLANE

0.32 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

62-lfbga-LS-8x10-400mic-4

4. Ball opening size is 0.32 mm ( 0.05 mm)

62-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE CODE: LS

S71236-02-000

6/04

35

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

TOP VIEW

10.00 0.20

BOTTOM VIEW

7.20

0.80

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

8.00 0.20

5.60

0.40 0.05

(64X)

0.80

A

B

C

D

E

F

G

H

J

K

J

H

G

F

E

D

C

B

A

A1 CORNER

1.30 0.10

SIDE VIEW

1mm

0.12

SEATING PLANE

0.32 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.32 mm ( 0.05 mm)

64-lfbga-L2S-8x10-400mic-1

64-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE CODE: L2S

S71236-02-000

6/04

36

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281 / SST32HF6481

SST32HF1621C / SST32HF1641C / SST32HF3241C

Preliminary Specifications

TOP VIEW

10.0 0.1

BOTTOM VIEW

7.20

0.80

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

8.0 0.1

5.60

0.40 0.05

(63X)

0.80

A

B

C

D

E

F

G

H

J

K

J

H

G

F

E

D

C

B

A

A1 CORNER

1.3 0.1

SIDE VIEW

1mm

0.12

SEATING PLANE

0.32 0.05

Note:

1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size: 0.32 mm ( 0.05 mm)

63-lfbga-LFS-8x10-400mic-1

63-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE CODE: LFS

TABLE 14: REVISION HISTORY

Number

00

Description

Date

Jul 2003

Jan 2004

•

Initial Release

01

Moved 64M Flash + 16M SRAM to S71247 data sheet

Changed all TBD MPNs to L2S

Removed BFS MPNs for all devices

Updated all timing diagrams

02

Jun 2004

Added SST32HF1621C device and associated MPNs

Removed SST32HF3281C and SST32HF6481C devices and associated MPNs

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

S71236-02-000

6/04

37


型号：	SST32HF1641-70-4C-LFS
厂家：	SILICON
描述：	Memory Circuit, 1MX16, CMOS, PBGA63, 8 X 10 MM, 1.40 MM HEIGHT, MO-210, LFBGA-63 静态存储器内存集成电路
文件：	总37页 (文件大小：427K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SST32HF1641-70-4C-LFS [SILICON]

相关型号：

SST32HF1641-90-4C-LS

SST32HF1641C

SST32HF1641C-70-4C-LFS

SST32HF1641C-70-4C-LFSE

SST32HF1641C-70-4C-LS

SST32HF1641C-70-4C-LSE

SST32HF1641C-70-4E-LSE

SST32HF1641C-90-4C-LFS

SST32HF1641C-90-4E-LFS

SST32HF1641C-90-4E-LS

SST32HF1642

SST32HF1642-70-4C-LFS