SST34HF164G-70-4E-L3KE [SILICON]
Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA48, 6 X 8 MM, 1.40 MM HEIGHT, LEAD FREE, MO-210AB-1, LFBGA-48;
| 型号： | SST34HF164G-70-4E-L3KE |
| 厂家： | 
SILICON |
| 描述： | Memory Circuit, Flash+SRAM, 1MX16, CMOS, PBGA48, 6 X 8 MM, 1.40 MM HEIGHT, LEAD FREE, MO-210AB-1, LFBGA-48 静态存储器 |
| 文件： | 总31页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
SST34HF162G/164G16Mb Dual-Bank Flash + 2/4 Mb SRAM MCP ComboMemory
Preliminary Specifications
FEATURES:
•
Flash Organization: 1M x16
– 16 Mbit: 12 Mbit + 4 Mbit
Concurrent Operation
•
•
Block-Erase Capability
– Uniform 32 KWord blocks
Read Access Time
•
– Read from or Write to SRAM while
Erase/Program Flash
– Flash: 70 ns
– SRAM: 70 ns
•
SRAM Organization:
•
•
•
Erase-Suspend / Erase-Resume Capabilities
Latched Address and Data
– 2 Mbit:128K x16
– 4 Mbit: 256K x16
Fast Erase and Word-Program (typical):
•
•
Single 2.7-3.3V Read and Write Operations
Superior Reliability
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
•
•
Low Power Consumption: (typical values @ 5 MHz)
– Active Current: Flash 10 mA (typical)
SRAM 6 mA (typical)
– Standby Current: 10 µA (typical)
– Toggle Bit
– Data# Polling
Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Packages Available
•
•
Hardware Reset Pin (RST#)
– 48-ball LFBGA (6mm x 8mm)
– 48-ball LBGA (10mm x 12mm)
– Non-Pb (lead-free) packages available
– Resets the internal state machine to reading
data array
Sector-Erase Capability
– Uniform 2 KWord sectors
PRODUCT DESCRIPTION
The SST34HF16xG ComboMemory devices integrate a
1M x16 CMOS flash memory bank with either 128K x16 or
256K x16 CMOS SRAM memory bank in a multi-chip
package (MCP). These devices are fabricated using SST’s
proprietary, high-performance CMOS SuperFlash technol-
ogy incorporating the split-gate cell design and thick-oxide
tunneling injector to attain better reliability and manufactur-
ability compared with alternate approaches. The
SST34HF16xG devices are ideal for applications such as
cellular phones, GPS devices, PDAs, and other portable
electronic devices in a low power and small form factor sys-
tem.
operations, the flash memory banks provide a typical Pro-
gram time of 7 µsec. The entire flash memory bank can be
erased and programmed word-by-word in 4 seconds (typi-
cally) for the SST34HF16xG, when using interface features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of Program operation. To protect against inadvertent
flash write, the SST34HF16xG devices contain on-chip
hardware and software data protection schemes.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
SRAM bank enable signal, BES#, selects the SRAM bank.
The flash memory bank enable signal, BEF#, has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The memory banks are
superimposed in the same memory address space where
they share common address lines, data lines, WE# and
OE# which minimize power consumption and area. See
Figure 1 for memory organization.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF16xG devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high-performance Program
©2004 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71276-00-000
1
11/04
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Designed, manufactured, and tested for applications requir-
ing low power and small form factor, the SST34HF16xG
are offered in both commercial and extended temperatures
and a small footprint package to meet board space con-
straint requirements. See Figure 2 for pin assignments.
Flash Program Operation
These devices are programmed on a word-by-word basis.
Before programming, one must ensure that the sector
which is being programmed is fully erased.
The Program operation is accomplished in three steps:
Device Operation
1. Software Data Protection is initiated using the
three-byte load sequence.
The SST34HF16xG use BES# and BEF# to control opera-
tion of either the flash or the SRAM memory bank. When
BEF# is low, the flash bank is activated for Read, Program
or Erase operation. When BES# is low the SRAM is acti-
vated for Read and Write operation. BEF# and BES# can-
not be at low level at the same time. If all bank enable
signals are asserted, bus contention will result and the
device may suffer permanent damage. All address,
data, and control lines are shared by flash and SRAM
memory banks which minimizes power consumption and
loading. The device goes into standby when BEF# and
BES# bank enables are raised to VIHC (Logic High) or
when BEF# is high.
2. Address and data are loaded.
During the Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the
rising edge of either BEF# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or BEF#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
See Figures 8 and 9 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 21 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
Concurrent Read/Write Operation
The SST34HF16xG provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. The following table lists all valid states.
Flash Sector- /Block-Erase Operation
CONCURRENT READ/WRITE STATE TABLE
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis.
The sector architecture is based on a uniform sector size of
2 KWord. The Block-Erase mode is based on a uniform
block size of 32 KWord. The Sector-Erase operation is initi-
ated by executing a six-byte command sequence with a
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-Erase
command (50H) and block address (BA) in the last bus
cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse.
The internal Erase operation begins after the sixth WE#
pulse. Any commands issued during the Block- or Sector-
Erase operation are ignored except Erase-Suspend and
Erase-Resume. See Figures 13 and 14 for timing wave-
forms.
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read Operation
The Read operation of the SST34HF16xG is controlled by
BEF# and OE#, both have to be low for the system to
obtain data from the outputs. BEF# is used for device
selection. When BEF# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either BEF# or OE# is
high. Refer to the Read cycle timing diagram for further
details (Figure 7).
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
2
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling
(DQ7) or Toggle Bit (DQ6) read may be simultaneous with
the completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
Flash Chip-Erase Operation
The SST34HF16xG provide a Chip-Erase operation, which
allows the user to erase all sectors/blocks to the “1” state.
This is useful when the device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
BEF#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bits or Data# Polling. See
Table 5 for the command sequence, Figure 12 for timing
diagram, and Figure 24 for the flowchart. Any commands
issued during the Chip-Erase operation are ignored.
Flash Data# Polling (DQ7)
When the device is in an internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed, DQ7
will produce true data. During internal Erase operation, any
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
BEF#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 10 for Data# Poll-
ing (DQ7) timing diagram and Figure 22 for a flowchart.
Flash Erase-Suspend/-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs after
the Erase-Suspend command had been issued. Valid data
can be read from any sector or block that is not suspended
from an Erase operation. Reading at address location
within erase-suspended sectors/blocks will output DQ2 tog-
gling and DQ6 at “1”. While in Erase-Suspend mode, a Pro-
gram operation is allowed except for the sector or block
selected for Erase-Suspend. To resume Sector-Erase or
Block-Erase operation which has been suspended, the
system must issue an Erase-Resume command. The
operation is executed by issuing a one-byte command
sequence with Erase Resume command (30H) at any
address in the one-byte sequence.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ6 will
toggle.
Flash Write Operation Status Detection
The SST34HF16xG provides two software means to
detect the completion of a Write (Program or Erase)
cycle, in order to optimize the system Write cycle time.
The software detection includes two status bits: Data#
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write
detection mode is enabled after the rising edge of WE#,
which initiates the internal Program or Erase operation.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 11 for Toggle Bit tim-
ing diagram and Figure 22 for a flowchart.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
3
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 1: WRITE OPERATION STATUS
Hardware Reset (RST#) - L3K only
Status
DQ7
DQ6
DQ2
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 18). When no internal
Program/Erase operation is in progress, a minimum period
of TRHR is required after RST# is driven high before a valid
Read can take place (see Figure 17).
Normal
Operation
Standard
Program
DQ7#
Toggle
No Toggle
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity. See Figures 17 and 18 for timing
diagrams.
Block
Read From
Non-Erase
Suspended
Sector/
Data
Data
Data
Block
Software Data Protection (SDP)
Program
DQ7#
Toggle
No Toggle
T1.0 1276
The SST34HF16xG provide the JEDEC standard Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of the three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte
sequence. The SST34HF16xG are shipped with the Soft-
ware Data Protection permanently enabled. See Table 5 for
the specific software command codes. During SDP com-
mand sequence, invalid commands will abort the device to
Read mode within TRC. The contents of DQ15-DQ8 are
“Don’t Care” during any SDP command sequence.
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information.
Data Protection
The SST34HF16xG provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST34HF16xG provide a hardware block protection
which protects the outermost 8 KWord in Bank 1. The block
is protected when WP# is held low. See Figure 1 for Block-
Protection location.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
4
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Product Identification
SRAM Operation
The Product Identification mode identifies the device as
SST34HF162G or SST34HF164G and the manufacturer
as SST. This mode may be accessed by software opera-
tions only. The hardware device ID Read operation, which
is typically used by programmers cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, application of
high voltage to pin A9 may damage this device. Users may
use the software Product Identification operation to identify
the part (i.e., using the device ID) when using multiple man-
ufacturers in the same socket. For details, see Tables 4 and
5 for software operation, Figure 15 for the Software ID
Entry and Read timing diagram and Figure 23 for the ID
Entry command sequence flowchart.
With BES# low and BEF# high, the SST34HF162G/164G
operate as either 128K x16 or 256K x16 CMOS SRAM,
with fully static operation requiring no external clocks or
timing strobes. The SST34HF162G/164G SRAM is
mapped into the first 128 KWord address space. When
BES# and BEF# are high, all memory banks are dese-
lected and the device enters standby. Read and Write
cycle times are equal. The control signals UBS# and LBS#
provide access to the upper data byte and lower data byte.
See Table 4 for SRAM Read and Write data byte control
modes of operation.
SRAM Read
The SRAM Read operation of the SST34HF162G/164G is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the Read cycle timing diagram, Figure 4, for fur-
ther details.
TABLE 2: PRODUCT IDENTIFICATION
ADDRESS DATA
Manufacturer’s ID
Device ID
BK0000H
00BFH
SST34HF16xG
BK0001H
734BH
T2.0 1276
SRAM Write
Note: BK = Bank Address (A19-A18
)
The SRAM Write operation of the SST34HF162G/164G is
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. During the Word-Write oper-
ation, the addresses and data are referenced to the rising
edge of either BES# or WE# whichever occurs first. The
write time is measured from the last falling edge of BES#
or WE# to the first rising edge of BES# or WE#. Refer to
the Write cycle timing diagrams, Figures 5 and 6, for fur-
ther details.
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit
command is ignored during an internal Program or Erase
operation. See Table 5 for software command codes, Fig-
ure 16 for timing waveform and Figure 23 for a flowchart.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
5
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
FUNCTIONAL BLOCK DIAGRAM
Address
Buffers
A
A
1- A
2- A
MSF
MSS
0
0
SuperFlash Memory
(Bank 1)
WP#
RST3#
BEF#
LBS#
UBS#
WE#
SuperFlash Memory
(Bank 2)
Control
Logic
I/O Buffers
DQ - DQ
15
0
OE#
BES#
Address
Buffers
2/4 Mbit SRAM
1276 B1.0
Notes: 1. A
= Most significant flash address
MSF
MSF
MSS
MSS
A
2. A
A
= A for SST34HF162G/164G
19
= Most significant SRAM address
= A for SST34HF162G and A for SST34HF164G
16
17
3. RST# is only available on L3K package.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
6
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Sector Protection; 32 KWord Blocks; 2 KWord Sectors
FFFFFH
F8000H
F7FFFH
F0000H
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
07FFFH
02000H
01FFFH
00000H
Block 0
8 KWord Bottom Sector Protection
(4-2 KWord Sectors)
1276 F01.0
FIGURE 1: DUAL-BANK MEMORY ORGANIZATION
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
7
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TOP VIEW (balls facing down)
SST34HF162G/164G
6
V
A13 A12 A14 A15 A16 UBS# DQ15
SS
5
4
3
2
1
DQ6
DQ4
DQ3
DQ1
A9
WE# RST# LBS# A19 DQ5 DQ12
BES# WP# A18 NC DQ2 DQ10 DQ11
A8
A10 A11 DQ7 DQ14 DQ13
V
DD
A7
A3
A17
A4
A6
A2
A5
A1
DQ0 DQ8 DQ9
A0 BEF# OE#
V
SS
A
B
C
D
E
F
G
H
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL LFBGA (6MM X 8MM)
TOP VIEW (balls facing down)
SST34HF162G/164G
6
5
4
3
2
1
BES#
V
DQ1 A1
A2
A3
A4
A7
A19
NC A14
A15
SS
A9
A10 DQ5 DQ2 A0
OE# DQ7 DQ4 DQ0
A6 A18
WP#
A11 A8
A5 DQ8 DQ3 DQ12 A12 LBS#
A13 A17 UBS# BEF# DQ10
V
DQ6 DQ15
DDF
WE#
V
A16
V
DQ9 DQ11 DQ13 DQ14
DDS
SS
A B C D E F G H
FIGURE 3: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM)
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
8
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 3: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMSS1 to A0 Address Inputs
To provide flash address, A19-A0.
To provide SRAM address, AMSS-A0
DQ15-DQ0 Data Inputs/Outputs
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE#, BES#, and BEF# are high.
BEF#
BES#
OE#
Flash Memory Bank Enable
To activate the Flash memory bank when BEF# is low
To activate the SRAM memory bank when BES# is low
To gate the data output buffers
SRAM Memory Bank Enable
Output Enable
WE#
UBS#
LBS#
WP#
Write Enable
To control the Write operations
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
Write Protect
To enable DQ15-DQ8
To enable DQ7-DQ0
To protect and unprotect the bottom 8 KWord (4 sectors)
from Erase or Program operation
RST#
VSS
Reset
To Reset and return the device to Read mode
Ground
VDD
Power Supply2
Power Supply (Flash)
Power Supply (SRAM)
No Connection
2.7-3.3V Power Supply
VDDF
2.7-3.3V Power Supply to Flash only
2.7-3.3V Power Supply to SRAM only
Unconnected pins
VDD
S
NC
T3.0 1276
1. AMSS = Most Significant Address
AMSS = A16 for SST34HF162G and A17 for SST34HF164G
2. L3K package only
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
9
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 4: OPERATIONAL MODES SELECTION FOR SRAM
Mode
BEF#1
BES#1,2
VIH
X
OE#2
X
WE#2
X
LBS#2 UBS#2
DQ15-0
DQ15-8
Full Standby
VIH
X
X
X
X
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
DOUT
DIN
HIGH-Z
HIGH-Z
HIGH-Z
X
X
Output Disable
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
X
VIH
X
X
X
HIGH-Z
HIGH-Z
DOUT
DIN
VIH
X
VIH
X
VIH
VIH
Flash Read
Flash Write
Flash Erase
SRAM Read
VIH
X
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIH
X
X
X
X
X
X
DQ15-8=HIGH-Z
DQ15-8=HIGH-Z
X
VIH
X
VIH
X
X
X
VIL
VIL
VIH
VIL
VIL
VIH
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
DOUT
HIGH-Z
DOUT
DIN
DOUT
DOUT
HIGH-Z
DIN
DOUT
DOUT
HIGH-Z
DIN
SRAM Write
VIH
VIL
X
VIL
HIGH-Z
DIN
DIN
DIN
HIGH-Z
HIGH-Z
Product
Identification3
VIL
VIH
VIL
VIH
Manufacturer’s ID4
Device ID4
T4.0 1276
1. Do not apply BEF# = VIL and BES# = VIL at the same time
2. X can be VIL or VIH, but no other value.
3. Software mode only
4. With A19-A18 = VIL;SST Manufacturer’s ID = BFH, is read with A0=0,
SST34HF16xG Device ID = 734BH, is read with A0=1
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
10
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 5: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
555H
555H
AAH
AAH
AAH
AAH
B0H
30H
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
80H
WA3
555H
555H
555H
Data
AAH
AAH
AAH
Program
4
4
2AAH
2AAH
2AAH
55H
55H
55H
SAX
BAX
30H
50H
10H
Sector-Erase
Block-Erase
555H
555H
555H
Chip-Erase
XXXXH
XXXXH
555H
Erase-Suspend
Erase-Resume
Software ID Entry5
6
2AAH
2AAH
55H
55H
BKX
90H
F0H
555H
555H
XXH
AAH
F0H
555H
Software ID Exit
Software ID Exit
T5.0 1276
1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses A19-A10 address lines
BAX for Block-Erase; uses A19-A15 address lines
5. The device does not remain in Software Product Identification mode if powered down.
6. A19 and A18 = VIL
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . “with-Pb” units2: 240°C for 3 seconds
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . “non-Pb” units: 260°C for 3 seconds
Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Certain “with-Pb” package types are capable of 260°C for 3 seconds; please consult the factory for the latest information.
3. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 19 and 20
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
11
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 6: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input = VILT/VIHT, at f=5 MHz,
1
IDD
Active VDD Current
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
15
10
45
mA
mA
mA
BEF#=VIL, BES#=VIH
BEF#=VIH, BES#=VIL
BEF#=VIH, BES#=VIL
WE#=VIL
SRAM
Concurrent Operation
Write2
Flash
40
30
30
30
1
mA
mA
µA
µA
µA
µA
V
BEF#=VIL, BES#=VIH, OE#=VIH
BEF#=VIH, BES#=VIL
VDD = VDD Max, BEF#=BES#=VIHC
RST#=GND
SRAM
ISB
Standby VDD Current
Reset VDD Current3
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
Input High Voltage
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
SRAM Output Low Voltage
SRAM Output High Voltage
IRT
ILI
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
10
0.8
0.3
VIL
VILC
VIH
V
VDD=VDD Max
0.7 VDD
VDD-0.3
V
VDD=VDD Max
VIHC
VOLF
VOHF
VOLS
VOHS
V
VDD=VDD Max
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL =1 mA, VDD=VDD Min
IOH =-500 µA, VDD=VDD Min
VDD-0.2
2.2
V
V
V
T6.0 1276
1. See Figure 19
2. IDD active while Erase or Program is in progress.
3. L3K package only
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
12
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
100
100
1
TPU-WRITE
µs
T7.0 1276
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
20 pF
16 pF
1
CIN
VIN = 0V
T8.0 1276
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T9.0 1276
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
13
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
AC CHARACTERISTICS
TABLE 10: SRAM READ CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
ns
TRCS
TAAS
TBES
TOES
TBYES
Read Cycle Time
70
Address Access Time
70
70
35
70
ns
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
ns
ns
1
TBLZS
TOLZS
0
0
0
ns
1
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
ns
1
TOHZS
TBYHZS
TOHS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
ns
1
ns
10
ns
T10.0 1276
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: SRAM WRITE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
70
60
60
0
Max
Units
ns
TWCS
TBWS
TAWS
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
ns
30
ns
0
30
0
ns
ns
TDHS
Data Hold from Write Time
ns
T11.0 1276
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
14
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 12: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V
Symbol Parameter
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
70
Chip Enable Access Time
Address Access Time
70
70
35
ns
ns
TOE
TCLZ
TOLZ
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
1
0
0
ns
ns
1
1
TCHZ
20
20
ns
TOHZ
ns
1
TOH
0
ns
1,2
TRP
500
50
ns
1,2
TRHR
RST# High Before Read
RST# Pin Low to Read
ns
1,2,3
TRY
20
µs
T12.0 1276
1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
2. L3K package only
3. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.
TABLE 13: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
µs
TBP
Program Time
12
TAS
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
0
40
0
ns
ns
ns
TAH
TCS
TCH
TOES
TOEH
TCP
0
ns
0
ns
ns
ns
10
40
40
30
30
30
0
TWP
TWPH
ns
ns
ns
1
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
1
TCPH
TDS
ns
ns
ns
1
TDH
Data Hold Time
1
TIDA
Software ID Access and Exit Time
Erase-Suspend Latency
Bus# Recovery Time
Sector-Erase
150
20
1
TES
µs
1
TBR
µs
TSE
25
25
50
ms
ms
TBE
Block-Erase
TSCE
Chip-Erase
ms
T13.1 1276
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
15
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
T
RCS
ADDRESSES
A
MSS-0
T
T
T
OHS
AAS
T
BES
BES#
T
BLZS
BHZS
T
OES
OE#
T
OLZS
T
OHZS
T
BYES
UBS#, LBS#
T
BYLZS
T
BYHZS
DQ
15-0
DATA VALID
1276 F04.0
Note: AMSS = Most Significant Address
MSS = A16 for SST34HF162G and A17 SST34HF164G
A
FIGURE 4: SRAM READ CYCLE TIMING DIAGRAM
T
WCS
ADDRESSES
3
A
MSS -0
T
T
ASTS
T
WPS
WRS
WE#
T
AWS
T
T
BWS
BES#
BYWS
UBS#, LBS#
T
OEWS
T
DHS
T
ODWS
T
DSS
VALID DATA IN
NOTE 2
NOTE 2
DQ
DQ
7-0
15-8,
1276 F05.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes low coincident with or after WE# goes low, the output will remain at high impedance.
If BES# goes high coincident with or before WE# goes high, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
A
MSS = A16 for SST34HF162G and A17 for SST34HF164G
FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
16
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
T
WCS
ADDRESSES
3-0
A
MSS
T
T
WRS
WPS
WE#
T
BWS
BES#
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
NOTE 2
NOTE 2
VALID DATA IN
DQ
DQ
7-0
15-8,
1276 F06.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A16 for SST34HF162G and A17 for SST34HF164G
FIGURE 6: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
T
T
AA
RC
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OE
T
OHZ
T
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1276 F07.0
FIGURE 7: FLASH READ CYCLE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
17
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
T
BP
555
2AA
555
ADDR
ADDRESS A
19-0
T
AH
T
WP
WE#
OE#
T
WPH
T
AS
T
CH
BEF#
T
CS
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
1276 F08.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 8: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
T
BP
555
2AA
555
ADDR
ADDRESS A
19-0
T
AH
T
CP
BEF#
OE#
T
CPH
T
AS
T
CH
WE#
T
DS
T
CS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
1276 F09.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 9: FLASH BEF# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
18
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
DQ
7
DATA
DATA#
DATA#
DATA
1276 F10.0
FIGURE 10: FLASH DATA# POLLING TIMING DIAGRAM
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OEH
T
OE
WE#
T
BR
VALID DATA
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
1276 F11.0
FIGURE 11: FLASH TOGGLE BIT TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
19
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
T
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
SCE
555
2AA
555
ADDRESS A
19-0
BEF#
OE#
T
WP
WE#
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
DQ
15-0
1276 F12.0
Note: This device also supports BEF# controlled Chip-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.)
X can be VIL or VIH, but no other value.
FIGURE 12: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS
555
2AA
555
555
2AA
BA
X
A
19-0
BEF#
OE#
T
WP
WE#
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
DQ
15-0
1276 F13.0
Note: This device also supports BEF# controlled Block-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.)
BAX = Block Address
X can be VIL or VIH, but no other value.
FIGURE 13: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
20
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS
T
SE
555
2AA
555
555
2AA
SA
X
A
19-0
BEF#
OE#
T
WP
WE#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
1276 F14.0
Note: This device also supports BEF# controlled Sector-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.)
SAX = Sector Address
X can be VIL or VIH, but no other value.
FIGURE 14: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
Three-Byte Sequence For Software ID Entry
555
2AA
555
0000
0001
ADDRESS A
14-0
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
Device ID
XXAA
XX55
XX90
00BF
DQ
15-0
1276 F15.0
Note: X can be VIL or VIH, but no other value.
Device ID - 734BH for SST34HF16xG
FIGURE 15: FLASH SOFTWARE ID ENTRY AND READ
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
21
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Three-Byte Sequence for Software ID Exit and Reset
555
2AA
555
ADDRESS A
DQ
14-0
15-0
XXAA
XX55
XXF0
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
1276 F16.0
Note: X can be V or V , but no other value
IL
IH
FIGURE 16: FLASH SOFTWARE ID EXIT
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
22
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
RY/BY#
0V
T
RP
RST#
BEF#/OE#
T
RHR
1252 F17.0
FIGURE 17: RST# TIMING (WHEN NO INTERNAL OPERATION IS IN PROGRESS) L3K PACKAGE ONLY
T
RY
RY/BY#
RST#
BEF#
OE#
T
RP
T
BR
1252 F18.0
FIGURE 18: RST# TIMING (DURING SECTOR- OR BLOCK-ERASE OPERATION) L3K PACKAGE ONLY
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
23
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
V
V
IHT
V
OT
V
IT
INPUT
REFERENCE POINTS
OUTPUT
ILT
1276 F19.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 19: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1276 F20.0
FIGURE 20: A TEST LOAD EXAMPLE
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
24
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load
Address/Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1276 F21.0
Note: X can be VIL or V but no other value.
IH,
FIGURE 21: PROGRAM ALGORITHM
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
25
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read
byte/word
Read DQ
7
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
byte/word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1276 F22.0
FIGURE 22: WAIT OPTIONS
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
26
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Software Product ID Entry
Command Sequence
Software ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX90H
Address: 555
Load data: XXF0H
Address: 555H
Wait T
Wait T
IDA
IDA
Return to normal
operation
Read Software ID
1276 F23.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 23: SOFTWARE PRODUCT ID COMMAND FLOWCHARTS
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
27
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1276 F24.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 24: ERASE COMMAND SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
28
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST34HF162G - XXX
-
XX
-
XXXX
Package Attribute
E1 = non-Pb
Package Modifier
K = 48 balls
Package Type
L3 = LFBGA (6mm x 8mm x 1.4mm, 0.45mm ball size)
LB = LBGA (10mm x 12mm x 1.4mm, 0.50mm ball size)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 =10,000 cycles
Read Access Speed
70 = 70 ns
Version
G = Flash WP# and RST# + SRAM
SRAM Density
2 = 2 Mbit
4 = 4 Mbit
Flash Density
16 = 16 Mbit
Voltage
H = 2.7-3.3V
Product Series
34 = Dual-Bank Flash + SRAM ComboMemory
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST34HF162G
SST34HF162G-70-4C-LBK
SST34HF162G-70-4E-LBK
SST34HF162G-70-4C-L3KE
SST34HF162G-70-4E-L3KE
Valid combinations for SST34HF164G
SST34HF164G-70-4C-LBK
SST34HF164G-70-4E-LBK
SST34HF164G-70-4C-L3KE
SST34HF164G-70-4E-L3KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
29
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
PACKAGING DIAGRAMS
TOP VIEW
8.00 ± 0.20
BOTTOM VIEW
5.60
0.45 ± 0.05
(48X)
0.80
6
5
6
5
4
3
2
1
4.00
4
3
6.00 ± 0.20
2
1
0.80
H
G F E D C B A
A
B C D E F G H
A1 CORNER
A1 CORNER
1.30 ± 0.10
SIDE VIEW
0.12
1mm
SEATING PLANE
0.35 ± 0.05
Note:
1. Except for total height dimension, complies with JEDEC Publication 95, MO-210, variant 'AB-1',
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
48-lfbga-L3K-6x8-450mic-5
48-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 6MM X 8MM
SST PACKAGE CODE: L3K
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
30
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TOP VIEW
12.00 ± 0.20
BOTTOM VIEW
7.0
1.0
6
5
4
3
2
1
6
5
4
3
2
1
5.0
10.00 ± 0.20
1.0
0.50 ± 0.05
(48X)
H
G
F
E
D
C
B
A
A
B
C
D
E
F
G
H
A1 CORNER
A1 CORNER
1.4 Max
SIDE VIEW
0.12
SEATING PLANE
1mm
0.40 ± 0.05
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
48-lbga-LBK-10x12-500mic-2
4. Ball opening size is 0.4 mm (± 0.05 mm)
48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM X 12MM
SST PACKAGE CODE: LBK
TABLE 14: REVISION HISTORY
Number
Description
Date
00
Nov 2004
•
Initial Release
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
31
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